From patchwork Tue May 11 04:20:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 434148 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3460753jao; Mon, 10 May 2021 21:20:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz3b7032F8ZKip0MOjgAwJuO5JNmN2OZuQG6WhEwTpWW4+9/9InFXc6YfbVxdqVFq4rv5iI X-Received: by 2002:a05:6a00:134b:b029:2bf:2c30:ebbd with SMTP id k11-20020a056a00134bb02902bf2c30ebbdmr8809108pfu.74.1620706858809; Mon, 10 May 2021 21:20:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620706858; cv=none; d=google.com; s=arc-20160816; b=hv/dvG4PsY1MSXUTY0SgSZ7uI7ra5XKhZk9PdWpZdYjt+9HusDi7OyvKWrPdj1CV0t qJJMBN5GvFTHrj09UyQqvJZv3rbXjPh2gz+ssn8Gq8Ygzf/oz77FndICkMi7gHU8qu52 Bi8UPZOcpi0Nkk0wgzCyv9LTRWkfEpCUegDTkR1bOm8InkGJuvzaO4V2gJlIR2Zr0sRm LjEBRwkYronE7LoXIwb8mFtQis59o+EhKcP06fxk78Bn7839gYVoxBxtsy/Dd9LEe5DT w4XkaYSuQgxMexx909atg13moT5xoetMIP2LfXCvrmIW1e8z5mMsiShFNN93YIx700ht 8EnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:delivered-to; bh=OcpXm0EDMnP4dra5e7iyBpiH9cJegx8S0SHhpEQspRs=; b=UCjjVSmmKsa+SlXJsOE32Pob/YWiwvkC4//mxUbK5Lg5S5HZx37exPI0yG8ggZl8rZ aDdFAyyayTKmzYZoyJCAVHdj1sE41f9Z5i6l2DuOTprdoSsHskvspDPzhibOb+gnrwWg qarGqqfHDyWY4WbdCqJoRwMWxd8LjEvcOSntI6hOsG9wKxJ2w1Ubv0eGdPm9lBX/hA0s f6QlscmGPHfW98LeEAv5bKnDZzieyng2SkTg/9QkMyKCBFnk8vz4I3K00G3Z3AK5n5/U 6jk5O260kpbTHIZgN/aYPWngks6QR8v3ztM3KRbb0q8nEnuyjDsdnq7/GDHmsoHA0MS5 jHEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uy35xOt8; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id n15si19913391plc.112.2021.05.10.21.20.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 21:20:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uy35xOt8; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B7BAF6E9AE; Tue, 11 May 2021 04:20:56 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-oo1-xc36.google.com (mail-oo1-xc36.google.com [IPv6:2607:f8b0:4864:20::c36]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2F9266E9B0 for ; Tue, 11 May 2021 04:20:55 +0000 (UTC) Received: by mail-oo1-xc36.google.com with SMTP id p6-20020a4adc060000b02901f9a8fc324fso3950220oov.10 for ; Mon, 10 May 2021 21:20:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OcpXm0EDMnP4dra5e7iyBpiH9cJegx8S0SHhpEQspRs=; b=uy35xOt8NlWv2bH/rJeOkeWy/DdvsU2ILjJHieExX+E824ktjTUD7GWuxkWugIEz0Z SrasuBXe/RGJ+jckNzWj9U5MNJmIWcn4NvHz1ym51cvjVK6SpYTKkUD7o7yGfnrGxQ7f RnWNPOZofts9QPo6ptIIQR7wZ363rAPgox9S8upKUJKJMLxwFu5/FPMh/1QUw8rNZt04 kEEwUeM+XWuD+NjZ/8Gdq29/fc5Mfhb9wtpAWZgex1pGtmpoNSTJpehdIejYTureT4iG ipeO67SMP3v99f8j+K+PerjxbCPOJzAG4DymV4lo3KwY4RcUKuvWfNbaufRtk3xjxVrL W76Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OcpXm0EDMnP4dra5e7iyBpiH9cJegx8S0SHhpEQspRs=; b=U5xZDlpDe8h4cQvbi0F0z3HqoEHH02ElcRdbUdzu/hFNUDPnlOSPhO59gxW8GcV4ZN vAcz2CRXnvoa06G2QfIUwQ6mMa0jMuWmL9/ldmqPVZDCzQsJsUekswORk1HeGqhtZuFQ LIuaC7Uy6k4VMqS7HmB3I01tFzL+dd0Sw0V9yJJlTgQOECV3LMhHtqflCiaCKvdgwNB4 P2k+WaMjh+L6oxNkimd8E7C3n1N5mIb8xzVhGCzCQryOwcfGUFS+M5emv8WvMHoXGsYm Hgnvxd0ydphNMw4+6HRK+MroRVZPn1+VgRaFw7Lj24K2hxr4Z3vcL9B1vdATwe+UkVTP kZOA== X-Gm-Message-State: AOAM530cs0Fm1FOwGPO+Rcs63cXx8UItPbr/5poFIUOpYFDvJxPOMxHT Ls/x8mNbCU+Q+Cj2psSoOd8a8Q== X-Received: by 2002:a4a:b102:: with SMTP id a2mr21819330ooo.30.1620706854521; Mon, 10 May 2021 21:20:54 -0700 (PDT) Received: from localhost.localdomain ([2607:fb90:e623:42c1:10df:adff:fec2:f1d]) by smtp.gmail.com with ESMTPSA id r124sm3042294oig.38.2021.05.10.21.20.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 21:20:54 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Stephen Boyd , sbillaka@codeaurora.org Subject: [PATCH 1/4] drm/msm/dp: Simplify the mvid/nvid calculation Date: Mon, 10 May 2021 23:20:40 -0500 Message-Id: <20210511042043.592802-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210511042043.592802-1-bjorn.andersson@linaro.org> References: <20210511042043.592802-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tanmay Shah , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Abhinav Kumar , Dmitry Baryshkov , freedreno@lists.freedesktop.org, Chandan Uddaraju Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In the search for causes to timing issues seen during implementation of eDP support for SC8180x a fair amount of time was spent concluding why the calculated mvid/nvid values where wrong. The overall conclusion is that the ratio of MVID/NVID describes, and should match, the ratio between the pixel and link clock. Downstream this calculation reads the M and N values off the pixel clock straight from DISP_CC and are then adjusted based on knowledge of how the link and vco_div (parent of the pixel clock) are derrived from the common VCO. While upstreaming, and then extracting the PHY driver, the resulting function performs the following steps: 1) Adjust the passed link rate based on the VCO divider used in the PHY driver, and multiply this by 10 based on the link rate divider. 2) Pick reasonable choices of M and N, by calculating the ratio between this new clock and the pixel clock. 3) Subtract M from N and flip the bits, to match the encoding of the N register in DISP_CC. 4) Flip the bits of N and add M, to get the value of N back. 5) Multiply M with 5, per the documentation. 6) Scale the values such that N is close to 0x8000 (or larger) 7) Multply M with 2 or 3 depending on the link rate of HBR2 or HBR3. Presumably step 3) was added to provide step 4) with expected input, so the two cancel each other out. The factor of 10 from step 1) goes into the denominator and is partially cancelled by the 5 in the numerator in step 5), resulting in step 7) simply cancelling out step 1). Left is the code that finds the ratio between the two arguments, scaled to keep the denominator close to or larger than 0x8000. And this is our mvid/nvid pair. Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/dp/dp_catalog.c | 41 +++++------------------------ 1 file changed, 6 insertions(+), 35 deletions(-) -- 2.29.2 diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index b1a9b1b98f5f..2eb37ee48e42 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -415,39 +415,16 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, bool fixed_nvid) { - u32 pixel_m, pixel_n; - u32 mvid, nvid, pixel_div = 0, dispcc_input_rate; u32 const nvid_fixed = DP_LINK_CONSTANT_N_VALUE; - u32 const link_rate_hbr2 = 540000; - u32 const link_rate_hbr3 = 810000; - unsigned long den, num; - + unsigned long mvid, nvid; struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - if (rate == link_rate_hbr3) - pixel_div = 6; - else if (rate == 1620000 || rate == 270000) - pixel_div = 2; - else if (rate == link_rate_hbr2) - pixel_div = 4; - else - DRM_ERROR("Invalid pixel mux divider\n"); - - dispcc_input_rate = (rate * 10) / pixel_div; - - rational_best_approximation(dispcc_input_rate, stream_rate_khz, - (unsigned long)(1 << 16) - 1, - (unsigned long)(1 << 16) - 1, &den, &num); - - den = ~(den - num); - den = den & 0xFFFF; - pixel_m = num; - pixel_n = den; - - mvid = (pixel_m & 0xFFFF) * 5; - nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF); + rational_best_approximation(stream_rate_khz, rate, + (1 << 16) - 1, (1 << 16) - 1, + &mvid, &nvid); + /* Adjust values so that nvid is close to DP_LINK_CONSTANT_N_VALUE */ if (nvid < nvid_fixed) { u32 temp; @@ -456,13 +433,7 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, nvid = temp; } - if (link_rate_hbr2 == rate) - nvid *= 2; - - if (link_rate_hbr3 == rate) - nvid *= 3; - - DRM_DEBUG_DP("mvid=0x%x, nvid=0x%x\n", mvid, nvid); + DRM_DEBUG_DP("mvid=0x%lx, nvid=0x%lx\n", mvid, nvid); dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid); dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid); dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); From patchwork Tue May 11 04:18:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 434144 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3459770jao; Mon, 10 May 2021 21:19:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJypDAB1McfqLdAY5sS+4X1PZxDJ88Z+eZCVQQPH4V+vgAvNLy4aAEAf/MfofoxOYWSF483X X-Received: by 2002:a63:eb46:: with SMTP id b6mr28306775pgk.199.1620706750670; Mon, 10 May 2021 21:19:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620706750; cv=none; d=google.com; s=arc-20160816; b=JKwitysloVu5t4PCKNu/Nr3IYJYK7Gge9a3lEdi1tpj4MIpZvhT6ZTxp3CBCAA1xo+ Po5xDAS9W9rhRTq/MQJggd5RDm1gx6NhFdAdmUW14nYnZIE3AKMO1yx+3yAMgfGeRNcG gnJIz1pGUwp2ZL1iBuB+2GVO41rhPuLZh3UQRLm7gs4s85h0ZO3rHH4MvegvOl6iLFaB ZBYbkFH0xbfhmEmcaw4/d7r7G3KaimBMA9vS4N+eS5cVyAUfImzkda9nSbXlZSPZ4Kun YaDCvYCoqPugb3z+rU7CG02Gbz5YSpyRvGuCVqWihXfOQ2c/9lNGDyMOH2Mqf2EMbbDI 4s+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:delivered-to; bh=rN0DT3zlZfmYWomZy/xhSTmw4G63PXYLKWmt/5607Kk=; b=0Kvom0ANZb/p0Kwo3ArGhyVCSX/7GpKxrqrpq++HptmXCywNG9n/L7vsgJx62bZZLa e/wKhQgSJbZcsw2zMpWUUq4wf/I77JZbcyR8Jc7lRDyBWrTUaMRa0D+lAgyRZPdT3z/k V9HKCik9vW7MKJnpJA/VGhxVSj7PTmigjOLxl+eoixqdaGDTv9ICe5GZzHTvBipE94B4 9nncUUtHpgYTARSJzZ3C2Zi9XVrZRUVrGl6fgnwsGtojAlGw5El5XjtEa7RH44Dfe8q4 vHoqDAdw/fpYBm3ua7xMTOxkLh/dFVjV5bPDHMSINqgm/KelfxluamJPb2dAzeTmdll8 OhNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Pol1SjKq; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id f14si10759001pfj.276.2021.05.10.21.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 21:19:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Pol1SjKq; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5DE816E9B4; Tue, 11 May 2021 04:19:04 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-oo1-xc36.google.com (mail-oo1-xc36.google.com [IPv6:2607:f8b0:4864:20::c36]) by gabe.freedesktop.org (Postfix) with ESMTPS id CD4956E9B5 for ; Tue, 11 May 2021 04:19:02 +0000 (UTC) Received: by mail-oo1-xc36.google.com with SMTP id v14-20020a4ae6ce0000b02901fe68cd377fso3938972oot.13 for ; Mon, 10 May 2021 21:19:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rN0DT3zlZfmYWomZy/xhSTmw4G63PXYLKWmt/5607Kk=; b=Pol1SjKqEVGlx/WScV9FX5CZvpeia/m9qrHo+ror/7kmCvGHG3QC38IWj6KzE3c9XH ce7ASja3E5wkKuCbXBH0Uk9ac82RNb6ROPT8XyBHYsDx42bPg78cUCyXPZn18+QG3km6 GHnFlUN/BJdAjN8ZVP6vqoMiMpzRA6yMcEAV6P3ZS8zezHZux1hL/s+4V5gFGP+t4lpx +2z0/WFKljoMLNXwPxTF9G7CnMZ5Ka0eT/NRsIK0GOKzWHFak7VozsDigy9BrW9EkSp9 WGorcxAarLHSepbVVfB6Ep7Jd0fbSRcsjLUDQB666W08InmAu/Dwpj9hsnfuib1vDWBj uhAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rN0DT3zlZfmYWomZy/xhSTmw4G63PXYLKWmt/5607Kk=; b=ljVeceihhaDwGuzSdRmNxvFHpiRCoGdFXNDH7m4pilg9pd70JtWbIe0fktdAGfye8z Fb3T/FsX98dGG7pEQoyTi8EffkZ8ntvE+UeRJ2z4S2mo3lPVx8JnjvFeSYRu2TrV2+8E XBAgOFNIOdmTgULt0BgioMWZEEbpvpEgbXvzmAAmqXC82etedqYxbOsMAe1p788H2kDR 2oxBl2nCCgLRmj3vp9oxtP5TtQg3nTdmRYOBFPI/3CSJwSAs/fF3QBQ5oxVT+3rIvy7D hHsZkUg4wFMpPXhmh5tbmTamX3BxPGpcM/Ipq3mrUJoImkIxz9QIZG0P8fVUvKMK+jQ/ JV6A== X-Gm-Message-State: AOAM5327c+lOz0tRKegP44WCfkfm05/AYX98I7YulUTgkMdhWMWIbYYn c5wSzSJuUB++YBUdxe4PFJR8dA== X-Received: by 2002:a4a:d4c7:: with SMTP id r7mr6433326oos.85.1620706742050; Mon, 10 May 2021 21:19:02 -0700 (PDT) Received: from localhost.localdomain ([2607:fb90:e623:42c1:10df:adff:fec2:f1d]) by smtp.gmail.com with ESMTPSA id z15sm558647otp.20.2021.05.10.21.19.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 21:19:01 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Dmitry Baryshkov Subject: [PATCH 4/4] dpu: hack up the irq table for 8180 intf_5 Date: Mon, 10 May 2021 23:18:52 -0500 Message-Id: <20210511041852.592295-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210511041852.592295-1-bjorn.andersson@linaro.org> References: <20210511041852.592295-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Signed-off-by: Bjorn Andersson --- This is a hack and as discussed on IRC this should be replaced by some sane mechanism for dealing with the old and new IRQ layout. Including it in the series for completeness. drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) -- 2.29.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 48c96b812126..fa576c617f86 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -72,11 +72,13 @@ #define DPU_INTR_INTF_1_UNDERRUN BIT(26) #define DPU_INTR_INTF_2_UNDERRUN BIT(28) #define DPU_INTR_INTF_3_UNDERRUN BIT(30) +#define DPU_INTR_INTF_4_UNDERRUN BIT(20) #define DPU_INTR_INTF_5_UNDERRUN BIT(22) #define DPU_INTR_INTF_0_VSYNC BIT(25) #define DPU_INTR_INTF_1_VSYNC BIT(27) #define DPU_INTR_INTF_2_VSYNC BIT(29) #define DPU_INTR_INTF_3_VSYNC BIT(31) +#define DPU_INTR_INTF_4_VSYNC BIT(21) #define DPU_INTR_INTF_5_VSYNC BIT(23) /** @@ -310,14 +312,10 @@ static const struct dpu_irq_type dpu_irq_map[] = { { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3, DPU_INTR_PING_PONG_3_WR_PTR, 0}, /* irq_idx: 20-23 */ - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0, - DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1, - DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2, - DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3, - DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0}, + { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_4, DPU_INTR_INTF_4_UNDERRUN, 0}, + { DPU_IRQ_TYPE_INTF_VSYNC, INTF_4, DPU_INTR_INTF_4_VSYNC, 0}, + { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0}, + { DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0}, /* irq_idx: 24-27 */ { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, DPU_INTR_INTF_0_UNDERRUN, 0}, { DPU_IRQ_TYPE_INTF_VSYNC, INTF_0, DPU_INTR_INTF_0_VSYNC, 0},