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X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v3 1/5] target/arm: support reading of CNT[VCT|FRQ]_EL0 from user-space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since kernel commit a86bd139f2 (arm64: arch_timer: Enable CNTVCT_EL0 trap..) user-space has been able to read these system registers. As we can't use QEMUTimer's in linux-user mode we just directly call cpu_get_clock(). Signed-off-by: Alex Bennée --- v2 - include CNTFRQ_EL0 for PL0_R only v3 - use NANOSECONDS_PER_SECOND / GTIMER_SCALE --- target/arm/helper.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 1248d84e6f..6e6b1762e8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2166,11 +2166,32 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { }; #else -/* In user-mode none of the generic timer registers are accessible, - * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, - * so instead just don't register any of them. + +/* In user-mode most of the generic timer registers are inaccessible + * however modern kernels (4.12+) allow access to cntvct_el0 */ + +static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* Currently we have no support for QEMUTimer in linux-user so we + * can't call gt_get_countervalue(env), instead we directly + * call the lower level functions. + */ + return cpu_get_clock() / GTIMER_SCALE; +} + static const ARMCPRegInfo generic_timer_cp_reginfo[] = { + { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, + .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, + .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), + .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, + }, + { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, + .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, + .readfn = gt_virt_cnt_read, + }, REGINFO_SENTINEL }; From patchwork Mon Jun 25 16:00:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139864 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4166241lji; Mon, 25 Jun 2018 09:06:49 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfEtulRRXuFL/p24LhXi5hp0E0tZkNPQF+4azjKYwyiy6CDQoJOkdguYKc2hyJglu+sLc37 X-Received: by 2002:aed:3d4a:: with SMTP id h10-v6mr8673710qtf.363.1529942809829; Mon, 25 Jun 2018 09:06:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529942809; cv=none; d=google.com; s=arc-20160816; b=SJXaazFCtuEyUkbMXEduwFyGY6YYmtleoCkKOU4vETu+c5Q/TigwHzYbz9OMBqBWqh v87JQWIUVaV3nkvQ8k9CvDZ/Llnx9m478x7224gVxI1fVvuKrpjskudFuUhYiLB5WY8u slAqXD+lCnoTsKTp98NBCA8cPOCkN9GDgSGZzNFOVVh/cfsdZPZkpfPK2XvzaOua9cvF KMdT/zC3mrgibNHzl9bZLdwG9SNKThm2sLJZv6U7zqexaS4P6xUwC4a4pemrJEnWhAz9 Cf21nHNhoTnSi+x2c5TidFpqQ56lnVM8NWGmgJStEmpHZJY5o/8o4O5Ff/ol4FKVxKdt R9ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=TwXHldywT1MI4fCv7QetLUNUwCIoFxeHYvHSCnIQVqw=; b=o7wUPaF7QeqZD9Z4mSM5+51XeRqzcUFceTblFLdTS3rOhZHIzjJ6VytxAFmSIpg6Qv thttMac/bJiIa3LRBhGtQZP/84n+DFNV8/D5GoIBvGuKLkanptokgNusazFMau1VhyNM T9rFd+JS7CtD6UqInfXpEjqhJ3avRS/j1GVEs7wvmpGe7sy39KkcMpzrLDQZ1SSIV5yT UDPTut/RUeGAr3D4CxHgoGZvD7XYdQN/vn1JxFg2CdskSX2ch9OxWkHc8YF21myt1bow 17Lkv9MFbVAXNv8/JdoAI47eOesPCOq8Q/TL4q54YJSy3miVjnkOwfRS1NhFb5UCxzAx D1vA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BBmxoVME; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v3 2/5] target/arm: relax permission checks for HWCAP_CPUID registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Although technically not visible to userspace the kernel does make them visible via trap and emulate. For user mode we can provide the value directly but we need to relax our permission checks to do this. Signed-off-by: Alex Bennée --- target/arm/helper.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 6e6b1762e8..9d81feb124 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5813,7 +5813,19 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (r->state != ARM_CP_STATE_AA32) { int mask = 0; switch (r->opc1) { - case 0: case 1: case 2: + case 0: +#ifdef CONFIG_USER_ONLY + /* Some AArch64 CPU ID/feature are exported to userspace + * by the kernel (see HWCAP_CPUID) */ + if (r->opc0 == 3 && r->crn == 0 && + (r->crm == 0 || + (r->crm >= 4 && r->crm <= 7))) { + mask = PL0_R; + break; + } +#endif + /* fall-through */ + case 1: case 2: /* min_EL EL1 */ mask = PL1_RW; break; From patchwork Mon Jun 25 16:00:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139865 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4170593lji; Mon, 25 Jun 2018 09:10:50 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJ6YBNTGklh3/3XUp5BAWUC+a59nyAghTqPySCq6yRIrUukmXHBWzW0wcp4B3mbOPztpmqy X-Received: by 2002:aed:35c2:: with SMTP id d2-v6mr5742000qte.219.1529943050545; Mon, 25 Jun 2018 09:10:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529943050; cv=none; d=google.com; s=arc-20160816; b=vELORE1lQ82k7Ax28aA1zt3BqbwK1UaDznPpoxMXfPZqzbE8DxOsVdoZnhKaUtMsSp CzaK9k2x5bABFmm+0D5uI+n4TmXN76EprxSRnZ5ulb5y8DtDO4BjNHutKcrBnTiU3ONB 8vB0Ijp5m/IrUVPyaq8Lxeh50wRrms5pmnruTrbbvgD6vG3I1oZA45n/t73BxrO61zbK k+hWgBHlxMPlQU+khloZOVb0QiOzjoBI88DxAu9W6yCJ+haerKmPB7qSz2A772/W1y26 J3n91STajzLdSuvjFkebK4L6U4CqK6VdtDpnQQw+pcHeL86epgvy0Gv/Jf8lj1crkn9p TFNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=L+CkdW7090xExY/8k1283u40u9PL7caTx+GsyIIpY34=; b=Nw/tqbko9pxltLmtIa23Qx9n7uOda4ZFd1l/Ag5Q+CP1TjTDcM9f9XuzwYHjnNr5rM QGEPmc2epYYmv/0pzDbH3tUQkRf47ZzobBbWIUTKKQrpIgQT7gFMBACexVCSQ+BtSi5J Rq391kjjd0s47OCxzul5742LQdYnnlbAxfMa8ErSu7Y6UzCjHoOXh66VUDd7s7vSJTcg TbkTkgmLdUYn9DZ+7ZTkzlPdfAlqj/GeO3CXs1ypNR/JXkO3fgnM/sfHWgNDVKk7O/W2 heWuWm8idT12tkRqE9YB8cuGGmNfBOmFejedSi44Euua+lNPcHiw49WIP9/omGUqtteG tmCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Qz6tS6f+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o3-v6si3288090qkc.17.2018.06.25.09.10.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 25 Jun 2018 09:10:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Qz6tS6f+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48087 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXU4n-00055V-H2 for patch@linaro.org; Mon, 25 Jun 2018 12:10:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52904) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXTue-000594-Me for qemu-devel@nongnu.org; Mon, 25 Jun 2018 12:00:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXTuY-00052w-Bs for qemu-devel@nongnu.org; Mon, 25 Jun 2018 12:00:20 -0400 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:34671) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fXTuY-00051r-2X for qemu-devel@nongnu.org; Mon, 25 Jun 2018 12:00:14 -0400 Received: by mail-wm0-x244.google.com with SMTP id l15-v6so12870413wmc.1 for ; Mon, 25 Jun 2018 09:00:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L+CkdW7090xExY/8k1283u40u9PL7caTx+GsyIIpY34=; b=Qz6tS6f+YHXESmgV5zWpIt0Uflvre60u516aFmi8/gBa21en0pLzJUn2Zr5fFAUXal 26VXYvfWwGGSwFNO6Ea/H4uQ7oQeFy4+yRE23uTDGqUaglRwAcMiG8paxh4/RTfPAcqZ /Pt/UTxOnGztd8jKvWp9QgYOqKOn8/scGQ6Cc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L+CkdW7090xExY/8k1283u40u9PL7caTx+GsyIIpY34=; b=WptKY1EwgjwQO3YfVeOQvPZd3xGrKn6cn7FtQT+DXvLZnh87tgzhe7JmPSP2f136Ro z5hDLMspaC0gZVxHfx6WKNfVRXiqdM6ZdQFwTo/TiJXst6V0apZG/us+V2B63gsQD0j/ h+jTXwoVr0b8SGqn410Crx9KPF1x3ZpdP3jRC9XRDB0j21KeTOZeMcNBtjjxyJWNEyMG 2vaVuxYysq/SZ5olehvqz0v8QyBFSbqPps8jdReKOKJ3mdaLoYe4VCYSYQ3nb0af7naz DUydvCBzF7sU78GVXIr8LX0Hz+TKgGrybc53aEExfY1DXEK5Qh9Rxp2TXd37769dMIrk I7rQ== X-Gm-Message-State: APt69E2mbVd4UETIzzM5JsRvicwSsTX2rZ2K5nsYt16SkxG3EuS427ZE xF2OPjssTVymyFfmeB8xEWrl3w== X-Received: by 2002:a1c:8cc8:: with SMTP id o191-v6mr1497881wmd.75.1529942412926; Mon, 25 Jun 2018 09:00:12 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id l67-v6sm12841639wmb.22.2018.06.25.09.00.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 25 Jun 2018 09:00:11 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 7277B3E08BB; Mon, 25 Jun 2018 17:00:09 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Mon, 25 Jun 2018 17:00:07 +0100 Message-Id: <20180625160009.17437-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180625160009.17437-1-alex.bennee@linaro.org> References: <20180625160009.17437-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v3 3/5] target/arm: expose CPUID registers to userspace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A number of CPUID registers are exposed to userspace by modern Linux kernels thanks to the "ARM64 CPU Feature Registers" ABI. For CONFIG_USER_ONLY we don't emulate the kernels trap and emulate but instead just lower the read permission to PL0_R (hidden behind the PL1U_R macro). The ID_AA64PFR0_EL1 is a little special as the GIC version is hidden from userspace so we can define a ARM_CP_CONST version of the register for usermode. Signed-off-by: Alex Bennée squash! target/arm: expose CPUID registers to userspace --- target/arm/cpu.h | 7 +++++++ target/arm/helper.c | 39 +++++++++++++++++++++++++-------------- 2 files changed, 32 insertions(+), 14 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a4507a2d6f..156c811654 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1924,6 +1924,13 @@ static inline bool cptype_valid(int cptype) #define PL0_R (0x02 | PL1_R) #define PL0_W (0x01 | PL1_W) +/* for AArch64 HWCAP_CPUID to userspace */ +#ifdef CONFIG_USER_ONLY +#define PL1U_R PL0_R +#else +#define PL1U_R PL1_R +#endif + #define PL3_RW (PL3_R | PL3_W) #define PL2_RW (PL2_R | PL2_W) #define PL1_RW (PL1_R | PL1_W) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9d81feb124..1ea0dc4593 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2987,7 +2987,7 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) static const ARMCPRegInfo mpidr_cp_reginfo[] = { { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, - .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, + .access = PL1U_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, REGINFO_SENTINEL }; @@ -4776,6 +4776,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr1; } +#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = arm_env_get_cpu(env); @@ -4786,6 +4787,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) } return pfr0; } +#endif void register_cp_regs_for_features(ARMCPU *cpu) { @@ -4934,18 +4936,26 @@ void register_cp_regs_for_features(ARMCPU *cpu) * define new registers here. */ ARMCPRegInfo v8_idregs[] = { - /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't - * know the right value for the GIC field until after we - * define these regs. + /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST for system + * emulation because we don't know the right value for the + * GIC field until after we define these regs. For + * user-mode HWCAP_CPUID emulation the gic bits are masked + * anyway. */ { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, +#ifndef CONFIG_USER_ONLY .access = PL1_R, .type = ARM_CP_NO_RAW, .readfn = id_aa64pfr0_read, - .writefn = arm_cp_write_ignore }, + .writefn = arm_cp_write_ignore +#else + .access = PL0_R, .type = ARM_CP_CONST, + .resetvalue = cpu->id_aa64pfr0 +#endif + }, { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL1U_R, .type = ARM_CP_CONST, .resetvalue = cpu->id_aa64pfr1}, { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, @@ -4973,11 +4983,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue = 0 }, { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL1U_R, .type = ARM_CP_CONST, .resetvalue = cpu->id_aa64dfr0 }, { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL1U_R, .type = ARM_CP_CONST, .resetvalue = cpu->id_aa64dfr1 }, { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, @@ -5005,11 +5015,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue = 0 }, { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL1U_R, .type = ARM_CP_CONST, .resetvalue = cpu->id_aa64isar0 }, { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL1U_R, .type = ARM_CP_CONST, .resetvalue = cpu->id_aa64isar1 }, { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, @@ -5037,11 +5047,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue = 0 }, { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL1U_R, .type = ARM_CP_CONST, .resetvalue = cpu->id_aa64mmfr0 }, { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL1U_R, .type = ARM_CP_CONST, .resetvalue = cpu->id_aa64mmfr1 }, { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, @@ -5335,7 +5345,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo id_v8_midr_cp_reginfo[] = { { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, + .access = PL1U_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), .readfn = midr_read }, /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ @@ -5347,7 +5357,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .resetvalue = cpu->midr }, { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, + .access = PL1U_R, .type = ARM_CP_CONST, + .resetvalue = cpu->revidr }, REGINFO_SENTINEL }; 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v3 4/5] linux-user/elfload: enable HWCAP_CPUID for AArch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Riku Voipio , qemu-arm@nongnu.org, =?utf-8?q?Alex_?= =?utf-8?q?Benn=C3=A9e?= , qemu-devel@nongnu.org, Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Userspace programs should (in theory) query the ELF HWCAP before probing these registers. Now we have implemented them all make it public. Signed-off-by: Alex Bennée --- linux-user/elfload.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 13bc78d0c8..76d7674649 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -566,6 +566,7 @@ static uint32_t get_elf_hwcap(void) hwcaps |= ARM_HWCAP_A64_FP; hwcaps |= ARM_HWCAP_A64_ASIMD; + hwcaps |= ARM_HWCAP_A64_CPUID; /* probe for the extra features */ #define GET_FEATURE(feat, hwcap) \ From patchwork Mon Jun 25 16:00:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139862 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4164370lji; Mon, 25 Jun 2018 09:05:15 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeo/z3QrzI0H3kF0wJ0+TeV0Rtr7FWXDtZm5p58Ur3UEy696t8y1CEmdTU7BLMYc23zLpAl X-Received: by 2002:aed:220e:: with SMTP id n14-v6mr11444782qtc.68.1529942715318; Mon, 25 Jun 2018 09:05:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529942715; cv=none; d=google.com; s=arc-20160816; b=iHXCT+UccNXyDqFG0kbJoY4+DTmvKUtviXFIYck+z1TltllzXn2n1ZS/xEL73dM1Fw Du99AeI4ZzVc3chanTulKzP/Br1KQfi/gVLK87SoVmsitMVblRM6D42Pa+5oL0BEe3IU 07rMakyx6eJxWSLxi/Iji2bJ/r8da7B3NERhBbXsflRcY6LOHySJrQ4eg9GhIefBEWLy eFWOhgAz7g2qJjmPjVeGp2YhRBSCVhiwhhkTPoeFFMwBPA7BXvb+cEpesfIK7/EHOqws k+NBJ/2AwqGvXZoqW/9CY+srSqI37+3dNYs9k2whOXWi4dYwjDs7mqRDcMGBy0NelJul /SJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=wvvefg7SIN2MnLMPoNxKILPy8nFjsmp3rK/nOlMAARw=; b=f7EMwCbyi1ExFg+iJaWp0qNHC0PF7hTv9HzkP8TUrAaEb84dxvPUCwSxWAoZoDr162 T9JsmxtgU6QoQwF3lqcCsFlq+InJHekY7enNn0cdwJKvtNyN4BczLeAckEeRCHyY5qr3 y+BdFvZYf8Iz6gig7WhuuWnBPnbq4ZNQ1VXoUYkJGLlU/3tNcivI5Zb78X5Czzo+KI4H W8sGjK58VXyWWU+qNbYfxUZzDxDolS7xskXQakVdgmo0kcMgoGMAQ9BUaTt27+KErZtV mXKuydxgpKDS2lTGQnL3VfVmKoP5b3s/9si4jGnCJGd7zGYpGU3BjeRaOEBM9wxkI1GG S87w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aFqFkmhr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g3-v6si376250qve.248.2018.06.25.09.05.14 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 25 Jun 2018 09:05:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aFqFkmhr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48022 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXTzO-0000GN-El for patch@linaro.org; Mon, 25 Jun 2018 12:05:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52851) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fXTub-0004yp-NM for qemu-devel@nongnu.org; Mon, 25 Jun 2018 12:00:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fXTua-00055E-Gg for qemu-devel@nongnu.org; Mon, 25 Jun 2018 12:00:17 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:38673) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fXTua-000548-A2 for qemu-devel@nongnu.org; Mon, 25 Jun 2018 12:00:16 -0400 Received: by mail-wm0-x241.google.com with SMTP id 69-v6so10601310wmf.3 for ; Mon, 25 Jun 2018 09:00:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wvvefg7SIN2MnLMPoNxKILPy8nFjsmp3rK/nOlMAARw=; b=aFqFkmhrxA/evWFvhHeb9/z1tCAfvGS3uhMYtVo16y+Qi4zZYx+Pi1CmFLvuMerWHh 6OqYpGl/gITolD0tEGRHC88lPu6f/kFG72tIswl9oCb1o7jwyVhkVrise6uTwoIjhSts 9oHG0pXnbVUUKw4lduhsqzWc7LmmE+MR2iRUo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wvvefg7SIN2MnLMPoNxKILPy8nFjsmp3rK/nOlMAARw=; b=llW7MtpVgfVYzv8omXnZyyqcx+HxLA/JxXT8C+E3xO8Ca9hu4jJF1x8sMyKCiQhXkB AW4VOtHkfnFR8ta9cjFnW/QdCzAWHzx4WakYP97GOFPjFf7uA9E/8WiNP1ZJFeAVGJl9 BU0u4bn7y/lfOQvobOjiBAaPMjw/h7uMuDhgQdnlKIbN0NtNhGahI7K+RK+5+mIReBB0 77YL75FRmm1SIDCxYLqsmlltI6d0UPaXfFl02NXlKtsxWHN7uUfbRO5OQKc1JJRACEpN oEqyjLamwvNPd77HvtFUt7nDTcC4YwBr244LQq78G71F42ISxYPT5I2RH9DN0xrDh3SX /dDQ== X-Gm-Message-State: APt69E0c9+YYgDtgjc5F0iW/7IWO1FhPvn4cQMw/8C7h/p6DNK739bZR qdvLovYotHtaSWUIvrw1X/VFaw== X-Received: by 2002:a1c:8c55:: with SMTP id o82-v6mr1420668wmd.60.1529942415020; Mon, 25 Jun 2018 09:00:15 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id a9-v6sm12494479wmh.38.2018.06.25.09.00.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 25 Jun 2018 09:00:12 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 99D6E3E08E5; Mon, 25 Jun 2018 17:00:09 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Mon, 25 Jun 2018 17:00:09 +0100 Message-Id: <20180625160009.17437-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180625160009.17437-1-alex.bennee@linaro.org> References: <20180625160009.17437-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v3 5/5] tests/tcg/aarch64: userspace system register test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This tests a bunch of registers that the kernel allows userspace to read including the CPUID registers. Signed-off-by: Alex Bennée --- tests/tcg/aarch64/Makefile.target | 2 +- tests/tcg/aarch64/sysregs.c | 99 +++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/sysregs.c -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 08c45b8470..cc1a7eb486 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -7,7 +7,7 @@ VPATH += $(AARCH64_SRC) # we don't build any of the ARM tests AARCH64_TESTS=$(filter-out $(ARM_TESTS), $(TESTS)) -AARCH64_TESTS+=fcvt +AARCH64_TESTS+=fcvt sysregs TESTS:=$(AARCH64_TESTS) fcvt: LDFLAGS+=-lm diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c new file mode 100644 index 0000000000..177d1fe33b --- /dev/null +++ b/tests/tcg/aarch64/sysregs.c @@ -0,0 +1,99 @@ +/* + * Check emulated system register access for linux-user mode. + * + * See: https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.txt + */ + +#include +#include +#include +#include +#include +#include + +#define get_cpu_reg(id) ({ \ + unsigned long __val = 0xdeadbeef; \ + asm("mrs %0, "#id : "=r" (__val)); \ + printf("%-20s: 0x%016lx\n", #id, __val); \ + }) + +bool should_fail; + +int should_fail_count; +int should_not_fail_count; +uintptr_t failed_pc[10]; + +void sigill_handler(int signo, siginfo_t *si, void *data) +{ + ucontext_t *uc = (ucontext_t *)data; + + if (should_fail) { + should_fail_count++; + } else { + uintptr_t pc = (uintptr_t) uc->uc_mcontext.pc; + failed_pc[should_not_fail_count++] = pc; + } + uc->uc_mcontext.pc += 4; +} + +int main(void) +{ + struct sigaction sa; + + /* Hook in a SIGILL handler */ + memset(&sa, 0, sizeof(struct sigaction)); + sa.sa_flags = SA_SIGINFO; + sa.sa_sigaction = &sigill_handler; + sigemptyset(&sa.sa_mask); + + if (sigaction(SIGILL, &sa, 0) != 0) { + perror("sigaction"); + return 1; + } + + /* since 4.12 */ + printf("Checking CNT registers\n"); + + get_cpu_reg(ctr_el0); + get_cpu_reg(cntvct_el0); + get_cpu_reg(cntfrq_el0); + + /* when (getauxval(AT_HWCAP) & HWCAP_CPUID), since 4.11*/ + if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { + printf("CPUID registers unavailable\n"); + return 1; + } else { + printf("Checking CPUID registers\n"); + } + + get_cpu_reg(id_aa64isar0_el1); + get_cpu_reg(id_aa64isar1_el1); + get_cpu_reg(id_aa64mmfr0_el1); + get_cpu_reg(id_aa64mmfr1_el1); + get_cpu_reg(id_aa64pfr0_el1); + get_cpu_reg(id_aa64pfr1_el1); + get_cpu_reg(id_aa64dfr0_el1); + get_cpu_reg(id_aa64dfr1_el1); + + get_cpu_reg(midr_el1); + get_cpu_reg(mpidr_el1); + get_cpu_reg(revidr_el1); + + printf("Remaining registers should fail\n"); + should_fail = true; + + /* Unexposed register access causes SIGILL */ + get_cpu_reg(id_mmfr0_el1); + + if (should_not_fail_count > 0) { + int i; + for (i = 0; i < should_not_fail_count; i++) { + uintptr_t pc = failed_pc[i]; + uint32_t insn = *(uint32_t *) pc; + printf("insn %#x @ %#lx unexpected FAIL\n", insn, pc); + } + return 1; + } + + return should_fail_count == 1 ? 0 : 1; +}