From patchwork Mon May 10 14:15:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 433265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4A9DC43461 for ; Mon, 10 May 2021 14:55:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B485661492 for ; Mon, 10 May 2021 14:55:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241085AbhEJO4K (ORCPT ); Mon, 10 May 2021 10:56:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241136AbhEJOzZ (ORCPT ); Mon, 10 May 2021 10:55:25 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C073EC046851 for ; Mon, 10 May 2021 07:15:15 -0700 (PDT) Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1lg6gg-0000Fk-4u; Mon, 10 May 2021 16:15:10 +0200 From: Lucas Stach To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Richard Zhu Cc: NXP Linux Team , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH 1/7] PCI: imx6: Move i.MX8MQ controller instance check to correct case statement Date: Mon, 10 May 2021 16:15:03 +0200 Message-Id: <20210510141509.929120-1-l.stach@pengutronix.de> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org While the i.MX8MQ case falls through to the i.MX7D case, it's quite confusing to have the i.MX8MQ specific controller instance check in that statement. Move it to the 8MQ case. Signed-off-by: Lucas Stach --- drivers/pci/controller/dwc/pci-imx6.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 0cf1333c0440..46b5f070939e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1060,11 +1060,11 @@ static int imx6_pcie_probe(struct platform_device *pdev) if (IS_ERR(imx6_pcie->pcie_aux)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), "pcie_aux clock source missing or invalid\n"); - fallthrough; - case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) imx6_pcie->controller_id = 1; + fallthrough; + case IMX7D: imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); if (IS_ERR(imx6_pcie->pciephy_reset)) { From patchwork Mon May 10 14:15:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 433264 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 495A0C43470 for ; Mon, 10 May 2021 14:55:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 25AE761421 for ; Mon, 10 May 2021 14:55:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237999AbhEJO4N (ORCPT ); Mon, 10 May 2021 10:56:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241706AbhEJOz0 (ORCPT ); Mon, 10 May 2021 10:55:26 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88F59C046855 for ; Mon, 10 May 2021 07:15:17 -0700 (PDT) Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1lg6gi-0000Fk-4j; Mon, 10 May 2021 16:15:12 +0200 From: Lucas Stach To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Richard Zhu Cc: NXP Linux Team , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH 5/7] PCI: imx6: Configure PHY refclock according to DT property Date: Mon, 10 May 2021 16:15:07 +0200 Message-Id: <20210510141509.929120-5-l.stach@pengutronix.de> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210510141509.929120-1-l.stach@pengutronix.de> References: <20210510141509.929120-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This configures the PHY reference clock input according to the newly introduced fsl,refclk-pad-mode DT property. The default in absence of this property is to use the refclk pad on i.MX8MQ and the internal reference clock on all other SoCs, keeping compatibility with existing devicetrees, but allowing boards to configure this when they differ from the default. Signed-off-by: Lucas Stach --- drivers/pci/controller/dwc/pci-imx6.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 5e13758222e8..f184077f6d17 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -79,6 +79,7 @@ struct imx6_pcie { u32 tx_deemph_gen2_6db; u32 tx_swing_full; u32 tx_swing_low; + u32 refclk_pad_mode; struct regulator *vpcie; void __iomem *phy_base; @@ -613,18 +614,17 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) { switch (imx6_pcie->drvdata->variant) { case IMX8MQ: - /* - * TODO: Currently this code assumes external - * oscillator is being used - */ regmap_update_bits(imx6_pcie->iomuxc_gpr, imx6_pcie_grp_offset(imx6_pcie), IMX8MQ_GPR_PCIE_REF_USE_PAD, - IMX8MQ_GPR_PCIE_REF_USE_PAD); + imx6_pcie->refclk_pad_mode == 1 ? + IMX8MQ_GPR_PCIE_REF_USE_PAD : 0); break; case IMX7D: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, + imx6_pcie->refclk_pad_mode == 1 ? + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL : 0); break; case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, @@ -1049,6 +1049,12 @@ static int imx6_pcie_probe(struct platform_device *pdev) "pcie_inbound_axi clock missing or invalid\n"); break; case IMX8MQ: + /* + * i.MX8MQ is special, as the default refclk pad mode is set to + * input in order to keep compatibility with old devicetrees. + */ + imx6_pcie->refclk_pad_mode = 1; + imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); if (IS_ERR(imx6_pcie->pcie_aux)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), @@ -1114,6 +1120,10 @@ static int imx6_pcie_probe(struct platform_device *pdev) &imx6_pcie->tx_swing_low)) imx6_pcie->tx_swing_low = 127; + /* get PHY refclk pad mode */ + of_property_read_u32(node, "fsl,refclk-pad-mode", + &imx6_pcie->refclk_pad_mode); + /* Limit link speed */ pci->link_gen = 1; ret = of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); From patchwork Mon May 10 14:15:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 433263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A7B2C43603 for ; Mon, 10 May 2021 14:55:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F150761493 for ; Mon, 10 May 2021 14:55:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343582AbhEJO4P (ORCPT ); Mon, 10 May 2021 10:56:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240362AbhEJOz1 (ORCPT ); Mon, 10 May 2021 10:55:27 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E61E1C04685A for ; Mon, 10 May 2021 07:15:17 -0700 (PDT) Received: from dude03.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::39]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1lg6gj-0000Fk-4j; Mon, 10 May 2021 16:15:13 +0200 From: Lucas Stach To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Richard Zhu Cc: NXP Linux Team , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH 7/7] PCI: imx6: Add i.MX8MM support Date: Mon, 10 May 2021 16:15:09 +0200 Message-Id: <20210510141509.929120-7-l.stach@pengutronix.de> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210510141509.929120-1-l.stach@pengutronix.de> References: <20210510141509.929120-1-l.stach@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org i.MX8MM PCIe works mostly like the i.MX8MQ one, but has a different PHY and allows to output the internal PHY reference clock via the refclk pad. Based on work in the downstream kernel by Richard Zhu. Signed-off-by: Lucas Stach --- drivers/pci/controller/dwc/pci-imx6.c | 105 +++++++++++++++++++++++++- 1 file changed, 102 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index f184077f6d17..1f3e806ade64 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -40,6 +40,14 @@ #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 +#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24) +#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3) +#define IMX8MM_GPR_PCIE_REF_CLK_EXT FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x2) +#define IMX8MM_GPR_PCIE_AUX_EN BIT(19) +#define IMX8MM_GPR_PCIE_CMN_RST BIT(18) +#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) +#define IMX8MM_GPR_PCIE_SSC_EN BIT(16) + #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) enum imx6_pcie_variants { @@ -48,6 +56,7 @@ enum imx6_pcie_variants { IMX6QP, IMX7D, IMX8MQ, + IMX8MM, }; #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) @@ -138,6 +147,17 @@ struct imx6_pcie { #define PCIE_PHY_CMN_REG26 0x98 #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC +#define PCIE_PHY_CMN_REG62 0x188 +#define PCIE_PHY_CMN_REG62_PLL_CLK_OUT BIT(3) +#define PCIE_PHY_CMN_REG64 0x190 +#define PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM 0x8C +#define PCIE_PHY_CMN_REG75 0x1D4 +#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3 +#define PCIE_PHY_TRSV_REG5 0x414 +#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D +#define PCIE_PHY_TRSV_REG6 0x418 +#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF + #define PHY_RX_OVRD_IN_LO 0x1005 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) @@ -370,6 +390,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) switch (imx6_pcie->drvdata->variant) { case IMX7D: case IMX8MQ: + case IMX8MM: reset_control_assert(imx6_pcie->pciephy_reset); reset_control_assert(imx6_pcie->apps_reset); break; @@ -406,7 +427,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) { - WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ); + WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && + imx6_pcie->drvdata->variant != IMX8MM); return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; } @@ -446,6 +468,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) case IMX7D: break; case IMX8MQ: + case IMX8MM: ret = clk_prepare_enable(imx6_pcie->pcie_aux); if (ret) { dev_err(dev, "unable to enable pcie_aux clock\n"); @@ -482,6 +505,19 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) dev_err(dev, "PCIe PLL lock timeout\n"); } +static void imx8mm_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) +{ + struct device *dev = imx6_pcie->pci->dev; + int ret; + u32 val; + + ret = readl_poll_timeout(imx6_pcie->phy_base + PCIE_PHY_CMN_REG75, + val, val == PCIE_PHY_CMN_REG75_PLL_DONE, + 10, 20000); + if (ret) + dev_err(dev, "PCIe PLL lock timeout\n"); +} + static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) { struct dw_pcie *pci = imx6_pcie->pci; @@ -537,6 +573,10 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) case IMX8MQ: reset_control_deassert(imx6_pcie->pciephy_reset); break; + case IMX8MM: + reset_control_deassert(imx6_pcie->pciephy_reset); + imx8mm_pcie_wait_for_phy_pll_lock(imx6_pcie); + break; case IMX7D: reset_control_deassert(imx6_pcie->pciephy_reset); @@ -613,6 +653,47 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) { switch (imx6_pcie->drvdata->variant) { + case IMX8MM: + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR14, + IMX8MQ_GPR_PCIE_REF_USE_PAD, + imx6_pcie->refclk_pad_mode == 1 ? + IMX8MQ_GPR_PCIE_REF_USE_PAD :0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_AUX_EN, + IMX8MM_GPR_PCIE_AUX_EN); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_POWER_OFF, 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_SSC_EN, 0); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_REF_CLK_SEL, + imx6_pcie->refclk_pad_mode == 1 ? + IMX8MM_GPR_PCIE_REF_CLK_EXT : + IMX8MM_GPR_PCIE_REF_CLK_PLL); + + usleep_range(100, 200); + + if (imx6_pcie->refclk_pad_mode == 2) { + /* Configure the PHY to output the refclock via pad */ + writel(PCIE_PHY_CMN_REG62_PLL_CLK_OUT, + imx6_pcie->phy_base + PCIE_PHY_CMN_REG62); + writel(PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM, + imx6_pcie->phy_base + PCIE_PHY_CMN_REG64); + } + + /* Do the PHY common block reset */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_CMN_RST, + IMX8MM_GPR_PCIE_CMN_RST); + usleep_range(200, 500); + + /* Tune PHY de-emphasis setting to pass PCIe compliance. */ + writel(PCIE_PHY_TRSV_REG5_GEN1_DEEMP, + imx6_pcie->phy_base + PCIE_PHY_TRSV_REG5); + writel(PCIE_PHY_TRSV_REG6_GEN2_DEEMP, + imx6_pcie->phy_base + PCIE_PHY_TRSV_REG6); + break; case IMX8MQ: regmap_update_bits(imx6_pcie->iomuxc_gpr, imx6_pcie_grp_offset(imx6_pcie), @@ -740,6 +821,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev) break; case IMX7D: case IMX8MQ: + case IMX8MM: reset_control_deassert(imx6_pcie->apps_reset); break; } @@ -858,6 +940,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev) IMX6Q_GPR12_PCIE_CTL_2, 0); break; case IMX7D: + case IMX8MM: reset_control_assert(imx6_pcie->apps_reset); break; default: @@ -917,6 +1000,7 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); break; case IMX8MQ: + case IMX8MM: clk_disable_unprepare(imx6_pcie->pcie_aux); break; default: @@ -991,8 +1075,17 @@ static int imx6_pcie_probe(struct platform_device *pdev) imx6_pcie->pci = pci; imx6_pcie->drvdata = of_device_get_match_data(dev); - /* Find the PHY if one is present in DT, only imx7d uses it */ - np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-pcie-phy"); + /* Find the PHY if one is present in DT */ + switch (imx6_pcie->drvdata->variant) { + case IMX7D: + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-pcie-phy"); + break; + case IMX8MM: + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-pcie-phy"); + break; + default: + break; + } if (np) { imx6_pcie->phy_base = devm_of_iomap(dev, np, 0, NULL); if (IS_ERR(imx6_pcie->phy_base)) { @@ -1055,6 +1148,8 @@ static int imx6_pcie_probe(struct platform_device *pdev) */ imx6_pcie->refclk_pad_mode = 1; + fallthrough; + case IMX8MM: imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); if (IS_ERR(imx6_pcie->pcie_aux)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), @@ -1188,6 +1283,9 @@ static const struct imx6_pcie_drvdata drvdata[] = { [IMX8MQ] = { .variant = IMX8MQ, }, + [IMX8MM] = { + .variant = IMX8MM, + }, }; static const struct of_device_id imx6_pcie_of_match[] = { @@ -1196,6 +1294,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } , + { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], } , {}, };