From patchwork Sat May 8 00:28:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03B0DC43460 for ; Sat, 8 May 2021 00:29:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D1A896145D for ; Sat, 8 May 2021 00:29:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230197AbhEHAaW (ORCPT ); Fri, 7 May 2021 20:30:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229812AbhEHAaV (ORCPT ); Fri, 7 May 2021 20:30:21 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6ED2C061574; Fri, 7 May 2021 17:29:19 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id s5-20020a7bc0c50000b0290147d0c21c51so5750717wmh.4; Fri, 07 May 2021 17:29:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Zzb7lt9+x9O2s44k4kSu1lzOPp+x1XlcNqKjooCHFzg=; b=s0BGHi3g9S7i92EBWHhs/u7b07WHcJYAaSjPWTS2I+9CBuWQ6iSCRMBTVp8AZw6sMt A0q6LqdHBxh7hUSIFz9Np6HdKI6+QwFsozgPHOhYSC1y3PcuGDL7TrXT6AoiLp8T9F8N S8faMkOxWx+nNCh0j6/P5uf5YJUVBj6+aNtPDJEN5jkhwriXvNk+cD188uvUYsuF3TCV h5IEOKlTW2ZeV5Z0ndkn9bl2Y7AOIcG5As7mZG0b/YXZeKFFzwRW5ibfTE2S77QMhvRB vq5gxfukb4Q7UBLBGh3PqXBlohAPbnsNonc+iJ0wsMM/Um+8gdJvc+gpJ0iEofXXXA65 AIbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Zzb7lt9+x9O2s44k4kSu1lzOPp+x1XlcNqKjooCHFzg=; b=SlLnrh65Hr9xlow6/Tv2JIQ0TArLinzQ3nTId1HVmBJRZ34vB+NHvrtnrbMSeXVPMl o2uAZ116HdhS1v9AiktnF+S/wE0XfFos1RmC4pQjI8K37lbNYwCpegHKp17fLJD3Q4PX lviJ73oLpdtY9KgcdVuTIK2SYc/tVT20EuRnZj4efu8oy9gdXSPOC/OJOpJp/5/mvBdw R7b9BaDaa9kKRLXIw29RpOVYaWko8g4GGlGBwpOBoRf2oS8RRLYkO1n1e08RgiOwfJ/S 5Yfr2snBRVKjEl/8klgSifIogbc0e6FD/JYdrNmAu3CfaMcAHx+zen06aiOTqQLZtYZ6 LBdA== X-Gm-Message-State: AOAM533GBWDZlyA2or/RY3TH8aT3hRi0xrl2oQz4oOU33Y61KcveDjfl /2PcsQDrvuPUYEEbgeBEnN0= X-Google-Smtp-Source: ABdhPJwGGbtKbVOUb99QhM7IxRgzszX/N68JVA8x41GPfbF0L3O8s7BNaObPJPmCbDuKjMZ+8Y0HLA== X-Received: by 2002:a7b:c94b:: with SMTP id i11mr1481097wml.120.1620433758489; Fri, 07 May 2021 17:29:18 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:18 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 01/28] net: mdio: ipq8064: clean whitespaces in define Date: Sat, 8 May 2021 02:28:51 +0200 Message-Id: <20210508002920.19945-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Fix mixed whitespace and tab for define spacing. Signed-off-by: Ansuel Smith Reviewed-by: Andrew Lunn Reviewed-by: Florian Fainelli Reviewed-by: Florian Fainelli --- drivers/net/mdio/mdio-ipq8064.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq8064.c b/drivers/net/mdio/mdio-ipq8064.c index 1bd18857e1c5..fb1614242e13 100644 --- a/drivers/net/mdio/mdio-ipq8064.c +++ b/drivers/net/mdio/mdio-ipq8064.c @@ -15,25 +15,26 @@ #include /* MII address register definitions */ -#define MII_ADDR_REG_ADDR 0x10 -#define MII_BUSY BIT(0) -#define MII_WRITE BIT(1) -#define MII_CLKRANGE_60_100M (0 << 2) -#define MII_CLKRANGE_100_150M (1 << 2) -#define MII_CLKRANGE_20_35M (2 << 2) -#define MII_CLKRANGE_35_60M (3 << 2) -#define MII_CLKRANGE_150_250M (4 << 2) -#define MII_CLKRANGE_250_300M (5 << 2) +#define MII_ADDR_REG_ADDR 0x10 +#define MII_BUSY BIT(0) +#define MII_WRITE BIT(1) +#define MII_CLKRANGE(x) ((x) << 2) +#define MII_CLKRANGE_60_100M MII_CLKRANGE(0) +#define MII_CLKRANGE_100_150M MII_CLKRANGE(1) +#define MII_CLKRANGE_20_35M MII_CLKRANGE(2) +#define MII_CLKRANGE_35_60M MII_CLKRANGE(3) +#define MII_CLKRANGE_150_250M MII_CLKRANGE(4) +#define MII_CLKRANGE_250_300M MII_CLKRANGE(5) #define MII_CLKRANGE_MASK GENMASK(4, 2) #define MII_REG_SHIFT 6 #define MII_REG_MASK GENMASK(10, 6) #define MII_ADDR_SHIFT 11 #define MII_ADDR_MASK GENMASK(15, 11) -#define MII_DATA_REG_ADDR 0x14 +#define MII_DATA_REG_ADDR 0x14 -#define MII_MDIO_DELAY_USEC (1000) -#define MII_MDIO_RETRY_MSEC (10) +#define MII_MDIO_DELAY_USEC (1000) +#define MII_MDIO_RETRY_MSEC (10) struct ipq8064_mdio { struct regmap *base; /* NSS_GMAC0_BASE */ From patchwork Sat May 8 00:28:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 433007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C897C43461 for ; Sat, 8 May 2021 00:29:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E1C1D60FF3 for ; Sat, 8 May 2021 00:29:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230235AbhEHAaX (ORCPT ); Fri, 7 May 2021 20:30:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229880AbhEHAaV (ORCPT ); Fri, 7 May 2021 20:30:21 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4157C061761; Fri, 7 May 2021 17:29:20 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id l14so10864011wrx.5; Fri, 07 May 2021 17:29:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IMGJC3f9H4OYqX3wBCM/mk0stFuB1KlCyCQlxa9ipnI=; b=rU36FNZN3Zp5VlSKeF9MX+GnfOslaMi7mHa9PKHXup7J+yzH+7rB6wMBT1BKKwusdb LBfeBwAEE9dwdHM2/gDVDN8+fpIEA3aRRxKP0AKMX7HmRKAhBDFZB3slXPu8CRVtdfFK GBW4nF0smoMKtyqSiymNPKJKpbuobBF5Ck//+IXshVbRQwYuD7Eg5HUBJBCdNNhaIbKD ozMTpP7TFC+X3wSQCrtiwYb36jvhwBcQcS4CUHiRwWKEK2cAcBqHilzNqhjfpPsDLT2n EVst/2CKvgBFJrJtr0AkfTqPmu80Ok2w0hOhA4Jp/Rewfta6+dGGZg0Ord9cq6r6BTfe N9+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IMGJC3f9H4OYqX3wBCM/mk0stFuB1KlCyCQlxa9ipnI=; b=lwrf8BPjM+XTK2ou5MzA2+N6Mqcfa1iI00eK2v2Ay7F2SS01y094zRQa8Z3vCeuW1t BQyOvi5vl5Oi3kjsN3/E/KSf9Q13HI7mxhqON5Q9S9yH0gqjVp6DRNgy4Otg5mMYrxeV 2O69In5qRoI6mCp38H+pv94BfNw73xvGkvZSSdcorbDFl/Gh1JS9OmYX3UcFHa86/Xm6 OaTP6t4nF+De7QjGIabs092jprF8etWKFCCpEtqPVKzAUc4CU4YyHxVTB5D/8Dbmnktg 63+5F7RteyobI1+NgU32qP/88HuYfyuRn/AwxFGVs4xxk30LRTXcZa4baSJSnzF7yU2I u7Gw== X-Gm-Message-State: AOAM5307mq/SAuUYU6/mhs6pVWpdlqPcL4z1yDowqbuQRtnv1+RqRW08 +KR5XgSBoUrPSdgOA6yMZbA= X-Google-Smtp-Source: ABdhPJwpGV9HWrc3IDQcUMUrJ8jFL5VcJzCj/ChKs6AR8W4iw6RM1KBIKh4jNI1jqK9xjtZt8dcbYw== X-Received: by 2002:adf:e9c2:: with SMTP id l2mr15340147wrn.323.1620433759454; Fri, 07 May 2021 17:29:19 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:19 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 02/28] net: mdio: ipq8064: add regmap config to disable REGCACHE Date: Sat, 8 May 2021 02:28:52 +0200 Message-Id: <20210508002920.19945-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org mdio drivers should not use REGCHACHE. Also disable locking since it's handled by the mdio users and regmap is always accessed atomically. Signed-off-by: Ansuel Smith --- drivers/net/mdio/mdio-ipq8064.c | 34 +++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq8064.c b/drivers/net/mdio/mdio-ipq8064.c index fb1614242e13..9862745d1cee 100644 --- a/drivers/net/mdio/mdio-ipq8064.c +++ b/drivers/net/mdio/mdio-ipq8064.c @@ -10,9 +10,8 @@ #include #include #include -#include +#include #include -#include /* MII address register definitions */ #define MII_ADDR_REG_ADDR 0x10 @@ -97,14 +96,34 @@ ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data) return ipq8064_mdio_wait_busy(priv); } +static const struct regmap_config ipq8064_mdio_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .can_multi_write = false, + /* the mdio lock is used by any user of this mdio driver */ + .disable_locking = true, + + .cache_type = REGCACHE_NONE, +}; + static int ipq8064_mdio_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct ipq8064_mdio *priv; + struct resource res; struct mii_bus *bus; + void __iomem *base; int ret; + if (of_address_to_resource(np, 0, &res)) + return -ENOMEM; + + base = ioremap(res.start, resource_size(&res)); + if (!base) + return -ENOMEM; + bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv)); if (!bus) return -ENOMEM; @@ -116,15 +135,10 @@ ipq8064_mdio_probe(struct platform_device *pdev) bus->parent = &pdev->dev; priv = bus->priv; - priv->base = device_node_to_regmap(np); - if (IS_ERR(priv->base)) { - if (priv->base == ERR_PTR(-EPROBE_DEFER)) - return -EPROBE_DEFER; - - dev_err(&pdev->dev, "error getting device regmap, error=%pe\n", - priv->base); + priv->base = devm_regmap_init_mmio(&pdev->dev, base, + &ipq8064_mdio_regmap_config); + if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - } ret = of_mdiobus_register(bus, np); if (ret) From patchwork Sat May 8 00:28:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 433006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54DC2C433B4 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:20 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 03/28] net: mdio: ipq8064: enlarge sleep after read/write operation Date: Sat, 8 May 2021 02:28:53 +0200 Message-Id: <20210508002920.19945-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org With the use of the qca8k dsa driver, some problem arised related to port status detection. With a load on a specific port (for example a simple speed test), the driver starts to behave in a strange way and garbage data is produced. To address this, enlarge the sleep delay and address a bug for the reg offset 31 that require additional delay for this specific reg. Signed-off-by: Ansuel Smith --- drivers/net/mdio/mdio-ipq8064.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq8064.c b/drivers/net/mdio/mdio-ipq8064.c index 9862745d1cee..a3f7f9de12b6 100644 --- a/drivers/net/mdio/mdio-ipq8064.c +++ b/drivers/net/mdio/mdio-ipq8064.c @@ -65,7 +65,7 @@ ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset) ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); - usleep_range(8, 10); + usleep_range(10, 13); err = ipq8064_mdio_wait_busy(priv); if (err) @@ -91,7 +91,14 @@ ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data) ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); - usleep_range(8, 10); + + /* For the specific reg 31 extra time is needed or the next + * read will produce garbage data. + */ + if (reg_offset == 31) + usleep_range(30, 43); + else + usleep_range(10, 13); return ipq8064_mdio_wait_busy(priv); } From patchwork Sat May 8 00:28:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FB49C43461 for ; Sat, 8 May 2021 00:29:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 50EF56145D for ; Sat, 8 May 2021 00:29:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230334AbhEHAa2 (ORCPT ); Fri, 7 May 2021 20:30:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230301AbhEHAaY (ORCPT ); Fri, 7 May 2021 20:30:24 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EED2FC061574; Fri, 7 May 2021 17:29:22 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id d11so10860530wrw.8; Fri, 07 May 2021 17:29:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7bk6dC/RhqBa/IIFsr+kb2YvIfeYb74QE7Ww5BRo2TY=; b=uyOW/b8QBjOw8OA1vNp/uR0EL2l+xxP33Cqrq0nxg9eGeHFv7dAhBM7M6dIMwbMYAJ MdK9JsykBlj8L9qeaathmaQe5Jnwgk0hqhSGXFR7/s9g0eYjZMuPzSYvNQtBWEoDrAgn WCIV5F3ocr5VF+MQuR+lYz7D18KMsV4v9VO8nO+2jcToLU7c4CpJWfKkdPnwv2H4HpRP EMhzr+uGR95VmGGB+XAB/U7K7sFxxD6GPlU1PwhYWf7pxLZYjN6mEeLfsDVE0uefBP3Q UEWqhfgeH28r4nWMeF8RlfESOU1qTSMiVjMwlo6OskEKYnJZ24tTvmWTGj2MIjpQc4bq Qffw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7bk6dC/RhqBa/IIFsr+kb2YvIfeYb74QE7Ww5BRo2TY=; b=pJOHTaeJ8KaYsEg7we5d5N1ULwUMYw56nNnkw4nb8X0ItjLgIlS6gPQHGTSucczR3T WjUk4pgVfu+MpnBSBnnzjsQ58/3EpkXUtx8aKiohwzGIlMyUG9hQa+Q1XYYk9LZggqcb 4Cb/CdnltI1DHoDn5n1TCSSqIW7r9N33Xh0NT50BsqHYSJoqPed9aDUEYdtBcu+ptjxf 0C6AKazhckHEKN9tGOuoZqiitmNPa99khrR7dWPRICDVttcdT67ZNz0HCcobBIWu/qYd boObvAg9f5XFODxk9XcFXZegwXadvu3+lUMxPrHIuDO0D6yc60LNg+JZYU1TT0Y0X6U1 8KjQ== X-Gm-Message-State: AOAM533ajG3MtxYPBLMzxzjm/FK+r4LE9aIsagtyqHhGe6a76iP5D78h ZKh6wkTI7hRdhxjHQOWGKiU= X-Google-Smtp-Source: ABdhPJzUVLPq3wTfAMJuclxNm6eharoZw9hAXbNdlFDPjujU4cTQt5vanFMGq+ay73Q3ICd/gLtkEA== X-Received: by 2002:a5d:5047:: with SMTP id h7mr15661690wrt.287.1620433761674; Fri, 07 May 2021 17:29:21 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:21 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 04/28] net: dsa: qca8k: change simple print to dev variant Date: Sat, 8 May 2021 02:28:54 +0200 Message-Id: <20210508002920.19945-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Change pr_err and pr_warn to dev variant. Signed-off-by: Ansuel Smith Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca8k.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index cdaf9f85a2cb..0b295da6c356 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -701,7 +701,7 @@ qca8k_setup(struct dsa_switch *ds) /* Make sure that port 0 is the cpu port */ if (!dsa_is_cpu_port(ds, 0)) { - pr_err("port 0 is not the CPU port\n"); + dev_err(priv->dev, "port 0 is not the CPU port"); return -EINVAL; } @@ -711,7 +711,7 @@ qca8k_setup(struct dsa_switch *ds) priv->regmap = devm_regmap_init(ds->dev, NULL, priv, &qca8k_regmap_config); if (IS_ERR(priv->regmap)) - pr_warn("regmap initialization failed"); + dev_warn(priv->dev, "regmap initialization failed"); ret = qca8k_setup_mdio_bus(priv); if (ret) From patchwork Sat May 8 00:28:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 433005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C4EBC43470 for ; Sat, 8 May 2021 00:29:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6F83061451 for ; Sat, 8 May 2021 00:29:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230373AbhEHAab (ORCPT ); Fri, 7 May 2021 20:30:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230306AbhEHAaY (ORCPT ); Fri, 7 May 2021 20:30:24 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39827C061761; Fri, 7 May 2021 17:29:24 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id o127so6101775wmo.4; Fri, 07 May 2021 17:29:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2QCVXYSj9SYA6gAv2qNpAxSSXr1KuYSPUFWzE5IhrRM=; b=B/ZWVHYw5pZcAbi1RwkJgtU7cz+XXiVgcjOGEfJ1Ey3QmI1NI+Zq+yiHUNspTeKWFG PmcW60YIPe8sRjrC9gponmLw6jDwdXvbkaHvM144skr58JV1YQL1WTFm85Q841tRttcf zvH5QXLh+HNcjWajj34vHLCyVU1wk6IS2ioCoap9m65YfjCs6K5GoCKUBgkd9mfRSErL uVwgV+ysLeeJuyy+j9grlGjtUYzUrFJ5+PdrFYr5mT323SJ8rLmuixbSJWFXKJbSuztz DPG+nO3o1MzBxucjJbNO43LbGjQYRDgFGqPv4LaTP9S1DBK2cYdMePVS/tfVZh3zXd5b i5XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2QCVXYSj9SYA6gAv2qNpAxSSXr1KuYSPUFWzE5IhrRM=; b=rmxvkdzzgcxKBkBlA1/dQdpfwq3wu1dmoStG+Hz+95g3lvWWahVU4jlfrQBBW7icY9 BS8yeEOmenNHO6PAgnFwOctDEDmPl3xpB+db99FyFytBjUL558ZVlTjY5/iuI/C3TWTP Ud0fVR4C2RnKF959hrh8aJdTgtmGPO8x+K7vBC9CySaivPMRp0//Cw/SQCbr36xe72Il vM7IpZ7eSBTS7K7YkcsCDgaHhUUoGiY1ZlSHB1R3Q26OAjf9jY4cQMtC4COrtF9ZTyTN 56fk6n0LcjvEW+Wy97Xah/Be6c8wpwjzo/NAI6ULLETBUUIom4sWVi7/YMLWZmYts9RJ Oe9w== X-Gm-Message-State: AOAM533pcCX8dkMwtfPJj63pTvQ5+36s+xfKsDyWCqbph4nYqbeD5mAq jThrqw7Hl+CLPV1J7R5peAR+oM7/s30wCQ== X-Google-Smtp-Source: ABdhPJzrxkYUUuAIg33RbQF0Q8mQt4FtY97J1yWc8I1Q17ChZqVVYGZWIpYzjCzjz6IjFQJytHzq8g== X-Received: by 2002:a1c:f705:: with SMTP id v5mr22465708wmh.69.1620433762899; Fri, 07 May 2021 17:29:22 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:22 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 05/28] net: dsa: qca8k: use iopoll macro for qca8k_busy_wait Date: Sat, 8 May 2021 02:28:55 +0200 Message-Id: <20210508002920.19945-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Use iopoll macro instead of while loop. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 23 +++++++++++------------ drivers/net/dsa/qca8k.h | 2 ++ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 0b295da6c356..0bfb7ae4c128 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -262,21 +262,20 @@ static struct regmap_config qca8k_regmap_config = { static int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) { - unsigned long timeout; - - timeout = jiffies + msecs_to_jiffies(20); + u32 val; + int ret; - /* loop until the busy flag has cleared */ - do { - u32 val = qca8k_read(priv, reg); - int busy = val & mask; + ret = read_poll_timeout(qca8k_read, val, !(val & mask), + 0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, + priv, reg); - if (!busy) - break; - cond_resched(); - } while (!time_after_eq(jiffies, timeout)); + /* Check if qca8k_read has failed for a different reason + * before returnting -ETIMEDOUT + */ + if (ret < 0 && val < 0) + return val; - return time_after_eq(jiffies, timeout); + return ret; } static void diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 7ca4b93e0bb5..86c585b7ec4a 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -18,6 +18,8 @@ #define PHY_ID_QCA8337 0x004dd036 #define QCA8K_ID_QCA8337 0x13 +#define QCA8K_BUSY_WAIT_TIMEOUT 20 + #define QCA8K_NUM_FDB_RECORDS 2048 #define QCA8K_CPU_PORT 0 From patchwork Sat May 8 00:28:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0916C433ED for ; Sat, 8 May 2021 00:29:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 97FBA6113E for ; Sat, 8 May 2021 00:29:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230398AbhEHAad (ORCPT ); Fri, 7 May 2021 20:30:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230324AbhEHAa0 (ORCPT ); Fri, 7 May 2021 20:30:26 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45EB1C061574; Fri, 7 May 2021 17:29:25 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id v12so10848590wrq.6; Fri, 07 May 2021 17:29:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z9wCRjYirG2CaGU6+kOVn0TlYvq1oqjexUwBHWJt75s=; b=q2PnkNSsoi7TSeENWe+Ou9vfHs3gdi5kY9cvEAWtSKoAfX39LRxfJjEkb4DPhBVVIC u7/omJueeZbt/0BTogCfPhzdDfEFaeOHJaFMU853tigyllX/RZUB5+dnjyn54hCDYLvc uh6BTgbrKN7CEJDeStIbbsLoSNfLgqaI+8wLA9SL+uMxbvOrX0p9qW37RRDR0zsCbhcl LOQpd13HH0bpTIAmqqTg+lJN5iVXLyOeIQMWozZI4C77FpMS60BCAxqapAX6jpv2li7J F5emNlXLe1QYqye2W2obXvnpdgA5XtheTiMSNDx2B8FI68M73Qt8Tf/SIZGL5zkm25F3 JDqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z9wCRjYirG2CaGU6+kOVn0TlYvq1oqjexUwBHWJt75s=; b=e+T7da3VEch8RXlxy+3zmwUNGgHdX8AIy8566SzQpGefUEo8VDttqh9G5OGTN6tBef tuY7pNko3tnTbMPr8STPeRPZQ6cc1qlk1jLFIT5VTZtMMx+o3qwmJrTgAGg4KWniJi82 bXkHxE9cO7opkIjodobOEFgt2qSIzf+baRuocZ4R4lr03IZR/atyY775/07uYsvM7IWy wbtqjU/vjw8h8TSA+fA4aNyZtoWLZdZu848imDL8SRDAHM6FKPSicWhr/YNoRDekk7Hu oEWdzuE5LIylu0MMq1VhdmqTR2Y62rAfjSxH3UF3sUqtIEsBEWXhlAZYwCCN10P4tEji fXoQ== X-Gm-Message-State: AOAM532J6wqumDOgn474u2+jpOTUpQBUjwjS8tf3CZ/yfA7A6ced7mOn fIpaFcQrEQzipnBDX3TlTl8= X-Google-Smtp-Source: ABdhPJytE2aUU8Xb9aL4qL5aFQQ+lv6kndFg6TvNHyaG6rRtSNhBEeFGKVlxjMJoVO50QK7a8zoS0Q== X-Received: by 2002:adf:fb87:: with SMTP id a7mr15890359wrr.58.1620433763952; Fri, 07 May 2021 17:29:23 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:23 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 06/28] net: dsa: qca8k: improve qca8k read/write/rmw bus access Date: Sat, 8 May 2021 02:28:56 +0200 Message-Id: <20210508002920.19945-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Put bus in local variable to improve faster access to the mdio bus. Signed-off-by: Ansuel Smith Reviewed-by: Andrew Lunn --- drivers/net/dsa/qca8k.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 0bfb7ae4c128..f58d4543ef1e 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -142,17 +142,18 @@ qca8k_set_page(struct mii_bus *bus, u16 page) static u32 qca8k_read(struct qca8k_priv *priv, u32 reg) { + struct mii_bus *bus = priv->bus; u16 r1, r2, page; u32 val; qca8k_split_addr(reg, &r1, &r2, &page); - mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - qca8k_set_page(priv->bus, page); - val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); + qca8k_set_page(bus, page); + val = qca8k_mii_read32(bus, 0x10 | r2, r1); - mutex_unlock(&priv->bus->mdio_lock); + mutex_unlock(&bus->mdio_lock); return val; } @@ -160,35 +161,37 @@ qca8k_read(struct qca8k_priv *priv, u32 reg) static void qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) { + struct mii_bus *bus = priv->bus; u16 r1, r2, page; qca8k_split_addr(reg, &r1, &r2, &page); - mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - qca8k_set_page(priv->bus, page); - qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); + qca8k_set_page(bus, page); + qca8k_mii_write32(bus, 0x10 | r2, r1, val); - mutex_unlock(&priv->bus->mdio_lock); + mutex_unlock(&bus->mdio_lock); } static u32 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) { + struct mii_bus *bus = priv->bus; u16 r1, r2, page; u32 ret; qca8k_split_addr(reg, &r1, &r2, &page); - mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - qca8k_set_page(priv->bus, page); - ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); + qca8k_set_page(bus, page); + ret = qca8k_mii_read32(bus, 0x10 | r2, r1); ret &= ~mask; ret |= val; - qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret); + qca8k_mii_write32(bus, 0x10 | r2, r1, ret); - mutex_unlock(&priv->bus->mdio_lock); + mutex_unlock(&bus->mdio_lock); return ret; } From patchwork Sat May 8 00:28:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 433004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD1C3C43461 for ; Sat, 8 May 2021 00:29:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE47961468 for ; Sat, 8 May 2021 00:29:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230435AbhEHAag (ORCPT ); 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:24 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 07/28] net: dsa: qca8k: handle qca8k_set_page errors Date: Sat, 8 May 2021 02:28:57 +0200 Message-Id: <20210508002920.19945-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org With a remote possibility, the set_page function can fail. Since this is a critical part of the write/read qca8k regs, propagate the error and terminate any read/write operation. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index f58d4543ef1e..1c52d1b262f1 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -127,16 +127,23 @@ qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val) "failed to write qca8k 32bit register\n"); } -static void +static int qca8k_set_page(struct mii_bus *bus, u16 page) { + int ret; + if (page == qca8k_current_page) - return; + return 0; - if (bus->write(bus, 0x18, 0, page) < 0) + ret = bus->write(bus, 0x18, 0, page); + if (ret < 0) { dev_err_ratelimited(&bus->dev, "failed to set qca8k page\n"); + return ret; + } + qca8k_current_page = page; + return 0; } static u32 @@ -150,11 +157,14 @@ qca8k_read(struct qca8k_priv *priv, u32 reg) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - qca8k_set_page(bus, page); + val = qca8k_set_page(bus, page); + if (val < 0) + goto exit; + val = qca8k_mii_read32(bus, 0x10 | r2, r1); +exit: mutex_unlock(&bus->mdio_lock); - return val; } @@ -163,14 +173,19 @@ qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) { struct mii_bus *bus = priv->bus; u16 r1, r2, page; + int ret; qca8k_split_addr(reg, &r1, &r2, &page); mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - qca8k_set_page(bus, page); + ret = qca8k_set_page(bus, page); + if (ret < 0) + goto exit; + qca8k_mii_write32(bus, 0x10 | r2, r1, val); +exit: mutex_unlock(&bus->mdio_lock); } @@ -185,12 +200,16 @@ qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - qca8k_set_page(bus, page); + ret = qca8k_set_page(bus, page); + if (ret < 0) + goto exit; + ret = qca8k_mii_read32(bus, 0x10 | r2, r1); ret &= ~mask; ret |= val; qca8k_mii_write32(bus, 0x10 | r2, r1, ret); +exit: mutex_unlock(&bus->mdio_lock); return ret; From patchwork Sat May 8 00:28:58 2021 Content-Type: text/plain; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:26 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 08/28] net: dsa: qca8k: handle error with qca8k_read operation Date: Sat, 8 May 2021 02:28:58 +0200 Message-Id: <20210508002920.19945-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org qca8k_read can fail. Rework any user to handle error values and correctly return. Signed-off-by: Ansuel Smith Reviewed-by: Andrew Lunn --- drivers/net/dsa/qca8k.c | 76 +++++++++++++++++++++++++++++++++-------- 1 file changed, 61 insertions(+), 15 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 1c52d1b262f1..5087ee8ecebb 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -231,8 +231,13 @@ static int qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) { struct qca8k_priv *priv = (struct qca8k_priv *)ctx; + int ret; + + ret = qca8k_read(priv, reg); + if (ret < 0) + return ret; - *val = qca8k_read(priv, reg); + *val = ret; return 0; } @@ -300,15 +305,20 @@ qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) return ret; } -static void +static int qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) { - u32 reg[4]; + u32 reg[4], val; int i; /* load the ARL table into an array */ - for (i = 0; i < 4; i++) - reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4)); + for (i = 0; i < 4; i++) { + val = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4)); + if (val < 0) + return val; + + reg[i] = val; + } /* vid - 83:72 */ fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M; @@ -323,6 +333,8 @@ qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff; fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff; fdb->mac[5] = reg[0] & 0xff; + + return 0; } static void @@ -374,6 +386,8 @@ qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) /* Check for table full violation when adding an entry */ if (cmd == QCA8K_FDB_LOAD) { reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC); + if (reg < 0) + return reg; if (reg & QCA8K_ATU_FUNC_FULL) return -1; } @@ -384,12 +398,15 @@ qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) static int qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port) { - int ret; + int ret, ret_read; qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging); ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port); - if (ret >= 0) - qca8k_fdb_read(priv, fdb); + if (ret >= 0) { + ret_read = qca8k_fdb_read(priv, fdb); + if (ret_read < 0) + return ret_read; + } return ret; } @@ -449,6 +466,8 @@ qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) /* Check for table full violation when adding an entry */ if (cmd == QCA8K_VLAN_LOAD) { reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC1); + if (reg < 0) + return reg; if (reg & QCA8K_VTU_FUNC1_FULL) return -ENOMEM; } @@ -475,6 +494,8 @@ qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged) goto out; reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0); + if (reg < 0) + return reg; reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN; reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port)); if (untagged) @@ -506,6 +527,8 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) goto out; reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0); + if (reg < 0) + return reg; reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port)); reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_S(port); @@ -621,8 +644,11 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) QCA8K_MDIO_MASTER_BUSY)) return -ETIMEDOUT; - val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) & - QCA8K_MDIO_MASTER_DATA_MASK); + val = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL); + if (val < 0) + return val; + + val &= QCA8K_MDIO_MASTER_DATA_MASK; return val; } @@ -978,6 +1004,8 @@ qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port, u32 reg; reg = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port)); + if (reg < 0) + return reg; state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP); state->an_complete = state->link; @@ -1078,18 +1106,26 @@ qca8k_get_ethtool_stats(struct dsa_switch *ds, int port, { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; const struct qca8k_mib_desc *mib; - u32 reg, i; + u32 reg, i, val; u64 hi; for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) { mib = &ar8327_mib[i]; reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset; - data[i] = qca8k_read(priv, reg); + val = qca8k_read(priv, reg); + if (val < 0) + continue; + if (mib->size == 2) { hi = qca8k_read(priv, reg + 4); - data[i] |= hi << 32; + if (hi < 0) + continue; } + + data[i] = val; + if (mib->size == 2) + data[i] |= hi << 32; } } @@ -1107,18 +1143,25 @@ qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port); + int ret = 0; u32 reg; mutex_lock(&priv->reg_mutex); reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL); + if (reg < 0) { + ret = reg; + goto exit; + } + if (eee->eee_enabled) reg |= lpi_en; else reg &= ~lpi_en; qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); - mutex_unlock(&priv->reg_mutex); - return 0; +exit: + mutex_unlock(&priv->reg_mutex); + return ret; } static int @@ -1443,6 +1486,9 @@ qca8k_sw_probe(struct mdio_device *mdiodev) /* read the switches ID register */ id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); + if (id < 0) + return id; + id >>= QCA8K_MASK_CTRL_ID_S; id &= QCA8K_MASK_CTRL_ID_M; if (id != QCA8K_ID_QCA8337) From patchwork Sat May 8 00:28:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 433001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84763C433B4 for ; Sat, 8 May 2021 00:29:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6583B61057 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:27 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 09/28] net: dsa: qca8k: handle error with qca8k_write operation Date: Sat, 8 May 2021 02:28:59 +0200 Message-Id: <20210508002920.19945-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org qca8k_write can fail. Rework any user to handle error values and correctly return. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 103 ++++++++++++++++++++++++++-------------- 1 file changed, 68 insertions(+), 35 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 5087ee8ecebb..0ec95ef16143 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -168,7 +168,7 @@ qca8k_read(struct qca8k_priv *priv, u32 reg) return val; } -static void +static int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) { struct mii_bus *bus = priv->bus; @@ -187,6 +187,7 @@ qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) exit: mutex_unlock(&bus->mdio_lock); + return ret; } static u32 @@ -247,9 +248,7 @@ qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val) { struct qca8k_priv *priv = (struct qca8k_priv *)ctx; - qca8k_write(priv, reg, val); - - return 0; + return qca8k_write(priv, reg, val); } static const struct regmap_range qca8k_readable_ranges[] = { @@ -367,6 +366,7 @@ static int qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) { u32 reg; + int ret; /* Set the command and FDB index */ reg = QCA8K_ATU_FUNC_BUSY; @@ -377,7 +377,9 @@ qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) } /* Write the function register triggering the table access */ - qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); + ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); + if (ret) + return ret; /* wait for completion */ if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY)) @@ -450,6 +452,7 @@ static int qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) { u32 reg; + int ret; /* Set the command and VLAN index */ reg = QCA8K_VTU_FUNC1_BUSY; @@ -457,7 +460,9 @@ qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) reg |= vid << QCA8K_VTU_FUNC1_VID_S; /* Write the function register triggering the table access */ - qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); + ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); + if (ret) + return ret; /* wait for completion */ if (qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY)) @@ -505,7 +510,9 @@ qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged) reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_S(port); - qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); + ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); + if (ret) + return ret; ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); out: @@ -548,7 +555,9 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) if (del) { ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid); } else { - qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); + ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); + if (ret) + return ret; ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); } @@ -558,15 +567,21 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) return ret; } -static void +static int qca8k_mib_init(struct qca8k_priv *priv) { + int ret; + mutex_lock(&priv->reg_mutex); qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); - qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); + + ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); + +exit: mutex_unlock(&priv->reg_mutex); + return ret; } static void @@ -603,6 +618,7 @@ static int qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) { u32 phy, val; + int ret; if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) return -EINVAL; @@ -616,7 +632,9 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) QCA8K_MDIO_MASTER_REG_ADDR(regnum) | QCA8K_MDIO_MASTER_DATA(data); - qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + if (ret) + return ret; return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, QCA8K_MDIO_MASTER_BUSY); @@ -626,6 +644,7 @@ static int qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) { u32 phy, val; + int ret; if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) return -EINVAL; @@ -638,7 +657,9 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | QCA8K_MDIO_MASTER_REG_ADDR(regnum); - qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + if (ret) + return ret; if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, QCA8K_MDIO_MASTER_BUSY)) @@ -769,12 +790,18 @@ qca8k_setup(struct dsa_switch *ds) QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); /* Enable MIB counters */ - qca8k_mib_init(priv); + ret = qca8k_mib_init(priv); + if (ret) + dev_warn(priv->dev, "mib init failed"); /* Enable QCA header mode on the cpu port */ - qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); + ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), + QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | + QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); + if (ret) { + dev_err(priv->dev, "failed enabling QCA header mode"); + return ret; + } /* Disable forwarding by default on all ports */ for (i = 0; i < QCA8K_NUM_PORTS; i++) @@ -786,11 +813,13 @@ qca8k_setup(struct dsa_switch *ds) qca8k_port_set_status(priv, i, 0); /* Forward all unknown frames to CPU port for Linux processing */ - qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); + ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, + BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | + BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | + BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | + BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); + if (ret) + return ret; /* Setup connection between CPU port & user ports */ for (i = 0; i < QCA8K_NUM_PORTS; i++) { @@ -818,16 +847,20 @@ qca8k_setup(struct dsa_switch *ds) qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), 0xfff << shift, QCA8K_PORT_VID_DEF << shift); - qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i), - QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | - QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); + ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i), + QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | + QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); + if (ret) + return ret; } } /* Setup our port MTUs to match power on defaults */ for (i = 0; i < QCA8K_NUM_PORTS; i++) priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; - qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); + ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); + if (ret) + dev_warn(priv->dev, "failed setting MTU settings"); /* Flush the FDB table */ qca8k_fdb_flush(priv); @@ -1143,8 +1176,8 @@ qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port); - int ret = 0; u32 reg; + int ret; mutex_lock(&priv->reg_mutex); reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL); @@ -1157,7 +1190,7 @@ qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee) reg |= lpi_en; else reg &= ~lpi_en; - qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); + ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); exit: mutex_unlock(&priv->reg_mutex); @@ -1287,9 +1320,7 @@ qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) mtu = priv->port_mtu[i]; /* Include L2 header / FCS length */ - qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN); - - return 0; + return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN); } static int @@ -1384,7 +1415,7 @@ qca8k_port_vlan_add(struct dsa_switch *ds, int port, bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; struct qca8k_priv *priv = ds->priv; - int ret = 0; + int ret; ret = qca8k_vlan_add(priv, port, vlan->vid, untagged); if (ret) { @@ -1397,9 +1428,11 @@ qca8k_port_vlan_add(struct dsa_switch *ds, int port, qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), 0xfff << shift, vlan->vid << shift); - qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), - QCA8K_PORT_VLAN_CVID(vlan->vid) | - QCA8K_PORT_VLAN_SVID(vlan->vid)); + ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), + QCA8K_PORT_VLAN_CVID(vlan->vid) | + QCA8K_PORT_VLAN_SVID(vlan->vid)); + if (ret) + return ret; } return 0; @@ -1410,7 +1443,7 @@ qca8k_port_vlan_del(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan) { struct qca8k_priv *priv = ds->priv; - int ret = 0; + int ret; ret = qca8k_vlan_del(priv, port, vlan->vid); if (ret) From patchwork Sat May 8 00:29:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9491DC433ED for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:28 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 10/28] net: dsa: qca8k: handle error with qca8k_rmw operation Date: Sat, 8 May 2021 02:29:00 +0200 Message-Id: <20210508002920.19945-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org qca8k_rmw can fail. Rework any user to handle error values and correctly return. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 127 ++++++++++++++++++++++++++-------------- 1 file changed, 84 insertions(+), 43 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 0ec95ef16143..16ffff478de0 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -206,6 +206,9 @@ qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) goto exit; ret = qca8k_mii_read32(bus, 0x10 | r2, r1); + if (ret < 0) + goto exit; + ret &= ~mask; ret |= val; qca8k_mii_write32(bus, 0x10 | r2, r1, ret); @@ -216,16 +219,28 @@ qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) return ret; } -static void +static int qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val) { - qca8k_rmw(priv, reg, 0, val); + int ret; + + ret = qca8k_rmw(priv, reg, 0, val); + if (ret < 0) + return ret; + + return 0; } -static void +static int qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val) { - qca8k_rmw(priv, reg, val, 0); + int ret; + + ret = qca8k_rmw(priv, reg, val, 0); + if (ret < 0) + return ret; + + return 0; } static int @@ -573,9 +588,15 @@ qca8k_mib_init(struct qca8k_priv *priv) int ret; mutex_lock(&priv->reg_mutex); - qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); + ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); + if (ret) + goto exit; + qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); - qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); + + ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); + if (ret) + goto exit; ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); @@ -751,9 +772,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) * a dt-overlay and driver reload changed the configuration */ - qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_EN); - return 0; + return qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); } priv->ops.phy_read = qca8k_phy_read; @@ -786,8 +806,12 @@ qca8k_setup(struct dsa_switch *ds) return ret; /* Enable CPU Port */ - qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, - QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); + ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, + QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); + if (ret) { + dev_err(priv->dev, "failed enabling CPU port"); + return ret; + } /* Enable MIB counters */ ret = qca8k_mib_init(priv); @@ -804,9 +828,12 @@ qca8k_setup(struct dsa_switch *ds) } /* Disable forwarding by default on all ports */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_MEMBER, 0); + for (i = 0; i < QCA8K_NUM_PORTS; i++) { + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), + QCA8K_PORT_LOOKUP_MEMBER, 0); + if (ret < 0) + return ret; + } /* Disable MAC by default on all ports */ for (i = 1; i < QCA8K_NUM_PORTS; i++) @@ -825,28 +852,37 @@ qca8k_setup(struct dsa_switch *ds) for (i = 0; i < QCA8K_NUM_PORTS; i++) { /* CPU port gets connected to all user ports of the switch */ if (dsa_is_cpu_port(ds, i)) { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), - QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), + QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); + if (ret < 0) + return ret; } /* Individual user ports get connected to CPU port only */ if (dsa_is_user_port(ds, i)) { int shift = 16 * (i % 2); - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_MEMBER, - BIT(QCA8K_CPU_PORT)); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), + QCA8K_PORT_LOOKUP_MEMBER, + BIT(QCA8K_CPU_PORT)); + if (ret < 0) + return ret; /* Enable ARP Auto-learning by default */ - qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_LEARN); + ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i), + QCA8K_PORT_LOOKUP_LEARN); + if (ret) + return ret; /* For port based vlans to work we need to set the * default egress vid */ - qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), - 0xfff << shift, - QCA8K_PORT_VID_DEF << shift); + ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), + 0xfff << shift, + QCA8K_PORT_VID_DEF << shift); + if (ret < 0) + return ret; + ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i), QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); @@ -1238,7 +1274,7 @@ qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; int port_mask = BIT(QCA8K_CPU_PORT); - int i; + int i, ret; for (i = 1; i < QCA8K_NUM_PORTS; i++) { if (dsa_to_port(ds, i)->bridge_dev != br) @@ -1246,17 +1282,20 @@ qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br) /* Add this port to the portvlan mask of the other ports * in the bridge */ - qca8k_reg_set(priv, - QCA8K_PORT_LOOKUP_CTRL(i), - BIT(port)); + ret = qca8k_reg_set(priv, + QCA8K_PORT_LOOKUP_CTRL(i), + BIT(port)); + if (ret) + return ret; if (i != port) port_mask |= BIT(i); } + /* Add all other ports to this ports portvlan mask */ - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_MEMBER, port_mask); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_MEMBER, port_mask); - return 0; + return ret < 0 ? ret : 0; } static void @@ -1393,18 +1432,19 @@ qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, struct netlink_ext_ack *extack) { struct qca8k_priv *priv = ds->priv; + int ret; if (vlan_filtering) { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_VLAN_MODE, - QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_VLAN_MODE, + QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE); } else { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_VLAN_MODE, - QCA8K_PORT_LOOKUP_VLAN_MODE_NONE); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_VLAN_MODE, + QCA8K_PORT_LOOKUP_VLAN_MODE_NONE); } - return 0; + return ret < 0 ? ret : 0; } static int @@ -1426,16 +1466,17 @@ qca8k_port_vlan_add(struct dsa_switch *ds, int port, if (pvid) { int shift = 16 * (port % 2); - qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), - 0xfff << shift, vlan->vid << shift); + ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), + 0xfff << shift, vlan->vid << shift); + if (ret < 0) + return ret; + ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), QCA8K_PORT_VLAN_CVID(vlan->vid) | QCA8K_PORT_VLAN_SVID(vlan->vid)); - if (ret) - return ret; } - return 0; + return ret; } static int From patchwork Sat May 8 00:29:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C06CAC433B4 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:29 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 11/28] net: dsa: qca8k: handle error from qca8k_busy_wait Date: Sat, 8 May 2021 02:29:01 +0200 Message-Id: <20210508002920.19945-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Propagate errors from qca8k_busy_wait instead of hardcoding return value. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 16ffff478de0..6c65c6013c5f 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -397,8 +397,9 @@ qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) return ret; /* wait for completion */ - if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY)) - return -1; + ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY); + if (ret) + return ret; /* Check for table full violation when adding an entry */ if (cmd == QCA8K_FDB_LOAD) { @@ -480,8 +481,9 @@ qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) return ret; /* wait for completion */ - if (qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY)) - return -ETIMEDOUT; + ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY); + if (ret) + return ret; /* Check for table full violation when adding an entry */ if (cmd == QCA8K_VLAN_LOAD) { @@ -592,7 +594,9 @@ qca8k_mib_init(struct qca8k_priv *priv) if (ret) goto exit; - qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); + ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); + if (ret) + goto exit; ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); if (ret) @@ -682,9 +686,10 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) if (ret) return ret; - if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY)) - return -ETIMEDOUT; + ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY); + if (ret) + return ret; val = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL); if (val < 0) From patchwork Sat May 8 00:29:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 433002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D811FC433B4 for ; Sat, 8 May 2021 00:29:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BB75C6113E for ; Sat, 8 May 2021 00:29:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231145AbhEHAap (ORCPT ); Fri, 7 May 2021 20:30:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230410AbhEHAae (ORCPT ); Fri, 7 May 2021 20:30:34 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C71CC06138C; Fri, 7 May 2021 17:29:32 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id d11so10860746wrw.8; Fri, 07 May 2021 17:29:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=00Pu0epvTDq6aKqmx0t8XhDKxiRQECjav0p2CQIy/GA=; b=iIQrBmM1/iHiq8mGh0SqCxAAd8OH7aYCoIp9QlSH1YGbXsmlMPaA4nzq9uERZGoNwv jOdTRYf7Miyj+4ic4Lsf1ihaMEEov4dIUC+m8577NUY6oHrap3m8YBrwK3IecbzsJyDV 84oL+6atB3szyEhlxtLvNs3EQ/ckWJ2gL7TanxgUIkIwPh5NOe4RKoOv0It1vnkLvikv dtQX3vUjxyRIVct/ZjOy/Kn7uNJ9kz6gFv7wvg/HO+Osw5giEEUchPMFh59VgHaHgcep zI6xElPfXn21ZRD5gz14boTauzH2BgnwIuS6ykv8Cwdisd4TrBcqsFcGo5wIKYL5sSQW UXHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=00Pu0epvTDq6aKqmx0t8XhDKxiRQECjav0p2CQIy/GA=; b=tTT+M3IZSqZNAl2nAVmID6x3EZ8LybWmMFIDlGNmpWmX2ex7JRVPSj1T640pjiXCm5 FbSdoDClq2M0V+AuDEWroUglqqADEnbjhsTh1Ra2ACJOb8CB/tQBK+iX7UWpRNGsKGyY UprA2fe9ZvNrNTHynYvdyBtMsjw+gpI03NY+Or+mSSS6T3+q3AdKVXiljrOGtmWgezxG JFWmFAQO/5m7WP4Xs1d7pQBWF0EGmQqPgS8x97v1hOYA6Y+don95Df7L9USFbBeRNKFR Hr+k61bgwRdCKp6u+pJh0Fe6Nm+IkgcQumz9YaDCjWxGr+Xml9vbdcx6rQiVa/4maMQ9 Jz1A== X-Gm-Message-State: AOAM533SSmCDfiLvQzt4k8y+zXJ7ZA04rIzxn+28TW0MbZFvkIWCD3Rt wR1pvgkVTfTbVS8dBBEeSWHss2WUyf2VVg== X-Google-Smtp-Source: ABdhPJzXxF49KrnOJGye3mSXXc6pRLFzOcWLoqNDojTuI7k1VsftXvWQwoaZyIbERyQ+CbGO6qE/Rg== X-Received: by 2002:a5d:6e0d:: with SMTP id h13mr16056309wrz.118.1620433771292; Fri, 07 May 2021 17:29:31 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:30 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vladimir Oltean , Vivien Didelot , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 12/28] net: dsa: qca8k: add support for qca8327 switch Date: Sat, 8 May 2021 02:29:02 +0200 Message-Id: <20210508002920.19945-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org qca8327 switch is a low tier version of the more recent qca8337. It does share the same regs used by the qca8k driver and can be supported with minimal change. Signed-off-by: Ansuel Smith Reviewed-by: Andrew Lunn Reviewed-by: Vladimir Oltean --- drivers/net/dsa/qca8k.c | 23 ++++++++++++++++++++--- drivers/net/dsa/qca8k.h | 6 ++++++ 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 6c65c6013c5f..9c2f09e84364 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1536,6 +1536,7 @@ static const struct dsa_switch_ops qca8k_switch_ops = { static int qca8k_sw_probe(struct mdio_device *mdiodev) { + const struct qca8k_match_data *data; struct qca8k_priv *priv; u32 id; @@ -1563,6 +1564,11 @@ qca8k_sw_probe(struct mdio_device *mdiodev) gpiod_set_value_cansleep(priv->reset_gpio, 0); } + /* get the switches ID from the compatible */ + data = of_device_get_match_data(&mdiodev->dev); + if (!data) + return -ENODEV; + /* read the switches ID register */ id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); if (id < 0) @@ -1570,8 +1576,10 @@ qca8k_sw_probe(struct mdio_device *mdiodev) id >>= QCA8K_MASK_CTRL_ID_S; id &= QCA8K_MASK_CTRL_ID_M; - if (id != QCA8K_ID_QCA8337) + if (id != data->id) { + dev_err(&mdiodev->dev, "Switch id detected %x but expected %x", id, data->id); return -ENODEV; + } priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); if (!priv->ds) @@ -1636,9 +1644,18 @@ static int qca8k_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, qca8k_suspend, qca8k_resume); +static const struct qca8k_match_data qca832x = { + .id = QCA8K_ID_QCA8327, +}; + +static const struct qca8k_match_data qca833x = { + .id = QCA8K_ID_QCA8337, +}; + static const struct of_device_id qca8k_of_match[] = { - { .compatible = "qca,qca8334" }, - { .compatible = "qca,qca8337" }, + { .compatible = "qca,qca8327", .data = &qca832x }, + { .compatible = "qca,qca8334", .data = &qca833x }, + { .compatible = "qca,qca8337", .data = &qca833x }, { /* sentinel */ }, }; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 86c585b7ec4a..87a8b10459c6 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -15,6 +15,8 @@ #define QCA8K_NUM_PORTS 7 #define QCA8K_MAX_MTU 9000 +#define PHY_ID_QCA8327 0x004dd034 +#define QCA8K_ID_QCA8327 0x12 #define PHY_ID_QCA8337 0x004dd036 #define QCA8K_ID_QCA8337 0x13 @@ -213,6 +215,10 @@ struct ar8xxx_port_status { int enabled; }; +struct qca8k_match_data { + u8 id; +}; + struct qca8k_priv { struct regmap *regmap; struct mii_bus *bus; From patchwork Sat May 8 00:29:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D952C43460 for ; Sat, 8 May 2021 00:29:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0DDEB61057 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:32 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Rob Herring , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 13/28] devicetree: net: dsa: qca8k: Document new compatible qca8327 Date: Sat, 8 May 2021 02:29:03 +0200 Message-Id: <20210508002920.19945-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for qca8327 in the compatible list. Signed-off-by: Ansuel Smith Reviewed-by: Andrew Lunn Acked-by: Rob Herring Reviewed-by: Florian Fainelli --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index ccbc6d89325d..1daf68e7ae19 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -3,6 +3,7 @@ Required properties: - compatible: should be one of: + "qca,qca8327" "qca,qca8334" "qca,qca8337" From patchwork Sat May 8 00:29:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17233C433ED for ; Sat, 8 May 2021 00:30:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EFB1761451 for ; Sat, 8 May 2021 00:30:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230357AbhEHAbK (ORCPT ); Fri, 7 May 2021 20:31:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230487AbhEHAak (ORCPT ); Fri, 7 May 2021 20:30:40 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 636E1C061763; Fri, 7 May 2021 17:29:35 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id d4so10847571wru.7; Fri, 07 May 2021 17:29:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1MDsVjWJ6ZEIkzs2xX7L6tkHclI0+FffWAk7X84jZYU=; b=Lb4Z8qaFj4jiH5tYze8PuV3T7M/XYRxE+1sPsAodY8WnAsypfQxn2JrUbQwDSHVyiO TmJtrjvN0jXOwY15gi5FES7YGSFEd1+dpwWITHZ9y1jkX4fskj5GWK4crCQ8piMCJ201 Oc7dE2AVpcID5D4AKIjXxtqMIMc2qknFUcQAsFz/4PBzv26C/UHtap59+Xdbj7gTAdu2 zht7SgGDh19ppmzhRvGYUIjrqNP7b8Wmw8WCAe1gBmQMgxdTddG5KAHytSkEMv4W+krK +ubQ0WXsffsQRpahxFEW+HAT9gZ+H7ORKsfHaX0whaJgsuAZtDF4bCufv7WEyZrW+hTU HNBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1MDsVjWJ6ZEIkzs2xX7L6tkHclI0+FffWAk7X84jZYU=; b=qPc8IQfvlM5kc3A/zq64xyMv040x5Hrnlne/29jizywGwzxzPlgPEXb5UrlBfzP3Ya UzYIoaXy2drh/s1HaVnMYNk68p72Dh0GMGHWDtzj7fYd4PNckBFE3x9c2cMkMxluV7cc AueM8JwjkEZof/aObUMylSmuW6ozoG5xMrTXYss/09fI/3t7xniKHuqAGxbnzLyyl3dL qvOnv5t3fZ2uRoWuEcsdr9+EmyjxmLXZoz0x5M26p97avg7KzUdF09c7aAwZ29Wt43+7 emVegCXq0lpZ/5YwRebGMpBnLjUoZQvKivjKnqpl+BPkQDi3nasjtcShaGiMbhF6T4d2 xQVw== X-Gm-Message-State: AOAM531jaF5Mb0+zZW7j3wPvFIF8of5WboP8bsNehjhEuCiP7KQ0CHPM 24AuCx5ibXOZAf1DCWbl658= X-Google-Smtp-Source: ABdhPJxlhVbZrqukrCgc8v8YzVq1UoQV0LRT1rgQ2GKGe88DhjK38kYSPgq0gHU2jzCNKWMwPNEmSA== X-Received: by 2002:a5d:610d:: with SMTP id v13mr15718770wrt.173.1620433773975; Fri, 07 May 2021 17:29:33 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:33 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 14/28] net: dsa: qca8k: add priority tweak to qca8337 switch Date: Sat, 8 May 2021 02:29:04 +0200 Message-Id: <20210508002920.19945-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The port 5 of the qca8337 have some problem in flood condition. The original legacy driver had some specific buffer and priority settings for the different port suggested by the QCA switch team. Add this missing settings to improve switch stability under load condition. The packet priority tweak is only needed for the qca8337 switch and other qca8k switch are not affected. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 47 +++++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 25 ++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 9c2f09e84364..69fd526344cc 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -791,6 +791,7 @@ qca8k_setup(struct dsa_switch *ds) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; int ret, i; + u32 mask; /* Make sure that port 0 is the cpu port */ if (!dsa_is_cpu_port(ds, 0)) { @@ -896,6 +897,51 @@ qca8k_setup(struct dsa_switch *ds) } } + /* The port 5 of the qca8337 have some problem in flood condition. The + * original legacy driver had some specific buffer and priority settings + * for the different port suggested by the QCA switch team. Add this + * missing settings to improve switch stability under load condition. + * This problem is limited to qca8337 and other qca8k switch are not affected. + */ + if (priv->switch_id == QCA8K_ID_QCA8337) { + for (i = 0; i < QCA8K_NUM_PORTS; i++) { + switch (i) { + /* The 2 CPU port and port 5 requires some different + * priority than any other ports. + */ + case 0: + case 5: + case 6: + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) | + QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) | + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e); + break; + default: + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) | + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) | + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19); + } + qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask); + + mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) | + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | + QCA8K_PORT_HOL_CTRL1_WRED_EN; + qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i), + QCA8K_PORT_HOL_CTRL1_ING_BUF | + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | + QCA8K_PORT_HOL_CTRL1_WRED_EN, + mask); + } + } + /* Setup our port MTUs to match power on defaults */ for (i = 0; i < QCA8K_NUM_PORTS; i++) priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; @@ -1581,6 +1627,7 @@ qca8k_sw_probe(struct mdio_device *mdiodev) return -ENODEV; } + priv->switch_id = id; priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); if (!priv->ds) return -ENOMEM; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 87a8b10459c6..42d90836dffa 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -168,6 +168,30 @@ #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) #define QCA8K_PORT_LOOKUP_LEARN BIT(20) +#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20) +#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24) +#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24) + +#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) +#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0) +#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0) +#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6) +#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7) +#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8) +#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) + /* Pkt edit registers */ #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2))) @@ -220,6 +244,7 @@ struct qca8k_match_data { }; struct qca8k_priv { + u8 switch_id; struct regmap *regmap; struct mii_bus *bus; struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; From patchwork Sat May 8 00:29:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 433000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3BEAC43460 for ; Sat, 8 May 2021 00:30:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A532D60FF3 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:34 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 15/28] net: dsa: qca8k: limit port5 delay to qca8337 Date: Sat, 8 May 2021 02:29:05 +0200 Message-Id: <20210508002920.19945-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Limit port5 rx delay to qca8337. This is taken from the legacy QSDK code that limits the rx delay on port5 to only this particular switch version, on other switch only the tx and rx delay for port0 are needed. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 69fd526344cc..612fa77164ae 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1015,8 +1015,10 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, QCA8K_PORT_PAD_RGMII_EN | QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) | QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY)); - qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); + /* QCA8337 requires to set rgmii rx delay */ + if (priv->switch_id == QCA8K_ID_QCA8337) + qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); break; case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_1000BASEX: From patchwork Sat May 8 00:29:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432813 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65881C433B4 for ; Sat, 8 May 2021 00:30:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4659060FF3 for ; Sat, 8 May 2021 00:30:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231320AbhEHAbG (ORCPT ); Fri, 7 May 2021 20:31:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230468AbhEHAaj (ORCPT ); Fri, 7 May 2021 20:30:39 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9ABB9C061574; Fri, 7 May 2021 17:29:37 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id h4so10842301wrt.12; Fri, 07 May 2021 17:29:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nIxHNmyeWsGG00RmLkvPUBT8RdWEEbTr8lmBCb8DBrk=; b=MnPwvLVCtjpd+6BffzjxuDm8/yeXzUPZuUL24wfWqDFMtbnElQJ7MFPVJorS6NPfU6 H0CR+p05O20QJC0uiTLJzxmaWHHyZy1BqzvnZMuxRNmC0+Gz+vFBAc+Dd9uGPByXTibd C6/7OfPpQcafZl8J9/iVFFzKixgBDMWrU+6lVYP0SH3TU7bMwEWd2CIVK/rudcCl2ZKP p31hGn63AJdQkERmEijaxuV3HaFNBumkqyUPpow3r4NFP4Ilso5cmejLliSwFfxMs1Oq 05/vAdySsrrf0jplDoaZspLRU+C2l7YdFXFh8MvqljCyqWSqaLsI5DqipzgYdsZdi1cs G3fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nIxHNmyeWsGG00RmLkvPUBT8RdWEEbTr8lmBCb8DBrk=; b=RHne6X3PFmDJYVPsjV65rHXm9/4j8KFctC9UP37nxsL4d1OtgrMjG9ZKds6smpDYrK 9mIQUjP1uDYkbA4msJP1o3s1dOk2gNHcQmMHkgCXWZq+VGr3pCcVkSw+9V7AuRBMaBCU 5GBB8nYvG0KNfaH/ORx6jVl5ZEfgXEifr8sduzqeu/qlBXKrrc5xYu+ZBwCZ57TMAzEh sPaGPFWdSNi0Um5aknHxeIiKyhYD7MsO6seUNLGJbUFhDYxJDRLlSbBHWJ0JEnPXHB6S VmXBEEC67iMNV4mqE/QM2psVs72PGpdB0JqTcieg5EEkCSwZCt1jSA9kgY2kG5fBSeK6 RBPQ== X-Gm-Message-State: AOAM5336PAwvTvpE97R6dMGD72QCEy1Km0a/iOexcrL9ZCPRnfjLGlBS nephQtLwH84qyFCpIf6Bxo4YNzNl7cC6ow== X-Google-Smtp-Source: ABdhPJy3uxQM8EF/5R0xi5CTzAQecacq2oz9G68dUZXgr5rIfQUWrV3hrAM+FIghs8Mj5TkjYigr4A== X-Received: by 2002:adf:da51:: with SMTP id r17mr3448958wrl.232.1620433776296; Fri, 07 May 2021 17:29:36 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:35 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 16/28] net: dsa: qca8k: add GLOBAL_FC settings needed for qca8327 Date: Sat, 8 May 2021 02:29:06 +0200 Message-Id: <20210508002920.19945-16-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Switch qca8327 needs special settings for the GLOBAL_FC_THRES regs. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 10 ++++++++++ drivers/net/dsa/qca8k.h | 6 ++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 612fa77164ae..301bb94aba84 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -942,6 +942,16 @@ qca8k_setup(struct dsa_switch *ds) } } + /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */ + if (priv->switch_id == QCA8K_ID_QCA8327) { + mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) | + QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496); + qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH, + QCA8K_GLOBAL_FC_GOL_XON_THRES_S | + QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S, + mask); + } + /* Setup our port MTUs to match power on defaults */ for (i = 0; i < QCA8K_NUM_PORTS; i++) priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 42d90836dffa..eceeacfe2c5d 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -168,6 +168,12 @@ #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) #define QCA8K_PORT_LOOKUP_LEARN BIT(20) +#define QCA8K_REG_GLOBAL_FC_THRESH 0x800 +#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16) +#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16) +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0) +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0) + #define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) #define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) #define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0) From patchwork Sat May 8 00:29:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE203C433ED for ; Sat, 8 May 2021 00:30:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C10DA60FF3 for ; Sat, 8 May 2021 00:30:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231382AbhEHAbQ (ORCPT ); Fri, 7 May 2021 20:31:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230495AbhEHAak (ORCPT ); Fri, 7 May 2021 20:30:40 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE484C061346; Fri, 7 May 2021 17:29:38 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id m9so10873040wrx.3; Fri, 07 May 2021 17:29:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+h+ej8+g7K6vmS4t/5VTu2T/0hfaLSCmNjTS7IqFOgY=; b=sMJZr77+1/wamSKH/xUsZN+mc9C2LRhaCYwIW98u+p3FhHx9derCBCW+HGgWOwuPEa or96BhYc+/fC+OG/RS5CTtqhl3Gu9kWG/TTcpGwdUkAlbpnS9EtqtG21/zlaMYtAzR8l AsbK2XfqAY6dkshISoWF+8u5X9wEpBpw6XvqBzUy3ZfDjQS63MWiGYBzLxEx0jzEKKGF WAMewSi270f1Sz9klMIU1SlItUkqChOBxJ+vyMk0Duyun2+C3KS7gPh8vXFgiGzg77o2 NA0ZdHmvv0yUUA6vk88Dur4kAqTs1v6Wgfp7RrFXREoxiynlAfZxSVL8D7Zb/Hf1NMQH aAxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+h+ej8+g7K6vmS4t/5VTu2T/0hfaLSCmNjTS7IqFOgY=; b=gslR4ntH3DhAsl5mvQdpeyAtpOjQpqtuCR18odgZdd5g07drzdm4IehBlAqUyWGSpk B0kCIF91BpNazmmhVFIG5zjdy3kkXHvMNFOm0yXr2VT3+57tYP1grlaT3r/UYd17EMTK d0h9orsfmYhEMhDsDpt/RZAkQv9haxmtICas+cJIPRjFefpn1xnxxsgEKq4Ci+tWJ9kW dJH0gl7+XnRtYq261dQVrT2AtdU/q65iUvFwdocVxM00exNn6R3dij4i5vVY3JLyLelL GF/JApLBLJM9JtHf7+9sRQut35LbsvW64p0TnO1AHMM6c97rWKzx8TW3h50TDkMFk58L h6EQ== X-Gm-Message-State: AOAM533109aSvaKtQG6q8DdGrrbbOcJ/GaLJJ8pwjbrnLJL2ep+WaX6E wWxHS2cvkfnvf6ZChrAvVIY= X-Google-Smtp-Source: ABdhPJzGe3xuQ84gdFqTNK1f457u/DJD1Y2yuy6kSlAa4lkGjQewp7/GgDjczJoetoF5oCQzdCaruQ== X-Received: by 2002:a5d:64c7:: with SMTP id f7mr15499727wri.257.1620433777425; Fri, 07 May 2021 17:29:37 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:37 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 17/28] net: dsa: qca8k: add support for switch rev Date: Sat, 8 May 2021 02:29:07 +0200 Message-Id: <20210508002920.19945-17-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org qca8k internal phy driver require some special debug value to be set based on the switch revision. Rework the switch id read function to also read the chip revision. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 53 ++++++++++++++++++++++++++--------------- drivers/net/dsa/qca8k.h | 7 ++++-- 2 files changed, 39 insertions(+), 21 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 301bb94aba84..9905a2631420 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1591,12 +1591,40 @@ static const struct dsa_switch_ops qca8k_switch_ops = { .phylink_mac_link_up = qca8k_phylink_mac_link_up, }; +static int qca8k_read_switch_id(struct qca8k_priv *priv) +{ + const struct qca8k_match_data *data; + u32 val; + u8 id; + + /* get the switches ID from the compatible */ + data = of_device_get_match_data(priv->dev); + if (!data) + return -ENODEV; + + val = qca8k_read(priv, QCA8K_REG_MASK_CTRL); + if (val < 0) + return -ENODEV; + + id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK); + if (id != data->id) { + dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id); + return -ENODEV; + } + + priv->switch_id = id; + + /* Save revision to communicate to the internal PHY driver */ + priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK); + + return 0; +} + static int qca8k_sw_probe(struct mdio_device *mdiodev) { - const struct qca8k_match_data *data; struct qca8k_priv *priv; - u32 id; + int ret; /* allocate the private data struct so that we can probe the switches * ID register @@ -1622,24 +1650,11 @@ qca8k_sw_probe(struct mdio_device *mdiodev) gpiod_set_value_cansleep(priv->reset_gpio, 0); } - /* get the switches ID from the compatible */ - data = of_device_get_match_data(&mdiodev->dev); - if (!data) - return -ENODEV; - - /* read the switches ID register */ - id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); - if (id < 0) - return id; - - id >>= QCA8K_MASK_CTRL_ID_S; - id &= QCA8K_MASK_CTRL_ID_M; - if (id != data->id) { - dev_err(&mdiodev->dev, "Switch id detected %x but expected %x", id, data->id); - return -ENODEV; - } + /* Check the detected switch id */ + ret = qca8k_read_switch_id(priv); + if (ret) + return ret; - priv->switch_id = id; priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); if (!priv->ds) return -ENOMEM; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index eceeacfe2c5d..338277978ec0 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -30,8 +30,10 @@ /* Global control registers */ #define QCA8K_REG_MASK_CTRL 0x000 -#define QCA8K_MASK_CTRL_ID_M 0xff -#define QCA8K_MASK_CTRL_ID_S 8 +#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0) +#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0) +#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) +#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) #define QCA8K_REG_PORT0_PAD_CTRL 0x004 #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c @@ -251,6 +253,7 @@ struct qca8k_match_data { struct qca8k_priv { u8 switch_id; + u8 switch_revision; struct regmap *regmap; struct mii_bus *bus; struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; From patchwork Sat May 8 00:29:08 2021 Content-Type: text/plain; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:38 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 18/28] net: dsa: qca8k: add ethernet-ports fallback to setup_mdio_bus Date: Sat, 8 May 2021 02:29:08 +0200 Message-Id: <20210508002920.19945-18-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Dsa now also supports ethernet-ports. Add this new binding as a fallback if the ports node can't be found. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 9905a2631420..285cce4fab9f 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -730,6 +730,9 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) int err; ports = of_get_child_by_name(priv->dev->of_node, "ports"); + if (!ports) + ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports"); + if (!ports) return -EINVAL; From patchwork Sat May 8 00:29:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A07EC433ED for ; Sat, 8 May 2021 00:30:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1C4BB6113E for ; Sat, 8 May 2021 00:30:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231481AbhEHAbd (ORCPT ); Fri, 7 May 2021 20:31:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230330AbhEHAam (ORCPT ); Fri, 7 May 2021 20:30:42 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 085D5C06138F; Fri, 7 May 2021 17:29:41 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id l14so10864471wrx.5; Fri, 07 May 2021 17:29:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+ZXTotwH/H9zAiZZ9satckfQe8BvSUWtUnJjdJJzzOY=; b=mWdIHY474zMAMcnDllo8BAMta3HITEVnPH6OMFtW1NQIKH3bI0WbXZcl5JwGZN7oIe l6OL0xPdbLA3zSST65ivnc9B7C6rH+QYNLfUh44dCaDUrpfOUj9ZCQdslrko2dwnM75r PE4Yh19Gp+crlS3y9RPUfBF8IIdkCrcxdguC5FxTWRbOzIZ+/xa0lQEXS/YY+DuSqTsv fnAq0CQHqrACNwkLwvM31pf3qc66XanvXC6JSlRRdfREkOnYoDalvt/R6AJN8dLYI20h hU26GEuHNXZi3/YGLGcH/BQJABVqxmYY9Di4TZLDi4VqXpU0V//XiohY78du1muwEcsa HCjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+ZXTotwH/H9zAiZZ9satckfQe8BvSUWtUnJjdJJzzOY=; b=YOCQkICYXKj4xe84C8tNLhZw9U3TTWhp1qOXCgcBhNo2pRI5kG+mxjJMBuXD10vtxM cvDZJr5vAynJjk9gbzDf37IKnz/46pNFPV0vY7CspJF3158Ss6AGrW9OJnD2IgRi5IMW lwvrj2M7MwfW8oeV0EMT/3onrRX4OhIhtc+1vH5+pmHSDUBpw3kV3sGOdf96kTtDpruV P0OPw81ZukaPzxy7iHMY6WmcbuJcAoRnV9x7JWTEEnOZqACZGoMh5Q01f5Ks5oUx1tNy tu6XzKuJpG+8LPu4FCnmREz371q1F/zf6HdnQkb73uyeufVAbR1Y2X2qeU3UF0I5HxHl 6ouw== X-Gm-Message-State: AOAM5319JlO39FReBl/Ab9mccsDYFmVQTrs3q0OMNHDPzq8dy0K4Uf8q 53F0ceslPxbFDJkXPHsOo5w= X-Google-Smtp-Source: ABdhPJyhHvBh2CCCLQE4kZhv8UkamlV0Wjswj6XsrKHZk9ucKVvZB0/RhLn85plIsOGjHsE4sGPCOw== X-Received: by 2002:adf:dc8e:: with SMTP id r14mr1467696wrj.44.1620433779671; Fri, 07 May 2021 17:29:39 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:39 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 19/28] net: dsa: qca8k: make rgmii delay configurable Date: Sat, 8 May 2021 02:29:09 +0200 Message-Id: <20210508002920.19945-19-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The legacy qsdk code used a different delay instead of the max value. Qsdk use 1 ps for rx and 2 ps for tx. Make these values configurable using the standard rx/tx-internal-delay-ps ethernet binding and apply qsdk values by default. The connected gmac doesn't add any delay so no additional delay is added to tx/rx. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 54 +++++++++++++++++++++++++++++++++++++++-- drivers/net/dsa/qca8k.h | 11 +++++---- 2 files changed, 58 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 285cce4fab9f..0c53b6fdf6ee 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -789,6 +789,50 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) return 0; } +static int +qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv) +{ + struct device_node *ports, *port; + u32 val; + + ports = of_get_child_by_name(priv->dev->of_node, "ports"); + if (!ports) + ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports"); + + if (!ports) + return -EINVAL; + + /* Assume only one port with rgmii-id mode */ + for_each_available_child_of_node(ports, port) { + if (!of_property_match_string(port, "phy-mode", "rgmii-id")) + continue; + + if (of_property_read_u32(port, "rx-internal-delay-ps", &val)) + val = 2; + + if (val > QCA8K_MAX_DELAY) { + dev_err(priv->dev, "rgmii rx delay is limited to more than 3ps, setting to the max value"); + priv->rgmii_rx_delay = 3; + } else { + priv->rgmii_rx_delay = val; + } + + if (of_property_read_u32(port, "tx-internal-delay-ps", &val)) + val = 1; + + if (val > QCA8K_MAX_DELAY) { + dev_err(priv->dev, "rgmii tx delay is limited to more than 3ps, setting to the max value"); + priv->rgmii_tx_delay = 3; + } else { + priv->rgmii_tx_delay = val; + } + } + + of_node_put(ports); + + return 0; +} + static int qca8k_setup(struct dsa_switch *ds) { @@ -814,6 +858,10 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; + ret = qca8k_setup_of_rgmii_delay(priv); + if (ret) + return ret; + /* Enable CPU Port */ ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); @@ -1026,8 +1074,10 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, */ qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN | - QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) | - QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY)); + QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) | + QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) | + QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); /* QCA8337 requires to set rgmii rx delay */ if (priv->switch_id == QCA8K_ID_QCA8337) qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 338277978ec0..a878486d9bcd 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -38,12 +38,11 @@ #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c #define QCA8K_PORT_PAD_RGMII_EN BIT(26) -#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \ - ((0x8 + (x & 0x3)) << 22) -#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \ - ((0x10 + (x & 0x3)) << 20) -#define QCA8K_MAX_DELAY 3 +#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22) +#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20) +#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25) #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) +#define QCA8K_MAX_DELAY 3 #define QCA8K_PORT_PAD_SGMII_EN BIT(7) #define QCA8K_REG_PWS 0x010 #define QCA8K_PWS_SERDES_AEN_DIS BIT(7) @@ -254,6 +253,8 @@ struct qca8k_match_data { struct qca8k_priv { u8 switch_id; u8 switch_revision; + u8 rgmii_tx_delay; + u8 rgmii_rx_delay; struct regmap *regmap; struct mii_bus *bus; struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; From patchwork Sat May 8 00:29:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 161DEC43460 for ; Sat, 8 May 2021 00:31:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE17E60FF3 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:40 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 20/28] net: dsa: qca8k: clear MASTER_EN after phy read/write Date: Sat, 8 May 2021 02:29:10 +0200 Message-Id: <20210508002920.19945-20-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Clear MDIO_MASTER_EN bit from MDIO_MASTER_CTRL after read/write operation. The MDIO_MASTER_EN bit is not reset after read/write operation and the next operation can be wrongly interpreted by the switch as a mdio operation. This cause a production of wrong/garbage data from the switch and underfined bheavior. (random port drop, unplugged port flagged with link up, wrong port speed) Also on driver remove the MASTER_CTRL can be left set and cause the malfunction of any next driver using the mdio device. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 0c53b6fdf6ee..2e0d2f918efe 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -661,8 +661,14 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) if (ret) return ret; - return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); + ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY); + + /* even if the busy_wait timeouts try to clear the MASTER_EN */ + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); + + return ret; } static int @@ -697,6 +703,10 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) val &= QCA8K_MDIO_MASTER_DATA_MASK; + /* even if the busy_wait timeouts try to clear the MASTER_EN */ + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); + return val; } From patchwork Sat May 8 00:29:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD5C9C433ED for ; Sat, 8 May 2021 00:31:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A45ED60FF3 for ; Sat, 8 May 2021 00:31:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231262AbhEHAcJ (ORCPT ); Fri, 7 May 2021 20:32:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231263AbhEHAa6 (ORCPT ); Fri, 7 May 2021 20:30:58 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BCDEC06134F; Fri, 7 May 2021 17:29:43 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id m9so10873125wrx.3; Fri, 07 May 2021 17:29:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VXJeCZ6p+84hYUeYtR84+eoPuhkPjIoXlDYRmPpn2+8=; b=DPeGUdJcSUo+UoxhjoUaNJfdVkwp640u3cPmrm2GUFftpL96BlYx+M9lIclfy07z9w IwkZz2QpxQv9scdQaXdyyzlOee6h7L0ePa6hBNW9iV/CNXK2R5AJxC1IgFf3F90Ri0gb 3bFXEZob8kzLh5G0zZefvMcyEUezUgKCzJOCWqo6OYrqvlNZo++PgU2uM1CwECXikUVq kgzv46bjSDRNh1o19wqCdk6bem99KQ8XPVVo1p8phdtMz2DdC9uCAjACWUplYVTGeHff elckCnBZDS5QfarhjGtmEcy0OajKpi4YqzYBEij2GAiZUYjWyXf/wivqRAb3gMdm8OjV 0M5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VXJeCZ6p+84hYUeYtR84+eoPuhkPjIoXlDYRmPpn2+8=; b=sYVT1AZkMly0db0FAU/9fCYuGEWwPIo8nevqhdQvVumIGYiXa/uTNZHg2sqBbud47p hQmnDK0W139Y95DHHhmOA9kgRNFK40C/FLijDSw/Ie3vM4kM8lK9N9nKBHs8fZ00XyuB EUFAyQt5Fk1RJIHp+KXU1KXEvhty8QrweLnnSLU044P0FDiVDmlDhI90bwN8TfPeHlwM AEEiCblvNRfWBxIU3OgLKsh3cJ+iAfw3cXmqkjH3w51XX6gsiG/HFq2BSueB68F5Xfxn 8g/+7D9ISFhuk0G9G8oZh3gvkgWjesJYbA1t9kRvXQvTy+PziGgWicnDKqYxguiIZZdZ XBkw== X-Gm-Message-State: AOAM530f6OII+aN7xMglwug14ovAdjSuUgAf+0Rb6Ty2gifElZnpwjJh HGHOlJerHJ1Ba5+nRuWPqu4= X-Google-Smtp-Source: ABdhPJyH62MH2gubA6pgUluB4iCFQc8a5Y0s9n7M7Qax7f3RiG9lHrJUS9t+BPySpGJNkHEyNW1hqA== X-Received: by 2002:a5d:6811:: with SMTP id w17mr16067723wru.348.1620433781868; Fri, 07 May 2021 17:29:41 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:41 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 21/28] net: dsa: qca8k: dsa: qca8k: protect MASTER busy_wait with mdio mutex Date: Sat, 8 May 2021 02:29:11 +0200 Message-Id: <20210508002920.19945-21-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org MDIO_MASTER operation have a dedicated busy wait that is not protected by the mdio mutex. This can cause situation where the MASTER operation is done and a normal operation is executed between the MASTER read/write and the MASTER busy_wait. Rework the qca8k_mdio_read/write function to address this issue by binding the lock for the whole MASTER operation and not only the mdio read/write common operation. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 68 +++++++++++++++++++++++++++++++++-------- 1 file changed, 55 insertions(+), 13 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 2e0d2f918efe..e272ccaaa7f6 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -639,9 +639,32 @@ qca8k_port_to_phy(int port) return port - 1; } +static int +qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) +{ + u16 r1, r2, page; + u32 val; + int ret; + + qca8k_split_addr(reg, &r1, &r2, &page); + + ret = read_poll_timeout(qca8k_mii_read32, val, !(val & mask), 0, + QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, + priv->bus, 0x10 | r2, r1); + + /* Check if qca8k_read has failed for a different reason + * before returnting -ETIMEDOUT + */ + if (ret < 0 && val < 0) + return val; + + return ret; +} + static int qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) { + u16 r1, r2, page; u32 phy, val; int ret; @@ -657,12 +680,21 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) QCA8K_MDIO_MASTER_REG_ADDR(regnum) | QCA8K_MDIO_MASTER_DATA(data); - ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); + + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + + ret = qca8k_set_page(priv->bus, page); if (ret) - return ret; + goto exit; + + qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); + + ret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY); - ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); +exit: + mutex_unlock(&priv->bus->mdio_lock); /* even if the busy_wait timeouts try to clear the MASTER_EN */ qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, @@ -674,6 +706,7 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) static int qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) { + u16 r1, r2, page; u32 phy, val; int ret; @@ -688,21 +721,30 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | QCA8K_MDIO_MASTER_REG_ADDR(regnum); - ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); - if (ret) - return ret; + qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); + + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); - ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); + ret = qca8k_set_page(priv->bus, page); if (ret) - return ret; + goto exit; - val = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL); - if (val < 0) - return val; + qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); + + ret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY); + if (ret) + goto exit; + val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); val &= QCA8K_MDIO_MASTER_DATA_MASK; +exit: + mutex_unlock(&priv->bus->mdio_lock); + + if (val >= 0) + val &= QCA8K_MDIO_MASTER_DATA_MASK; + /* even if the busy_wait timeouts try to clear the MASTER_EN */ qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, QCA8K_MDIO_MASTER_EN); From patchwork Sat May 8 00:29:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17368C433B4 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:42 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 22/28] net: dsa: qca8k: enlarge mdio delay and timeout Date: Sat, 8 May 2021 02:29:12 +0200 Message-Id: <20210508002920.19945-22-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The witch require some extra delay after setting page or the next read/write can use still use the old page. Add a delay after the set_page function to address this as it's done in QSDK legacy driver. Some timeouts were notice with VLAN and phy function, enlarge the mdio busy wait timeout to fix these problems. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 1 + drivers/net/dsa/qca8k.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index e272ccaaa7f6..f96579c0bd46 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -143,6 +143,7 @@ qca8k_set_page(struct mii_bus *bus, u16 page) } qca8k_current_page = page; + usleep_range(1000, 2000); return 0; } diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index a878486d9bcd..d365f85ab34f 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -20,7 +20,7 @@ #define PHY_ID_QCA8337 0x004dd036 #define QCA8K_ID_QCA8337 0x13 -#define QCA8K_BUSY_WAIT_TIMEOUT 20 +#define QCA8K_BUSY_WAIT_TIMEOUT 2000 #define QCA8K_NUM_FDB_RECORDS 2048 From patchwork Sat May 8 00:29:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432809 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BF14C43461 for ; Sat, 8 May 2021 00:31:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 58ABD61057 for ; Sat, 8 May 2021 00:31:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231534AbhEHAcU (ORCPT ); Fri, 7 May 2021 20:32:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230476AbhEHAbH (ORCPT ); Fri, 7 May 2021 20:31:07 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAFECC061354; Fri, 7 May 2021 17:29:45 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id s8so10863032wrw.10; Fri, 07 May 2021 17:29:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D5uILt9Mcik69GuSPXQVODEGZtxJwB3jkU/VveoNRJY=; b=aPiMybhdazAWHfH8VCeUfkKwZUm8E5m/BizfTo3J55KXdWXy4WiW6pvdWTnM0MrAxN CrIiTXZaWb+iuBurRdE1gXBWuWc42f+OMg8Tl9pR18vC3IH1eMh/0U81MOaXsZ2GncHW 9/xCu3Ph1Q+TyLQmTGcV8mrs9UwAHu3qT/8DDuA9bLBu+9qAlMtdvb96INgwR/EJuwDL ROybuA5PYWkHIH+uFgc2sOM7xGJ6ESqJB4G54lWcNiX9gK4IUEpv5onzzw/6GSg1BFwr NuGTGGTDDB9Zy3BMj8jytlYEbZn6ItCKqoYqiSUw8/gJP9MO2me+evYwovHQl+ZBAg+a PgpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D5uILt9Mcik69GuSPXQVODEGZtxJwB3jkU/VveoNRJY=; b=PDeVXaA6Q0B9nhJW4TlQz2fjkxilju/vX/7U40ysM+TJvpBbM7NUXwT/kDWcD3ftGC 4zTrsORtuybwmnkF5nPCFiAC2Kv0CMUwTeJuYfGqAAfahopbvFCRXoA6vgoRj1/k5XKc dvocVw3SmdKHVGU50dQA+XA8AyhYaZVCXzF4/nZIeMSOgmvsqcVf5iswqo1nh0/MOlE7 n7eIKqXVSTSzgYwazxkxNPza6bSuqmydEevh4C8ZEMNFfXXQx5BlK6CnvORzgqaixliA WF9zbJkLMCPm6T4B7wrjdxwaaxdeFTKGi0NXAbpgpP/UUMm6Y5aMUs89Xo1KDBo2drlZ /TJQ== X-Gm-Message-State: AOAM532SDaXU2Eq67mpz+n6hBAZCz8UiODwIbBnFqvkqKIO8zYC7oLh1 xwwzM4YdymyTFeP7hV4aKzY= X-Google-Smtp-Source: ABdhPJw/Pq+vvq3FZsqSdCfYPDj9ZmoQYsIpqvP0/xvnRbLpbJQx7oc9TOZRtKwz4t42P2Ac2sTsxQ== X-Received: by 2002:a5d:6342:: with SMTP id b2mr15854176wrw.203.1620433784443; Fri, 07 May 2021 17:29:44 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:44 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 23/28] net: dsa: register of_mdiobus if a mdio node is declared Date: Sat, 8 May 2021 02:29:13 +0200 Message-Id: <20210508002920.19945-23-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Some switch have phy port that use the internal switch mdio bus and can have different phy regs than the one declared in the ports node. Add support for this specific case by registering the mdiobus with the mdio node and permit the port to declare a phy-handle defined inside the switch node. This is an example from the qca8337 switch where the 5 phy port should use the internal mdiobus and would benefits from this. switch10: switch@10 { compatible = "qca,qca8337"; #address-cells = <1>; #size-cells = <0>; reg = <0x10>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "cpu"; ethernet = <&gmac1>; phy-mode = "rgmii-id"; fixed-link { speed = <1000>; full-duplex; }; }; port@1 { reg = <1>; label = "lan1"; phy-handle = <&phy_port0>; phy-mode = "internal"; }; port@2 { reg = <2>; label = "lan2"; phy-handle = <&phy_port1>; phy-mode = "internal"; }; port@3 { reg = <3>; label = "lan3"; phy-handle = <&phy_port2>; phy-mode = "internal"; }; port@4 { reg = <4>; label = "lan4"; phy-handle = <&phy_port3>; phy-mode = "internal"; }; port@5 { reg = <5>; label = "wan"; phy-handle = <&phy_port4>; phy-mode = "internal"; }; port@6 { reg = <6>; label = "cpu"; ethernet = <&gmac2>; phy-mode = "sgmii"; fixed-link { speed = <1000>; full-duplex; }; }; }; mdio { #address-cells = <1>; #size-cells = <0>; phy_port0: phy@0 { reg = <0>; }; phy_port1: phy@1 { reg = <1>; }; phy_port2: phy@2 { reg = <2>; }; phy_port3: phy@3 { reg = <3>; }; phy_port4: phy@4 { reg = <4>; }; }; }; Signed-off-by: Ansuel Smith --- net/dsa/dsa2.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/net/dsa/dsa2.c b/net/dsa/dsa2.c index 3c3e56a1f34d..79adabe3e2a7 100644 --- a/net/dsa/dsa2.c +++ b/net/dsa/dsa2.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "dsa_priv.h" @@ -721,6 +722,8 @@ static int dsa_switch_setup(struct dsa_switch *ds) devlink_params_publish(ds->devlink); if (!ds->slave_mii_bus && ds->ops->phy_read) { + struct device_node *mdio; + ds->slave_mii_bus = devm_mdiobus_alloc(ds->dev); if (!ds->slave_mii_bus) { err = -ENOMEM; @@ -729,7 +732,15 @@ static int dsa_switch_setup(struct dsa_switch *ds) dsa_slave_mii_bus_init(ds); - err = mdiobus_register(ds->slave_mii_bus); + mdio = of_get_child_by_name(ds->dev->of_node, "mdio"); + + if (mdio) { + err = of_mdiobus_register(ds->slave_mii_bus, mdio); + of_node_put(mdio); + } else { + err = mdiobus_register(ds->slave_mii_bus); + } + if (err < 0) goto teardown; } From patchwork Sat May 8 00:29:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C48DC433ED for ; Sat, 8 May 2021 00:31:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 60AD461493 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:45 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 24/28] devicetree: net: dsa: Document use of mdio node inside switch node Date: Sat, 8 May 2021 02:29:14 +0200 Message-Id: <20210508002920.19945-24-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Switch node can contain mdio node to describe internal mdio and PHYs connected to the switch ports. Signed-off-by: Ansuel Smith --- .../devicetree/bindings/net/dsa/dsa.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.yaml b/Documentation/devicetree/bindings/net/dsa/dsa.yaml index 8a3494db4d8d..fbefaca884cc 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa.yaml +++ b/Documentation/devicetree/bindings/net/dsa/dsa.yaml @@ -15,6 +15,9 @@ description: This binding represents Ethernet Switches which have a dedicated CPU port. That port is usually connected to an Ethernet Controller of the SoC. Such setups are typical for embedded devices. + Switch can also have PHY port connected to an internal mdio bus by + declaring a mdio node inside the switch node and declaring the + phy-handle for each required port. select: false @@ -87,6 +90,31 @@ patternProperties: additionalProperties: false +patternProperties: + mdio: + description: + Describes the internal mdio of the Ethernet switch + type: object + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + phy: + type: object + description: Ethernet switch internal PHY + + properties: + reg: + description: PHY address + + required: + - reg + + additionalProperties: false + oneOf: - required: - ports From patchwork Sat May 8 00:29:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 270A6C433ED for ; Sat, 8 May 2021 00:31:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E8A116113E for ; Sat, 8 May 2021 00:31:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231437AbhEHAch (ORCPT ); Fri, 7 May 2021 20:32:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231430AbhEHAbV (ORCPT ); Fri, 7 May 2021 20:31:21 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56BCFC061360; Fri, 7 May 2021 17:29:48 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id y124-20020a1c32820000b029010c93864955so8034900wmy.5; Fri, 07 May 2021 17:29:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Fogw8IcjT8TV14jKFrpaG7JVRrfLzwmnVNQap9rROkA=; b=QqhwFaqx728ggmXmnNTJJWph1ML8IRuA0gl5YzcTDWRe/wErQ1nBTq07kb+3+HlUIX NgCDA9bKw4zNvZLXK5f3Lvec+1bFezD+Zl4XGbIkd/N3UXVP5lH5xWd9Ic+xA0kNIfOy ih8A4ya9ag93361MWcPwyDICqwi9fJTd7fvQ4ri/ye4JV7dFgd5+/h2d3xDFhbKYVTwL hQWp+yPhq3ih4snD6fIu841E61cgdJiREFd2Te/bCKrpuOcL3DuF23zUxuIARwkAHYmB MDNJSVQpXRhMQPcUkrNhHpDAlDNTvdsetlguPI7eZK43H2CkrJSYbMvCAj1AcU/zH1TF fSCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Fogw8IcjT8TV14jKFrpaG7JVRrfLzwmnVNQap9rROkA=; b=R4MWLKfh7G5Cx+T+0wBEN8blV9GDJZov3rRH0zskwX561qo+FS9ib8Am1tQZw2z9CX Sh3rdZtTCGMEbHIRh+yNZNpZaPDm3CcrxJKz0Zn8LB0g3mlSR6SBza0AV4ONzRqWBFQw Wnl7ScxqpZ2jV3oQEshENgf//jM5ef403XvR3yD4Lr8exXvAE7q6QRWzSaF+mijKAFLh ltP9tDPiFnYhXrNMplwxgJlLUEQD4soRUI1d5T4wd1XRxXbBG86OCmjvhMLMbBc8QAg4 Ry0SMhwNS60dnj+8JR5mpWOl9mWGURSHcxCphj0VJR0I85vtvHeXnc016rF3BCsiI57E N0cQ== X-Gm-Message-State: AOAM533Y4NC6YwaNoXmO4N/CUXTUpQU/1I+I7rY05vIO9RmAIhT7IO1f 3ZIAJrtcRMIIeOVVwog/CjX4Brq7TkVefg== X-Google-Smtp-Source: ABdhPJwFhr40ax0mb5uX9wu2eHTNXPt7oDUlc4ydQje2FStzzUhWSvgHAmxqZAesYJWlJLfizpSX1A== X-Received: by 2002:a1c:a54a:: with SMTP id o71mr13067952wme.172.1620433787013; Fri, 07 May 2021 17:29:47 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:46 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 25/28] net: dsa: qca8k: add support for internal phy Date: Sat, 8 May 2021 02:29:15 +0200 Message-Id: <20210508002920.19945-25-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support to setup_mdio_bus for internal phy declaration. Introduce a flag to use the legacy port phy mapping by default and use the direct mapping if a mdio node is detected in the switch node. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 46 +++++++++++++++++++++++++++-------------- drivers/net/dsa/qca8k.h | 1 + 2 files changed, 32 insertions(+), 15 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index f96579c0bd46..3d195fdd7ed5 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -663,19 +663,15 @@ qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) } static int -qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) +qca8k_mdio_write(struct qca8k_priv *priv, int phy, u32 regnum, u16 data) { u16 r1, r2, page; - u32 phy, val; + u32 val; int ret; if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) return -EINVAL; - /* callee is responsible for not passing bad ports, - * but we still would like to make spills impossible. - */ - phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR; val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | QCA8K_MDIO_MASTER_REG_ADDR(regnum) | @@ -705,19 +701,15 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) } static int -qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) +qca8k_mdio_read(struct qca8k_priv *priv, int phy, u32 regnum) { u16 r1, r2, page; - u32 phy, val; + u32 val; int ret; if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) return -EINVAL; - /* callee is responsible for not passing bad ports, - * but we still would like to make spills impossible. - */ - phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR; val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | QCA8K_MDIO_MASTER_REG_ADDR(regnum); @@ -758,6 +750,13 @@ qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data) { struct qca8k_priv *priv = ds->priv; + /* Check if the legacy mapping should be used and the + * port is not correctly mapped to the right PHY in the + * devicetree + */ + if (priv->legacy_phy_port_mapping) + port = qca8k_port_to_phy(port) % PHY_MAX_ADDR; + return qca8k_mdio_write(priv, port, regnum, data); } @@ -767,6 +766,13 @@ qca8k_phy_read(struct dsa_switch *ds, int port, int regnum) struct qca8k_priv *priv = ds->priv; int ret; + /* Check if the legacy mapping should be used and the + * port is not correctly mapped to the right PHY in the + * devicetree + */ + if (priv->legacy_phy_port_mapping) + port = qca8k_port_to_phy(port) % PHY_MAX_ADDR; + ret = qca8k_mdio_read(priv, port, regnum); if (ret < 0) @@ -779,7 +785,7 @@ static int qca8k_setup_mdio_bus(struct qca8k_priv *priv) { u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg; - struct device_node *ports, *port; + struct device_node *ports, *port, *mdio; int err; ports = of_get_child_by_name(priv->dev->of_node, "ports"); @@ -800,7 +806,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) if (!dsa_is_user_port(priv->ds, reg)) continue; - if (of_property_read_bool(port, "phy-handle")) + if (of_property_read_bool(port, "phy-handle") && + of_property_match_string(port, "phy-mode", "internal") < 0) external_mdio_mask |= BIT(reg); else internal_mdio_mask |= BIT(reg); @@ -837,6 +844,14 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) QCA8K_MDIO_MASTER_EN); } + /* Check if the devicetree declare the port:phy mapping + * If a mapping can't be found the legacy mapping is used, + * using the qca8k_port_to_phy function + */ + mdio = of_get_child_by_name(priv->dev->of_node, "mdio"); + if (!mdio) + priv->legacy_phy_port_mapping = true; + priv->ops.phy_read = qca8k_phy_read; priv->ops.phy_write = qca8k_phy_write; return 0; @@ -1198,7 +1213,8 @@ qca8k_phylink_validate(struct dsa_switch *ds, int port, case 5: /* Internal PHY */ if (state->interface != PHY_INTERFACE_MODE_NA && - state->interface != PHY_INTERFACE_MODE_GMII) + state->interface != PHY_INTERFACE_MODE_GMII && + state->interface != PHY_INTERFACE_MODE_INTERNAL) goto unsupported; break; case 6: /* 2nd CPU port / external PHY */ diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index d365f85ab34f..ed3b05ad6745 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -255,6 +255,7 @@ struct qca8k_priv { u8 switch_revision; u8 rgmii_tx_delay; u8 rgmii_rx_delay; + bool legacy_phy_port_mapping; struct regmap *regmap; struct mii_bus *bus; struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; From patchwork Sat May 8 00:29:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432994 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3DCFC433ED for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:47 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 26/28] net: dsa: permit driver to provide custom phy_mii_mask for slave mdiobus Date: Sat, 8 May 2021 02:29:16 +0200 Message-Id: <20210508002920.19945-26-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Some switch doesn't have a 1:1 map phy to port. Permit driver to provide a custom phy_mii_mask so the internal mdiobus can correctly use the provided phy reg as it can differ from the port reg. The qca8k driver is provided as a first user of this function. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 30 ++++++++++++++++++++++++++++++ include/net/dsa.h | 7 +++++++ net/dsa/dsa2.c | 7 ++++++- 3 files changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 3d195fdd7ed5..3c3e05735b2d 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1685,7 +1685,37 @@ qca8k_get_tag_protocol(struct dsa_switch *ds, int port, return DSA_TAG_PROTO_QCA; } +static u32 +qca8k_get_phys_mii_mask(struct dsa_switch *ds) +{ + struct device_node *mdio, *phy; + u32 reg, phy_mii_mask = 0; + int err; + + mdio = of_get_child_by_name(ds->dev->of_node, "mdio"); + if (mdio) { + for_each_available_child_of_node(mdio, phy) { + err = of_property_read_u32(phy, "reg", ®); + if (err) { + of_node_put(phy); + of_node_put(mdio); + return 0; + } + + phy_mii_mask |= BIT(reg); + } + + of_node_put(mdio); + return phy_mii_mask; + } + + /* Fallback to the lagacy mapping if mdio node is not found */ + dev_warn(ds->dev, "Using the legacy phys_mii_mapping. Consider updating the dts."); + return dsa_user_ports(ds); +} + static const struct dsa_switch_ops qca8k_switch_ops = { + .get_phys_mii_mask = qca8k_get_phys_mii_mask, .get_tag_protocol = qca8k_get_tag_protocol, .setup = qca8k_setup, .get_strings = qca8k_get_strings, diff --git a/include/net/dsa.h b/include/net/dsa.h index 83a933e563fe..4003ffc659a4 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -511,6 +511,13 @@ struct dsa_switch_ops { void (*teardown)(struct dsa_switch *ds); u32 (*get_phy_flags)(struct dsa_switch *ds, int port); + /* + * Provide a custom phys_mii_mask for the dsa slave mdiobus instead + * of relying on the dsa_user_ports. Not every switch has a 1:1 map + * port to PHY, hence the driver can provide their fixed mask. + */ + u32 (*get_phys_mii_mask)(struct dsa_switch *ds); + /* * Access to the switch's PHY registers. */ diff --git a/net/dsa/dsa2.c b/net/dsa/dsa2.c index 79adabe3e2a7..7eabd4d67849 100644 --- a/net/dsa/dsa2.c +++ b/net/dsa/dsa2.c @@ -682,8 +682,13 @@ static int dsa_switch_setup(struct dsa_switch *ds) * driver and before ops->setup() has run, since the switch drivers and * the slave MDIO bus driver rely on these values for probing PHY * devices or not + * Driver can provide his on mask as some switch doesn't have a 1:1 map + * phy to port. */ - ds->phys_mii_mask |= dsa_user_ports(ds); + if (ds->ops->get_phys_mii_mask) + ds->phys_mii_mask = ds->ops->get_phys_mii_mask(ds); + else + ds->phys_mii_mask |= dsa_user_ports(ds); /* Add the switch to devlink before calling setup, so that setup can * add dpipe tables From patchwork Sat May 8 00:29:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A174C43460 for ; Sat, 8 May 2021 00:31:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1892161492 for ; Sat, 8 May 2021 00:31:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231445AbhEHAcw (ORCPT ); Fri, 7 May 2021 20:32:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231183AbhEHAcD (ORCPT ); Fri, 7 May 2021 20:32:03 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F6A4C061373; Fri, 7 May 2021 17:29:50 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id u5-20020a7bc0450000b02901480e40338bso7283504wmc.1; Fri, 07 May 2021 17:29:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aOXIFQ6B/eqAVp4zbCeNkJnyhpNrD5T3KEJwsOpWC3o=; b=s2rEjKatrA4fQGVJiVFY8oerE9fRBgjLNhXXup+DTfDYkDDHVM/7UUh6SiZ1I2Swnc TGB8BMO4oMB0hiHZskKCtnUmY5dOz+0achz4M4ThIGGrvInP9QxG4DKd2jcqQ96f0QGE 6j9GXXSc2nVtf8PGRNOinsBalqvk/AGU13eRX/AOdaua60yJdK3HdvUoEJKY5mCBhEpg +XERb9NcIgUmRe6U+ziNPcTT2FxXWm8RGhi2n2OvYRK9RSEdka/XzjsWW9M43Z0otDNN yB7gQSuEqb7QtJbxLJ2bLmQ/Scg9PQSjgpjNRC1UUbhPo/QpNk4QWhAkSm0DQZfCbKON tWRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aOXIFQ6B/eqAVp4zbCeNkJnyhpNrD5T3KEJwsOpWC3o=; b=bpG0micWGVnML3jXxaQN+zT6tDzPnTejYotXbfT6s+BO5Ag3M2Jg4BkS8OBnzoMsHu MMY8WQIYNCAspJXjnkgJkmstAo6i/2YXtCuDS9XPRm82R/dIk8vqlnY2O/vLo/MYJ1a4 rI4dmMOf1ly+zkagvnTE9o3EtY22SzH0Z0EvyLIUs0aeVgnoOoEc5cY21rXPfTb/oHo+ QkdxFNc0ZmHs98Qejusixjyl6bw0MLrvknuli5oB844Lf/dF/p++Nu871X0SEqx0Ibl9 mipPTNSVJ/tVR02JhmEVX4BLgqduHaI0tldu58Rqj0wfA1YcRJPrMM0ENRLKfwNrv7xf JFNA== X-Gm-Message-State: AOAM533xoV+jvozuy7uVjApknb3Vr0bz+aTqjA7kb6PeTmy2D1hhXdyf ZDxcZ0IPGC9cX/sPA9rJPEk= X-Google-Smtp-Source: ABdhPJxAxvHPKWcpJwC1QxE85Ah5URf4mvJNLseQKQUQsG4v9SCqdFFONKftYcwh19n3ptGYNrIirw== X-Received: by 2002:a1c:21d7:: with SMTP id h206mr12389354wmh.56.1620433789333; Fri, 07 May 2021 17:29:49 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:29:49 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v4 27/28] net: dsa: qca8k: pass switch_revision info to phy dev_flags Date: Sat, 8 May 2021 02:29:17 +0200 Message-Id: <20210508002920.19945-27-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Define get_phy_flags to pass switch_Revision needed to tweak the internal PHY with debug values based on the revision. Signed-off-by: Ansuel Smith Reviewed-by: Florian Fainelli --- drivers/net/dsa/qca8k.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 3c3e05735b2d..8dafa581b7fa 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1678,6 +1678,22 @@ qca8k_port_vlan_del(struct dsa_switch *ds, int port, return ret; } +static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port) +{ + struct qca8k_priv *priv = ds->priv; + + /* Communicate to the phy internal driver the switch revision. + * Based on the switch revision different values needs to be + * set to the dbg and mmd reg on the phy. + * The first 2 bit are used to communicate the switch revision + * to the phy driver. + */ + if (port > 0 && port < 6) + return priv->switch_revision; + + return 0; +} + static enum dsa_tag_protocol qca8k_get_tag_protocol(struct dsa_switch *ds, int port, enum dsa_tag_protocol mp) @@ -1741,6 +1757,7 @@ static const struct dsa_switch_ops qca8k_switch_ops = { .phylink_mac_config = qca8k_phylink_mac_config, .phylink_mac_link_down = qca8k_phylink_mac_link_down, .phylink_mac_link_up = qca8k_phylink_mac_link_up, + .get_phy_flags = qca8k_get_phy_flags, }; static int qca8k_read_switch_id(struct qca8k_priv *priv) From patchwork Sat May 8 00:29:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 432993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDE7FC433B4 for ; Sat, 8 May 2021 00:32:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C861161154 for ; Sat, 8 May 2021 00:32:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230452AbhEHAdX (ORCPT ); Fri, 7 May 2021 20:33:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230352AbhEHAdC (ORCPT ); Fri, 7 May 2021 20:33:02 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1103FC06138B; Fri, 7 May 2021 17:30:06 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id y124-20020a1c32820000b029010c93864955so8035135wmy.5; Fri, 07 May 2021 17:30:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qcblg99dKtUzLmP9mbJXQAISMB0uNfwt/9mCJ1r1c3U=; b=etIGs1jthj7TT3R3upyK1KJK/meiSJ/3xzDUsWPWzZfiC7je/C4T70+esGB1sqd/b2 ab+2+DqrTxCGhdOgKrs2h8rYxrzazKtdANaB6pYxwzmGNTZKbT68BE7PE0CuHuBrk3ej ppAlNioGZMxW1rJbd8clItMTwUyWK1jwwBx1iHZrsGtpABgfVlqmPVgO3SQLIp5vK0OT AMpPQuYXOitb3LyXClYxnyrQgpcUgoJ5Ae6NpU6f3rhV1VOoxGkhQQ1fI1WwuSb0NX8/ b54NV/G9f7cOsEtojWLpGK8fM/JXqlDlrHCjzxSNTUiDwL34StnLksXfA8nX6zAU1iqC xX1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qcblg99dKtUzLmP9mbJXQAISMB0uNfwt/9mCJ1r1c3U=; b=IeeeL7og55ZkxeLNTsgDPRUa0Xz5jMd5peICPv6uld+a0zBsV8N+1+6jSgreUdHuF/ z96wSOd3Qq7hLClbo8Kpzak9/I32qiqBSgNzh+1srtPto8ycxia887bxJRXw6ATPALf6 gBnZjbkaXal7ZS4nqgIvis5P/MVcaVPJ+yuzTG3XMeguhWIOn9lHoN8sL8OBbCdKmK1N +7ia2DBRBcwD+A7HmDZb4xkN5HDCKc1bBh89VEVuLliP1rOBHfxV8Uv1efq5z/x48XGe 3gJPEVYYNguQHL9elmWWiei86ZaBzZrdgruxFqh1/O8nJQATjJ9GBVeklyGZ5pYOAA1j jy+g== X-Gm-Message-State: AOAM530rli312ufZ+C64Y+PV9Eji3+1hyigu6QeFYYtPVD5RbY9evxLr XyyiUd2nJRoI2gjjO6CJgtA= X-Google-Smtp-Source: ABdhPJxA4mWVt96aVWdM3JrX/XlR3pFVe3a0oxDkqFUAQL1JUD98eNCjYiMTyTznve5LaPn67o04Dw== X-Received: by 2002:a1c:2097:: with SMTP id g145mr23480081wmg.33.1620433804651; Fri, 07 May 2021 17:30:04 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id f4sm10967597wrz.33.2021.05.07.17.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 17:30:04 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [RFC PATCH net-next v4 28/28] net: phy: add qca8k driver for qca8k switch internal PHY Date: Sat, 8 May 2021 02:29:18 +0200 Message-Id: <20210508002920.19945-28-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210508002920.19945-1-ansuelsmth@gmail.com> References: <20210508002920.19945-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add initial support for qca8k internal PHYs. The internal PHYs requires special mmd and debug values to be set based on the switch revision passwd using the dev_flags. Supports output of idle, receive and eee_wake errors stats. Some debug values sets can't be translated as the documentation lacks any reference about them. Signed-off-by: Ansuel Smith --- drivers/net/phy/Kconfig | 7 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/qca8k.c | 172 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 180 insertions(+) create mode 100644 drivers/net/phy/qca8k.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 698bea312adc..cdf01613eb37 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -245,6 +245,13 @@ config QSEMI_PHY help Currently supports the qs6612 +config QCA8K_PHY + tristate "Qualcomm Atheros AR833x Internal PHYs" + help + This PHY is for the internal PHYs present on the QCA833x switch. + + Currently supports the AR8334, AR8337 model + config REALTEK_PHY tristate "Realtek PHYs" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index a13e402074cf..5f3cfd5606bb 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc/ obj-$(CONFIG_NATIONAL_PHY) += national.o obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o obj-$(CONFIG_QSEMI_PHY) += qsemi.o +obj-$(CONFIG_QCA8K_PHY) += qca8k.o obj-$(CONFIG_REALTEK_PHY) += realtek.o obj-$(CONFIG_RENESAS_PHY) += uPD60620.o obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o diff --git a/drivers/net/phy/qca8k.c b/drivers/net/phy/qca8k.c new file mode 100644 index 000000000000..53bbd506d184 --- /dev/null +++ b/drivers/net/phy/qca8k.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include +#include +#include +#include +#include +#include +#include + +#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) + +#define QCA8K_PHY_ID_MASK 0xffffffff +#define QCA8K_PHY_ID_QCA8327 0x004dd034 +#define QCA8K_PHY_ID_QCA8337 0x004dd036 + +#define MDIO_AZ_DEBUG 0x800d + +#define MDIO_DBG_ANALOG_TEST 0x0 +#define MDIO_DBG_SYSTEM_CONTROL_MODE 0x5 +#define MDIO_DBG_CONTROL_FEATURE_CONF 0x3d + +/* QCA specific MII registers */ +#define MII_ATH_DBG_ADDR 0x1d +#define MII_ATH_DBG_DATA 0x1e + +/* QCA specific MII registers access function */ +static void qca8k_phy_dbg_write(struct mii_bus *bus, int phy_addr, u16 dbg_addr, u16 dbg_data) +{ + bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr); + bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data); +} + +enum stat_access_type { + PHY, + MMD +}; + +struct qca8k_hw_stat { + const char *string; + u8 reg; + u32 mask; + enum stat_access_type access_type; +}; + +static struct qca8k_hw_stat qca8k_hw_stats[] = { + { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, + { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, + { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, +}; + +struct qca8k_phy_priv { + u8 switch_revision; + u64 stats[ARRAY_SIZE(qca8k_hw_stats)]; +}; + +static int qca8k_get_sset_count(struct phy_device *phydev) +{ + return ARRAY_SIZE(qca8k_hw_stats); +} + +static void qca8k_get_strings(struct phy_device *phydev, u8 *data) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(qca8k_hw_stats); i++) { + strscpy(data + i * ETH_GSTRING_LEN, + qca8k_hw_stats[i].string, ETH_GSTRING_LEN); + } +} + +static u64 qca8k_get_stat(struct phy_device *phydev, int i) +{ + struct qca8k_hw_stat stat = qca8k_hw_stats[i]; + struct qca8k_phy_priv *priv = phydev->priv; + int val; + u64 ret; + + if (stat.access_type == MMD) + val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); + else + val = phy_read(phydev, stat.reg); + + if (val < 0) { + ret = U64_MAX; + } else { + val = val & stat.mask; + priv->stats[i] += val; + ret = priv->stats[i]; + } + + return ret; +} + +static void qca8k_get_stats(struct phy_device *phydev, + struct ethtool_stats *stats, u64 *data) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(qca8k_hw_stats); i++) + data[i] = qca8k_get_stat(phydev, i); +} + +static int qca8k_config_init(struct phy_device *phydev) +{ + struct qca8k_phy_priv *priv = phydev->priv; + struct mii_bus *bus = phydev->mdio.bus; + int phy_addr = phydev->mdio.addr; + + priv->switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; + + switch (priv->switch_revision) { + case 1: + /* For 100M waveform */ + qca8k_phy_dbg_write(bus, phy_addr, MDIO_DBG_ANALOG_TEST, 0x02ea); + /* Turn on Gigabit clock */ + qca8k_phy_dbg_write(bus, phy_addr, MDIO_DBG_CONTROL_FEATURE_CONF, 0x68a0); + break; + + case 2: + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); + fallthrough; + case 4: + phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); + qca8k_phy_dbg_write(bus, phy_addr, MDIO_DBG_CONTROL_FEATURE_CONF, 0x6860); + qca8k_phy_dbg_write(bus, phy_addr, MDIO_DBG_SYSTEM_CONTROL_MODE, 0x2c46); + qca8k_phy_dbg_write(bus, phy_addr, 0x3c, 0x6000); + break; + } + + return 0; +} + +static int qca8k_probe(struct phy_device *phydev) +{ + struct qca8k_phy_priv *priv; + + priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + phydev->priv = priv; + + return 0; +} + +static struct phy_driver qca8k_drivers[] = { + { + .phy_id = QCA8K_PHY_ID_QCA8337, + .phy_id_mask = QCA8K_PHY_ID_MASK, + .name = "QCA PHY 8337", + /* PHY_GBIT_FEATURES */ + .probe = qca8k_probe, + .flags = PHY_IS_INTERNAL, + .config_init = qca8k_config_init, + .soft_reset = genphy_soft_reset, + .get_sset_count = qca8k_get_sset_count, + .get_strings = qca8k_get_strings, + .get_stats = qca8k_get_stats, + }, +}; + +module_phy_driver(qca8k_drivers); + +static struct mdio_device_id __maybe_unused qca8k_tbl[] = { + { QCA8K_PHY_ID_QCA8337, QCA8K_PHY_ID_MASK }, + { } +}; + +MODULE_DEVICE_TABLE(mdio, qca8k_tbl); +MODULE_DESCRIPTION("Qualcomm QCA8k PHY driver"); +MODULE_AUTHOR("Ansuel Smith"); +MODULE_LICENSE("GPL");