From patchwork Sat May 8 07:09:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 432905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FB13C433B4 for ; Sat, 8 May 2021 07:09:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A22461458 for ; Sat, 8 May 2021 07:09:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229752AbhEHHKh (ORCPT ); Sat, 8 May 2021 03:10:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229481AbhEHHKh (ORCPT ); Sat, 8 May 2021 03:10:37 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE605C061574 for ; Sat, 8 May 2021 00:09:34 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id n205so6393286wmf.1 for ; Sat, 08 May 2021 00:09:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FOVnFr/nj3QWdNJlIgekW/kswIF2a4pE9kCJghjF1wk=; b=KD6hEPXs3SiHAtFucQrMWstIwnPMlliFvZ+psgoH92t4UwNZk4SD3w2uW4x4mj9P+9 Gfafckp4z/odwwCgWLWjerD3ZaLb3e20nbiln50ezdGz1ac3PCGkQflMCZuFCWUXkE9V vzVVUk1BTonqDveH8BnR9sUgXQx7HAuw+GGYfjTPwmcdQC7ynkbktpspFb6H8XK7GeXm jik+lpush9BCPw+AjWjVognoElO38vOB+H5yKXoIaPIU2RH+qD99GwXRb/utq8jrLWSK +XyPmZfF2SZyNNIt9he9JU3GzoHLI+XPTIlOiYxeRmfubX59hzRpxCZItWlbfxNcyEvF CXhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FOVnFr/nj3QWdNJlIgekW/kswIF2a4pE9kCJghjF1wk=; b=HIuU3OXdGuXtdMqZHK4BWqKXcaWupwGw52WRNRv4Xs7jcw+WnHCB+8fc5cZWBMKMMp ulOYr5ABZtMALP7fMp0d9b4xHSeFfQl2FEMs1yrgWClO2YTr/UGMh1wmyB96hisR0hHR Y2mFvVLM7bpteJ9q5mHnDkDuyi4tZ/4uzefrOzAtTCmhDFmxUcCWpbIC0xDSx24sVDzx I9x/aXtFzvzjjweQwOP3rhMGNFZDNPJ6bLwfHwc9nZEm8HMo5ATPrtnk8XkhqjueyNE/ 8G0pVMJZyg3OFsOylz8pnTrIFlte200MTcXfgaIQ/G1WQqeaaXKbkk9e4YOFsMf0p47d ne4w== X-Gm-Message-State: AOAM530epSeF+mLylcxJjXN5L5E2CeBLU0vexJSTIpPXguLRETJjFu9G nQvnQXYeFv02KvcQgB1Jc3c= X-Google-Smtp-Source: ABdhPJy/DIm2VbViVvEjtPiiZspbv60TIWMsgF6WkvgzjInz1GQL+I1YsOm/xug6DjWda8PWEVcYdQ== X-Received: by 2002:a1c:6606:: with SMTP id a6mr24959455wmc.160.1620457773780; Sat, 08 May 2021 00:09:33 -0700 (PDT) Received: from localhost.localdomain (231.red-83-51-243.dynamicip.rima-tde.net. [83.51.243.231]) by smtp.gmail.com with ESMTPSA id s18sm11740345wro.95.2021.05.08.00.09.32 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 May 2021 00:09:33 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: kishon@ti.com, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH RESEND v2 1/6] staging: mt7621-dts: use clock in pci phy nodes Date: Sat, 8 May 2021 09:09:25 +0200 Message-Id: <20210508070930.5290-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508070930.5290-1-sergio.paracuellos@gmail.com> References: <20210508070930.5290-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' Hence we can use the clock in pcie phy nodes to be able to get it from there in driver code. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 9ee11adefa79..840ba0c3ffed 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -548,12 +548,14 @@ pcie@2,0 { pcie0_phy: pcie-phy@1e149000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e149000 0x0700>; + clocks = <&sysc MT7621_CLK_XTAL>; #phy-cells = <1>; }; pcie2_phy: pcie-phy@1e14a000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e14a000 0x0700>; + clocks = <&sysc MT7621_CLK_XTAL>; #phy-cells = <1>; }; }; From patchwork Sat May 8 07:09:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 432904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2911DC43460 for ; Sat, 8 May 2021 07:09:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EF59561458 for ; Sat, 8 May 2021 07:09:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229841AbhEHHKi (ORCPT ); Sat, 8 May 2021 03:10:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229481AbhEHHKh (ORCPT ); Sat, 8 May 2021 03:10:37 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F844C061761 for ; Sat, 8 May 2021 00:09:36 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id v12so11364965wrq.6 for ; Sat, 08 May 2021 00:09:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HcVgM2vyvgzDYevyg/QfJoz8h0kWR0tPVu2/nxnMK08=; b=oQBOEU8joU5LNoeSGDS2505fZ52pdijNw8EXDD8PUyl871qBQ+EUV1zHQGNwO0ZrGS u99bMzj80z7cRcYzkmFiE2eZFNDAXLhnG2BKMHfS61rBk4vDTBFWt2KjDwBGdOTXoTCA 6yUeU1YB/04dP9XgL3i4u7p83VPQ7lc2zhCq0ZAmWlInVy1VuQw70Y7eFJILijFpFU29 gc2pKGXAURTVJvZWp5cdPZGn9eY1+/rANSMJLHh6up28IIvCzhwSoERCvuNz0t6N4ygS Hg53jVkGXckGQRjzq/34ro2gU3htal2yfCibZ77ujjn1AxoZFp7swGtJzoX2rcBjTX6/ rgjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HcVgM2vyvgzDYevyg/QfJoz8h0kWR0tPVu2/nxnMK08=; b=LOYtFvKJBbEMdecFX+uTK/h+lUT6DpiztpclVE7kgc1kOezd9dezHuIgF8WcmRCzug YGde/e5/sbS1st2I1NYVDK8eON6LyyFUekbqW/CludXFHUKN8zocjDrwoZCCpc1nOZNy 0IwTYVK26I7C/e9FwoRIySDEekeVSii+i4CGdj2mP2F6VzTN3h1fUbYarHbg6v/hHnG+ mz96FrqocanGdoAYl9qygBgwS1gIhfE+2A64OKMZ0MEDCDWGJTW/R/HdoxPzHvRIq+t3 MfCi+7/PjbsMB3X2rk935AIh/oncStAAOFLCtYeRgrX2NQ5udo0Gf2EFv6m1MBnAc5Le O1BA== X-Gm-Message-State: AOAM533yVRk32+4nIaPPp5uTNo0DazCvnkjHzrSxFt5PDHFlvyb/TMKJ 45hCaD7S1XVF2e8qsu74oBffT+YBm06bHw== X-Google-Smtp-Source: ABdhPJwv2tpuFMx/ij8r4UA+F3GGnnHZs5rMG0ie4Q88HHaz7t2ijVZwXBdGKTtDzNHE2yUl+JWpfQ== X-Received: by 2002:adf:f683:: with SMTP id v3mr17358197wrp.133.1620457774843; Sat, 08 May 2021 00:09:34 -0700 (PDT) Received: from localhost.localdomain (231.red-83-51-243.dynamicip.rima-tde.net. [83.51.243.231]) by smtp.gmail.com with ESMTPSA id s18sm11740345wro.95.2021.05.08.00.09.33 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 May 2021 00:09:34 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: kishon@ti.com, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH RESEND v2 2/6] dt-bindings: phy: mediatek, mt7621-pci-phy: add clock entries Date: Sat, 8 May 2021 09:09:26 +0200 Message-Id: <20210508070930.5290-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508070930.5290-1-sergio.paracuellos@gmail.com> References: <20210508070930.5290-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' Hence update schema with the add of the entries related to clock. Since until now things were not properly being done we mark also 'clock' as required in the binding since this will be now the only way to properly retrieve frequency to be able to make a correct configuration of the PCIe phy registers. Signed-off-by: Sergio Paracuellos Acked-by: Rob Herring --- .../devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml index 0ccaded3f245..29d4123323c2 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml @@ -16,6 +16,9 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + "#phy-cells": const: 1 description: selects if the phy is dual-ported @@ -23,6 +26,7 @@ properties: required: - compatible - reg + - clocks - "#phy-cells" additionalProperties: false @@ -32,5 +36,6 @@ examples: pcie0_phy: pcie-phy@1e149000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e149000 0x0700>; + clocks = <&sysc 0>; #phy-cells = <1>; }; From patchwork Sat May 8 07:09:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 432669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28A42C43462 for ; Sat, 8 May 2021 07:09:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 09D5C61458 for ; Sat, 8 May 2021 07:09:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229864AbhEHHKj (ORCPT ); Sat, 8 May 2021 03:10:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229481AbhEHHKj (ORCPT ); Sat, 8 May 2021 03:10:39 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F0E2C061574 for ; Sat, 8 May 2021 00:09:37 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id m9so11388684wrx.3 for ; Sat, 08 May 2021 00:09:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cbFyM8/48A5QwY5f+jcAHfVdDdKUhqPQqn/9aWFc+bo=; b=A+9tsp1WsUbv6YGsDOBneGaswtgeo3mlJsb7bEr16UTDC+I1DyqSE8OqjVMDWlx84n INVEaYq4+1Xa3BGmNbQKDaeOVPtcchcYAoi2y6w5X9T3oT2RZd13UocYSh8vsTemka5j d6qDiwd/0mJr2P5OwdCMSStIS4N5jrA9sCpparX9N+IXxQfDxuQCBLqUmlNa5J/OQ90J vV+JaQoDW1VQTaOLqIKSK/1jgUhcuaYg1ddVdFo5pozUFuxiofpbFJTaGQqiWbYds4M3 r1mvznDuSDeccrkpmoBEcsvtcaxekcXZrFuj5d8AYtp+xdWaY4o8BPsx08XImfFprYWc G+Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cbFyM8/48A5QwY5f+jcAHfVdDdKUhqPQqn/9aWFc+bo=; b=fCbw2N+xb3m+0rBzJmnyqXMMa1QB/xNw8T4ybFUae/lczLvYLaLQ8bi+kHtKkG9NMr J6geX4tTzq3+dL7gbAgiCIuTSWytNCYS5o9UMCTRoK7ZdY+ss6HXfIdOgrmcMGiEFTwv n+J1A56xLYV5rZPXIAoL79Cf1GNJrMIyo/0SFf4I32B0apYAnqu4dC249hRAYkWMCBDU ztoMwuvTMJxzii2M63+f0XFFPX1HsJaaWD3OQdsspvrRkF0C73TSnfM4xswphrgdIOPJ AphYFI2pXDEnnzS8SpamNH9lZxit8N6xcXZ0PB3HG/5NGgyEf2LXzAm1+EC0jfxP/nWJ zBSw== X-Gm-Message-State: AOAM530DQ/lMrwNjqiFvP+YbJwpbjS1cuLKTdaHPy6crwywHalngteVr 6QJyzQf35pRgGDnVj8NGbQg= X-Google-Smtp-Source: ABdhPJxyI2ENCVd++zyUNxuNgDHuy4rRseRL4FBlKqO4/h72eQ+TmEFWLiNrBX6g0GJrm+Q8EDOY3Q== X-Received: by 2002:a5d:6087:: with SMTP id w7mr16863668wrt.136.1620457775830; Sat, 08 May 2021 00:09:35 -0700 (PDT) Received: from localhost.localdomain (231.red-83-51-243.dynamicip.rima-tde.net. [83.51.243.231]) by smtp.gmail.com with ESMTPSA id s18sm11740345wro.95.2021.05.08.00.09.34 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 May 2021 00:09:35 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: kishon@ti.com, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH RESEND v2 3/6] phy: ralink: phy-mt7621-pci: use kernel clock APIS Date: Sat, 8 May 2021 09:09:27 +0200 Message-Id: <20210508070930.5290-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508070930.5290-1-sergio.paracuellos@gmail.com> References: <20210508070930.5290-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' This allow us to properly use kernel clock apis to get the clock frequency needed for the phy configuration instead of use custom architecture code to do the same. Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/phy-mt7621-pci.c | 33 +++++++++++++++++------------ 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/phy/ralink/phy-mt7621-pci.c b/drivers/phy/ralink/phy-mt7621-pci.c index 753cb5bab930..f56ff10b0885 100644 --- a/drivers/phy/ralink/phy-mt7621-pci.c +++ b/drivers/phy/ralink/phy-mt7621-pci.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -14,8 +15,6 @@ #include #include #include -#include -#include #define RG_PE1_PIPE_REG 0x02c #define RG_PE1_PIPE_RST BIT(12) @@ -62,8 +61,6 @@ #define RG_PE1_FRC_MSTCKDIV BIT(5) -#define XTAL_MASK GENMASK(8, 6) - #define MAX_PHYS 2 /** @@ -71,6 +68,7 @@ * @dev: pointer to device * @regmap: kernel regmap pointer * @phy: pointer to the kernel PHY device + * @sys_clk: pointer to the system XTAL clock * @port_base: base register * @has_dual_port: if the phy has dual ports. * @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst' @@ -80,6 +78,7 @@ struct mt7621_pci_phy { struct device *dev; struct regmap *regmap; struct phy *phy; + struct clk *sys_clk; void __iomem *port_base; bool has_dual_port; bool bypass_pipe_rst; @@ -116,12 +115,14 @@ static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy) } } -static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) +static int mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) { struct device *dev = phy->dev; - u32 xtal_mode; + unsigned long clk_rate; - xtal_mode = FIELD_GET(XTAL_MASK, rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0)); + clk_rate = clk_get_rate(phy->sys_clk); + if (!clk_rate) + return -EINVAL; /* Set PCIe Port PHY to disable SSC */ /* Debug Xtal Type */ @@ -139,13 +140,13 @@ static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN); } - if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */ + if (clk_rate == 40000000) { /* 40MHz Xtal */ /* Set Pre-divider ratio (for host mode) */ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x01)); dev_dbg(dev, "Xtal is 40MHz\n"); - } else if (xtal_mode >= 6) { /* 25MHz Xal */ + } else if (clk_rate == 25000000) { /* 25MHz Xal */ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x00)); @@ -196,13 +197,15 @@ static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG, RG_PE1_H_PLL_BR, FIELD_PREP(RG_PE1_H_PLL_BR, 0x00)); - if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */ + if (clk_rate == 40000000) { /* 40MHz Xtal */ /* set force mode enable of da_pe1_mstckdiv */ mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG, RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV, FIELD_PREP(RG_PE1_MSTCKDIV, 0x01) | RG_PE1_FRC_MSTCKDIV); } + + return 0; } static int mt7621_pci_phy_init(struct phy *phy) @@ -212,9 +215,7 @@ static int mt7621_pci_phy_init(struct phy *phy) if (mphy->bypass_pipe_rst) mt7621_bypass_pipe_rst(mphy); - mt7621_set_phy_for_ssc(mphy); - - return 0; + return mt7621_set_phy_for_ssc(mphy); } static int mt7621_pci_phy_power_on(struct phy *phy) @@ -324,6 +325,12 @@ static int mt7621_pci_phy_probe(struct platform_device *pdev) return PTR_ERR(phy->phy); } + phy->sys_clk = devm_clk_get(dev, NULL); + if (IS_ERR(phy->sys_clk)) { + dev_err(dev, "failed to get phy clock\n"); + return PTR_ERR(phy->sys_clk); + } + phy_set_drvdata(phy->phy, phy); provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate); From patchwork Sat May 8 07:09:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 432668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1FA6C43461 for ; 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[83.51.243.231]) by smtp.gmail.com with ESMTPSA id s18sm11740345wro.95.2021.05.08.00.09.35 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 May 2021 00:09:36 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: kishon@ti.com, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH RESEND v2 4/6] phy: ralink: Kconfig: enable COMPILE_TEST on mt7621-pci-phy driver Date: Sat, 8 May 2021 09:09:28 +0200 Message-Id: <20210508070930.5290-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508070930.5290-1-sergio.paracuellos@gmail.com> References: <20210508070930.5290-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org After use the clock apis and avoid custom architecture code this driver can properly be enabled for COMPILE_TEST. Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/ralink/Kconfig b/drivers/phy/ralink/Kconfig index ecc309ba9fee..c2373b30b8a6 100644 --- a/drivers/phy/ralink/Kconfig +++ b/drivers/phy/ralink/Kconfig @@ -4,7 +4,7 @@ # config PHY_MT7621_PCI tristate "MediaTek MT7621 PCI PHY Driver" - depends on RALINK && OF + depends on (RALINK && OF) || COMPILE_TEST select GENERIC_PHY select REGMAP_MMIO help From patchwork Sat May 8 07:09:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 432903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D461EC433ED for ; Sat, 8 May 2021 07:09:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ABB78608FE for ; Sat, 8 May 2021 07:09:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229481AbhEHHKl (ORCPT ); Sat, 8 May 2021 03:10:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229947AbhEHHKl (ORCPT ); Sat, 8 May 2021 03:10:41 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E395C061763 for ; Sat, 8 May 2021 00:09:39 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id t18so11383222wry.1 for ; Sat, 08 May 2021 00:09:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b+GCOf42Gs4UdMdK0477XZHtOpuU44Ecgu3QGsmZOXI=; b=bbTI9rbfa2hFA8sWR0y2bKXkMoIo6lVovlUGSGjC0ORfoxbvPR93j6krx4kaUygRfd poxvM6vH0MqvWkrlwr2vzHcpmYVIfoL/H4gDEqidJG3r0xJof8EipjMlucnWZcuGS1cj yALWhbYzKOcCWElu1TUVMBESQ4n+GNf9bX+mZ0EcISpMTRS5mcz5uKIdVfp7W52e6vE0 mMj/UshBOJd3LcF3oU42XkMK+V6eMOebzIjCySz2mopl0Eqdy7rQ+wlk6PBfB8wBhJTR UMJs+4frkCXHfokVeCQy+agUaUiKY408rhled2W4kVJIOkiQuVQr+YkFCgKc+vCMbgX9 ZZNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b+GCOf42Gs4UdMdK0477XZHtOpuU44Ecgu3QGsmZOXI=; b=VJ7wkxx9xmgO9HWlYwhamW7GmGoKyMSKKWkta65mVrD7NK2F1BkILpAMzbEpT6H2Z6 CtWhLMKXg9PzqyEF00AUsEqUK6BikidiRv18MO8VTTns+T4hEGMcRWGy7k9KEFjg7ZwM baj0jiQKK3PAZ+hKh6rIWD3woqwoZfvBcFmHlODZ1qZLA3rhZq7IGvYm3Abhk2P4zMoK H8+2pzNvoLjg19f+KuB71DFQICMwxr1UXmcpx4UI6yVTQdhnDYGgGywd5z11iomSvE1e tyQy2TNwLj2SglK7yVPJjTNNzlFcBGaoktoBjpO2XttR00sKNwOc3DqFL8WknMj9eTM/ /MAQ== X-Gm-Message-State: AOAM532TwEO2LlUmmgx5XzgWL4SIXMqyrSA7/FcPXHF8utPsCrresjx+ +H5YAV3GXsf4J0HFdX/voRk= X-Google-Smtp-Source: ABdhPJwJtfMcnMXZ71LUD3G3ySl8yYxNXaIZjyjmjxHNi2uX6EC9pMnol3hqM/xKNx6PUUK3mxZH7A== X-Received: by 2002:a5d:6a47:: with SMTP id t7mr17397147wrw.117.1620457777816; Sat, 08 May 2021 00:09:37 -0700 (PDT) Received: from localhost.localdomain (231.red-83-51-243.dynamicip.rima-tde.net. [83.51.243.231]) by smtp.gmail.com with ESMTPSA id s18sm11740345wro.95.2021.05.08.00.09.36 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 May 2021 00:09:37 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: kishon@ti.com, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH RESEND v2 5/6] phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool' Date: Sat, 8 May 2021 09:09:29 +0200 Message-Id: <20210508070930.5290-6-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508070930.5290-1-sergio.paracuellos@gmail.com> References: <20210508070930.5290-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Make dependent on PCI_MT7621 configuration option and mark this pci phy configuration as bool which has more sense. Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/ralink/Kconfig b/drivers/phy/ralink/Kconfig index c2373b30b8a6..ed0c71eff2c4 100644 --- a/drivers/phy/ralink/Kconfig +++ b/drivers/phy/ralink/Kconfig @@ -3,8 +3,8 @@ # PHY drivers for Ralink platforms. # config PHY_MT7621_PCI - tristate "MediaTek MT7621 PCI PHY Driver" - depends on (RALINK && OF) || COMPILE_TEST + bool "MediaTek MT7621 PCI PHY Driver" + depends on (RALINK && OF && PCI_MT7621) || COMPILE_TEST select GENERIC_PHY select REGMAP_MMIO help From patchwork Sat May 8 07:09:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 432667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 222E2C43470 for ; Sat, 8 May 2021 07:09:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0295361458 for ; Sat, 8 May 2021 07:09:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229947AbhEHHKm (ORCPT ); Sat, 8 May 2021 03:10:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229925AbhEHHKl (ORCPT ); Sat, 8 May 2021 03:10:41 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0CF7C061761 for ; Sat, 8 May 2021 00:09:39 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id z6so11379579wrm.4 for ; Sat, 08 May 2021 00:09:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5j0/SkQ5MnH/k0JVcJB2AM+3scDK+wjHcTxj/JFadC8=; b=GA+TKHud80mn4qE30fVhSRtcBi0OjBR1MavRxpfJqh0LQSgNZdUJOY80kToQ1cYmNG f9J159mvua6gFHdBOpfBuF0nXdkmsQEcbmAzpJqpGOhjfncF7mXYrkJDcw1A4+bDvBA3 x68H5TAhq8jY2YgIHk345vZUN/+UAu4VJHd5x2gJrUDfLwyuLr5zqGEJuFe3NrvQPjk+ 5CXvMW3rt3dz5BjNR2nAZ9vwAe8vLEkuw+jmZI4zGInQAqH28zJ/uBg8Pno9/oE57h73 fQDEDMijv6fQPYdxUcdzZ7TgdE6hT333DkE3sIssI0D15Jki6gCEqA4N3VKyfMkCmAMF /dNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5j0/SkQ5MnH/k0JVcJB2AM+3scDK+wjHcTxj/JFadC8=; b=m7aqox/w7fIK+k+F15hAaEHfGjgrKVNgplmZMfishNw15Zs04hXoaxReNYBaHmzUO9 WlYOjQv3vLOxNXNBgSSeOjtz4yu87nXISBJiRKvV3f0UaTMywh1OpO/wtPFq6JzMZQR8 dah0WW/zDdN26H6SD+yLG7qM60LrnkVrmKAbZDaTCNJl/q7ZzzBBRPPrVirPhPWI+KnQ fPxloRgODsPa5tcxBqxifSQRVQX28hsnbfeA5pkjKwAnwCqQtwGsCtTNZmL487POXWk6 l4xUk1DPCkZBu5K3qlPku6ws5nB+W1XyLhUe9ZI+OWevT+9G1Hkx1ks/0xpL2moi55Y7 Kc7A== X-Gm-Message-State: AOAM533tbQHgnDAW5Qhur6itqorBUB0XDGJM8UljD0gWcYGum/AyyopX yisGnjM8N4tDJM5aL3nrQXQ= X-Google-Smtp-Source: ABdhPJwjBXqL1KZBUhuCyAQwuynl0Jh6CqAysR/8Lz1mlmCIOEzf0l/RQ+mHfVULZtM07Z2hKEIZDg== X-Received: by 2002:a5d:525c:: with SMTP id k28mr17406270wrc.158.1620457778811; Sat, 08 May 2021 00:09:38 -0700 (PDT) Received: from localhost.localdomain (231.red-83-51-243.dynamicip.rima-tde.net. [83.51.243.231]) by smtp.gmail.com with ESMTPSA id s18sm11740345wro.95.2021.05.08.00.09.37 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 May 2021 00:09:38 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: kishon@ti.com, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com, kernel test robot Subject: [PATCH RESEND v2 6/6] phy: ralink: phy-mt7621-pci: properly print pointer address Date: Sat, 8 May 2021 09:09:30 +0200 Message-Id: <20210508070930.5290-7-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508070930.5290-1-sergio.paracuellos@gmail.com> References: <20210508070930.5290-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The way of printing the pointer address for the 'port_base' address got into compile warnings on some architectures [-Wpointer-to-int-cast]. Instead of use '%08x' and cast to an 'unsigned int' just make use of '%px' and avoid the cast. To avoid not really needed driver verbosity on normal behaviour change also from 'dev_info' to 'dev_dbg'. Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Reported-by: kernel test robot Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/phy-mt7621-pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/ralink/phy-mt7621-pci.c b/drivers/phy/ralink/phy-mt7621-pci.c index f56ff10b0885..242c5d8b8635 100644 --- a/drivers/phy/ralink/phy-mt7621-pci.c +++ b/drivers/phy/ralink/phy-mt7621-pci.c @@ -273,8 +273,8 @@ static struct phy *mt7621_pcie_phy_of_xlate(struct device *dev, mt7621_phy->has_dual_port = args->args[0]; - dev_info(dev, "PHY for 0x%08x (dual port = %d)\n", - (unsigned int)mt7621_phy->port_base, mt7621_phy->has_dual_port); + dev_dbg(dev, "PHY for 0x%px (dual port = %d)\n", + mt7621_phy->port_base, mt7621_phy->has_dual_port); return mt7621_phy->phy; }