From patchwork Fri Jun 22 16:06:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 139719 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp1052716lji; Fri, 22 Jun 2018 09:08:21 -0700 (PDT) X-Google-Smtp-Source: ADUXVKI0Jk/LCBnh/C851xrzoAybEAG1SwPbVyB2vjVj+5CfIx0hFni+3dDfDvjpWCIuRPQb5k8L X-Received: by 2002:a65:4985:: with SMTP id r5-v6mr1982598pgs.110.1529683701359; Fri, 22 Jun 2018 09:08:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529683701; cv=none; d=google.com; s=arc-20160816; b=mahYDzDmaJspkmVg/yJA9WAE8j5HkTF+OR1VW5CNLbSpXGrdMEm4oozKYSJeK7x7V9 IJ+KExmk1UpcUyrud74r59bqMDUZA8FTRcIvhx/6x3+tVeiBmv46qwlRvP065MPLycF0 bfEEYGfcZqZK3jvHpi75QgPZ8BW6eWOP0bEYqG61BdK1pacHUNLnPTKIwYUzO2j7vPAq Zi8JgJSWH5x/WDxyWbbWL0JXvjY5ceda2SQxocx+ymgnXFI/qfVTmv/+sAZbyq9O91wJ ynTSPBbMPPheUe7cvBJ1CrtmcKddl5x8pYuQU+yySbxvBiqDiGzlxZLhooVm5wF0eB9l Wnow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=v5vvfEGZMfiay+4sJMQnFpe/h/B2T8+PH26onq6v+BI=; b=lFYtFSVnzu0CDccawzmO3gT1CKzEex/wo/rE1eB2XPJmpWyBx2cFF1bwC36pEM40FX 80j5nrBxgwHpNrw1VSkioVPLYz4oUAgQcMb3UFTkjGUUWSw5ZM2QUnHP02XZzOoFQCox 4PARw57J//v2FRsx2YI1TeBKNsEUVzxVCB4sG3wA/wnHZqVGvbDgq4J4wFwYU8KDOXbV 5BmKnYSY5+i/4xGJ4/H+YDaQZdeAgSFp4vmHJIzvHyMIfoW2icA4aveWXUV5l5otA0Ed Z+TlHiuiakqOXtpo3n3iMKOPCB3zbGtphUEOFwmT971aG5gAzG/MirO20NYHfooT8jb8 9XSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=FYLHJJGM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b16-v6si6412433pgv.358.2018.06.22.09.08.21; Fri, 22 Jun 2018 09:08:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=FYLHJJGM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934140AbeFVQIT (ORCPT + 31 others); Fri, 22 Jun 2018 12:08:19 -0400 Received: from conuserg-12.nifty.com ([210.131.2.79]:30586 "EHLO conuserg-12.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933391AbeFVQIP (ORCPT ); Fri, 22 Jun 2018 12:08:15 -0400 Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-12.nifty.com with ESMTP id w5MG6m5c022587; Sat, 23 Jun 2018 01:06:50 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com w5MG6m5c022587 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1529683611; bh=v5vvfEGZMfiay+4sJMQnFpe/h/B2T8+PH26onq6v+BI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FYLHJJGMwHUfApoJm0g3k4Lu0FtrEKepenhM9lf4Xj4Vg9fnChQwCb8pq5n16IQ+R 37E00XOd7Ol1YYzhdDSY40Ugjdesb1Tf+Ba0UezpQXoShOVKlbjvC/JTtmrJT0vXpi +4BRHtVVnewNhWNwO6tCuMfXfrzN0N/66Aebvrnpgxmc/d1uX5KYxkV2yshwX8ITO3 2K4XfLLUKnlh5PuQ/HqYTivBZuVfCHBheE2sagcRxQCKkpn9DO6wqNucx0rCxVA9JW iW+b58LgUwswfvM3eYoSesWjnBRbOyR0hCp/0O3iyJb9MbUDtfSu4+x77rIcXJEYe0 Btji844rZZk4A== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Boris Brezillon Cc: Rob Herring , Miquel Raynal , Richard Weinberger , Masahiro Yamada , linux-kernel@vger.kernel.org, Marek Vasut , Brian Norris , David Woodhouse Subject: [PATCH v4 2/5] mtd: rawnand: denali_dt: use dev as a shorthand of &pdev->dev Date: Sat, 23 Jun 2018 01:06:35 +0900 Message-Id: <1529683598-25783-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529683598-25783-1-git-send-email-yamada.masahiro@socionext.com> References: <1529683598-25783-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The probe function references &pdev->dev many times, and I will add more soon. Add 'dev' as a shorthand. Signed-off-by: Masahiro Yamada Acked-by: Miquel Raynal Reviewed-by: Richard Weinberger Tested-by: Richard Weinberger Reviewed-by: Boris Brezillon --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/mtd/nand/raw/denali_dt.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 5869e90..6b4bd16 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -79,44 +79,45 @@ MODULE_DEVICE_TABLE(of, denali_nand_dt_ids); static int denali_dt_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct resource *res; struct denali_dt *dt; const struct denali_dt_data *data; struct denali_nand_info *denali; int ret; - dt = devm_kzalloc(&pdev->dev, sizeof(*dt), GFP_KERNEL); + dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL); if (!dt) return -ENOMEM; denali = &dt->denali; - data = of_device_get_match_data(&pdev->dev); + data = of_device_get_match_data(dev); if (data) { denali->revision = data->revision; denali->caps = data->caps; denali->ecc_caps = data->ecc_caps; } - denali->dev = &pdev->dev; + denali->dev = dev; denali->irq = platform_get_irq(pdev, 0); if (denali->irq < 0) { - dev_err(&pdev->dev, "no irq defined\n"); + dev_err(dev, "no irq defined\n"); return denali->irq; } res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "denali_reg"); - denali->reg = devm_ioremap_resource(&pdev->dev, res); + denali->reg = devm_ioremap_resource(dev, res); if (IS_ERR(denali->reg)) return PTR_ERR(denali->reg); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); - denali->host = devm_ioremap_resource(&pdev->dev, res); + denali->host = devm_ioremap_resource(dev, res); if (IS_ERR(denali->host)) return PTR_ERR(denali->host); - dt->clk = devm_clk_get(&pdev->dev, NULL); + dt->clk = devm_clk_get(dev, NULL); if (IS_ERR(dt->clk)) { - dev_err(&pdev->dev, "no clk available\n"); + dev_err(dev, "no clk available\n"); return PTR_ERR(dt->clk); } ret = clk_prepare_enable(dt->clk); From patchwork Fri Jun 22 16:06:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 139721 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp1052946lji; Fri, 22 Jun 2018 09:08:33 -0700 (PDT) X-Google-Smtp-Source: ADUXVKK+nKDU2ADppwhInYgwDHAOduIorHiGFJPiWaoRybgVx5IIdfsb6fdX9kQ+cD1t+XG++KsW X-Received: by 2002:a62:1013:: with SMTP id y19-v6mr2385941pfi.166.1529683713190; Fri, 22 Jun 2018 09:08:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529683713; cv=none; d=google.com; s=arc-20160816; b=OzeBxzj8sAfLVexqNKHLTpBhfB9MwtwKspjSmWOnsvnAglTx1nVwQMfVPb9XkJs83M hK3L4Y/EAYwW7sjgbGb7vKvc6eVtZChdkw57TToBFHrsRUAxU3iN/b8VxrYfigQdK4Oy MnepVSvyk7kzXxkkR2ILhGm64W4L45IArkNorZDYrKDgFql8sElEZXaTwZlXt5leWFOW 4xLX9j4dWRnX3LgKTElgt5KOP52xFQuq0L0C9nxVm2q0Kj/FqyPw2m24X2vVzQOJIhyk kkyGEpwznlHIjoWI80LTm9/ueUhMXS47wZAK5Z5Zjl5brY7/z9z5ScameLi4M4a0W2SG AvgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=TY7lBRRVAqb7hx/EXgO/qzEjGYj1dbl+Ee4pESpsL2Q=; b=Jw+0BUJ5rufisGjRkixIwCDz9GQ7PYNaly2VkvF2iV+f+CgxG1TOUsCsD2ZS/s8v0b PDz653nKn/2FNGay9/hdQXn9TABggx9Nqm9qeaOT/zjtpLLHgHUCTfEyOejQ8+qRASAi LH4k23Q/Td29IHKvroK60sbV8B4vBpszmBmM0hx+m3BCLctOAfqRXYVxuFwNurYwsUqo nfPrCEyAMb4OQRDUi5NXAOuKcL7MGFmyvxJqScBjImPYncqwCn1QurRzNLuGuU6b5OQS IK7h1fAHkxXM70xXGZ1IIjouVXWApV7+fIXsLxPms6CCg16oXnyR5cg0+Cv4pFttq/Ko N2hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=zKHPxcNU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u32-v6si6607235pgn.488.2018.06.22.09.08.32; Fri, 22 Jun 2018 09:08:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=zKHPxcNU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934094AbeFVQIR (ORCPT + 31 others); Fri, 22 Jun 2018 12:08:17 -0400 Received: from conuserg-12.nifty.com ([210.131.2.79]:30584 "EHLO conuserg-12.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933047AbeFVQIP (ORCPT ); Fri, 22 Jun 2018 12:08:15 -0400 Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-12.nifty.com with ESMTP id w5MG6m5e022587; Sat, 23 Jun 2018 01:06:52 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com w5MG6m5e022587 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1529683613; bh=TY7lBRRVAqb7hx/EXgO/qzEjGYj1dbl+Ee4pESpsL2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=zKHPxcNUsCGGVRdBjxmTTYeF0rATg1xiIBNStCDDLBx5T/AyTn33ZLDu4N6NFDelW a02MNy8e++zB9dGR76QbOQIdBzyYvGNN7fkKCEc0IQ76rEWByGkPlsxbGI8j65vBdw 98Gs9AzhPTHBeTgZB69/OdyJlR3MRGgwlf32KxyXZ+WGRmiannGXBE0WmtYxCU6rWx V9FH7WRe0QZTtTPpbMugg3zyR2nsFuRYRVAvtyWEh7xAiDijSuUAnF6SjNE6zRQ1E1 vdViTJLaS4aRQ2GHPPCGhdm+eV3Y6fizF6XkuDBGMrFBjfjZcpZEcacQGqrisR3tOp hwQsoLewV705Q== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Boris Brezillon Cc: Rob Herring , Miquel Raynal , Richard Weinberger , Masahiro Yamada , linux-kernel@vger.kernel.org, Marek Vasut , Brian Norris , David Woodhouse Subject: [PATCH v4 4/5] mtd: rawnand: denali_dt: add more clocks based on IP datasheet Date: Sat, 23 Jun 2018 01:06:37 +0900 Message-Id: <1529683598-25783-5-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529683598-25783-1-git-send-email-yamada.masahiro@socionext.com> References: <1529683598-25783-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently, denali_dt.c requires a single anonymous clock, but the Denali User's Guide requires three clocks for this IP: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run This commit supports these named clocks to represent the real hardware. For the backward compatibility, the driver still accepts a single clock just as before. The clk_x_rate is taken from the clock driver again if the named clock "clk_x" is available. This will happen only for future DT, hence the existing DT files are not affected. Signed-off-by: Masahiro Yamada Reviewed-by: Miquel Raynal Reviewed-by: Richard Weinberger Tested-by: Richard Weinberger --- Changes in v4: None Changes in v3: - Change the patch order so that the bug-fix one comes the first Changes in v2: - Split patches into sensible chunks drivers/mtd/nand/raw/denali_dt.c | 53 ++++++++++++++++++++++++++++++++++------ 1 file changed, 45 insertions(+), 8 deletions(-) -- 2.7.4 Reviewed-by: Boris Brezillon diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 6b4bd16..afaae37 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -27,7 +27,9 @@ struct denali_dt { struct denali_nand_info denali; - struct clk *clk; + struct clk *clk; /* core clock */ + struct clk *clk_x; /* bus interface clock */ + struct clk *clk_ecc; /* ECC circuit clock */ }; struct denali_dt_data { @@ -115,28 +117,61 @@ static int denali_dt_probe(struct platform_device *pdev) if (IS_ERR(denali->host)) return PTR_ERR(denali->host); - dt->clk = devm_clk_get(dev, NULL); + /* + * A single anonymous clock is supported for the backward compatibility. + * New platforms should support all the named clocks. + */ + dt->clk = devm_clk_get(dev, "nand"); + if (IS_ERR(dt->clk)) + dt->clk = devm_clk_get(dev, NULL); if (IS_ERR(dt->clk)) { dev_err(dev, "no clk available\n"); return PTR_ERR(dt->clk); } + + dt->clk_x = devm_clk_get(dev, "nand_x"); + if (IS_ERR(dt->clk_x)) + dt->clk_x = NULL; + + dt->clk_ecc = devm_clk_get(dev, "ecc"); + if (IS_ERR(dt->clk_ecc)) + dt->clk_ecc = NULL; + ret = clk_prepare_enable(dt->clk); if (ret) return ret; - /* - * Hardcode the clock rate for the backward compatibility. - * This works for both SOCFPGA and UniPhier. - */ - denali->clk_x_rate = 200000000; + ret = clk_prepare_enable(dt->clk_x); + if (ret) + goto out_disable_clk; + + ret = clk_prepare_enable(dt->clk_ecc); + if (ret) + goto out_disable_clk_x; + + if (dt->clk_x) { + denali->clk_x_rate = clk_get_rate(dt->clk_x); + } else { + /* + * Hardcode the clock rates for the backward compatibility. + * This works for both SOCFPGA and UniPhier. + */ + dev_notice(dev, + "necessary clock is missing. default clock rates are used.\n"); + denali->clk_x_rate = 200000000; + } ret = denali_init(denali); if (ret) - goto out_disable_clk; + goto out_disable_clk_ecc; platform_set_drvdata(pdev, dt); return 0; +out_disable_clk_ecc: + clk_disable_unprepare(dt->clk_ecc); +out_disable_clk_x: + clk_disable_unprepare(dt->clk_x); out_disable_clk: clk_disable_unprepare(dt->clk); @@ -148,6 +183,8 @@ static int denali_dt_remove(struct platform_device *pdev) struct denali_dt *dt = platform_get_drvdata(pdev); denali_remove(&dt->denali); + clk_disable_unprepare(dt->clk_ecc); + clk_disable_unprepare(dt->clk_x); clk_disable_unprepare(dt->clk); return 0; From patchwork Fri Jun 22 16:06:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 139722 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp1054095lji; Fri, 22 Jun 2018 09:09:32 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLfiJJ2uPh8cEnyf02wdBqlEZUBWCw8APNj525s7H8rPPdXuR2LUN/fc3NZyfu13noEXe6t X-Received: by 2002:a62:e903:: with SMTP id j3-v6mr2432467pfh.228.1529683772402; Fri, 22 Jun 2018 09:09:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529683772; cv=none; d=google.com; s=arc-20160816; b=hJfIY9kwnzKYWpiJNNQGmyi+/ok24DAxpqVTWa5QC/Az98oCrmv1SXJsfkC4LIom7Z 3RImFuZ+Qu5T4mwHAVycmQdjiggJdUDoCpmmJXZcjT96BG5rPVkkfmqS90HeoqVzYZpQ FjcULEHUnxLnmQW7xhD5N/mcO/7scCCqo0jvsi329LFSvTRs+osMGb3UZjA/p282HqUC ulojHX22A8iFSSR985qJnC2DbMsyTNS8npcpbqn4QTyBfiN3nuy3GrRwENaBV7fyyV6o ZVNIvoYCGtE+9zoYyOuLfUlXeb3uAqhobhtWBTsv54A4fW1NMsh7ZRfkhIfn3g4ZZeUD TZAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=RdRd6Yl+XblRnr2msBmQhSOsWpPyg+C6om9Qa8TBo4w=; b=Dfqz90oSCzsMQK1BXUcyAzvMQLINvVajjVD2rHYgZ6ELkCYAE6IuGEaDIHpYQ2T+Q1 roLnSR2IjdE2BTX/qZv59Vut+RerKrTKuUBnfIb5UbzpAQONDf68p4/c6ZLrJex3tY6Q ZAdgEX2c8u9JDAVdF+Jg9dBQ9vbDPVJG98krWCr32C5lfQ+BilzPX2ytTDItawkAJH95 8X+SjLFiAp+vEuhF/O3vsd0KCFBLL+Y034dJl5IPSWyzZ4sTL8SlImDH82QzB//cG86O 8fDzQBlPUprnjUaUXTbIy6Frf3/oaBTWvNzhCdPnwTTAqmW35uKB8xECPYyVvUUvUEGR ZDhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b="ig5ABEA/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x1-v6si1797867pga.205.2018.06.22.09.09.32; Fri, 22 Jun 2018 09:09:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b="ig5ABEA/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934327AbeFVQJa (ORCPT + 31 others); Fri, 22 Jun 2018 12:09:30 -0400 Received: from conuserg-12.nifty.com ([210.131.2.79]:30609 "EHLO conuserg-12.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934043AbeFVQIQ (ORCPT ); Fri, 22 Jun 2018 12:08:16 -0400 Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-12.nifty.com with ESMTP id w5MG6m5f022587; Sat, 23 Jun 2018 01:06:53 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com w5MG6m5f022587 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1529683613; bh=RdRd6Yl+XblRnr2msBmQhSOsWpPyg+C6om9Qa8TBo4w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ig5ABEA/+svCNuWmPJ+UvX8vMSQzxSc10N9ZtSuFSLfP9Q40ID0/At9DeFK5akMw8 ReZz29r5q/1e7LfW+dYGFerDaWTFE+h6iwo3V/Qa/dQvSGggBNcvQshsa7C8bd2xwx lZLB4J7b2J8d4gOKbZh1yDuROeIlHTFohWFUoAkr8iAKjhZmFm5mVI6QbzFS+L6e9b ehrhjpsLCDVbG+3wGFvP/iM031bA7c7Sj3ohSQBQjYqvKlzVt8wzovG+4VzuYoZEMM 6W3nMDiTaFVi4dXb+IRWElPKtZqy/p4200XbyQy/Td6xtuz61KixmhOGLxx00yz67y I6J6HaNgR9ajQ== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Boris Brezillon Cc: Rob Herring , Miquel Raynal , Richard Weinberger , Masahiro Yamada , linux-kernel@vger.kernel.org, Marek Vasut , Brian Norris , David Woodhouse Subject: [PATCH v4 5/5] mtd: rawnand: denali: optimize timing parameters for data interface Date: Sat, 23 Jun 2018 01:06:38 +0900 Message-Id: <1529683598-25783-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529683598-25783-1-git-send-email-yamada.masahiro@socionext.com> References: <1529683598-25783-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This commit improves the ->setup_data_interface() hook. The denali_setup_data_interface() needs the frequency of clk_x and the ratio of clk_x / clk. The latter is currently hardcoded in the driver, like this: #define DENALI_CLK_X_MULT 6 The IP datasheet requires that clk_x / clk be 4, 5, or 6. I just chose 6 because it is the most defensive value, but it is not optimal. By getting the clock rate of both "clk" and "clk_x", the driver can compute the timing values more precisely. To not break the existing platforms, the fallback value, 50 MHz is provided. It is true for all upstreamed platforms. Signed-off-by: Masahiro Yamada Reviewed-by: Richard Weinberger Tested-by: Richard Weinberger --- Changes in v4: None Changes in v3: None Changes in v2: - Split patches into sensible chunks drivers/mtd/nand/raw/denali.c | 49 +++++++++++++++++++-------------------- drivers/mtd/nand/raw/denali.h | 1 + drivers/mtd/nand/raw/denali_dt.c | 2 ++ drivers/mtd/nand/raw/denali_pci.c | 1 + 4 files changed, 28 insertions(+), 25 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index 2a302a1..2de46d4 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -51,14 +51,6 @@ MODULE_LICENSE("GPL"); #define DENALI_INVALID_BANK -1 #define DENALI_NR_BANKS 4 -/* - * The bus interface clock, clk_x, is phase aligned with the core clock. The - * clk_x is an integral multiple N of the core clk. The value N is configured - * at IP delivery time, and its available value is 4, 5, or 6. We need to align - * to the largest value to make it work with any possible configuration. - */ -#define DENALI_CLK_X_MULT 6 - static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) { return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); @@ -954,7 +946,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, { struct denali_nand_info *denali = mtd_to_denali(mtd); const struct nand_sdr_timings *timings; - unsigned long t_clk; + unsigned long t_x, mult_x; int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data; int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup; int addr_2_data_mask; @@ -965,15 +957,24 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, return PTR_ERR(timings); /* clk_x period in picoseconds */ - t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); - if (!t_clk) + t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); + if (!t_x) + return -EINVAL; + + /* + * The bus interface clock, clk_x, is phase aligned with the core clock. + * The clk_x is an integral multiple N of the core clk. The value N is + * configured at IP delivery time, and its available value is 4, 5, 6. + */ + mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate); + if (mult_x < 4 || mult_x > 6) return -EINVAL; if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) return 0; /* tREA -> ACC_CLKS */ - acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk); + acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x); acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE); tmp = ioread32(denali->reg + ACC_CLKS); @@ -982,7 +983,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + ACC_CLKS); /* tRWH -> RE_2_WE */ - re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk); + re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x); re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE); tmp = ioread32(denali->reg + RE_2_WE); @@ -991,7 +992,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + RE_2_WE); /* tRHZ -> RE_2_RE */ - re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk); + re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x); re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE); tmp = ioread32(denali->reg + RE_2_RE); @@ -1005,8 +1006,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, * With WE_2_RE properly set, the Denali controller automatically takes * care of the delay; the driver need not set NAND_WAIT_TCCS. */ - we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), - t_clk); + we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE); tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); @@ -1021,7 +1021,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, if (denali->revision < 0x0501) addr_2_data_mask >>= 1; - addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk); + addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x); addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); @@ -1031,7 +1031,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, /* tREH, tWH -> RDWR_EN_HI_CNT */ rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), - t_clk); + t_x); rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE); tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); @@ -1040,11 +1040,10 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); /* tRP, tWP -> RDWR_EN_LO_CNT */ - rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), - t_clk); + rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x); rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), - t_clk); - rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT); + t_x); + rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x); rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE); @@ -1054,8 +1053,8 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); /* tCS, tCEA -> CS_SETUP_CNT */ - cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo, - (int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks, + cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo, + (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks, 0); cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE); @@ -1282,7 +1281,7 @@ int denali_init(struct denali_nand_info *denali) } /* clk rate info is needed for setup_data_interface */ - if (denali->clk_x_rate) + if (denali->clk_rate && denali->clk_x_rate) chip->setup_data_interface = denali_setup_data_interface; ret = nand_scan_ident(mtd, denali->max_banks, NULL); diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index 9ad33d2..1f8feaf 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -300,6 +300,7 @@ struct denali_nand_info { struct nand_chip nand; + unsigned long clk_rate; /* core clock rate */ unsigned long clk_x_rate; /* bus interface clock rate */ int active_bank; /* currently selected bank */ struct device *dev; diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index afaae37..0faaad0 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -150,6 +150,7 @@ static int denali_dt_probe(struct platform_device *pdev) goto out_disable_clk_x; if (dt->clk_x) { + denali->clk_rate = clk_get_rate(dt->clk); denali->clk_x_rate = clk_get_rate(dt->clk_x); } else { /* @@ -158,6 +159,7 @@ static int denali_dt_probe(struct platform_device *pdev) */ dev_notice(dev, "necessary clock is missing. default clock rates are used.\n"); + denali->clk_rate = 50000000; denali->clk_x_rate = 200000000; } diff --git a/drivers/mtd/nand/raw/denali_pci.c b/drivers/mtd/nand/raw/denali_pci.c index 49cb3e1..7c8efc4 100644 --- a/drivers/mtd/nand/raw/denali_pci.c +++ b/drivers/mtd/nand/raw/denali_pci.c @@ -73,6 +73,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) denali->irq = dev->irq; denali->ecc_caps = &denali_pci_ecc_caps; denali->nand.ecc.options |= NAND_ECC_MAXIMIZE; + denali->clk_rate = 50000000; /* 50 MHz */ denali->clk_x_rate = 200000000; /* 200 MHz */ ret = pci_request_regions(dev, DENALI_NAND_NAME);