From patchwork Thu May 6 11:15:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 432264 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6229C43460 for ; Thu, 6 May 2021 11:15:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AB0CB611AC for ; Thu, 6 May 2021 11:15:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234726AbhEFLQg (ORCPT ); Thu, 6 May 2021 07:16:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234717AbhEFLQf (ORCPT ); Thu, 6 May 2021 07:16:35 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E762C061761; Thu, 6 May 2021 04:15:36 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id l24-20020a7bc4580000b029014ac3b80020so5118427wmi.1; Thu, 06 May 2021 04:15:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yB+63PgRDM1iyviDORNDC1cNZU2QIzi0OniCvWqYcas=; b=r5MNcwCk/unl+3evjl1ScAq7BM1g7s0th1VDYBoe31faBujaA8UxZV/AxfibTG4gdg 2CVeoKS2qXJun3cABqZGXijgW3sp/MQbDojoMTOb578htTrFotqlGRUdm9LyvRnVOrgU PJJD7mre6+zIyjlLZj5TLbGfZL0mYCHSDrO8yPS3tumjtsUx3Ydf1noHAYFuTS1YKT0m /oS1eUXTCekbWsKcw/6MHZeNB04mHSc0HxI1njeK3md3VN6LZMNPnK94HPEDGv+zeD4Z nBID16zPinnRGBpsxUPBxUt7xeo+K9oajkJjjdSdH3tot4/a/KffYdjcAnCf55IyNvkK /uVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yB+63PgRDM1iyviDORNDC1cNZU2QIzi0OniCvWqYcas=; b=NhGNeDBJJHeVDBAJy5Pa1jd//OFtyxlNIk9YquaQbLixAjLcGkzVcRtQ+rL7edMYWi 73t1QWRCdB0Dt+MWSNaLpBAUWPJgDjzYudtavNk7bu0yeqnGlN3d7VXXwXWL94SohcrB vFEGz89Rfi6IVdNbpLcYLZiB8Q8RG1BpPUAZv0tehEq8/2R43U0v1TAkK9jXaT+IvAg7 yzjm5eHLcKDuXu7HwcMjTNxYh1wIeB1No3FSoN6B/61kO9Sgy/j+vSQx4JYZkJ3a41NO HcePNEps60S33JrJXYeuccVDSzwgyI8bH2949DUS+BsYOm0CdLTd7hVucZe/0of+sAxQ dUZg== X-Gm-Message-State: AOAM532O23nsalm8RDw3JwYLyHOscKfaN3wpTFiaZA8x1mqrMhura1ee GJIWoE43m/1OqUWXuKNDatY= X-Google-Smtp-Source: ABdhPJwQfzxRYHpKnPIQCx/PqOoEanXnfY+4NyrQ2w7d5BnNcUH2wVkxSbnS4mrZ1TPCAsEetdFZYg== X-Received: by 2002:a7b:cc83:: with SMTP id p3mr3374846wma.170.1620299735254; Thu, 06 May 2021 04:15:35 -0700 (PDT) Received: from localhost.localdomain (231.red-83-51-243.dynamicip.rima-tde.net. [83.51.243.231]) by smtp.gmail.com with ESMTPSA id u5sm3642433wrt.38.2021.05.06.04.15.34 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 May 2021 04:15:34 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: linux-phy@lists.infradead.org, kishon@ti.com, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH 1/5] staging: mt7621-dts: use clock in pci phy nodes Date: Thu, 6 May 2021 13:15:27 +0200 Message-Id: <20210506111531.21978-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506111531.21978-1-sergio.paracuellos@gmail.com> References: <20210506111531.21978-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' Hence we can use the clock in pcie phy nodes to be able to get it from there in driver code. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 5623d542bcf2..001ff8f51033 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -549,12 +549,16 @@ pcie@2,0 { pcie0_phy: pcie-phy@1e149000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e149000 0x0700>; + clocks = <&sysc MT7621_CLK_XTAL>; + clock-names = "sys_clk"; #phy-cells = <1>; }; pcie2_phy: pcie-phy@1e14a000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e14a000 0x0700>; + clocks = <&sysc MT7621_CLK_XTAL>; + clock-names = "sys_clk"; #phy-cells = <1>; }; }; From patchwork Thu May 6 11:15:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 431772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E5DEC43462 for ; Thu, 6 May 2021 11:15:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D02061166 for ; Thu, 6 May 2021 11:15:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234731AbhEFLQg (ORCPT ); Thu, 6 May 2021 07:16:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234722AbhEFLQf (ORCPT ); Thu, 6 May 2021 07:16:35 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 620DAC061574; Thu, 6 May 2021 04:15:37 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id l2so5167746wrm.9; Thu, 06 May 2021 04:15:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bcj0pWWA8nFHZcaEeJrGAFY0Y2i6kRxQp4Wf+dRkrMc=; b=nx33U0MdKytL2LeL/A3OBCQcElimwWw/4yEPpHFwZbFDqisrnuREQLuAZyx6jvlrj5 58b3UFV9rfe94VikNAaI3ueEPEzBPPI+LdGlhP6ZOrbhn0oDAzn2XS6uyOGvYA+2NUb4 5/wGOKqulsUeNdvxzpb+ULOH/m6a1ggvUUwRszekCdlmOPSxOU8HFgjoNrL8JRhlJ1Wz MBgWZ4VCPS70SSWsFZVNMqkVCE1i50s7huEVZEx40X2N5gG7VzNMJO0FJfVyfTpLvAt3 6JrDRkA4VXw94kiB2n0LHLUE7Gywwcn/rSLvDehqTiOqtguPnMQ80xFnsF+znBHRqW6Y DybA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bcj0pWWA8nFHZcaEeJrGAFY0Y2i6kRxQp4Wf+dRkrMc=; b=EBs+HqQkbIC5Lawhv9rI7bDbT2AilmI3omSVE1MSIGOqTpNeF3Bw+JGaa4tzlbiTB+ KeazuXT6sNZtpvD0G+VzZSGVvbnTXbDcvTBEOvgZ1EiMNAttr/hPP7uFjbZTiHiZmfRB w6eygCNW7JvZYty+DXwmj8WT0Moqmg5PvWjjbDwqizAVnA2k8A/cp4RyqKRPfAHTQzkt LdAHkcVg62g2HJipX5VCBU3Pgi4qkCXXJep3Cge25pmbmVoGK24rxSXMJKRkS2k09Qq8 /GVHDTS9Oadxxt7IbWnKeh3QGZiPLQUOBf8iYNH471VoqrJuQqd3vE31/WP0SFolHIke tOAg== X-Gm-Message-State: AOAM5330KYFNRNcvVetRQc99pqhZo3hXEuq5Q9Dv4TC+WufmrTlmu3yC 7xeAyXqROh6pq3Or7Wst64s= X-Google-Smtp-Source: ABdhPJxJ9grl1B/XxF/8opkBocpLHYlo2dk8HqNadhlsu7dvjNCfyEqecrxPRlVTxJXSiMy/6ZpGiQ== X-Received: by 2002:a05:6000:1541:: with SMTP id 1mr4539384wry.364.1620299736213; Thu, 06 May 2021 04:15:36 -0700 (PDT) Received: from localhost.localdomain (231.red-83-51-243.dynamicip.rima-tde.net. [83.51.243.231]) by smtp.gmail.com with ESMTPSA id u5sm3642433wrt.38.2021.05.06.04.15.35 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 May 2021 04:15:35 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: linux-phy@lists.infradead.org, kishon@ti.com, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH 2/5] dt-bindings: phy: mediatek, mt7621-pci-phy: add clock entries Date: Thu, 6 May 2021 13:15:28 +0200 Message-Id: <20210506111531.21978-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506111531.21978-1-sergio.paracuellos@gmail.com> References: <20210506111531.21978-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' Hence update schema with the add of the entries related to clock. Signed-off-by: Sergio Paracuellos --- .../bindings/phy/mediatek,mt7621-pci-phy.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml index 0ccaded3f245..d8614ef8995c 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml @@ -16,6 +16,14 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + description: + PHY reference clock. Must contain an entry in clock-names. + + clock-names: + const: sys_clk + "#phy-cells": const: 1 description: selects if the phy is dual-ported @@ -23,6 +31,8 @@ properties: required: - compatible - reg + - clocks + - clock-names - "#phy-cells" additionalProperties: false @@ -32,5 +42,7 @@ examples: pcie0_phy: pcie-phy@1e149000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e149000 0x0700>; + clocks = <&sysc 0>; + clock-names = "sys_clk"; #phy-cells = <1>; }; From patchwork Thu May 6 11:15:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 432263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F12B8C43460 for ; Thu, 6 May 2021 11:15:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BDA6361166 for ; Thu, 6 May 2021 11:15:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234738AbhEFLQj (ORCPT ); Thu, 6 May 2021 07:16:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234741AbhEFLQh (ORCPT ); Thu, 6 May 2021 07:16:37 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85CC5C061574; Thu, 6 May 2021 04:15:38 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id d4so5171503wru.7; Thu, 06 May 2021 04:15:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VOXi5EtG92mh2v/zZTygCocGHAlghP72W6QLY75l19M=; b=pxzkAsfKZcA/wdsw0ENtktQOC/JOklFuvalj3l4oV2eh/0PVIRtFGwo5o94vuPiHTH Djx8SpTlNUe7L4KNGvCEwHWWtWg0UlV2VTBmJ9R/vNnBL3EHrxKY0dpno4luiMjgxdaB ds2jPVljk9Mh2X8iqqTZdcjKv5E5ZWI+sEf6dt9EA2aOypj8HWQRSEMtVV8arFmAmlCP 935qE5O8zZKRUtSEu1A+lFMHzeSwfcPyVAucB13HRga8hPEReswn9G5k+g3BR5Bh1rLJ yBuf3V3EEva4jUCWi4qvyD4s2Zi5wxFrHrel4Ov1KpsYlFOSUis9eZcZQP8ps2HNxIQC qVTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VOXi5EtG92mh2v/zZTygCocGHAlghP72W6QLY75l19M=; b=aI70Y1fKQqFm2nycD1GTEsS/bdQvJbZseqbo9q4eXBsJMTe3YWT6an3eV8ewfVnas+ gH8h8uFxf45Q+1YdURA1wzKUC3T5/I3I1v/zi60Vo98q1ihhlgENhRGScwrT1IoMdLlo Yb6YcZH9ItvOV9rDttW6hwkxDQXDq1wGXZWTTvKghhKS/76TB1MXJW1PNL5cA0+3kABn JqTkEn/0UhdYaysRNMLnf6j0+RNA5KOU1RoBoD38/5l97cJhgyc4WKyT7B7Y93ZwVV9X PYhpWgFXXk4JY9l6ijwyXa6z2VaDeuvCmIRqUvXCoiKgrV3WISSm+sSbcXcz3nuoX8fy +53A== X-Gm-Message-State: AOAM532RxekN912avuuFEU918Pb7NqMWMKPg6GJjAgdSMRWs+BLJ7OBK n9u0qMgy9AS9uK5CDxxfpLg= X-Google-Smtp-Source: ABdhPJxUEUmG7JhrrHTaTPsA7bglIxKepeD8Syw2pUKT/mf8O1Eob4CIrVJD5cakc4HURRW9j+p0sQ== X-Received: by 2002:adf:f152:: with SMTP id y18mr4480748wro.77.1620299737290; Thu, 06 May 2021 04:15:37 -0700 (PDT) Received: from localhost.localdomain (231.red-83-51-243.dynamicip.rima-tde.net. [83.51.243.231]) by smtp.gmail.com with ESMTPSA id u5sm3642433wrt.38.2021.05.06.04.15.36 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 May 2021 04:15:36 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: linux-phy@lists.infradead.org, kishon@ti.com, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH 3/5] phy: ralink: phy-mt7621-pci: use kernel clock APIS Date: Thu, 6 May 2021 13:15:29 +0200 Message-Id: <20210506111531.21978-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506111531.21978-1-sergio.paracuellos@gmail.com> References: <20210506111531.21978-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' This allow us to properly use kernel clock apis to get the clock frequency needed for the phy configuration instead of use custom architecture code to do the same. Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/phy-mt7621-pci.c | 33 +++++++++++++++++------------ 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/phy/ralink/phy-mt7621-pci.c b/drivers/phy/ralink/phy-mt7621-pci.c index 753cb5bab930..5222edc7be10 100644 --- a/drivers/phy/ralink/phy-mt7621-pci.c +++ b/drivers/phy/ralink/phy-mt7621-pci.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -14,8 +15,6 @@ #include #include #include -#include -#include #define RG_PE1_PIPE_REG 0x02c #define RG_PE1_PIPE_RST BIT(12) @@ -62,8 +61,6 @@ #define RG_PE1_FRC_MSTCKDIV BIT(5) -#define XTAL_MASK GENMASK(8, 6) - #define MAX_PHYS 2 /** @@ -71,6 +68,7 @@ * @dev: pointer to device * @regmap: kernel regmap pointer * @phy: pointer to the kernel PHY device + * @sys_clk: pointer to the system XTAL clock * @port_base: base register * @has_dual_port: if the phy has dual ports. * @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst' @@ -80,6 +78,7 @@ struct mt7621_pci_phy { struct device *dev; struct regmap *regmap; struct phy *phy; + struct clk *sys_clk; void __iomem *port_base; bool has_dual_port; bool bypass_pipe_rst; @@ -116,12 +115,14 @@ static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy) } } -static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) +static int mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) { struct device *dev = phy->dev; - u32 xtal_mode; + unsigned long clk_rate; - xtal_mode = FIELD_GET(XTAL_MASK, rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0)); + clk_rate = clk_get_rate(phy->sys_clk); + if (!clk_rate) + return -EINVAL; /* Set PCIe Port PHY to disable SSC */ /* Debug Xtal Type */ @@ -139,13 +140,13 @@ static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN); } - if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */ + if (clk_rate == 40000000) { /* 40MHz Xtal */ /* Set Pre-divider ratio (for host mode) */ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x01)); dev_dbg(dev, "Xtal is 40MHz\n"); - } else if (xtal_mode >= 6) { /* 25MHz Xal */ + } else if (clk_rate == 25000000) { /* 25MHz Xal */ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x00)); @@ -196,13 +197,15 @@ static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG, RG_PE1_H_PLL_BR, FIELD_PREP(RG_PE1_H_PLL_BR, 0x00)); - if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */ + if (clk_rate == 40000000) { /* 40MHz Xtal */ /* set force mode enable of da_pe1_mstckdiv */ mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG, RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV, FIELD_PREP(RG_PE1_MSTCKDIV, 0x01) | RG_PE1_FRC_MSTCKDIV); } + + return 0; } static int mt7621_pci_phy_init(struct phy *phy) @@ -212,9 +215,7 @@ static int mt7621_pci_phy_init(struct phy *phy) if (mphy->bypass_pipe_rst) mt7621_bypass_pipe_rst(mphy); - mt7621_set_phy_for_ssc(mphy); - - return 0; + return mt7621_set_phy_for_ssc(mphy); } static int mt7621_pci_phy_power_on(struct phy *phy) @@ -324,6 +325,12 @@ static int mt7621_pci_phy_probe(struct platform_device *pdev) return PTR_ERR(phy->phy); } + phy->sys_clk = devm_clk_get(dev, "sys_clk"); + if (IS_ERR(phy->sys_clk)) { + dev_err(dev, "failed to get phy clock\n"); + return PTR_ERR(phy->sys_clk); + } + phy_set_drvdata(phy->phy, phy); provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate); From patchwork Thu May 6 11:15:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 431771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83FD2C433B4 for ; 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[83.51.243.231]) by smtp.gmail.com with ESMTPSA id u5sm3642433wrt.38.2021.05.06.04.15.37 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 May 2021 04:15:37 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: linux-phy@lists.infradead.org, kishon@ti.com, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH 4/5] phy: ralink: Kconfig: enable COMPILE_TEST on mt7621-pci-phy driver Date: Thu, 6 May 2021 13:15:30 +0200 Message-Id: <20210506111531.21978-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506111531.21978-1-sergio.paracuellos@gmail.com> References: <20210506111531.21978-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org After use the clock apis and avoid custom architecture code this driver can properly be enabled for COMPILE_TEST. Signed-off-by: Sergio Paracuellos Reported-by: kernel test robot --- drivers/phy/ralink/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/ralink/Kconfig b/drivers/phy/ralink/Kconfig index ecc309ba9fee..c2373b30b8a6 100644 --- a/drivers/phy/ralink/Kconfig +++ b/drivers/phy/ralink/Kconfig @@ -4,7 +4,7 @@ # config PHY_MT7621_PCI tristate "MediaTek MT7621 PCI PHY Driver" - depends on RALINK && OF + depends on (RALINK && OF) || COMPILE_TEST select GENERIC_PHY select REGMAP_MMIO help From patchwork Thu May 6 11:15:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 432262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C87D6C43460 for ; Thu, 6 May 2021 11:15:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9DA7261168 for ; Thu, 6 May 2021 11:15:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234790AbhEFLQo (ORCPT ); Thu, 6 May 2021 07:16:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234736AbhEFLQj (ORCPT ); Thu, 6 May 2021 07:16:39 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72B22C061763; Thu, 6 May 2021 04:15:40 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id d4so5171596wru.7; Thu, 06 May 2021 04:15:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MT2OIJc0hWlPnCiaadINGKimv/o5gd+Xz7S2c7tjZ5A=; b=h2C/opMO/xlErlLNdiKWB3MBoV9Axf3M2fUjM5MeerPmbEYvsRMkdruuYJ+Us0E5yq FT/fa11B721XvsrdmV6OvnjhXN/xlJV5b2XuhiTGHANyvmiejdl8nMKH58WacAG9RTRz SwtigXWJKmFu+uwaQFVuMYeshCZgBeEdpYhfMP183k7c8uyMcXLS1uKBUpUPT1FoqJcL A/muttqnqY2WM+XULu4FuRtd6y2UXI9udvDwYHZAGYunuKQnbr7toKT2EMyT6wSZXGj4 0SThp8n/d6QywFcL8KaXTmFex/ziy1EpTG8pHgBvVtPTeJSpBtbsCmOirP+4mpdZ0Irc ydNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MT2OIJc0hWlPnCiaadINGKimv/o5gd+Xz7S2c7tjZ5A=; b=YvLzIi1z7RhxFgPzEZfw2IqeAe74GOBOGGhzi7xfeiqrpHSLZIhLiAnCPPx5RfxL2f YsvpbURbnkSu4HKcBQ6/kbnLoh4AXbyTVMkB8hZZf8pqRgpoLqZ8r2c0kvcrBjRpkyq0 xeUWnvoxPghO9PaFNah/Lc3Ehqtz6L2vgDw1hQCzy4G802DeynLW7637ql5VOdWduCql hIHQz0R6wBr0XqoT5Q1k7taf8czMfhOKmkUNb52pTpQTjdILlL+vlK6L08W0GJVG3QkT eScfBDyL5QTqvaOHfkITcqXt3cQ9W8TvcZyaIT+Czhde3b++3fj+lu8MLdvPT2Ov8az5 6I2A== X-Gm-Message-State: AOAM530TfH8BxgJGxVRxnacaYdWSVKcuCUml/ZSpGDeqMasw0kh5ONHg Ok8AchD/s5/dIhUFryIknG+LUfR2L3tAOA== X-Google-Smtp-Source: ABdhPJzGyRIuyk5j7KRK+KqSfoclECQr1Gfb2VaxcdMsLESXtKRSzk91U979iL7Z8FNB3REDhwBNRA== X-Received: by 2002:adf:ec4f:: with SMTP id w15mr4479506wrn.122.1620299739235; Thu, 06 May 2021 04:15:39 -0700 (PDT) Received: from localhost.localdomain (231.red-83-51-243.dynamicip.rima-tde.net. [83.51.243.231]) by smtp.gmail.com with ESMTPSA id u5sm3642433wrt.38.2021.05.06.04.15.38 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 May 2021 04:15:38 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: linux-phy@lists.infradead.org, kishon@ti.com, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH 5/5] phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool' Date: Thu, 6 May 2021 13:15:31 +0200 Message-Id: <20210506111531.21978-6-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506111531.21978-1-sergio.paracuellos@gmail.com> References: <20210506111531.21978-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Make dependant on PCI_MT7621 configuration option and mark this pci phy configuration as bool which has more sense. Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/ralink/Kconfig b/drivers/phy/ralink/Kconfig index c2373b30b8a6..ed0c71eff2c4 100644 --- a/drivers/phy/ralink/Kconfig +++ b/drivers/phy/ralink/Kconfig @@ -3,8 +3,8 @@ # PHY drivers for Ralink platforms. # config PHY_MT7621_PCI - tristate "MediaTek MT7621 PCI PHY Driver" - depends on (RALINK && OF) || COMPILE_TEST + bool "MediaTek MT7621 PCI PHY Driver" + depends on (RALINK && OF && PCI_MT7621) || COMPILE_TEST select GENERIC_PHY select REGMAP_MMIO help