From patchwork Sun May 2 23:06:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47367C433B4 for ; Sun, 2 May 2021 23:07:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 19AD861057 for ; Sun, 2 May 2021 23:07:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232401AbhEBXIJ (ORCPT ); Sun, 2 May 2021 19:08:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230036AbhEBXII (ORCPT ); Sun, 2 May 2021 19:08:08 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CF09C06174A; Sun, 2 May 2021 16:07:16 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id i3so4297147edt.1; Sun, 02 May 2021 16:07:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=YV5eZFougkqLFomRpziIWM5ZZI90CmJhUMytWBI8Wm4=; b=rd0W9tymiNxIFuUmY+vuiJfgGh9N2rTEEGxZgWNKZJTKmqCcYt0LQJDDKkRUDsmf+m 4FbmTuZ6eUMxzjaapNf+kxxl0e+1IAbQSICzahVmb18Q5FmiQWmp/sKTKeHyaSKeDJs7 fuOyruNbELKFcG7nt0Da1xlWaVyg9FiCkpnoCvrchmyJQUKHvjh9IYzHBPEfb9l7PobQ L/5Xq2rITf11MwguHP/T/bA38wEDQiaabksvnSCLFxu+5H6PPXixvBYi0qwvNJYtDH0X szrVpJnB9vD9D6MZijm676LkbKGxWWfEmo3sEpqPqIcgFfbdg5iXKIVE0f2Sus2W1ple zH9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=YV5eZFougkqLFomRpziIWM5ZZI90CmJhUMytWBI8Wm4=; b=D+kkbK9CQJYXiB5Orze5H4nm37rVc4Mi2TbsOHonCktqtKCTkXkjWJA685aZI2crVr ChSUYH+ncuqh3CVKhRU7qJULaOFDC9jHKcWh+JGb6vNlr0VcPdc8OT7C51Sm6tBJA371 35S83Gw3+tNdNe3Q4XnkK6xBPTA0g/8xTJCU2yucgVseQ+JqsVr3rCRgT4xoxE+S0ZJZ 85d/+647XCQotgwx1MvGc13tQIKgovU6S7xa+51qNh3JYjHKwjE/uYGHAPNWkyTTypct P7sT55iJAeLbFXxWBAfamP0ZVA2EwGGD/7gk7M9mP4huFaFPx8Vbmp/G6QwCwIY5jMpX rrBg== X-Gm-Message-State: AOAM531djw9wRODtmuZBDpp7fFYalUSW4c5k+hGnbzoI7pxpCG8yy4DC eZvhLDbku37VsXt+C4kAmzPcuBvyKBQN+A== X-Google-Smtp-Source: ABdhPJwVBh7wJUhGOy1LSnWyvTmgnUG5D+JXXLj51NICpJoi6dhF7Gbx1RciO2S6g2kPvy5Iv74HFw== X-Received: by 2002:aa7:dc4e:: with SMTP id g14mr3688636edu.11.1619996834830; Sun, 02 May 2021 16:07:14 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:14 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 01/17] net: mdio: ipq8064: clean whitespaces in define Date: Mon, 3 May 2021 01:06:53 +0200 Message-Id: <20210502230710.30676-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Fix mixed whitespace and tab for define spacing. Signed-off-by: Ansuel Smith --- drivers/net/mdio/mdio-ipq8064.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq8064.c b/drivers/net/mdio/mdio-ipq8064.c index 1bd18857e1c5..fb1614242e13 100644 --- a/drivers/net/mdio/mdio-ipq8064.c +++ b/drivers/net/mdio/mdio-ipq8064.c @@ -15,25 +15,26 @@ #include /* MII address register definitions */ -#define MII_ADDR_REG_ADDR 0x10 -#define MII_BUSY BIT(0) -#define MII_WRITE BIT(1) -#define MII_CLKRANGE_60_100M (0 << 2) -#define MII_CLKRANGE_100_150M (1 << 2) -#define MII_CLKRANGE_20_35M (2 << 2) -#define MII_CLKRANGE_35_60M (3 << 2) -#define MII_CLKRANGE_150_250M (4 << 2) -#define MII_CLKRANGE_250_300M (5 << 2) +#define MII_ADDR_REG_ADDR 0x10 +#define MII_BUSY BIT(0) +#define MII_WRITE BIT(1) +#define MII_CLKRANGE(x) ((x) << 2) +#define MII_CLKRANGE_60_100M MII_CLKRANGE(0) +#define MII_CLKRANGE_100_150M MII_CLKRANGE(1) +#define MII_CLKRANGE_20_35M MII_CLKRANGE(2) +#define MII_CLKRANGE_35_60M MII_CLKRANGE(3) +#define MII_CLKRANGE_150_250M MII_CLKRANGE(4) +#define MII_CLKRANGE_250_300M MII_CLKRANGE(5) #define MII_CLKRANGE_MASK GENMASK(4, 2) #define MII_REG_SHIFT 6 #define MII_REG_MASK GENMASK(10, 6) #define MII_ADDR_SHIFT 11 #define MII_ADDR_MASK GENMASK(15, 11) -#define MII_DATA_REG_ADDR 0x14 +#define MII_DATA_REG_ADDR 0x14 -#define MII_MDIO_DELAY_USEC (1000) -#define MII_MDIO_RETRY_MSEC (10) +#define MII_MDIO_DELAY_USEC (1000) +#define MII_MDIO_RETRY_MSEC (10) struct ipq8064_mdio { struct regmap *base; /* NSS_GMAC0_BASE */ From patchwork Sun May 2 23:06:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C98DC433B4 for ; Sun, 2 May 2021 23:07:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 29D8461284 for ; Sun, 2 May 2021 23:07:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232489AbhEBXIM (ORCPT ); Sun, 2 May 2021 19:08:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232421AbhEBXIJ (ORCPT ); Sun, 2 May 2021 19:08:09 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3254FC06174A; Sun, 2 May 2021 16:07:17 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id bf4so4253955edb.11; Sun, 02 May 2021 16:07:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P7Z9vR7PmZB+FbpQMXDhgB1Mrkmc9cjF+wzn558Eoxg=; b=dO8MNXghtiBXAlxyb+d9USyiqJRO7/GvRVIVn0H41u8jpDfgxmrqqSZnxEEiG87yIM +2TZdGMJaXX3+WOLfIRGwtBA6EPipczcTkYs0nLUcwhOPfs+OA0m3m5rF4WpEXDEr6/G a8L60vgl+wgesS74zS3zQIeOAtJ3kHdwdy+Y+HFLjT9xqxEjF9KykUqY7Q8TsY3c5BUp 4p9xU36OAnnrqNR2B7mhfIpMncXCPhXK70XxnR05z1OiS5cItw0VV+G/PniDFwP65Lh+ cNM+n3EayInyFMC1bSAR7z7nTUp2SJEDws/gaVArwsK+U9VsUrDSns5/x5UE4/C9777M S7gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P7Z9vR7PmZB+FbpQMXDhgB1Mrkmc9cjF+wzn558Eoxg=; b=R8s0HhiIOWl9aNN6I2vxVkDlYG6gFpvEJAz53XsaEk5T9sS/CNOgNpQrkRafTtqXdO LU8+7pbItQHoBhUWaPvJw7OP/5siJgjEuISc+pUmIgPCw+nKrxJifKJ8cm37haxLhjSd DsCH8gAFAuaEVDZsVPO1pvpC2FRYYCUed9G0JEjHoZBMjOh3N/KwLUmX8Jc9wTFInnkY rp4mjwSgzdojqcxfmPeG6kUwee+c6lsb7cmgEl7EtwyasFBh+EtSdiGB3+lpqjXx90qr i2N6+kGomZMCiyDgV1GH+S8Ur3dCzhRBPJXP/d81lRJgrNnZEisVqeban2bd/4k0Lrxu qQRg== X-Gm-Message-State: AOAM530sJz9C6q0oR+YXVjWtwqK6UpIrmC4NbCbK15V3HNxcZe3uawu9 jC0RzaUcwxAd4OVIG6Bv7Gc= X-Google-Smtp-Source: ABdhPJzPSMWuTrrLqttVmBSbc2cvi30WucIYSerrSCr0BlMY4KVGRfyCur+mY+zkkWHNVWpFWothHQ== X-Received: by 2002:aa7:c2d2:: with SMTP id m18mr16729476edp.96.1619996835872; Sun, 02 May 2021 16:07:15 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:15 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 02/17] net: mdio: ipq8064: switch to write/readl function Date: Mon, 3 May 2021 01:06:54 +0200 Message-Id: <20210502230710.30676-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Use readl/writel function instead of regmap function to make sure no value is cached and align to other similar mdio driver. Signed-off-by: Ansuel Smith --- drivers/net/mdio/mdio-ipq8064.c | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq8064.c b/drivers/net/mdio/mdio-ipq8064.c index fb1614242e13..8ae5379eda9d 100644 --- a/drivers/net/mdio/mdio-ipq8064.c +++ b/drivers/net/mdio/mdio-ipq8064.c @@ -37,7 +37,7 @@ #define MII_MDIO_RETRY_MSEC (10) struct ipq8064_mdio { - struct regmap *base; /* NSS_GMAC0_BASE */ + void __iomem *base; /* NSS_GMAC0_BASE */ }; static int @@ -45,9 +45,9 @@ ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv) { u32 busy; - return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy, - !(busy & MII_BUSY), MII_MDIO_DELAY_USEC, - MII_MDIO_RETRY_MSEC * USEC_PER_MSEC); + return readl_poll_timeout(priv->base + MII_ADDR_REG_ADDR, busy, + !(busy & MII_BUSY), MII_MDIO_DELAY_USEC, + MII_MDIO_RETRY_MSEC * USEC_PER_MSEC); } static int @@ -55,7 +55,6 @@ ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset) { u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M; struct ipq8064_mdio *priv = bus->priv; - u32 ret_val; int err; /* Reject clause 45 */ @@ -65,15 +64,14 @@ ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset) miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); - regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); + writel(miiaddr, priv->base + MII_ADDR_REG_ADDR); usleep_range(8, 10); err = ipq8064_mdio_wait_busy(priv); if (err) return err; - regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val); - return (int)ret_val; + return (int)readl(priv->base + MII_DATA_REG_ADDR); } static int @@ -86,12 +84,12 @@ ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data) if (reg_offset & MII_ADDR_C45) return -EOPNOTSUPP; - regmap_write(priv->base, MII_DATA_REG_ADDR, data); + writel(data, priv->base + MII_DATA_REG_ADDR); miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); - regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); + writel(miiaddr, priv->base + MII_ADDR_REG_ADDR); usleep_range(8, 10); return ipq8064_mdio_wait_busy(priv); @@ -116,15 +114,9 @@ ipq8064_mdio_probe(struct platform_device *pdev) bus->parent = &pdev->dev; priv = bus->priv; - priv->base = device_node_to_regmap(np); - if (IS_ERR(priv->base)) { - if (priv->base == ERR_PTR(-EPROBE_DEFER)) - return -EPROBE_DEFER; - - dev_err(&pdev->dev, "error getting device regmap, error=%pe\n", - priv->base); + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - } ret = of_mdiobus_register(bus, np); if (ret) From patchwork Sun May 2 23:06:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56E4BC43460 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:16 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 03/17] net: mdio: ipq8064: enlarge sleep after read/write operation Date: Mon, 3 May 2021 01:06:55 +0200 Message-Id: <20210502230710.30676-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org With the use of the qca8k dsa driver, some problem arised related to port status detection. With a load on a specific port (for example a simple speed test), the driver starts to behave in a strange way and garbage data is produced. To address this, enlarge the sleep delay and address a bug for the reg offset 31 that require additional delay for this specific reg. Signed-off-by: Ansuel Smith --- drivers/net/mdio/mdio-ipq8064.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq8064.c b/drivers/net/mdio/mdio-ipq8064.c index 8ae5379eda9d..bba2fb0d6af8 100644 --- a/drivers/net/mdio/mdio-ipq8064.c +++ b/drivers/net/mdio/mdio-ipq8064.c @@ -65,7 +65,7 @@ ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset) ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); writel(miiaddr, priv->base + MII_ADDR_REG_ADDR); - usleep_range(8, 10); + usleep_range(10, 13); err = ipq8064_mdio_wait_busy(priv); if (err) @@ -90,7 +90,14 @@ ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data) ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); writel(miiaddr, priv->base + MII_ADDR_REG_ADDR); - usleep_range(8, 10); + + /* For the specific reg 31 extra time is needed or the next + * read will produce garbage data. + */ + if (reg_offset == 31) + usleep_range(30, 43); + else + usleep_range(10, 13); return ipq8064_mdio_wait_busy(priv); } From patchwork Sun May 2 23:06:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4891AC43461 for ; Sun, 2 May 2021 23:07:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 25EF3613AC for ; Sun, 2 May 2021 23:07:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232622AbhEBXIT (ORCPT ); Sun, 2 May 2021 19:08:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232488AbhEBXIM (ORCPT ); Sun, 2 May 2021 19:08:12 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FAFEC06174A; Sun, 2 May 2021 16:07:19 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id u13so1573405edd.3; Sun, 02 May 2021 16:07:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EKiBURo81wsJ4/lLUH5a5jR3jUHw4EI7m6JCuTtTWYU=; b=OSbLIqidQlgKjpBOsLEzyRcrcOAFEhO1mEnNFns68s3bOoRreDsH/bW9KWmWPcfCNj h9w5t8eX9iCo0pDyP0/IlXOXVA+zTYEwINxK29Qp+O6U979CKNu7XSo+598Gzf+MoSBq RDZ195yMUKqpFXgyPIh+QLT9UDXGN0/BtF+8wFEdOvXAZBYLvpGJWYqKEAAFttqEoVKM De2Ps5zLeEVLL1dha5WcHUQtNwsnQIRIkJ/+JNmcFXgiToHsmF7m2irRlVdRbD1/mouV QIsoJRhYlWDGqgKXfANkCOYxjNGFy+V4w9wqRXrNyD2d0nT4g4XpkouAUeZGc+YhoyxI aMPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EKiBURo81wsJ4/lLUH5a5jR3jUHw4EI7m6JCuTtTWYU=; b=gjgsbh/P+Fqi+r9Q2iTUyQ1N2yEYrplBamELUUva02/+S50VdvGXEP8pvdzC7+K+9Z YWTLty1jdUctIkbw9Z20mP+Y+tQpN/RY0/6y582zrvysddRO7NBGrJKpOL8H4miebeK0 Lp3c/kPcfTp7PaU8pEzfqlJaJl/V6XzsVks0yMKED1ixoZBwDTfN7Kme//ytqhPnHgLA boyKyT+s4M3lT+5pTU+HLRH5k6uBpSyAHgzRvd+BJa2xQislLO63vK2BvqzwgECy//Tl XGSoO2W2jZbnKFPscq9a3qlWLxFAXWFpy8snAAVNlR5rDS37MQ97XatoSgaGbgHKiZ/h 0AsA== X-Gm-Message-State: AOAM533CZbhrFOeYadVGUpSU0vGY7EsI3n2AoSe4UT4S7pSS2rkhaqKl dIyy+tf2Er6AM2LScrxsxqI= X-Google-Smtp-Source: ABdhPJxtZDkHhPmNEUo0ks36gDCt6lqgG83sGbXC/Rlc73PEIO7SZ2UeFwHOigHfyccEFPnX17JaCw== X-Received: by 2002:a05:6402:120c:: with SMTP id c12mr17003302edw.98.1619996838103; Sun, 02 May 2021 16:07:18 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:17 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 04/17] net: dsa: qca8k: rework read/write/set_page to provide error Date: Mon, 3 May 2021 01:06:56 +0200 Message-Id: <20210502230710.30676-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Better handle function qca8k_set_page. Rework read/write function to return an error and rework the driver to handle error from these function. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 405 ++++++++++++++++++++++++++-------------- 1 file changed, 269 insertions(+), 136 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index cdaf9f85a2cb..0678c213065f 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -127,82 +127,105 @@ qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val) "failed to write qca8k 32bit register\n"); } -static void +static int qca8k_set_page(struct mii_bus *bus, u16 page) { if (page == qca8k_current_page) - return; + return 0; - if (bus->write(bus, 0x18, 0, page) < 0) + if (bus->write(bus, 0x18, 0, page)) { dev_err_ratelimited(&bus->dev, "failed to set qca8k page\n"); + return -EBUSY; + } + qca8k_current_page = page; + return 0; } -static u32 -qca8k_read(struct qca8k_priv *priv, u32 reg) +static int +qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *ret_val) { + struct mii_bus *bus = priv->bus; u16 r1, r2, page; - u32 val; + int ret = 0; qca8k_split_addr(reg, &r1, &r2, &page); - mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - qca8k_set_page(priv->bus, page); - val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); + ret = qca8k_set_page(bus, page); + if (ret) + goto exit; - mutex_unlock(&priv->bus->mdio_lock); + *ret_val = qca8k_mii_read32(bus, 0x10 | r2, r1); - return val; +exit: + mutex_unlock(&bus->mdio_lock); + return ret; } -static void +static int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) { + struct mii_bus *bus = priv->bus; u16 r1, r2, page; + int ret = 0; qca8k_split_addr(reg, &r1, &r2, &page); - mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - qca8k_set_page(priv->bus, page); - qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); + ret = qca8k_set_page(bus, page); + if (ret) + goto exit; - mutex_unlock(&priv->bus->mdio_lock); + qca8k_mii_write32(bus, 0x10 | r2, r1, val); + +exit: + mutex_unlock(&bus->mdio_lock); + return ret; } -static u32 -qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) +static int +qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val, u32 *ret_val) { + struct mii_bus *bus = priv->bus; u16 r1, r2, page; - u32 ret; + int ret = 0; qca8k_split_addr(reg, &r1, &r2, &page); - mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - qca8k_set_page(priv->bus, page); - ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); - ret &= ~mask; - ret |= val; - qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret); + qca8k_set_page(bus, page); + if (ret) + goto exit; - mutex_unlock(&priv->bus->mdio_lock); + *ret_val = qca8k_mii_read32(bus, 0x10 | r2, r1); + *ret_val &= ~mask; + *ret_val |= val; + qca8k_mii_write32(bus, 0x10 | r2, r1, ret); +exit: + mutex_unlock(&bus->mdio_lock); return ret; } -static void +static int qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val) { - qca8k_rmw(priv, reg, 0, val); + u32 ret_val; + + return qca8k_rmw(priv, reg, 0, val, &ret_val); } -static void +static int qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val) { - qca8k_rmw(priv, reg, val, 0); + u32 ret_val; + + return qca8k_rmw(priv, reg, val, 0, &ret_val); } static int @@ -210,9 +233,7 @@ qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) { struct qca8k_priv *priv = (struct qca8k_priv *)ctx; - *val = qca8k_read(priv, reg); - - return 0; + return qca8k_read(priv, reg, val); } static int @@ -220,9 +241,7 @@ qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val) { struct qca8k_priv *priv = (struct qca8k_priv *)ctx; - qca8k_write(priv, reg, val); - - return 0; + return qca8k_write(priv, reg, val); } static const struct regmap_range qca8k_readable_ranges[] = { @@ -263,15 +282,18 @@ static int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) { unsigned long timeout; + int ret; + u32 val; timeout = jiffies + msecs_to_jiffies(20); /* loop until the busy flag has cleared */ do { - u32 val = qca8k_read(priv, reg); - int busy = val & mask; + ret = qca8k_read(priv, reg, &val); + if (ret) + continue; - if (!busy) + if (!(val & mask)) break; cond_resched(); } while (!time_after_eq(jiffies, timeout)); @@ -279,15 +301,18 @@ qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) return time_after_eq(jiffies, timeout); } -static void +static int qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) { u32 reg[4]; - int i; + int ret, i; /* load the ARL table into an array */ - for (i = 0; i < 4; i++) - reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4)); + for (i = 0; i < 4; i++) { + ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg + i); + if (ret) + return ret; + } /* vid - 83:72 */ fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M; @@ -302,6 +327,8 @@ qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff; fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff; fdb->mac[5] = reg[0] & 0xff; + + return 0; } static void @@ -334,6 +361,7 @@ static int qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) { u32 reg; + int ret; /* Set the command and FDB index */ reg = QCA8K_ATU_FUNC_BUSY; @@ -344,7 +372,9 @@ qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) } /* Write the function register triggering the table access */ - qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); + ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); + if (ret) + return ret; /* wait for completion */ if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY)) @@ -352,7 +382,9 @@ qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) /* Check for table full violation when adding an entry */ if (cmd == QCA8K_FDB_LOAD) { - reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC); + ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, ®); + if (ret) + return ret; if (reg & QCA8K_ATU_FUNC_FULL) return -1; } @@ -363,14 +395,17 @@ qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) static int qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port) { - int ret; + int ret, ret_val; qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging); - ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port); - if (ret >= 0) - qca8k_fdb_read(priv, fdb); + ret_val = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port); + if (ret_val >= 0) { + ret = qca8k_fdb_read(priv, fdb); + if (ret) + return ret; + } - return ret; + return ret_val; } static int @@ -412,6 +447,7 @@ static int qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) { u32 reg; + int ret; /* Set the command and VLAN index */ reg = QCA8K_VTU_FUNC1_BUSY; @@ -419,7 +455,9 @@ qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) reg |= vid << QCA8K_VTU_FUNC1_VID_S; /* Write the function register triggering the table access */ - qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); + ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); + if (ret) + return ret; /* wait for completion */ if (qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY)) @@ -427,7 +465,9 @@ qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) /* Check for table full violation when adding an entry */ if (cmd == QCA8K_VLAN_LOAD) { - reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC1); + ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, ®); + if (ret) + return ret; if (reg & QCA8K_VTU_FUNC1_FULL) return -ENOMEM; } @@ -453,7 +493,9 @@ qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged) if (ret < 0) goto out; - reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0); + ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); + if (ret) + return ret; reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN; reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port)); if (untagged) @@ -463,7 +505,9 @@ qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged) reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_S(port); - qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); + ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); + if (ret) + return ret; ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); out: @@ -484,7 +528,9 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) if (ret < 0) goto out; - reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0); + ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); + if (ret) + return ret; reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port)); reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_S(port); @@ -504,7 +550,9 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) if (del) { ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid); } else { - qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); + ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); + if (ret) + return ret; ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); } @@ -514,15 +562,29 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) return ret; } -static void +static int qca8k_mib_init(struct qca8k_priv *priv) { + int ret; + mutex_lock(&priv->reg_mutex); - qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); - qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); - qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); - qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); + ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); + if (ret) + goto exit; + + ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); + if (ret) + goto exit; + + ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); + if (ret) + goto exit; + + ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); + +exit: mutex_unlock(&priv->reg_mutex); + return ret; } static void @@ -559,6 +621,7 @@ static int qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) { u32 phy, val; + int ret; if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) return -EINVAL; @@ -572,7 +635,9 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) QCA8K_MDIO_MASTER_REG_ADDR(regnum) | QCA8K_MDIO_MASTER_DATA(data); - qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + if (ret) + return ret; return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, QCA8K_MDIO_MASTER_BUSY); @@ -582,6 +647,7 @@ static int qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) { u32 phy, val; + int ret; if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) return -EINVAL; @@ -594,14 +660,19 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | QCA8K_MDIO_MASTER_REG_ADDR(regnum); - qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + if (ret) + return ret; if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, QCA8K_MDIO_MASTER_BUSY)) return -ETIMEDOUT; - val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) & - QCA8K_MDIO_MASTER_DATA_MASK); + ret = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL, &val); + if (ret) + return ret; + + val &= QCA8K_MDIO_MASTER_DATA_MASK; return val; } @@ -683,9 +754,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) * a dt-overlay and driver reload changed the configuration */ - qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_EN); - return 0; + return qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); } priv->ops.phy_read = qca8k_phy_read; @@ -698,6 +768,7 @@ qca8k_setup(struct dsa_switch *ds) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; int ret, i; + u32 ret_val; /* Make sure that port 0 is the cpu port */ if (!dsa_is_cpu_port(ds, 0)) { @@ -718,69 +789,98 @@ qca8k_setup(struct dsa_switch *ds) return ret; /* Enable CPU Port */ - qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, - QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); + ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, + QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); + if (ret) { + pr_err("failed enabling CPU port"); + return ret; + } /* Enable MIB counters */ - qca8k_mib_init(priv); + ret = qca8k_mib_init(priv); + if (ret) + pr_warn("mib init failed"); /* Enable QCA header mode on the cpu port */ - qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); + ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), + QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | + QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); + if (ret) { + pr_err("failed enabling QCA header mode"); + return ret; + } /* Disable forwarding by default on all ports */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_MEMBER, 0); + for (i = 0; i < QCA8K_NUM_PORTS; i++) { + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), + QCA8K_PORT_LOOKUP_MEMBER, 0, &ret_val); + if (ret) + return ret; + } /* Disable MAC by default on all ports */ for (i = 1; i < QCA8K_NUM_PORTS; i++) qca8k_port_set_status(priv, i, 0); /* Forward all unknown frames to CPU port for Linux processing */ - qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | - BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); + ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, + BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | + BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | + BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | + BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); + if (ret) + return ret; /* Setup connection between CPU port & user ports */ for (i = 0; i < QCA8K_NUM_PORTS; i++) { /* CPU port gets connected to all user ports of the switch */ if (dsa_is_cpu_port(ds, i)) { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), - QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), + QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds), + &ret_val); + if (ret) + return ret; } /* Individual user ports get connected to CPU port only */ if (dsa_is_user_port(ds, i)) { int shift = 16 * (i % 2); - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_MEMBER, - BIT(QCA8K_CPU_PORT)); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), + QCA8K_PORT_LOOKUP_MEMBER, + BIT(QCA8K_CPU_PORT), &ret_val); + if (ret) + return ret; /* Enable ARP Auto-learning by default */ - qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_LEARN); + ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i), + QCA8K_PORT_LOOKUP_LEARN); + if (ret) + return ret; /* For port based vlans to work we need to set the * default egress vid */ - qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), - 0xfff << shift, - QCA8K_PORT_VID_DEF << shift); - qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i), - QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | - QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); + ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), + 0xfff << shift, + QCA8K_PORT_VID_DEF << shift, + &ret_val); + if (ret) + return ret; + ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i), + QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | + QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); + if (ret) + return ret; } } /* Setup our port MTUs to match power on defaults */ for (i = 0; i < QCA8K_NUM_PORTS; i++) priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; - qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); + ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); + if (ret) + pr_warn("failed setting MTU settings"); /* Flush the FDB table */ qca8k_fdb_flush(priv); @@ -857,7 +957,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN); /* Enable/disable SerDes auto-negotiation as necessary */ - val = qca8k_read(priv, QCA8K_REG_PWS); + qca8k_read(priv, QCA8K_REG_PWS, &val); if (phylink_autoneg_inband(mode)) val &= ~QCA8K_PWS_SERDES_AEN_DIS; else @@ -865,7 +965,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, qca8k_write(priv, QCA8K_REG_PWS, val); /* Configure the SGMII parameters */ - val = qca8k_read(priv, QCA8K_REG_SGMII_CTRL); + qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val); val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD; @@ -955,8 +1055,11 @@ qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port, { struct qca8k_priv *priv = ds->priv; u32 reg; + int ret; - reg = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port)); + ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), ®); + if (ret) + return ret; state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP); state->an_complete = state->link; @@ -1057,18 +1160,27 @@ qca8k_get_ethtool_stats(struct dsa_switch *ds, int port, { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; const struct qca8k_mib_desc *mib; - u32 reg, i; + u32 reg, i, val; + int ret; u64 hi; for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) { mib = &ar8327_mib[i]; reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset; - data[i] = qca8k_read(priv, reg); + ret = qca8k_read(priv, reg, &val); + if (ret) + continue; + if (mib->size == 2) { - hi = qca8k_read(priv, reg + 4); - data[i] |= hi << 32; + ret = qca8k_read(priv, reg + 4, (u32 *)&hi); + if (ret) + continue; } + + data[i] = val; + if (mib->size == 2) + data[i] |= hi << 32; } } @@ -1087,17 +1199,22 @@ qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee) struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port); u32 reg; + int ret; mutex_lock(&priv->reg_mutex); - reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL); + ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, ®); + if (ret) + goto exit; + if (eee->eee_enabled) reg |= lpi_en; else reg &= ~lpi_en; - qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); - mutex_unlock(&priv->reg_mutex); + ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); - return 0; +exit: + mutex_unlock(&priv->reg_mutex); + return ret; } static int @@ -1111,7 +1228,7 @@ static void qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - u32 stp_state; + u32 stp_state, ret_val; switch (state) { case BR_STATE_DISABLED: @@ -1133,7 +1250,8 @@ qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) } qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_STATE_MASK, stp_state); + QCA8K_PORT_LOOKUP_STATE_MASK, stp_state, + &ret_val); } static int @@ -1141,7 +1259,8 @@ qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; int port_mask = BIT(QCA8K_CPU_PORT); - int i; + u32 ret_val; + int i, ret; for (i = 1; i < QCA8K_NUM_PORTS; i++) { if (dsa_to_port(ds, i)->bridge_dev != br) @@ -1149,23 +1268,26 @@ qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br) /* Add this port to the portvlan mask of the other ports * in the bridge */ - qca8k_reg_set(priv, - QCA8K_PORT_LOOKUP_CTRL(i), - BIT(port)); + ret = qca8k_reg_set(priv, + QCA8K_PORT_LOOKUP_CTRL(i), + BIT(port)); + if (ret) + return ret; if (i != port) port_mask |= BIT(i); } - /* Add all other ports to this ports portvlan mask */ - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_MEMBER, port_mask); - return 0; + /* Add all other ports to this ports portvlan mask */ + return qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_MEMBER, port_mask, + &ret_val); } static void qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; + u32 ret_val; int i; for (i = 1; i < QCA8K_NUM_PORTS; i++) { @@ -1183,7 +1305,8 @@ qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br) * this port */ qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT)); + QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT), + &ret_val); } static int @@ -1223,9 +1346,7 @@ qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) mtu = priv->port_mtu[i]; /* Include L2 header / FCS length */ - qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN); - - return 0; + return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN); } static int @@ -1298,18 +1419,22 @@ qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, struct netlink_ext_ack *extack) { struct qca8k_priv *priv = ds->priv; + u32 ret_val; + int ret; if (vlan_filtering) { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_VLAN_MODE, - QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_VLAN_MODE, + QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE, + &ret_val); } else { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_VLAN_MODE, - QCA8K_PORT_LOOKUP_VLAN_MODE_NONE); + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), + QCA8K_PORT_LOOKUP_VLAN_MODE, + QCA8K_PORT_LOOKUP_VLAN_MODE_NONE, + &ret_val); } - return 0; + return ret; } static int @@ -1320,7 +1445,8 @@ qca8k_port_vlan_add(struct dsa_switch *ds, int port, bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; struct qca8k_priv *priv = ds->priv; - int ret = 0; + u32 ret_val; + int ret; ret = qca8k_vlan_add(priv, port, vlan->vid, untagged); if (ret) { @@ -1331,14 +1457,17 @@ qca8k_port_vlan_add(struct dsa_switch *ds, int port, if (pvid) { int shift = 16 * (port % 2); - qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), - 0xfff << shift, vlan->vid << shift); - qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), - QCA8K_PORT_VLAN_CVID(vlan->vid) | - QCA8K_PORT_VLAN_SVID(vlan->vid)); + ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), + 0xfff << shift, vlan->vid << shift, + &ret_val); + if (ret) + return ret; + ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), + QCA8K_PORT_VLAN_CVID(vlan->vid) | + QCA8K_PORT_VLAN_SVID(vlan->vid)); } - return 0; + return ret; } static int @@ -1394,6 +1523,7 @@ static int qca8k_sw_probe(struct mdio_device *mdiodev) { struct qca8k_priv *priv; + int ret; u32 id; /* allocate the private data struct so that we can probe the switches @@ -1421,7 +1551,10 @@ qca8k_sw_probe(struct mdio_device *mdiodev) } /* read the switches ID register */ - id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); + ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &id); + if (ret) + return ret; + id >>= QCA8K_MASK_CTRL_ID_S; id &= QCA8K_MASK_CTRL_ID_M; if (id != QCA8K_ID_QCA8337) From patchwork Sun May 2 23:06:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50FD6C43462 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:18 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 05/17] net: dsa: qca8k: add support for qca8327 switch Date: Mon, 3 May 2021 01:06:57 +0200 Message-Id: <20210502230710.30676-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org qca8327 switch is a low tier version of the more recent qca8337. It does share the same regs used by the qca8k driver and can be supported with minimal change. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 23 ++++++++++++++++++++--- drivers/net/dsa/qca8k.h | 6 ++++++ 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 0678c213065f..acfe072e9430 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1522,6 +1522,7 @@ static const struct dsa_switch_ops qca8k_switch_ops = { static int qca8k_sw_probe(struct mdio_device *mdiodev) { + const struct qca8k_match_data *data; struct qca8k_priv *priv; int ret; u32 id; @@ -1550,6 +1551,11 @@ qca8k_sw_probe(struct mdio_device *mdiodev) gpiod_set_value_cansleep(priv->reset_gpio, 0); } + /* get the switches ID from the compatible */ + data = of_device_get_match_data(&mdiodev->dev); + if (!data) + return -ENODEV; + /* read the switches ID register */ ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &id); if (ret) @@ -1557,8 +1563,10 @@ qca8k_sw_probe(struct mdio_device *mdiodev) id >>= QCA8K_MASK_CTRL_ID_S; id &= QCA8K_MASK_CTRL_ID_M; - if (id != QCA8K_ID_QCA8337) + if (id != data->id) { + dev_err(&mdiodev->dev, "Switch id detected %x but expected %x", id, data->id); return -ENODEV; + } priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); if (!priv->ds) @@ -1623,9 +1631,18 @@ static int qca8k_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, qca8k_suspend, qca8k_resume); +static const struct qca8k_match_data qca832x = { + .id = QCA8K_ID_QCA8327, +}; + +static const struct qca8k_match_data qca833x = { + .id = QCA8K_ID_QCA8337, +}; + static const struct of_device_id qca8k_of_match[] = { - { .compatible = "qca,qca8334" }, - { .compatible = "qca,qca8337" }, + { .compatible = "qca,qca8327", .data = &qca832x }, + { .compatible = "qca,qca8334", .data = &qca833x }, + { .compatible = "qca,qca8337", .data = &qca833x }, { /* sentinel */ }, }; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 7ca4b93e0bb5..86e8d479c9f9 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -15,6 +15,8 @@ #define QCA8K_NUM_PORTS 7 #define QCA8K_MAX_MTU 9000 +#define PHY_ID_QCA8327 0x004dd034 +#define QCA8K_ID_QCA8327 0x12 #define PHY_ID_QCA8337 0x004dd036 #define QCA8K_ID_QCA8337 0x13 @@ -211,6 +213,10 @@ struct ar8xxx_port_status { int enabled; }; +struct qca8k_match_data { + u8 id; +}; + struct qca8k_priv { struct regmap *regmap; struct mii_bus *bus; From patchwork Sun May 2 23:06:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4075DC43460 for ; Sun, 2 May 2021 23:07:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 22F9361057 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:20 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 06/17] devicetree: net: dsa: qca8k: Document new compatible qca8327 Date: Mon, 3 May 2021 01:06:58 +0200 Message-Id: <20210502230710.30676-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for qca8327 in the compatible list. Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index ccbc6d89325d..1daf68e7ae19 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -3,6 +3,7 @@ Required properties: - compatible: should be one of: + "qca,qca8327" "qca,qca8334" "qca,qca8337" From patchwork Sun May 2 23:06:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430550 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E58DC433ED for ; Sun, 2 May 2021 23:07:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E3AE661057 for ; Sun, 2 May 2021 23:07:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232727AbhEBXIa (ORCPT ); Sun, 2 May 2021 19:08:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232561AbhEBXIP (ORCPT ); Sun, 2 May 2021 19:08:15 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCB64C061342; Sun, 2 May 2021 16:07:22 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id j28so4257502edy.9; Sun, 02 May 2021 16:07:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XvWV3QATAdpcnotfieSYs9tCIavWA9iJ+0pfqun32JQ=; b=plGMc6/5voUuFmDHjtYl3GwJWjHrC7kp9N8oivzN5rHFM5RNfb0WSqAayelIXC6G5L jbkfuQcM2WBT/8CHyKzR0PMMGxY0OaeGLmOX1ySiKVK68yXICWGqoocyBzRMgb1+HtO7 aVo+Fp4WkZY1F5wCwqkH5hNkqJNn2g25qaiE7XERQmn5D1EjjHVsMjIQRq/lK/Pd6Vc5 2mjP0qXoUIuKhwZAaL8g+pTiztpx+9g2bPa5lb9u6I7v3GEZySdl2bhiAGKknWUXDyVs Z0vOviSn88JRMLPrk1IFxswiM5YJhtraXjobabuJiJQLqgiM6hN9E4gHZCi8JnxXLaQ6 7mEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XvWV3QATAdpcnotfieSYs9tCIavWA9iJ+0pfqun32JQ=; b=NZIW34gDZvF1prv88bqCLUxit18BDkQL4fowCF6Y5oXcRItGCbAEAXIQKmMC+jW34J 0Eea1QlyWJNMiNOLdD1Z64yeFN2cCl+6mPm1EH0xGlXQBsPiNwvecrdb4mGOrotWjjQ0 KHTT8Nrhs0Aytm/Lrr5LeASqXMRkRiU4PXvgGovVQvvbp/A+ZLhFhtDUDeDlEXBX0MHC mJ7qY4e1Htb4hXlKQt9AQGgwQ/4HZvcVRpmhl4q0UxOoy0SluG5PQ+Gn8hpyPp0zmkYy a7q5t6Z/bmcS9062027duRXlx6R4MG9SrKtv34Nh1GXGRAexl48wMhFcCOgSHF/RqYH9 FMvQ== X-Gm-Message-State: AOAM531zoOzd9SWLRL0TWkpo0DBcog13f4PHWjScsRkjz+5PZjwF5eUO ciqlLPUxdu7olDI0u+q5WtJ6BgmTm4ExLA== X-Google-Smtp-Source: ABdhPJxFkf2XPx6hG1Jt+vbzulLiL/OEBx2gVTcrqdjmCX64qJL6aqLwDjYgd8SxtvshhwiiXEDLRA== X-Received: by 2002:a05:6402:254f:: with SMTP id l15mr17362979edb.189.1619996841446; Sun, 02 May 2021 16:07:21 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:21 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 07/17] net: dsa: qca8k: add priority tweak to qca8337 switch Date: Mon, 3 May 2021 01:06:59 +0200 Message-Id: <20210502230710.30676-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The port 5 of the ar8337 have some problem in flood condition. The original legacy driver had some specific buffer and priority settings for the different port suggested by the QCA switch team. Add this missing settings to improve switch stability under load condition. The packet priority tweak and the rx delay is specific to qca8337. Limit this changes to qca8337 as now we also support 8327 switch. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 55 ++++++++++++++++++++++++++++++++++++++--- drivers/net/dsa/qca8k.h | 24 ++++++++++++++++++ 2 files changed, 76 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index acfe072e9430..a91c9c36c70e 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -767,8 +767,12 @@ static int qca8k_setup(struct dsa_switch *ds) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; + const struct qca8k_match_data *data; + u32 ret_val, mask; int ret, i; - u32 ret_val; + + /* get the switches ID from the compatible */ + data = of_device_get_match_data(priv->dev); /* Make sure that port 0 is the cpu port */ if (!dsa_is_cpu_port(ds, 0)) { @@ -875,6 +879,45 @@ qca8k_setup(struct dsa_switch *ds) } } + if (data->id == QCA8K_ID_QCA8337) { + for (i = 0; i < QCA8K_NUM_PORTS; i++) { + switch (i) { + /* The 2 CPU port and port 5 requires some different + * priority than any other ports. + */ + case 0: + case 5: + case 6: + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) | + QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) | + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e); + break; + default: + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) | + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) | + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19); + } + qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask); + + mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) | + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | + QCA8K_PORT_HOL_CTRL1_WRED_EN; + qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i), + QCA8K_PORT_HOL_CTRL1_ING_BUF | + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | + QCA8K_PORT_HOL_CTRL1_WRED_EN, + mask, &ret_val); + } + } + /* Setup our port MTUs to match power on defaults */ for (i = 0; i < QCA8K_NUM_PORTS; i++) priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; @@ -895,9 +938,13 @@ static void qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { + const struct qca8k_match_data *data; struct qca8k_priv *priv = ds->priv; u32 reg, val; + /* get the switches ID from the compatible */ + data = of_device_get_match_data(priv->dev); + switch (port) { case 0: /* 1st CPU port */ if (state->interface != PHY_INTERFACE_MODE_RGMII && @@ -948,8 +995,10 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, QCA8K_PORT_PAD_RGMII_EN | QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) | QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY)); - qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); + /* QCA8337 requires to set rgmii rx delay */ + if (data->id == QCA8K_ID_QCA8337) + qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); break; case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_1000BASEX: diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 86e8d479c9f9..34c5522e7202 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -166,6 +166,30 @@ #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) #define QCA8K_PORT_LOOKUP_LEARN BIT(20) +#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20) +#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24) +#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24) + +#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) +#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0) +#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0) +#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6) +#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7) +#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8) +#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) + /* Pkt edit registers */ #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2))) From patchwork Sun May 2 23:07:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF61DC433ED for ; Sun, 2 May 2021 23:07:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B8C4261264 for ; Sun, 2 May 2021 23:07:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232768AbhEBXIf (ORCPT ); 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:22 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 08/17] net: dsa: qca8k: add GLOBAL_FC settings needed for qca8327 Date: Mon, 3 May 2021 01:07:00 +0200 Message-Id: <20210502230710.30676-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Switch qca8327 needs special settings for the GLOBAL_FC_THRES regs. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 10 ++++++++++ drivers/net/dsa/qca8k.h | 7 +++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index a91c9c36c70e..3f42d731756c 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -918,6 +918,16 @@ qca8k_setup(struct dsa_switch *ds) } } + /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */ + if (data->id == QCA8K_ID_QCA8327) { + mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) | + QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496); + qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH, + QCA8K_GLOBAL_FC_GOL_XON_THRES_S | + QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S, + mask, &ret_val); + } + /* Setup our port MTUs to match power on defaults */ for (i = 0; i < QCA8K_NUM_PORTS; i++) priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 34c5522e7202..5fb68dbfa85a 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -166,6 +166,12 @@ #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) #define QCA8K_PORT_LOOKUP_LEARN BIT(20) +#define QCA8K_REG_GLOBAL_FC_THRESH 0x800 +#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16) +#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16) +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0) +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0) + #define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) #define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) #define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0) @@ -242,6 +248,7 @@ struct qca8k_match_data { }; struct qca8k_priv { + u8 switch_revision; struct regmap *regmap; struct mii_bus *bus; struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; From patchwork Sun May 2 23:07:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430764 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2662C433B4 for ; Sun, 2 May 2021 23:07:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9BFEA6117A for ; Sun, 2 May 2021 23:07:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232665AbhEBXIl (ORCPT ); Sun, 2 May 2021 19:08:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232545AbhEBXIS (ORCPT ); Sun, 2 May 2021 19:08:18 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0182C06174A; Sun, 2 May 2021 16:07:24 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id b17so1248128ede.0; Sun, 02 May 2021 16:07:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M7IuqxRJ6jU2t1Hv3Nddvu1V+0+EBDkzBN54YvUkIFk=; b=Cd8hnCBRLLmTWTHFbsKHXTj+QlcrZpTjmk4Yf0MSaiLnxyNAqM/32pedYb+7G3Mv2X FLCheRxoG+3uJozJaACCZBoSGSogLpDRTXG15uknq8T2uQHVjVF5ACJgahwrCuhxoJAg +J+GPGjXLBoWDc6CRaO6dqDos+dSoAE6LSYJyf4n2XybtW2UYeQbDmPUfempaDS4K40k XS+wMJQL0MGLHwQN0VLRrJ/zCsWMWOoz3yGn3OGmxHxLAHTcF1nEdQvYGSRpVnLZoGmL NnTZuJrEnR9JIs6jDM05tWXg13Q1yVqOl6TzDDEpcxrcsVGUUnWTAUASLFvG69f825af tpBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M7IuqxRJ6jU2t1Hv3Nddvu1V+0+EBDkzBN54YvUkIFk=; b=adPA13HBsI6kQaNFO3D1sYW8U6ylZnxEjjFa/ZGaG/LNyS8LP4yGL/FE2oeS5XpjfJ +JavESNcyZu0nRYTWCJ1m1mfL1N5BHqyDwSQ2MnDmTUzvN9V+ZgwN4Wg65sNk+SP00sJ +QWm4TlWCaqoHvUBtYNWwtFhkCpMWW0FdP9biuPvYYiRSzWWhzj39asen/VsMdUCpcXp utlrPXnueMCao71Qca1aEM134pUkPZmy4kgYmCtWgVsuYnrqpuXYvN53YXpqSBozP6Ww TFxZ6BOauxon+TS6K39i/8nKTn/dRD2Hs3vmnsafHKUzSTJdYqL9IXgXmG1JfJ5fsLO2 Xwbg== X-Gm-Message-State: AOAM5332Zcho9RPPJg3VS4KX4Fg8OJ9iFEoGPUW80pG5LuKZfCvqesGN uwP7tUN6iQN7xa3/kBVF9Dw= X-Google-Smtp-Source: ABdhPJyQp/zvvXW+y1DD9DV3RhZKfKc7kKRB9gKX9aLiCKe+wJp4RuerGKX7prGvVD+y7g+kOpCVMA== X-Received: by 2002:aa7:d915:: with SMTP id a21mr17553679edr.357.1619996843520; Sun, 02 May 2021 16:07:23 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:23 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 09/17] net: dsa: qca8k: add support for switch rev Date: Mon, 3 May 2021 01:07:01 +0200 Message-Id: <20210502230710.30676-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org qca8k internal phy driver require some special debug value to be set based on the switch revision. Rework the switch id read function to also read the chip revision. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 46 +++++++++++++++++++++++++++-------------- drivers/net/dsa/qca8k.h | 6 ++++-- 2 files changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 3f42d731756c..5478bee39c6e 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1578,13 +1578,39 @@ static const struct dsa_switch_ops qca8k_switch_ops = { .phylink_mac_link_up = qca8k_phylink_mac_link_up, }; +static int qca8k_read_switch_id(struct qca8k_priv *priv) +{ + const struct qca8k_match_data *data; + int ret; + u32 val; + u8 id; + + /* get the switches ID from the compatible */ + data = of_device_get_match_data(priv->dev); + if (!data) + return -ENODEV; + + ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val); + if (ret) + return -ENODEV; + + id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK); + if (id != data->id) { + dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id); + return -ENODEV; + } + + /* Save revision to communicate to the internal PHY driver */ + priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK); + + return 0; +} + static int qca8k_sw_probe(struct mdio_device *mdiodev) { - const struct qca8k_match_data *data; struct qca8k_priv *priv; int ret; - u32 id; /* allocate the private data struct so that we can probe the switches * ID register @@ -1610,23 +1636,11 @@ qca8k_sw_probe(struct mdio_device *mdiodev) gpiod_set_value_cansleep(priv->reset_gpio, 0); } - /* get the switches ID from the compatible */ - data = of_device_get_match_data(&mdiodev->dev); - if (!data) - return -ENODEV; - - /* read the switches ID register */ - ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &id); + /* Check the detected switch id */ + ret = qca8k_read_switch_id(priv); if (ret) return ret; - id >>= QCA8K_MASK_CTRL_ID_S; - id &= QCA8K_MASK_CTRL_ID_M; - if (id != data->id) { - dev_err(&mdiodev->dev, "Switch id detected %x but expected %x", id, data->id); - return -ENODEV; - } - priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); if (!priv->ds) return -ENOMEM; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 5fb68dbfa85a..0b503f78bf92 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -28,8 +28,10 @@ /* Global control registers */ #define QCA8K_REG_MASK_CTRL 0x000 -#define QCA8K_MASK_CTRL_ID_M 0xff -#define QCA8K_MASK_CTRL_ID_S 8 +#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0) +#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0) +#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) +#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) #define QCA8K_REG_PORT0_PAD_CTRL 0x004 #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c From patchwork Sun May 2 23:07:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1EF0C433ED for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:24 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 10/17] net: dsa: qca8k: make rgmii delay configurable Date: Mon, 3 May 2021 01:07:02 +0200 Message-Id: <20210502230710.30676-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The legacy qsdk code used a different delay instead of the max value. Qsdk use 1 ps for rx and 2 ps for tx. Make these values configurable using the standard rx/tx-internal-delay-ps ethernet binding and apply qsdk values by default. The connected gmac doesn't add any delay so no additional delay is added to tx/rx. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 51 +++++++++++++++++++++++++++++++++++++++-- drivers/net/dsa/qca8k.h | 11 +++++---- 2 files changed, 55 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 5478bee39c6e..d522398d504e 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -763,6 +763,47 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv) return 0; } +static int +qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv) +{ + struct device_node *ports, *port; + u32 val; + + ports = of_get_child_by_name(priv->dev->of_node, "ports"); + if (!ports) + return -EINVAL; + + /* Assume only one port with rgmii-id mode */ + for_each_available_child_of_node(ports, port) { + if (!of_property_match_string(port, "phy-mode", "rgmii-id")) + continue; + + if (of_property_read_u32(port, "rx-internal-delay-ps", &val)) + val = 2; + + if (val > QCA8K_MAX_DELAY) { + dev_err(priv->dev, "rgmii rx delay is limited to more than 3ps, setting to the max value"); + priv->rgmii_rx_delay = 3; + } else { + priv->rgmii_rx_delay = val; + } + + if (of_property_read_u32(port, "rx-internal-delay-ps", &val)) + val = 1; + + if (val > QCA8K_MAX_DELAY) { + dev_err(priv->dev, "rgmii tx delay is limited to more than 3ps, setting to the max value"); + priv->rgmii_tx_delay = 3; + } else { + priv->rgmii_rx_delay = val; + } + } + + of_node_put(ports); + + return 0; +} + static int qca8k_setup(struct dsa_switch *ds) { @@ -792,6 +833,10 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; + ret = qca8k_setup_of_rgmii_delay(priv); + if (ret) + return ret; + /* Enable CPU Port */ ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); @@ -1003,8 +1048,10 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, */ qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN | - QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) | - QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY)); + QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) | + QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) | + QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); /* QCA8337 requires to set rgmii rx delay */ if (data->id == QCA8K_ID_QCA8337) qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 0b503f78bf92..80830bb42736 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -36,12 +36,11 @@ #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c #define QCA8K_PORT_PAD_RGMII_EN BIT(26) -#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \ - ((0x8 + (x & 0x3)) << 22) -#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \ - ((0x10 + (x & 0x3)) << 20) -#define QCA8K_MAX_DELAY 3 +#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22) +#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20) +#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25) #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) +#define QCA8K_MAX_DELAY 3 #define QCA8K_PORT_PAD_SGMII_EN BIT(7) #define QCA8K_REG_PWS 0x010 #define QCA8K_PWS_SERDES_AEN_DIS BIT(7) @@ -251,6 +250,8 @@ struct qca8k_match_data { struct qca8k_priv { u8 switch_revision; + u8 rgmii_tx_delay; + u8 rgmii_rx_delay; struct regmap *regmap; struct mii_bus *bus; struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; From patchwork Sun May 2 23:07:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430548 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9481C43460 for ; Sun, 2 May 2021 23:07:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9354C6127A for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:25 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 11/17] net: dsa: qca8k: clear MASTER_EN after phy read/write Date: Mon, 3 May 2021 01:07:03 +0200 Message-Id: <20210502230710.30676-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Clear MDIO_MASTER_EN bit from MDIO_MASTER_CTRL after read/write operation. The MDIO_MASTER_EN bit is not reset after read/write operation and the next operation can be wrongly interpreted by the switch as a mdio operation. This cause a production of wrong/garbage data from the switch and underfined bheavior. (random port drop, unplugged port flagged with link up, wrong port speed) Also on driver remove the MASTER_CTRL can be left set and cause the malfunction of any next driver using the mdio device. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index d522398d504e..f64e3215a515 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -639,8 +639,14 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) if (ret) return ret; - return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); + ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY); + + /* even if the busy_wait timeouts try to clear the MASTER_EN */ + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); + + return ret; } static int @@ -674,6 +680,10 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) val &= QCA8K_MDIO_MASTER_DATA_MASK; + /* even if the busy_wait timeouts try to clear the MASTER_EN */ + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); + return val; } From patchwork Sun May 2 23:07:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FDBFC433B4 for ; Sun, 2 May 2021 23:07:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 749076139A for ; Sun, 2 May 2021 23:07:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232873AbhEBXIp (ORCPT ); Sun, 2 May 2021 19:08:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232640AbhEBXIV (ORCPT ); Sun, 2 May 2021 19:08:21 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E18E2C061756; Sun, 2 May 2021 16:07:27 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id l4so5163808ejc.10; Sun, 02 May 2021 16:07:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KPsZZdgMA7BtF65x6SfTv4t8+0Feb9wvJOWOkienFUs=; b=tT73OGngfrJQoKadgIyzQwP2q6BhkxbShBQJ6WyYwVLr3IruizoeRAJhjAZ3CR0eWt 585grTBrCiaJuJw0BGuG6eZpynQpQYQ7FXBDmPOwEkkeja03MV7hVugw/mjkW/kgi6Bb QWUj8+jrBEbXPp8zHGKWxel4zjXmur2vCBJgK77IZdBA6V8Peg9IihZNVlVE93YOXK1u oTXx5Hp1Rvy6BCKV5YPmkoePjWsM8fiADVjflNZliq6rlTFAbI3ko8QPyXWhee8zHTTg 50KVy0e3KmQJNOE8se7h3gNktfCLnQJxfYd3Caq/gwOmtOSwwoqYft733GWlaADOiNty UPUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KPsZZdgMA7BtF65x6SfTv4t8+0Feb9wvJOWOkienFUs=; b=KyydO2dKrrSno4vfliniGIZgXudpDhFtFVQpduqL2rc2srrlS6hYbUO20pgw731UHa v+5cIN+MGFnS8ciZXwyJq6X2Pk9EkiRjkqtX7nx0HNe8b7IWVy0QQ9g6541TAaRU/qkD 8/iYvfEw1rFCE+6g/S4lneBtcU0y+1bYd0OJN12pqMxPaNufjZedgn4Mm94r1vGfK6kI 0VdRJtMmdDQ2icipjlnBX7tzNJdxpFYimZZeDv//A3D7j/i1xwEcUnxDUgp97T/fkBCH dQTNDOihWWNxLaRADV/J0Oq2SCCVmUBEtJ2if+7JNasUPxkuaf9SbE6riq9v1dx9jJ9+ DOrQ== X-Gm-Message-State: AOAM531LtAW+SLRZ7EF0OtyXJdeWrhgkoeoxSXWhFk7R6PVV5oC4CPMd MJY5uxFPTCrfVDplZOlJm4Q= X-Google-Smtp-Source: ABdhPJxfS76dzh0jBCP4uOyNEM0ak4zEu4+yNAerhVXxezSMxw3trfwXHspIfzGn/TKokLOz3P+XOg== X-Received: by 2002:a17:906:6ace:: with SMTP id q14mr14784849ejs.79.1619996846542; Sun, 02 May 2021 16:07:26 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:26 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 12/17] net: dsa: qca8k: dsa: qca8k: protect MASTER busy_wait with mdio mutex Date: Mon, 3 May 2021 01:07:04 +0200 Message-Id: <20210502230710.30676-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org MDIO_MASTER operation have a dedicated busy wait that is not protected by the mdio mutex. This can cause situation where the MASTER operation is done and a normal operation is executed between the MASTER read/write and the MASTER busy_wait. Rework the qca8k_mdio_read/write function to address this issue by binding the lock for the whole MASTER operation and not only the mdio read/write common operation. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 69 ++++++++++++++++++++++++++++++++++------- 1 file changed, 57 insertions(+), 12 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index f64e3215a515..9a1b28bcaff0 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -617,9 +617,33 @@ qca8k_port_to_phy(int port) return port - 1; } +static int +qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) +{ + unsigned long timeout; + u16 r1, r2, page; + + qca8k_split_addr(reg, &r1, &r2, &page); + + timeout = jiffies + msecs_to_jiffies(20); + + /* loop until the busy flag has cleared */ + do { + u32 val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); + int busy = val & mask; + + if (!busy) + break; + cond_resched(); + } while (!time_after_eq(jiffies, timeout)); + + return time_after_eq(jiffies, timeout); +} + static int qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) { + u16 r1, r2, page; u32 phy, val; int ret; @@ -635,12 +659,22 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) QCA8K_MDIO_MASTER_REG_ADDR(regnum) | QCA8K_MDIO_MASTER_DATA(data); - ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); + + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + + ret = qca8k_set_page(priv->bus, page); if (ret) - return ret; + goto exit; + + qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); - ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); + if (qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY)) + ret = -ETIMEDOUT; + +exit: + mutex_unlock(&priv->bus->mdio_lock); /* even if the busy_wait timeouts try to clear the MASTER_EN */ qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, @@ -652,6 +686,7 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) static int qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) { + u16 r1, r2, page; u32 phy, val; int ret; @@ -666,20 +701,30 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | QCA8K_MDIO_MASTER_REG_ADDR(regnum); - ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); - if (ret) - return ret; + qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); - if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY)) - return -ETIMEDOUT; + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); - ret = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL, &val); + ret = qca8k_set_page(priv->bus, page); if (ret) - return ret; + goto exit; + + qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); + + if (qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY)) + val = -ETIMEDOUT; + else + val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); val &= QCA8K_MDIO_MASTER_DATA_MASK; +exit: + mutex_unlock(&priv->bus->mdio_lock); + + if (val >= 0) + val &= QCA8K_MDIO_MASTER_DATA_MASK; + /* even if the busy_wait timeouts try to clear the MASTER_EN */ qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, QCA8K_MDIO_MASTER_EN); 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:27 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 13/17] net: dsa: qca8k: enlarge mdio delay and timeout Date: Mon, 3 May 2021 01:07:05 +0200 Message-Id: <20210502230710.30676-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org - Enlarge set page delay to QDSK source - Enlarge mdio MASTER timeout busy wait Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 9a1b28bcaff0..7f72504f003a 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -140,6 +140,7 @@ qca8k_set_page(struct mii_bus *bus, u16 page) } qca8k_current_page = page; + usleep_range(1000, 2000); return 0; } @@ -625,7 +626,7 @@ qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) qca8k_split_addr(reg, &r1, &r2, &page); - timeout = jiffies + msecs_to_jiffies(20); + timeout = jiffies + msecs_to_jiffies(2000); /* loop until the busy flag has cleared */ do { From patchwork Sun May 2 23:07:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE0DAC433B4 for ; Sun, 2 May 2021 23:10:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C2D7261057 for ; Sun, 2 May 2021 23:10:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232939AbhEBXIw (ORCPT ); Sun, 2 May 2021 19:08:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232682AbhEBXIX (ORCPT ); Sun, 2 May 2021 19:08:23 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D94EC06174A; Sun, 2 May 2021 16:07:30 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id b25so5208124eju.5; Sun, 02 May 2021 16:07:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6S33qsxdfzNRrx5uD8qxn/D0pG+Cha3VUrhtZ9or8eA=; b=GMSR8+IT91Jetc9jxJURyS2Y1Pi+DiRUCKLIv/RIKiopbaBxWxJnyptWU7mxkXsxFq FrAJPAQlrQxqBl7u5oVE9H3dGC2mRlngx+NtgMOgFgbHRb1WuH9oUUbWBSOP+lBYCExE iy4Zwka0zFPUwu7eZB5RXcmIAS1hKfv28U3eI+cTYOOZ1Cz8uc11eoasg1pny9d9DW8f UHYphsL8RdWcS+VxDgZpdOvt1LFRAfdk6Xu5SmsSyp7lQTG+rjlBfIOmiCpuA39ldnoM Qv46NdGn0trY954ptxAoTWQa5TIsmdeh+o1leLp87cYTZj7u94jaXCUNWkKOSvd+EiS9 4Nsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6S33qsxdfzNRrx5uD8qxn/D0pG+Cha3VUrhtZ9or8eA=; b=SyvswEbv/UqiN4zTfreiCCuyb87bK6FVaLVocyhvbexo5fHoFaFBSb0J6aKJ3smFyL yRmNTmGpZNKjmBBKQKnlWcLtFmmEFRZEyK/chnDZSb1T7G/9vi+tNRH9suO6i+J0tthr TGYYVnF1YMcneYAvJlSU/1vaXkR46T8pZl/S+yKPzrTuqs5jK84dRnA9PLNskvTCsgfP 8bB7JJm8PbaGZ4OsIwwhg+xzcd6vH2h3FjHe0rgD7VqHSNXDk9txtBEuYHGaTeB9kNmV HANrXIIa62oq5GVxzBm3M95rxLhkHeqSkhGEVoWkMnPwu4cskogTi69ahbTE/7jRkZRj 9q2w== X-Gm-Message-State: AOAM531BxJ95Qw6UdRNygmq7FJczOheBq6jo5rB9fUDg6JW/9XhSL5s0 itmePJ9cJKq35uG6G8Ji40E= X-Google-Smtp-Source: ABdhPJx9KOBGhGLbtuv3/swOFbNxuNnCdUmC/zZOPQWFwhcwpiAZV4wYqcVzl5GN6v1KJUPQtEjJ7w== X-Received: by 2002:a17:906:c09:: with SMTP id s9mr14070974ejf.145.1619996849203; Sun, 02 May 2021 16:07:29 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:28 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Nicolas Ferre , Claudiu Beznea , "David S. Miller" , Jakub Kicinski , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Russell King , Andrew Lunn , Heiner Kallweit , Vivien Didelot , Vladimir Oltean , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH net-next v2 14/17] net: phy: phylink: permit to pass dev_flags to phylink_connect_phy Date: Mon, 3 May 2021 01:07:06 +0200 Message-Id: <20210502230710.30676-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for phylink_connect_phy to pass dev_flags to the PHY driver. Change any user of phylink_connect_phy to pass 0 as dev_flags by default. Signed-off-by: Ansuel Smith --- drivers/net/ethernet/cadence/macb_main.c | 2 +- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +- drivers/net/phy/phylink.c | 12 +++++++----- include/linux/phylink.h | 2 +- net/dsa/slave.c | 2 +- 5 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 0f6a6cb7e98d..459243c08b0c 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -834,7 +834,7 @@ static int macb_phylink_connect(struct macb *bp) } /* attach the mac to the phy */ - ret = phylink_connect_phy(bp->phylink, phydev); + ret = phylink_connect_phy(bp->phylink, phydev, 0); } if (ret) { diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 4749bd0af160..ece84bb64b37 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -1099,7 +1099,7 @@ static int stmmac_init_phy(struct net_device *dev) return -ENODEV; } - ret = phylink_connect_phy(priv->phylink, phydev); + ret = phylink_connect_phy(priv->phylink, phydev, 0); } phylink_ethtool_get_wol(priv->phylink, &wol); diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index dc2800beacc3..95f6a10e90ef 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -1018,7 +1018,7 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy, } static int phylink_attach_phy(struct phylink *pl, struct phy_device *phy, - phy_interface_t interface) + phy_interface_t interface, u32 flags) { if (WARN_ON(pl->cfg_link_an_mode == MLO_AN_FIXED || (pl->cfg_link_an_mode == MLO_AN_INBAND && @@ -1028,13 +1028,14 @@ static int phylink_attach_phy(struct phylink *pl, struct phy_device *phy, if (pl->phydev) return -EBUSY; - return phy_attach_direct(pl->netdev, phy, 0, interface); + return phy_attach_direct(pl->netdev, phy, flags, interface); } /** * phylink_connect_phy() - connect a PHY to the phylink instance * @pl: a pointer to a &struct phylink returned from phylink_create() * @phy: a pointer to a &struct phy_device. + * @flags: PHY-specific flags to communicate to the PHY device driver * * Connect @phy to the phylink instance specified by @pl by calling * phy_attach_direct(). Configure the @phy according to the MAC driver's @@ -1046,7 +1047,8 @@ static int phylink_attach_phy(struct phylink *pl, struct phy_device *phy, * * Returns 0 on success or a negative errno. */ -int phylink_connect_phy(struct phylink *pl, struct phy_device *phy) +int phylink_connect_phy(struct phylink *pl, struct phy_device *phy, + u32 flags) { int ret; @@ -1056,7 +1058,7 @@ int phylink_connect_phy(struct phylink *pl, struct phy_device *phy) pl->link_config.interface = pl->link_interface; } - ret = phylink_attach_phy(pl, phy, pl->link_interface); + ret = phylink_attach_phy(pl, phy, pl->link_interface, flags); if (ret < 0) return ret; @@ -2207,7 +2209,7 @@ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy) return ret; interface = pl->link_config.interface; - ret = phylink_attach_phy(pl, phy, interface); + ret = phylink_attach_phy(pl, phy, interface, 0); if (ret < 0) return ret; diff --git a/include/linux/phylink.h b/include/linux/phylink.h index d81a714cfbbd..cd563ba67ca0 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -437,7 +437,7 @@ struct phylink *phylink_create(struct phylink_config *, struct fwnode_handle *, void phylink_set_pcs(struct phylink *, struct phylink_pcs *pcs); void phylink_destroy(struct phylink *); -int phylink_connect_phy(struct phylink *, struct phy_device *); +int phylink_connect_phy(struct phylink *, struct phy_device *, u32 flags); int phylink_of_phy_connect(struct phylink *, struct device_node *, u32 flags); void phylink_disconnect_phy(struct phylink *); diff --git a/net/dsa/slave.c b/net/dsa/slave.c index 992fcab4b552..8ecfcb553ac1 100644 --- a/net/dsa/slave.c +++ b/net/dsa/slave.c @@ -1718,7 +1718,7 @@ static int dsa_slave_phy_connect(struct net_device *slave_dev, int addr) return -ENODEV; } - return phylink_connect_phy(dp->pl, slave_dev->phydev); + return phylink_connect_phy(dp->pl, slave_dev->phydev, 0); } static int dsa_slave_phy_setup(struct net_device *slave_dev) From patchwork Sun May 2 23:07:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D959C43460 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:29 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 15/17] net: dsa: slave: pass dev_flags also to internal PHY Date: Mon, 3 May 2021 01:07:07 +0200 Message-Id: <20210502230710.30676-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support to dsa_slave_phy_connect to properly pass dev_flags if defined by the dsa driver. Signed-off-by: Ansuel Smith --- net/dsa/slave.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/net/dsa/slave.c b/net/dsa/slave.c index 8ecfcb553ac1..339280330357 100644 --- a/net/dsa/slave.c +++ b/net/dsa/slave.c @@ -1707,7 +1707,7 @@ static void dsa_slave_phylink_fixed_state(struct phylink_config *config, } /* slave device setup *******************************************************/ -static int dsa_slave_phy_connect(struct net_device *slave_dev, int addr) +static int dsa_slave_phy_connect(struct net_device *slave_dev, int addr, u32 flags) { struct dsa_port *dp = dsa_slave_to_port(slave_dev); struct dsa_switch *ds = dp->ds; @@ -1718,7 +1718,7 @@ static int dsa_slave_phy_connect(struct net_device *slave_dev, int addr) return -ENODEV; } - return phylink_connect_phy(dp->pl, slave_dev->phydev, 0); + return phylink_connect_phy(dp->pl, slave_dev->phydev, flags); } static int dsa_slave_phy_setup(struct net_device *slave_dev) @@ -1762,7 +1762,7 @@ static int dsa_slave_phy_setup(struct net_device *slave_dev) /* We could not connect to a designated PHY or SFP, so try to * use the switch internal MDIO bus instead */ - ret = dsa_slave_phy_connect(slave_dev, dp->index); + ret = dsa_slave_phy_connect(slave_dev, dp->index, phy_flags); if (ret) { netdev_err(slave_dev, "failed to connect to port %d: %d\n", From patchwork Sun May 2 23:07:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AF73C43461 for ; Sun, 2 May 2021 23:10:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0B5776127A for ; Sun, 2 May 2021 23:10:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232584AbhEBXK4 (ORCPT ); Sun, 2 May 2021 19:10:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232701AbhEBXIZ (ORCPT ); Sun, 2 May 2021 19:08:25 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76BF9C06134A; Sun, 2 May 2021 16:07:32 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id i3so4297555edt.1; Sun, 02 May 2021 16:07:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NKTRQprkTz8Es1vpeCKAiDwS5E2KGCF4GkOy7VVlnTM=; b=RR+R4svU7HfLRIbW1Dg+ftaXQrrRk8ByYL0bivVB14zKPbA3XTTwUEKjupYLcdYE5t A35pwzU+UBxw+yGHkaAZ4r/niC0+IIX5eJGzFlcAZCysgv/Nk264jhvw0a9wDsZfdHwR 5G2UwDTJ4Um2pQa+tlQo/k6ewxFUwpiTRbiV1FhC7Rzj8K1wixckAxHYZ38tx7PuN2bB 6vMa9D6CNOVC+WHTROVN5iBdq677cVrsyO4P9dvbiukqfIKO8ilHLcQvd9Hay86lf0Jm 40Fs0VBm+48f+3wZ99/4wCq1r62WflscgC1R5TAeF9Mw9SV6pQSAeo1boNo1HtsGqy98 LEDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NKTRQprkTz8Es1vpeCKAiDwS5E2KGCF4GkOy7VVlnTM=; b=XslJplmBimrRLRzpQVmijmwq1fcaKcRALIz//CTV9ggKmoPrysjDRoG+oU6KBa1mKW oOhCelobF64YD8cmq6e9G+oM6gZLm3JvUKYw5DbcIjcNU+Y/TKNeqlB7QuekdKifvQTR YrDYlaLSgZ4wr6uvL9TQZHFbe5b8SiBlwm9I3ML3eUsGV7EWduV6EVeb+zR/LiLN57+Y 5rRJaoRvDt3B0lbE5f2fSzK0mp5OmNbzM+77CwPQSKCrd9T4ZWItlB8ehyVytf1f0dcg tsaGYflHa84Vr8k7Z5P6Dhtiu8q0KQF9KqN41FH3NaVCpviiU3TIiQcAejk6feix6JPD n+Bw== X-Gm-Message-State: AOAM533QWQZQYJ9GLgXrRMRnCpAPHl6Fgg9qhwfSgXLN8u2zheNXApJB L2xaeOXNscqSoDCc075ZM8A= X-Google-Smtp-Source: ABdhPJzil6UL6gdwAawl8DttnSW9epvdA2SgFnr0bFzzRh2HoEuaDioZ7AjZXKevFnvtA1pd2YOomQ== X-Received: by 2002:a05:6402:7d1:: with SMTP id u17mr17306853edy.312.1619996851190; Sun, 02 May 2021 16:07:31 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:30 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 16/17] net: dsa: qca8k: pass switch_revision info to phy dev_flags Date: Mon, 3 May 2021 01:07:08 +0200 Message-Id: <20210502230710.30676-16-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Define get_phy_flags to pass switch_Revision needed to tweak the internal PHY with debug values based on the revision. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 7f72504f003a..1be1064586ae 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1646,6 +1646,24 @@ qca8k_port_vlan_del(struct dsa_switch *ds, int port, return ret; } +static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port) +{ + struct qca8k_priv *priv = ds->priv; + + pr_info("revision from phy %d", priv->switch_revision); + + /* Communicate to the phy internal driver the switch revision. + * Based on the switch revision different values needs to be + * set to the dbg and mmd reg on the phy. + * The first 2 bit are used to communicate the switch revision + * to the phy driver. + */ + if (port > 0 && port < 6) + return priv->switch_revision; + + return 0; +} + static enum dsa_tag_protocol qca8k_get_tag_protocol(struct dsa_switch *ds, int port, enum dsa_tag_protocol mp) @@ -1679,6 +1697,7 @@ static const struct dsa_switch_ops qca8k_switch_ops = { .phylink_mac_config = qca8k_phylink_mac_config, .phylink_mac_link_down = qca8k_phylink_mac_link_down, .phylink_mac_link_up = qca8k_phylink_mac_link_up, + .get_phy_flags = qca8k_get_phy_flags, }; static int qca8k_read_switch_id(struct qca8k_priv *priv) From patchwork Sun May 2 23:07:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 430760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1E2DC433B4 for ; Sun, 2 May 2021 23:13:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9D3EA6117A for ; Sun, 2 May 2021 23:13:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232681AbhEBXLA (ORCPT ); Sun, 2 May 2021 19:11:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232630AbhEBXI3 (ORCPT ); Sun, 2 May 2021 19:08:29 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1EF61C061756; Sun, 2 May 2021 16:07:35 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id f24so5193351ejc.6; Sun, 02 May 2021 16:07:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8BSDZrcoNzp9syAi7bEm0jAyw49NztLzfWnEeA37gIc=; b=ZDYVD871lhik5K5mVNlJ99tXYD5swZCiTQt7fWVrl1VA0OiS3x31eEOPDElraz5kTn rCGWJGcUqJ5VS5bhx205wn3ZpFvujHyc2AUR/c+kWWS4YcXs5rJ/BrEYrk8V9DyXdsy1 9/URq5N2nvLCkj92PL9H4ZYdCLmdFDsXVYMwR8WESX1xYBNLed7QHNAXrKSt3MLfO3Yg I8kdwh0OQQqwHbsXqq9CzWlur6FU/fQMD4PcnBy67PkWsr2Btw+zolYjZl4dkWDgEGxy Gfuipwf1O0TA1brqtCA7vwo+vUIzY4fBVTytW+B/hwTl9UTBT54I5NlojhixfHwysPrB o4ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8BSDZrcoNzp9syAi7bEm0jAyw49NztLzfWnEeA37gIc=; b=fbxPgit75rk6Rpbo72VxeWB7NNoaCtRIDiDIWAD3u29DpF2qWS/YZwyOsOXMXYbCTm wqFJQglK/Mz0lHuaL3e9cmmVTd/LrqB6zPkx8hy1hwGvLpYRfjz8GyNYUuCGAR3S+yRC TgldirM/haOp9ao/O6XYZ4HlZKY8AunGMTkAzgQsnwP3pqK9zLV4ibW6DtBub46i27JF jjae6O3ipnPesSe2Bfr2Mg+V5VZV55TW8Mcdm1px0EoxV1Sca0JKjWcuLbZDeDhTQK0m Bx72AY2s7UZQWRB4QpJ++i5ngLIogjrTFly3gXoBOMAtaLszTDbY3xs+3+DueZLc9sC7 YsjA== X-Gm-Message-State: AOAM530hBYIOya3ZBsWsxym2ePeZ6L+tP2KDnllUwKx39ATF3KXHuUL6 3n3ozwYSWPcknjvwn9IhziI= X-Google-Smtp-Source: ABdhPJzi2VmcYnM6N+fKMgtDA2WTfH7iLLgMyoqSsXw+7wVpjnYuiTPoD4yV1wmed0+wjdvuNruycg== X-Received: by 2002:a17:907:2623:: with SMTP id aq3mr13691136ejc.262.1619996853770; Sun, 02 May 2021 16:07:33 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id z17sm10003874ejc.69.2021.05.02.16.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 16:07:33 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [RFC PATCH net-next v2 17/17] net: phy: add qca8k driver for qca8k switch internal PHY Date: Mon, 3 May 2021 01:07:09 +0200 Message-Id: <20210502230710.30676-17-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210502230710.30676-1-ansuelsmth@gmail.com> References: <20210502230710.30676-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add initial support for qca8k internal PHYs. The internal PHYs requires special mmd and debug values to be set based on the switch revision passwd using the dev_flags. Supports output of idle, receive and eee_wake errors stats. Some debug values sets can't be translated as the documentation lacks any reference about them. Signed-off-by: Ansuel Smith --- drivers/net/phy/Kconfig | 7 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/qca8k.c | 174 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 182 insertions(+) create mode 100644 drivers/net/phy/qca8k.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 698bea312adc..cdf01613eb37 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -245,6 +245,13 @@ config QSEMI_PHY help Currently supports the qs6612 +config QCA8K_PHY + tristate "Qualcomm Atheros AR833x Internal PHYs" + help + This PHY is for the internal PHYs present on the QCA833x switch. + + Currently supports the AR8334, AR8337 model + config REALTEK_PHY tristate "Realtek PHYs" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index a13e402074cf..5f3cfd5606bb 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc/ obj-$(CONFIG_NATIONAL_PHY) += national.o obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o obj-$(CONFIG_QSEMI_PHY) += qsemi.o +obj-$(CONFIG_QCA8K_PHY) += qca8k.o obj-$(CONFIG_REALTEK_PHY) += realtek.o obj-$(CONFIG_RENESAS_PHY) += uPD60620.o obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o diff --git a/drivers/net/phy/qca8k.c b/drivers/net/phy/qca8k.c new file mode 100644 index 000000000000..514250bb9e71 --- /dev/null +++ b/drivers/net/phy/qca8k.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include +#include +#include +#include +#include +#include +#include + +#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) + +#define QCA8K_PHY_ID_MASK 0xffffffff +#define QCA8K_PHY_ID_QCA8327 0x004dd034 +#define QCA8K_PHY_ID_QCA8337 0x004dd036 + +#define MDIO_AZ_DEBUG 0x800d + +#define MDIO_DBG_ANALOG_TEST 0x0 +#define MDIO_DBG_SYSTEM_CONTROL_MODE 0x5 +#define MDIO_DBG_CONTROL_FEATURE_CONF 0x3d + +/* QCA specific MII registers */ +#define MII_ATH_DBG_ADDR 0x1d +#define MII_ATH_DBG_DATA 0x1e + +/* QCA specific MII registers access function */ +static void qca8k_phy_dbg_write(struct mii_bus *bus, int phy_addr, u16 dbg_addr, u16 dbg_data) +{ + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr); + bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data); + mutex_unlock(&bus->mdio_lock); +} + +enum stat_access_type { + PHY, + MMD +}; + +struct qca8k_hw_stat { + const char *string; + u8 reg; + u32 mask; + enum stat_access_type access_type; +}; + +static struct qca8k_hw_stat qca8k_hw_stats[] = { + { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, + { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, + { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, +}; + +struct qca8k_phy_priv { + u8 switch_revision; + u64 stats[ARRAY_SIZE(qca8k_hw_stats)]; +}; + +static int qca8k_get_sset_count(struct phy_device *phydev) +{ + return ARRAY_SIZE(qca8k_hw_stats); +} + +static void qca8k_get_strings(struct phy_device *phydev, u8 *data) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(qca8k_hw_stats); i++) { + strscpy(data + i * ETH_GSTRING_LEN, + qca8k_hw_stats[i].string, ETH_GSTRING_LEN); + } +} + +static u64 qca8k_get_stat(struct phy_device *phydev, int i) +{ + struct qca8k_hw_stat stat = qca8k_hw_stats[i]; + struct qca8k_phy_priv *priv = phydev->priv; + int val; + u64 ret; + + if (stat.access_type == MMD) + val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); + else + val = phy_read(phydev, stat.reg); + + if (val < 0) { + ret = U64_MAX; + } else { + val = val & stat.mask; + priv->stats[i] += val; + ret = priv->stats[i]; + } + + return ret; +} + +static void qca8k_get_stats(struct phy_device *phydev, + struct ethtool_stats *stats, u64 *data) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(qca8k_hw_stats); i++) + data[i] = qca8k_get_stat(phydev, i); +} + +static int qca8k_config_init(struct phy_device *phydev) +{ + struct qca8k_phy_priv *priv = phydev->priv; + struct mii_bus *bus = phydev->mdio.bus; + int phy_addr = phydev->mdio.addr; + + priv->switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; + + switch (priv->switch_revision) { + case 1: + /* For 100M waveform */ + qca8k_phy_dbg_write(bus, phy_addr, MDIO_DBG_ANALOG_TEST, 0x02ea); + /* Turn on Gigabit clock */ + qca8k_phy_dbg_write(bus, phy_addr, MDIO_DBG_CONTROL_FEATURE_CONF, 0x68a0); + break; + + case 2: + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); + fallthrough; + case 4: + phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); + qca8k_phy_dbg_write(bus, phy_addr, MDIO_DBG_CONTROL_FEATURE_CONF, 0x6860); + qca8k_phy_dbg_write(bus, phy_addr, MDIO_DBG_SYSTEM_CONTROL_MODE, 0x2c46); + qca8k_phy_dbg_write(bus, phy_addr, 0x3c, 0x6000); + break; + } + + return 0; +} + +static int qca8k_probe(struct phy_device *phydev) +{ + struct qca8k_phy_priv *priv; + + priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + phydev->priv = priv; + + return 0; +} + +static struct phy_driver qca8k_drivers[] = { + { + .phy_id = QCA8K_PHY_ID_QCA8337, + .phy_id_mask = QCA8K_PHY_ID_MASK, + .name = "QCA PHY 8337", + /* PHY_GBIT_FEATURES */ + .probe = qca8k_probe, + .flags = PHY_IS_INTERNAL, + .config_init = qca8k_config_init, + .soft_reset = genphy_soft_reset, + .get_sset_count = qca8k_get_sset_count, + .get_strings = qca8k_get_strings, + .get_stats = qca8k_get_stats, + }, +}; + +module_phy_driver(qca8k_drivers); + +static struct mdio_device_id __maybe_unused qca8k_tbl[] = { + { QCA8K_PHY_ID_QCA8337, QCA8K_PHY_ID_MASK }, + { } +}; + +MODULE_DEVICE_TABLE(mdio, qca8k_tbl); +MODULE_DESCRIPTION("Qualcomm QCA8k PHY driver"); +MODULE_AUTHOR("Ansuel Smith"); +MODULE_LICENSE("GPL");