From patchwork Thu Apr 29 03:45:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 429388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C597C433B4 for ; Thu, 29 Apr 2021 03:45:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D79E161451 for ; Thu, 29 Apr 2021 03:45:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237239AbhD2Dql (ORCPT ); Wed, 28 Apr 2021 23:46:41 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:38534 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S236997AbhD2Dql (ORCPT ); Wed, 28 Apr 2021 23:46:41 -0400 X-UUID: eef5b7c0afea42ccacc8a52fdd6551cf-20210429 X-UUID: eef5b7c0afea42ccacc8a52fdd6551cf-20210429 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 384933692; Thu, 29 Apr 2021 11:45:52 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 11:45:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 29 Apr 2021 11:45:50 +0800 From: Rex-BC Chen To: , CC: , , , , , Rex-BC Chen , Jitao Shi Subject: [v3,PATCH 1/3] drm/mediatek: dpi dual edge sample mode support Date: Thu, 29 Apr 2021 11:45:46 +0800 Message-ID: <20210429034548.28030-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210429034548.28030-1-rex-bc.chen@mediatek.com> References: <20210429034548.28030-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DPI can sample on falling, rising or both edge. When DPI sample the data both rising and falling edge. It can reduce half data io pins. Signed-off-by: Jitao Shi Signed-off-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index b05f900d9322..79f3e83f40ef 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -83,6 +83,7 @@ struct mtk_dpi { struct pinctrl *pinctrl; struct pinctrl_state *pins_gpio; struct pinctrl_state *pins_dpi; + bool ddr_edge_sel; int refcount; }; @@ -121,6 +122,7 @@ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); u32 reg_h_fre_con; bool edge_sel_en; + bool dual_edge; }; static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -380,6 +382,15 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, } } +static void mtk_dpi_dual_edge(struct mtk_dpi *dpi) +{ + if (dpi->conf->dual_edge) { + mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, + DDR_EN | DDR_4PHASE); + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, dpi->ddr_edge_sel ? EDGE_SEL : 0, EDGE_SEL); + } +} + static void mtk_dpi_power_off(struct mtk_dpi *dpi) { if (WARN_ON(dpi->refcount == 0)) @@ -454,7 +465,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, pll_rate = clk_get_rate(dpi->tvd_clk); vm.pixelclock = pll_rate / factor; - clk_set_rate(dpi->pixel_clk, vm.pixelclock); + clk_set_rate(dpi->pixel_clk, vm.pixelclock * (dpi->conf->dual_edge ? 2 : 1)); vm.pixelclock = clk_get_rate(dpi->pixel_clk); dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", @@ -518,6 +529,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); mtk_dpi_config_disable_edge(dpi); mtk_dpi_sw_reset(dpi, false); From patchwork Thu Apr 29 03:45:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 430038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DADEBC433ED for ; Thu, 29 Apr 2021 03:45:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B500961455 for ; Thu, 29 Apr 2021 03:45:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237142AbhD2Dqk (ORCPT ); Wed, 28 Apr 2021 23:46:40 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:38534 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S236938AbhD2Dqk (ORCPT ); Wed, 28 Apr 2021 23:46:40 -0400 X-UUID: 1c707d146259400da4022e0d926574c4-20210429 X-UUID: 1c707d146259400da4022e0d926574c4-20210429 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1614369852; Thu, 29 Apr 2021 11:45:52 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 11:45:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 29 Apr 2021 11:45:50 +0800 From: Rex-BC Chen To: , CC: , , , , , Rex-BC Chen , Jitao Shi Subject: [v3, PATCH 2/3] drm/mediatek: config mt8183 driver data to support dual edge sample Date: Thu, 29 Apr 2021 11:45:47 +0800 Message-ID: <20210429034548.28030-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210429034548.28030-1-rex-bc.chen@mediatek.com> References: <20210429034548.28030-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org add dual_edge value for mt8183_conf Signed-off-by: Jitao Shi Signed-off-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 79f3e83f40ef..c548780dd3a5 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -691,6 +691,7 @@ static const struct mtk_dpi_conf mt2701_conf = { static const struct mtk_dpi_conf mt8183_conf = { .cal_factor = mt8183_calculate_factor, .reg_h_fre_con = 0xe0, + .dual_edge = true, }; static int mtk_dpi_probe(struct platform_device *pdev) From patchwork Thu Apr 29 03:45:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 429387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F1BEC433ED for ; Thu, 29 Apr 2021 03:45:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 41C1161453 for ; Thu, 29 Apr 2021 03:45:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236938AbhD2Dqm (ORCPT ); Wed, 28 Apr 2021 23:46:42 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:38534 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237209AbhD2Dql (ORCPT ); Wed, 28 Apr 2021 23:46:41 -0400 X-UUID: 957f3940e6c14b6a925b2dc7270d90e7-20210429 X-UUID: 957f3940e6c14b6a925b2dc7270d90e7-20210429 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 602636878; Thu, 29 Apr 2021 11:45:52 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 11:45:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 29 Apr 2021 11:45:51 +0800 From: Rex-BC Chen To: , CC: , , , , , Rex-BC Chen , Jitao Shi Subject: [v3,PATCH 3/3] drm/mediatek: dpi: add bus format negotiation Date: Thu, 29 Apr 2021 11:45:48 +0800 Message-ID: <20210429034548.28030-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210429034548.28030-1-rex-bc.chen@mediatek.com> References: <20210429034548.28030-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the atomic_get_output_bus_fmts, atomic_get_input_bus_fmts to negotiate the possible output and input formats for the current mode and monitor, and use the negotiated formats in a basic atomic_check callback. Signed-off-by: Jitao Shi Signed-off-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 92 ++++++++++++++++++++++++++++-- 1 file changed, 87 insertions(+), 5 deletions(-) .mode_set = mtk_dpi_bridge_mode_set, .disable = mtk_dpi_bridge_disable, .enable = mtk_dpi_bridge_enable, + .atomic_check = mtk_dpi_bridge_atomic_check, + .atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts, + .atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, }; void mtk_dpi_start(struct device *dev) @@ -620,11 +707,6 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) } drm_connector_attach_encoder(dpi->connector, &dpi->encoder); - dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; - dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; - dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; - return 0; err_cleanup: diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index c548780dd3a5..8822d9448ae8 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -536,6 +536,87 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, return 0; } +#define MAX_OUTPUT_SEL_FORMATS 2 + +static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + u32 *output_fmts; + struct mtk_dpi *dpi = bridge_to_dpi(bridge); + + *num_output_fmts = 0; + + output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), + GFP_KERNEL); + if (!output_fmts) + return NULL; + + /* Default 8bit RGB fallback */ + if (dpi->conf->dual_edge) { + output_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE; + output_fmts[1] = MEDIA_BUS_FMT_RGB888_2X12_BE; + *num_output_fmts = 2; + } else { + output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; + *num_output_fmts = 1; + } + + return output_fmts; +} + +#define MAX_INPUT_SEL_FORMATS 1 + +static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + *num_input_fmts = 0; + + input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), + GFP_KERNEL); + if (!input_fmts) + return NULL; + + *num_input_fmts = 1; + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; + + return input_fmts; +} + +static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct mtk_dpi *dpi = bridge->driver_private; + unsigned int out_bus_format; + + out_bus_format = bridge_state->output_bus_cfg.format; + + dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", + bridge_state->input_bus_cfg.format, + bridge_state->output_bus_cfg.format); + + dpi->ddr_edge_sel = (out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_LE) ? + true : false; + + dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; + dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; + dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; + dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; + + return 0; +} + static int mtk_dpi_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags) { @@ -574,6 +655,12 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {