From patchwork Tue Jun 19 19:43:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 139255 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5621145lji; Tue, 19 Jun 2018 12:53:24 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJbqDE12idPumugfw/ZpMgAwsfc2DF3K5i8geUutGZ/zvBGRPZPbaKf6PtDJGZcwCzhQvUv X-Received: by 2002:a17:902:70ca:: with SMTP id l10-v6mr7363145plt.174.1529438004033; Tue, 19 Jun 2018 12:53:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529438004; cv=none; d=google.com; s=arc-20160816; b=eq1KMv/9KgLAZXWy3XrZLAkdQdXnz+QKLyfsvq+wHQNS6qNfA8ASZMp/LXbJZq30Pu /Spstv5kI6pt0irvdHb2sG2/Fu0kYNBRWX3F62/2MCN7nNO7pnhxqtd+mwtYn3vwf/gL cJjtt5GyfHdBW8YIfddA0jY3u3nNp+IXjwz8fW4fOdhnqToy6Ded8A0R1nvo8QD7cX9A heGMakLGCJEdj4fhHg5+Y3rJ3DAXATIII/eW6ezL0z+XtS1ZN69OFT8tpeXUKCKCZZBc GyWgyew1qXHFooQUOR183EzGBDtiAmJ5tVgzYNXZdDpc66Y+9+tQRareOmPkrNtG4VmO /1ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=iG1a6hrZC1OZv9XhqmdvLFvpwbE9VvlZfH8NcaYKvK0=; b=t6kVPNEfWTIhj8YHVcvhkennDGxP7A01+x0pFemyFvn4z5OMRNErgjY7FlnCSVDeaS d9UGcypUasTpxS9+Ap7CtrLe4JiU2HLhFjCsCSyvwfWKu+jPSg5J7NHQCl1Zw+jmqjVh 8e16sfFMk4BdF56c3fUeX6TpfLKKgXgy3EtcsLZrK3DR/kwxmEOPSo75gEmvT9M5kof8 dJSYegp5rG9g5WAOmEbbhlqJ1TuxUu+WBPhKbw04NplDINmHBPW0Cxx6E/ucKwJ/SKYn vjmLN4d7cGNB+K/AZyzKr8ZjavrYRlTqMFhUgSV2Rxuh9Q8lDgVcyOPWMXwFSpryOFQM QZfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SPsLcnG3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 2-v6si480018pfj.6.2018.06.19.12.53.23; Tue, 19 Jun 2018 12:53:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SPsLcnG3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030661AbeFSTxW (ORCPT + 30 others); Tue, 19 Jun 2018 15:53:22 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:56644 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030504AbeFSTxU (ORCPT ); Tue, 19 Jun 2018 15:53:20 -0400 X-Greylist: delayed 578 seconds by postgrey-1.27 at vger.kernel.org; Tue, 19 Jun 2018 15:53:20 EDT Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w5JJhbhT021336; Tue, 19 Jun 2018 14:43:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1529437418; bh=iG1a6hrZC1OZv9XhqmdvLFvpwbE9VvlZfH8NcaYKvK0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SPsLcnG39b4dq3PtfS0Xt177zKMjOoKOJHf/4s3MHZmk0izYDTcdE21nXD1533X3S WhGHD6MA9/Vcsy/Dc186uX7LziKIEg4NjRthd+GiFeEtbL8yqTtw1U/kAPqNaV5LUn QYv1fumXVfwHoh2G6U4ugbVqcqtFe6QUwOjyInlA= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5JJhbKU024508; Tue, 19 Jun 2018 14:43:37 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 19 Jun 2018 14:43:37 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 19 Jun 2018 14:43:37 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5JJhblu017890; Tue, 19 Jun 2018 14:43:37 -0500 From: Nishanth Menon To: Jassi Brar , Mark Rutland , Rob Herring CC: Nishanth Menon , Suman Anna , Tero Kristo , , Subject: [PATCH 1/6] mailbox: ti-msgmgr: Get rid of unused structure members Date: Tue, 19 Jun 2018 14:43:32 -0500 Message-ID: <20180619194337.31522-2-nm@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180619194337.31522-1-nm@ti.com> References: <20180619194337.31522-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Though q_proxies and q_slices do describe the hardware configuration, they are not necessary for operation given that the values are always default. Hence drop the same. Signed-off-by: Nishanth Menon --- Changes since RFC: None RFC: https://patchwork.kernel.org/patch/10447665/ drivers/mailbox/ti-msgmgr.c | 6 ------ 1 file changed, 6 deletions(-) -- 2.15.1 diff --git a/drivers/mailbox/ti-msgmgr.c b/drivers/mailbox/ti-msgmgr.c index 5d04738c3c8a..5fe6ce200264 100644 --- a/drivers/mailbox/ti-msgmgr.c +++ b/drivers/mailbox/ti-msgmgr.c @@ -42,8 +42,6 @@ struct ti_msgmgr_valid_queue_desc { * @queue_count: Number of Queues * @max_message_size: Message size in bytes * @max_messages: Number of messages - * @q_slices: Number of queue engines - * @q_proxies: Number of queue proxies per page * @data_first_reg: First data register for proxy data region * @data_last_reg: Last data register for proxy data region * @tx_polled: Do I need to use polled mechanism for tx @@ -58,8 +56,6 @@ struct ti_msgmgr_desc { u8 queue_count; u8 max_message_size; u8 max_messages; - u8 q_slices; - u8 q_proxies; u8 data_first_reg; u8 data_last_reg; bool tx_polled; @@ -494,8 +490,6 @@ static const struct ti_msgmgr_desc k2g_desc = { .queue_count = 64, .max_message_size = 64, .max_messages = 128, - .q_slices = 1, - .q_proxies = 1, .data_first_reg = 16, .data_last_reg = 31, .tx_polled = false, From patchwork Tue Jun 19 19:43:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 139242 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5612658lji; Tue, 19 Jun 2018 12:43:51 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKiVTpgCFt8UIxvpsyNKPWwNicWcQtfuClFz2vqZflzavuoSxrodH7+EeI68rfcfAILaBBG X-Received: by 2002:a62:9513:: with SMTP id p19-v6mr19495528pfd.239.1529437431031; Tue, 19 Jun 2018 12:43:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529437431; cv=none; d=google.com; s=arc-20160816; b=iNs5yfcq5rT6YeQ3VUpXuqxBdw5TKmi6Sa2nRm1OdoXuDdS4Y0iE/ZzsW/5I3+6vMa Rb0h/x6H8Q7KEMV2ffDMbM9/Azfn0argXY2sGBRDa3UmthbLOyy21tVmPDCNsTdxAlFK IdVUzW2EoeF0NNMP2ixk4PWYNJ8AnGJuKprBRAWsTvKpA5448Dm/BY0gRTNAe2L5CpYy Fhm2VQ/aLjqCT4Krsm04ae8hMp9XRJUNgEKOvNhRqckuNQuRWP+xWkl1v13rCw7Dzcc9 sACh3r4HAabIBVvckSoLYNmHMlal9KmJwSwY35j4LQ/Y9c+7G9nN0BvV4vdd9vaIwETV ezbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=JaojuIEE3X5kvJBZyUWRzgfYPZdvaCHIVA3zLg9T8Fs=; b=dwPd6HRdzPzjpoTnJjQAI4DQYKnua36D4Te21rR0qYbz/RtaR0c+0YDSK5rnrbHqKv TzmnbRzMwaWRGUjYJ+hfydhTgut9yECrzoGlsRYPHp/KqeiZ77+VRybTtEGSF7zGCrkI t1WDUkwT6N2FXailWELYZ6TB+AmesFUYxrRGg3ZDm7TE7Ma3IjcTKz3ZY0TU32/K05MY 3yKRoTYSwr8+9x4fR9/sH9JeTbm6fyXt1YvjvO01TQAChIAY8cF6BJF8a7WhhX9bORzr y3IOeGkbrLSfBEgTT+u19+dgczhANO3caoB3QnFwXcPbxv1Zu0XCC5KYCazmk3TIRjZJ 5xUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=GombzLiN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o12-v6si457792pfd.52.2018.06.19.12.43.50; Tue, 19 Jun 2018 12:43:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=GombzLiN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030554AbeFSTnq (ORCPT + 30 others); Tue, 19 Jun 2018 15:43:46 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:39333 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030374AbeFSTnm (ORCPT ); Tue, 19 Jun 2018 15:43:42 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w5JJhbqi013455; Tue, 19 Jun 2018 14:43:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1529437417; bh=JaojuIEE3X5kvJBZyUWRzgfYPZdvaCHIVA3zLg9T8Fs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GombzLiNyP6vD0V2/UI1ZPeZGqxzV1+H1l2VrJlt+3EloNff65FGD0j2igtVqOyZj 4k+7TqyRVGmvYFKe9E9vnHRUtFycWsrWSYDiOGzaFffBIzh1pyyb2dBrJx0ZSFWIiO bZ4mxC7Xqwofyhrsb7baWFayqTu2JLIIn2peo4KI= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5JJhbKB009151; Tue, 19 Jun 2018 14:43:37 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 19 Jun 2018 14:43:37 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 19 Jun 2018 14:43:37 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5JJhbhN026532; Tue, 19 Jun 2018 14:43:37 -0500 From: Nishanth Menon To: Jassi Brar , Mark Rutland , Rob Herring CC: Nishanth Menon , Suman Anna , Tero Kristo , , Subject: [PATCH 2/6] mailbox: ti-msgmgr: Allocate Rx channel resources only on request Date: Tue, 19 Jun 2018 14:43:33 -0500 Message-ID: <20180619194337.31522-3-nm@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180619194337.31522-1-nm@ti.com> References: <20180619194337.31522-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In a much bigger system SoCs, the number of Rx channels can be many and mostly unused based on the system of choice, and not all Rx channels need IRQs and allocating all memory at probe will be inefficient. Some SoCs could have total threads in the 100s and usage would be just 1 Rx thread. Thus, request and map the IRQs and allocate memory only when needed. Since these channels are requested by client drivers on need, our utilization will be optimal. Signed-off-by: Nishanth Menon --- Changes since RFC: None RFC: https://patchwork.kernel.org/patch/10447701/ drivers/mailbox/ti-msgmgr.c | 91 ++++++++++++++++++++++++++++++--------------- 1 file changed, 61 insertions(+), 30 deletions(-) -- 2.15.1 diff --git a/drivers/mailbox/ti-msgmgr.c b/drivers/mailbox/ti-msgmgr.c index 5fe6ce200264..91c955979008 100644 --- a/drivers/mailbox/ti-msgmgr.c +++ b/drivers/mailbox/ti-msgmgr.c @@ -310,6 +310,51 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data) return 0; } +/** + * ti_msgmgr_queue_rx_irq_req() - RX IRQ request + * @dev: device pointer + * @qinst: Queue instance + * @chan: Channel pointer + */ +static int ti_msgmgr_queue_rx_irq_req(struct device *dev, + struct ti_queue_inst *qinst, + struct mbox_chan *chan) +{ + int ret = 0; + char of_rx_irq_name[7]; + struct device_node *np; + + snprintf(of_rx_irq_name, sizeof(of_rx_irq_name), + "rx_%03d", qinst->queue_id); + + /* Get the IRQ if not found */ + if (qinst->irq < 0) { + np = of_node_get(dev->of_node); + if (!np) + return -ENODATA; + qinst->irq = of_irq_get_byname(np, of_rx_irq_name); + of_node_put(np); + + if (qinst->irq < 0) { + dev_err(dev, + "QID %d PID %d:No IRQ[%s]: %d\n", + qinst->queue_id, qinst->proxy_id, + of_rx_irq_name, qinst->irq); + return qinst->irq; + } + } + + /* With the expectation that the IRQ might be shared in SoC */ + ret = request_irq(qinst->irq, ti_msgmgr_queue_rx_interrupt, + IRQF_SHARED, qinst->name, chan); + if (ret) { + dev_err(dev, "Unable to get IRQ %d on %s(res=%d)\n", + qinst->irq, qinst->name, ret); + } + + return ret; +} + /** * ti_msgmgr_queue_startup() - Startup queue * @chan: Channel pointer @@ -318,19 +363,21 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data) */ static int ti_msgmgr_queue_startup(struct mbox_chan *chan) { - struct ti_queue_inst *qinst = chan->con_priv; struct device *dev = chan->mbox->dev; + struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); + struct ti_queue_inst *qinst = chan->con_priv; + const struct ti_msgmgr_desc *d = inst->desc; int ret; if (!qinst->is_tx) { - /* - * With the expectation that the IRQ might be shared in SoC - */ - ret = request_irq(qinst->irq, ti_msgmgr_queue_rx_interrupt, - IRQF_SHARED, qinst->name, chan); + /* Allocate usage buffer for rx */ + qinst->rx_buff = kzalloc(d->max_message_size, GFP_KERNEL); + if (!qinst->rx_buff) + return -ENOMEM; + /* Request IRQ */ + ret = ti_msgmgr_queue_rx_irq_req(dev, qinst, chan); if (ret) { - dev_err(dev, "Unable to get IRQ %d on %s(res=%d)\n", - qinst->irq, qinst->name, ret); + kfree(qinst->rx_buff); return ret; } } @@ -346,8 +393,10 @@ static void ti_msgmgr_queue_shutdown(struct mbox_chan *chan) { struct ti_queue_inst *qinst = chan->con_priv; - if (!qinst->is_tx) + if (!qinst->is_tx) { free_irq(qinst->irq, chan); + kfree(qinst->rx_buff); + } } /** @@ -425,27 +474,6 @@ static int ti_msgmgr_queue_setup(int idx, struct device *dev, dev_name(dev), qinst->is_tx ? "tx" : "rx", qinst->queue_id, qinst->proxy_id); - if (!qinst->is_tx) { - char of_rx_irq_name[7]; - - snprintf(of_rx_irq_name, sizeof(of_rx_irq_name), - "rx_%03d", qinst->queue_id); - - qinst->irq = of_irq_get_byname(np, of_rx_irq_name); - if (qinst->irq < 0) { - dev_crit(dev, - "[%d]QID %d PID %d:No IRQ[%s]: %d\n", - idx, qinst->queue_id, qinst->proxy_id, - of_rx_irq_name, qinst->irq); - return qinst->irq; - } - /* Allocate usage buffer for rx */ - qinst->rx_buff = devm_kzalloc(dev, - d->max_message_size, GFP_KERNEL); - if (!qinst->rx_buff) - return -ENOMEM; - } - qinst->queue_buff_start = inst->queue_proxy_region + Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, d->data_first_reg); qinst->queue_buff_end = inst->queue_proxy_region + @@ -454,6 +482,9 @@ static int ti_msgmgr_queue_setup(int idx, struct device *dev, Q_STATE_OFFSET(qinst->queue_id); qinst->chan = chan; + /* Setup an error value for IRQ - Lazy allocation */ + qinst->irq = -EINVAL; + chan->con_priv = qinst; dev_dbg(dev, "[%d] qidx=%d pidx=%d irq=%d q_s=%p q_e = %p\n", From patchwork Tue Jun 19 19:43:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 139256 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5621236lji; Tue, 19 Jun 2018 12:53:29 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKrJzo7djLuLlqVX5v6t1dUPdFw7Xct4XYpt31rdhdq0gOryP1J5/opAni7cCPb0gG7kIfm X-Received: by 2002:a17:902:3081:: with SMTP id v1-v6mr20914233plb.266.1529438009332; Tue, 19 Jun 2018 12:53:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529438009; cv=none; d=google.com; s=arc-20160816; b=SYP+ejWNIM9E/8iT8EMPrEa0vCDePs2WBytrlVGTPESTUwSmY63pk6IiRFPfQbGgvg NqtcBsGNguSY9GmimqywrQ0YhYIN5Qk+NrpzGN+7SQzre8Gy4uw7MPDHMKBzT7ZvO9um ZVZZEcvdnrKqn9pYLweXpmq7bcNrNAmLvmD0xrGjE9Tth9mOtew4yhvl7qfWZEdgn742 EI9N2jr3jvPdecqqttUoNX+7jYY+q4eOfRelPR1+x4F8MkYNfjPW/C3vgUBSMKbe8g6Y PItV8TFaEdnOaM8ngaWT35HqyI5gzzP/aaDRMqqP7rYsRlz8pM2b86D3RTW6wx7iZPnq PmCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=IimCBbSGgD/Jq/whZwfROOGdjUZof6W0KJe2fBLtX5M=; b=w2rxFXqcLfyV5NBXpYMYmn/7k52mYdqJVXmPVLvL+H/BgbJQ8pMOVfxbrRgBln1buV y1Nfx/qjFV+/WJLc7ys2XG3V3D6pAlliIFybJ6w6ZDh9if6Q60RWYledndH0fLvLZMvF fNhadz1PitfMtHQcBlqJgyAUJxOJqWQfFyiGp0yWqg0KOTSDc338NhdlymDeSYlYcIyD PSa2NIo4ndl7mnG956WUAvS7BWDJxYz3OGCU9G4q2vaJG/VTaBw32amjAHHiYWQV6BYz ttrlJoIOeviZCNpRkzQmRz/BOO0Pq1x33xVwYdgZ/xhir65y6K1kggq/fcPDftG1+xZF dPQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="C3Nw0j6/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x14-v6si399571pgq.242.2018.06.19.12.53.28; Tue, 19 Jun 2018 12:53:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="C3Nw0j6/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030685AbeFSTx0 (ORCPT + 30 others); Tue, 19 Jun 2018 15:53:26 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:56644 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030504AbeFSTxW (ORCPT ); Tue, 19 Jun 2018 15:53:22 -0400 X-Greylist: delayed 578 seconds by postgrey-1.27 at vger.kernel.org; Tue, 19 Jun 2018 15:53:20 EDT Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w5JJhciD021340; Tue, 19 Jun 2018 14:43:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1529437418; bh=IimCBbSGgD/Jq/whZwfROOGdjUZof6W0KJe2fBLtX5M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=C3Nw0j6/Jceo3gHm3KQsxYddnWll5/4ycum2StUG8zTfWYl26QoMfkDb+WCipQvcV MIqhdU0zD6J8MdkK/naIspkBQw/8LhnsX25S0Q5juNCh2ne1xUVn3F8QjApoFRQRUM yvm2RZOQ9QiLbPp/vG2wb6WwVkt2PMThfXqKm5dU= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5JJhbEO024510; Tue, 19 Jun 2018 14:43:38 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 19 Jun 2018 14:43:37 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 19 Jun 2018 14:43:37 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5JJhbxo017299; Tue, 19 Jun 2018 14:43:37 -0500 From: Nishanth Menon To: Jassi Brar , Mark Rutland , Rob Herring CC: Nishanth Menon , Suman Anna , Tero Kristo , , Subject: [PATCH 3/6] mailbox: ti-msgmgr: Change message count mask to be descriptor based Date: Tue, 19 Jun 2018 14:43:34 -0500 Message-ID: <20180619194337.31522-4-nm@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180619194337.31522-1-nm@ti.com> References: <20180619194337.31522-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Change mask used to extract the message count to be descriptor based. This is to support changes for count location for various SoC solutions. Signed-off-by: Nishanth Menon --- Changes since RFC: None RFC: https://patchwork.kernel.org/patch/10447671/ drivers/mailbox/ti-msgmgr.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) -- 2.15.1 diff --git a/drivers/mailbox/ti-msgmgr.c b/drivers/mailbox/ti-msgmgr.c index 91c955979008..7d2eb4b359ba 100644 --- a/drivers/mailbox/ti-msgmgr.c +++ b/drivers/mailbox/ti-msgmgr.c @@ -44,6 +44,7 @@ struct ti_msgmgr_valid_queue_desc { * @max_messages: Number of messages * @data_first_reg: First data register for proxy data region * @data_last_reg: Last data register for proxy data region + * @status_cnt_mask: Mask for getting the status value * @tx_polled: Do I need to use polled mechanism for tx * @tx_poll_timeout_ms: Timeout in ms if polled * @valid_queues: List of Valid queues that the processor can access @@ -58,6 +59,7 @@ struct ti_msgmgr_desc { u8 max_messages; u8 data_first_reg; u8 data_last_reg; + u32 status_cnt_mask; bool tx_polled; int tx_poll_timeout_ms; const struct ti_msgmgr_valid_queue_desc *valid_queues; @@ -116,20 +118,24 @@ struct ti_msgmgr_inst { /** * ti_msgmgr_queue_get_num_messages() - Get the number of pending messages + * @d: Description of message manager * @qinst: Queue instance for which we check the number of pending messages * * Return: number of messages pending in the queue (0 == no pending messages) */ -static inline int ti_msgmgr_queue_get_num_messages(struct ti_queue_inst *qinst) +static inline int +ti_msgmgr_queue_get_num_messages(const struct ti_msgmgr_desc *d, + struct ti_queue_inst *qinst) { u32 val; + u32 status_cnt_mask = d->status_cnt_mask; /* * We cannot use relaxed operation here - update may happen * real-time. */ - val = readl(qinst->queue_state) & Q_STATE_ENTRY_COUNT_MASK; - val >>= __ffs(Q_STATE_ENTRY_COUNT_MASK); + val = readl(qinst->queue_state) & status_cnt_mask; + val >>= __ffs(status_cnt_mask); return val; } @@ -167,8 +173,9 @@ static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p) return IRQ_NONE; } + desc = inst->desc; /* Do I actually have messages to read? */ - msg_count = ti_msgmgr_queue_get_num_messages(qinst); + msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst); if (!msg_count) { /* Shared IRQ? */ dev_dbg(dev, "Spurious event - 0 pending data!\n"); @@ -181,7 +188,6 @@ static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p) * of how many bytes I should be reading. Let the client figure this * out.. I just read the full message and pass it on.. */ - desc = inst->desc; message.len = desc->max_message_size; message.buf = (u8 *)qinst->rx_buff; @@ -224,12 +230,14 @@ static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p) static bool ti_msgmgr_queue_peek_data(struct mbox_chan *chan) { struct ti_queue_inst *qinst = chan->con_priv; + struct device *dev = chan->mbox->dev; + struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); int msg_count; if (qinst->is_tx) return false; - msg_count = ti_msgmgr_queue_get_num_messages(qinst); + msg_count = ti_msgmgr_queue_get_num_messages(inst->desc, qinst); return msg_count ? true : false; } @@ -243,12 +251,14 @@ static bool ti_msgmgr_queue_peek_data(struct mbox_chan *chan) static bool ti_msgmgr_last_tx_done(struct mbox_chan *chan) { struct ti_queue_inst *qinst = chan->con_priv; + struct device *dev = chan->mbox->dev; + struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); int msg_count; if (!qinst->is_tx) return false; - msg_count = ti_msgmgr_queue_get_num_messages(qinst); + msg_count = ti_msgmgr_queue_get_num_messages(inst->desc, qinst); /* if we have any messages pending.. */ return msg_count ? false : true; @@ -523,6 +533,7 @@ static const struct ti_msgmgr_desc k2g_desc = { .max_messages = 128, .data_first_reg = 16, .data_last_reg = 31, + .status_cnt_mask = Q_STATE_ENTRY_COUNT_MASK, .tx_polled = false, .valid_queues = k2g_valid_queues, .num_valid_queues = ARRAY_SIZE(k2g_valid_queues), From patchwork Tue Jun 19 19:43:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 139258 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5621899lji; Tue, 19 Jun 2018 12:54:15 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIw5ICs7AfQyqtp/VBAIc/h7q3A4ta8lo6MYEQAN+t+RHnAXVr0ix2zKFOjjbkHBn4t6y3B X-Received: by 2002:a65:560f:: with SMTP id l15-v6mr16485029pgs.260.1529438055703; Tue, 19 Jun 2018 12:54:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529438055; cv=none; d=google.com; s=arc-20160816; b=IlpqWUEnBOHaEw7xWu6O0A66OI1CeTDN2DfjK/mXkp9SjE6uipQoHKMjVJcTbYaIJ7 XQWAQCooZK4Df71yWnGqhFoEHRyR2xJ/QAkXPvxovHtiHJv427DggMbIkF2YaQQ88TY5 CXIcWSR6toOgac+v20R0Kfz06+svkSzTb4dPB8QUFJIGIk/UYDQouOe2wkBQl/X/5erK 0IXhe/cXrsnD35XXpPeK0YBl8KkpI//a1l4V0KkvZOmbso8mg1WC/GU18xKKu5BAJOHQ suakGf8ztelzZir2e2QpZK4ewWTeDb7ADJqnD4rD1YHS7Xx/seFcZk5HVaLFjyFSGm7R Iuag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=+Rub31iQblYBjhtSV3poMjva4ONmHPWl3ILrDKsZYCM=; b=aZDtBdU0toJhkRslfWPU8FDYS5teBuBlRs1mEsujg5gdzfrwfpMU0oZyZB/mnJ/Smi 8GKNm2+N9cPGRqodtN2h8UDaCgJ0fDPy45GONa4GB/WQGi27Bi+BKkXj2PaEmVaNwNvj 0bnWH9JfXHzr40NzcBRVhaZxCIOGPcKDVIQQeIR+LBmzOYAZpdC3mL115t+4u+COmKd6 qJaNNJLWpgb/PR/SzIohYsHU8eDfjk/WhYTzas3Iu32ZVXDZhURsbl2+2z8/o0qoqtXR dpnZ/ODPTZrFf9VFnrwq3RlidQakr487se0aXkV/xNOnGlcnKDHFSyJh0EF1yQYtvE9B NDXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ubKfUYtP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n4-v6si440070plp.128.2018.06.19.12.54.15; Tue, 19 Jun 2018 12:54:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ubKfUYtP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030730AbeFSTyN (ORCPT + 30 others); Tue, 19 Jun 2018 15:54:13 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:56644 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030510AbeFSTxV (ORCPT ); Tue, 19 Jun 2018 15:53:21 -0400 X-Greylist: delayed 578 seconds by postgrey-1.27 at vger.kernel.org; Tue, 19 Jun 2018 15:53:20 EDT Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w5JJhcFe021344; Tue, 19 Jun 2018 14:43:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1529437418; bh=+Rub31iQblYBjhtSV3poMjva4ONmHPWl3ILrDKsZYCM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ubKfUYtPy1OUVdOAN47TF9WQRPWxJFdabq9HuJGMNDKO042OPu/E1HGgrdrkVrqdO L5WVJydMmqPMfx4adu69DsS2LSwzxTB5vV/PsDL6XvZchshigqxeRWGjwpxXg9kklU 8a9/DgW0K7gZzwkNbTynbUukhVPO0ILDT1dgivog= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5JJhcbm024520; Tue, 19 Jun 2018 14:43:38 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 19 Jun 2018 14:43:37 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 19 Jun 2018 14:43:37 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5JJhbKB017893; Tue, 19 Jun 2018 14:43:37 -0500 From: Nishanth Menon To: Jassi Brar , Mark Rutland , Rob Herring CC: Nishanth Menon , Suman Anna , Tero Kristo , , Subject: [PATCH 5/6] dt-bindings: mailbox: Add support for secure proxy threads Date: Tue, 19 Jun 2018 14:43:36 -0500 Message-ID: <20180619194337.31522-6-nm@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180619194337.31522-1-nm@ti.com> References: <20180619194337.31522-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Secure Proxy is another communication scheme in Texas Instrument's devices intended to provide an unique communication path from various processors in the System on Chip(SoC) to a central System Controller. Secure proxy is, in effect, an evolution of current generation Message Manager hardware block found in K2G devices. However the following changes have taken place: Secure Proxy instance exposes "threads" or "proxies" which is primary representation of "a" communication channel. Each thread is preconfigured by System controller configuration based on SoC usage requirements. Secure proxy by itself represents a single "queue" of communication but allows the proxies to be independently operated. Each Secure proxy thread can uniquely have their own error and threshold interrupts allowing for more fine control of IRQ handling. Provide an hardware description of the same for device tree representation. See AM65x Technical Reference Manual (SPRUID7, April 2018) for further details: http://www.ti.com/lit/pdf/spruid7 Signed-off-by: Nishanth Menon --- Changes since RFC: * DT binding have been seperated into it's own file following Rob's feedback. RFC: https://patchwork.kernel.org/patch/10447695/ .../bindings/mailbox/ti,secure-proxy.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt -- 2.15.1 diff --git a/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt b/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt new file mode 100644 index 000000000000..ea2ccc607b35 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt @@ -0,0 +1,50 @@ +Texas Instruments' Secure Proxy +======================================== + +The Texas Instruments' secure proxy is a mailbox controller that has +configurable queues selectable at SoC(System on Chip) integration. The +Message manager is broken up into different address regions that are +called "threads" or "proxies" - each instance is unidirectional and is +instantiated at SoC integration level by system controller to indicate +receive or transmit path. + +Message Manager Device Node: +=========================== +Required properties: +-------------------- +- compatible: Shall be "ti,am654-secure-proxy" +- reg-names target_data - Map the proxy data region + rt - Map the realtime status region + scfg - Map the configuration region +- reg: Contains the register map per reg-names. +- #mbox-cells Shall be 1 and shall refer to the transfer path + called thread. +- interrupt-names: Contains interrupt names matching the rx transfer path + for a given SoC. Receive interrupts shall be of the + format: "rx_". +- interrupts: Contains the interrupt information corresponding to + interrupt-names property. + +Example(AM654): +------------ + + secure_proxy: secure_proxy@32c00000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x32c00000 0x0 0x100000>, + <0x0 0x32400000 0x0 0x100000>, + <0x0 0x32800000 0x0 0x100000>; + interrupt-names = "rx_011"; + interrupts = ; + }; + + dmsc: dmsc { + [...] + mbox-names = "rx", "tx"; + # RX Thread ID is 11 + # TX Thread ID is 13 + mboxes= <&secure_proxy 11>, + <&secure_proxy 13>; + [...] + }; From patchwork Tue Jun 19 19:43:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 139244 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5612680lji; Tue, 19 Jun 2018 12:43:52 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIX1BPVXnaiNwu7vDwL94Yq4hbsnTiE+tG0v9RES5EsiUb47XE+lPfw+8KgAZfvv2OKCnGE X-Received: by 2002:a17:902:1566:: with SMTP id b35-v6mr20474904plh.107.1529437432793; Tue, 19 Jun 2018 12:43:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529437432; cv=none; d=google.com; s=arc-20160816; b=bxdtaNWEZm2DTJREOdQvpI/jOUdo79gCxmCxDa+ZwrFurtv243JKhHtMnGns+4ZNV0 PYHaaAVl6E1okTOqD5cHqu0xtlw7KFAsbNaeI7ig5Ehp8/RhYNaj8RrINEyzisEzpxUw DbeQcJFFFDvxHl9HYGe7PYB5AQSvMPpfAZ/oDSoJr8LLUWKU/ldS/dCMlhGuJx5y/Fcc fFqN+uF4jQhT/Gq4oKeq1wW0dDuHnGnLOKk6wrYzrTLBFm2RB/VKilO+JswDOlkzcS1t yFpzxCGWcuz3Fc/2xxGZQCiI++9uwlIfp655fWTbdYyqm1E+ncit6I/zIOf9qIc87Inz AY/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=NZuTxUb9R4H1zntJzO6MoiXIEA6eHuGSdZrsA2W9vHQ=; b=sb6DKYzI81NEC51vzUlBq7ZKTYpORpCpMMbe5sta2JGOhxv0dEITWLWjUYmyQNIyHG RjVLqn1+MynvS9YexhENtCv7MrJSSuUja/d23dI739M3UIPcXWHsqQ6X67+ZfKx0bLIi ffmV0EVYVXzI058mCp8/C+b22hPP+5ZWcXo1Wy5hwZMtOM7qH53JLmpVYlvA5w4zfOg+ VdMPUjparlsRsUw73A83sm9/3nGQB4MlhN8TuBJvY6rdKacLnIXQu/j1CpbdJzN7NSBz t36wDqYqTCpYaV6v8BNchaAzaVP651tAxKMheLFszbV7OPqcULNYah3sqjFGoGoJlB5r M88g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=VWjCZUx9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o12-v6si457792pfd.52.2018.06.19.12.43.52; Tue, 19 Jun 2018 12:43:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=VWjCZUx9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030600AbeFSTnt (ORCPT + 30 others); Tue, 19 Jun 2018 15:43:49 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:24543 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030433AbeFSTnm (ORCPT ); Tue, 19 Jun 2018 15:43:42 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w5JJhcON022549; Tue, 19 Jun 2018 14:43:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1529437418; bh=NZuTxUb9R4H1zntJzO6MoiXIEA6eHuGSdZrsA2W9vHQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VWjCZUx9UC0Z+3L+4BJAyREZz9sLo6LIf/Ph0hDo7XOrRwpb9XByq7ZIO74D3YllL UhosjWH4qsi2BhfV8l5FgCEIbOYp6UrqqUAY4gNsDOZYjC18JTZKCu2QfDvidIz8CV C+2smfPM+2CpUwsrRjgvgFACeoYzX4JFmQh5wauc= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5JJhcxi024525; Tue, 19 Jun 2018 14:43:38 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 19 Jun 2018 14:43:37 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 19 Jun 2018 14:43:37 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5JJhbAf026540; Tue, 19 Jun 2018 14:43:37 -0500 From: Nishanth Menon To: Jassi Brar , Mark Rutland , Rob Herring CC: Nishanth Menon , Suman Anna , Tero Kristo , , Subject: [PATCH 6/6] mailbox: ti-msgmgr: Add support for Secure Proxy Date: Tue, 19 Jun 2018 14:43:37 -0500 Message-ID: <20180619194337.31522-7-nm@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180619194337.31522-1-nm@ti.com> References: <20180619194337.31522-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Secure Proxy is another communication scheme in Texas Instrument's devices intended to provide an unique communication path from various processors in the System on Chip(SoC) to a central System Controller. Secure proxy is, in effect, an evolution of current generation Message Manager hardware block found in K2G devices. However the following changes have taken place: Secure Proxy instance exposes "threads" or "proxies" which is primary representation of "a" communication channel. Each thread is preconfigured by System controller configuration based on SoC usage requirements. Secure proxy by itself represents a single "queue" of communication but allows the proxies to be independently operated. Each Secure proxy thread can uniquely have their own error and threshold interrupts allowing for more fine control of IRQ handling. Provide the driver support for Secure Proxy and thread instances. NOTE: Secure proxy configuration is only done by System Controller, hence these are assumed to be pre-configured instances. See AM65x Technical Reference Manual (SPRUID7, April 2018) for further details: http://www.ti.com/lit/pdf/spruid7 Signed-off-by: Nishanth Menon --- Changes since RFC: None RFC: https://patchwork.kernel.org/patch/10447703/ drivers/mailbox/ti-msgmgr.c | 233 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 205 insertions(+), 28 deletions(-) -- 2.15.1 diff --git a/drivers/mailbox/ti-msgmgr.c b/drivers/mailbox/ti-msgmgr.c index 7167cc708f44..5bceafbf6699 100644 --- a/drivers/mailbox/ti-msgmgr.c +++ b/drivers/mailbox/ti-msgmgr.c @@ -25,6 +25,17 @@ #define Q_STATE_OFFSET(queue) ((queue) * 0x4) #define Q_STATE_ENTRY_COUNT_MASK (0xFFF000) +#define SPROXY_THREAD_OFFSET(tid) (0x1000 * (tid)) +#define SPROXY_THREAD_DATA_OFFSET(tid, reg) \ + (SPROXY_THREAD_OFFSET(tid) + ((reg) * 0x4) + 0x4) + +#define SPROXY_THREAD_STATUS_OFFSET(tid) (SPROXY_THREAD_OFFSET(tid)) + +#define SPROXY_THREAD_STATUS_COUNT_MASK (0xFF) + +#define SPROXY_THREAD_CTRL_OFFSET(tid) (0x1000 + SPROXY_THREAD_OFFSET(tid)) +#define SPROXY_THREAD_CTRL_DIR_MASK (0x1 << 31) + /** * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor * @queue_id: Queue Number for this path @@ -45,12 +56,15 @@ struct ti_msgmgr_valid_queue_desc { * @data_first_reg: First data register for proxy data region * @data_last_reg: Last data register for proxy data region * @status_cnt_mask: Mask for getting the status value + * @status_err_mask: Mask for getting the error value, if applicable * @tx_polled: Do I need to use polled mechanism for tx * @tx_poll_timeout_ms: Timeout in ms if polled * @valid_queues: List of Valid queues that the processor can access * @data_region_name: Name of the proxy data region * @status_region_name: Name of the proxy status region + * @ctrl_region_name: Name of the proxy control region * @num_valid_queues: Number of valid queues + * @is_sproxy: Is this an Secure Proxy instance? * * This structure is used in of match data to describe how integration * for a specific compatible SoC is done. @@ -62,12 +76,15 @@ struct ti_msgmgr_desc { u8 data_first_reg; u8 data_last_reg; u32 status_cnt_mask; + u32 status_err_mask; bool tx_polled; int tx_poll_timeout_ms; const struct ti_msgmgr_valid_queue_desc *valid_queues; const char *data_region_name; const char *status_region_name; + const char *ctrl_region_name; int num_valid_queues; + bool is_sproxy; }; /** @@ -80,6 +97,7 @@ struct ti_msgmgr_desc { * @queue_buff_start: First register of Data Buffer * @queue_buff_end: Last (or confirmation) register of Data buffer * @queue_state: Queue status register + * @queue_ctrl: Queue Control register * @chan: Mailbox channel * @rx_buff: Receive buffer pointer allocated at probe, max_message_size */ @@ -92,6 +110,7 @@ struct ti_queue_inst { void __iomem *queue_buff_start; void __iomem *queue_buff_end; void __iomem *queue_state; + void __iomem *queue_ctrl; struct mbox_chan *chan; u32 *rx_buff; }; @@ -102,6 +121,7 @@ struct ti_queue_inst { * @desc: Description of the SoC integration * @queue_proxy_region: Queue proxy region where queue buffers are located * @queue_state_debug_region: Queue status register regions + * @queue_ctrl_region: Queue Control register regions * @num_valid_queues: Number of valid queues defined for the processor * Note: other queues are probably reserved for other processors * in the SoC. @@ -114,6 +134,7 @@ struct ti_msgmgr_inst { const struct ti_msgmgr_desc *desc; void __iomem *queue_proxy_region; void __iomem *queue_state_debug_region; + void __iomem *queue_ctrl_region; u8 num_valid_queues; struct ti_queue_inst *qinsts; struct mbox_controller mbox; @@ -144,6 +165,31 @@ ti_msgmgr_queue_get_num_messages(const struct ti_msgmgr_desc *d, return val; } +/** + * ti_msgmgr_queue_is_error() - Check to see if there is queue error + * @d: Description of message manager + * @qinst: Queue instance for which we check the number of pending messages + * + * Return: true if error, else false + */ +static inline bool ti_msgmgr_queue_is_error(const struct ti_msgmgr_desc *d, + struct ti_queue_inst *qinst) +{ + u32 val; + + /* Msgmgr has no error detection */ + if (!d->is_sproxy) + return false; + + /* + * We cannot use relaxed operation here - update may happen + * real-time. + */ + val = readl(qinst->queue_state) & d->status_err_mask; + + return val ? true : false; +} + /** * ti_msgmgr_queue_rx_interrupt() - Interrupt handler for receive Queue * @irq: Interrupt number @@ -178,6 +224,11 @@ static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p) } desc = inst->desc; + if (ti_msgmgr_queue_is_error(desc, qinst)) { + dev_err(dev, "Error on Rx channel %s\n", qinst->name); + return IRQ_NONE; + } + /* Do I actually have messages to read? */ msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst); if (!msg_count) { @@ -236,12 +287,18 @@ static bool ti_msgmgr_queue_peek_data(struct mbox_chan *chan) struct ti_queue_inst *qinst = chan->con_priv; struct device *dev = chan->mbox->dev; struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); + const struct ti_msgmgr_desc *desc = inst->desc; int msg_count; if (qinst->is_tx) return false; - msg_count = ti_msgmgr_queue_get_num_messages(inst->desc, qinst); + if (ti_msgmgr_queue_is_error(desc, qinst)) { + dev_err(dev, "Error on channel %s\n", qinst->name); + return false; + } + + msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst); return msg_count ? true : false; } @@ -257,12 +314,23 @@ static bool ti_msgmgr_last_tx_done(struct mbox_chan *chan) struct ti_queue_inst *qinst = chan->con_priv; struct device *dev = chan->mbox->dev; struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); + const struct ti_msgmgr_desc *desc = inst->desc; int msg_count; if (!qinst->is_tx) return false; - msg_count = ti_msgmgr_queue_get_num_messages(inst->desc, qinst); + if (ti_msgmgr_queue_is_error(desc, qinst)) { + dev_err(dev, "Error on channel %s\n", qinst->name); + return false; + } + + msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst); + + if (desc->is_sproxy) { + /* In secure proxy, msg_count indicates how many we can send */ + return msg_count ? true : false; + } /* if we have any messages pending.. */ return msg_count ? false : true; @@ -292,6 +360,11 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data) } desc = inst->desc; + if (ti_msgmgr_queue_is_error(desc, qinst)) { + dev_err(dev, "Error on channel %s\n", qinst->name); + return false; + } + if (desc->max_message_size < message->len) { dev_err(dev, "Queue %s message length %zu > max %d\n", qinst->name, message->len, desc->max_message_size); @@ -327,10 +400,12 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data) /** * ti_msgmgr_queue_rx_irq_req() - RX IRQ request * @dev: device pointer + * @d: descriptor for ti_msgmgr * @qinst: Queue instance * @chan: Channel pointer */ static int ti_msgmgr_queue_rx_irq_req(struct device *dev, + const struct ti_msgmgr_desc *d, struct ti_queue_inst *qinst, struct mbox_chan *chan) { @@ -339,7 +414,7 @@ static int ti_msgmgr_queue_rx_irq_req(struct device *dev, struct device_node *np; snprintf(of_rx_irq_name, sizeof(of_rx_irq_name), - "rx_%03d", qinst->queue_id); + "rx_%03d", d->is_sproxy ? qinst->proxy_id : qinst->queue_id); /* Get the IRQ if not found */ if (qinst->irq < 0) { @@ -382,6 +457,24 @@ static int ti_msgmgr_queue_startup(struct mbox_chan *chan) struct ti_queue_inst *qinst = chan->con_priv; const struct ti_msgmgr_desc *d = inst->desc; int ret; + int msg_count; + + /* + * If sproxy is starting and can send messages, we are a Tx thread, + * else Rx + */ + if (d->is_sproxy) { + qinst->is_tx = (readl(qinst->queue_ctrl) & + SPROXY_THREAD_CTRL_DIR_MASK) ? false : true; + + msg_count = ti_msgmgr_queue_get_num_messages(d, qinst); + + if (!msg_count && qinst->is_tx) { + dev_err(dev, "%s: Cannot transmit with 0 credits!\n", + qinst->name); + return -EINVAL; + } + } if (!qinst->is_tx) { /* Allocate usage buffer for rx */ @@ -389,7 +482,7 @@ static int ti_msgmgr_queue_startup(struct mbox_chan *chan) if (!qinst->rx_buff) return -ENOMEM; /* Request IRQ */ - ret = ti_msgmgr_queue_rx_irq_req(dev, qinst, chan); + ret = ti_msgmgr_queue_rx_irq_req(dev, d, qinst, chan); if (ret) { kfree(qinst->rx_buff); return ret; @@ -427,20 +520,38 @@ static struct mbox_chan *ti_msgmgr_of_xlate(struct mbox_controller *mbox, struct ti_msgmgr_inst *inst; int req_qid, req_pid; struct ti_queue_inst *qinst; - int i; + const struct ti_msgmgr_desc *d; + int i, ncells; inst = container_of(mbox, struct ti_msgmgr_inst, mbox); if (WARN_ON(!inst)) return ERR_PTR(-EINVAL); - /* #mbox-cells is 2 */ - if (p->args_count != 2) { - dev_err(inst->dev, "Invalid arguments in dt[%d] instead of 2\n", - p->args_count); + d = inst->desc; + + if (d->is_sproxy) + ncells = 1; + else + ncells = 2; + if (p->args_count != ncells) { + dev_err(inst->dev, "Invalid arguments in dt[%d]. Must be %d\n", + p->args_count, ncells); return ERR_PTR(-EINVAL); } - req_qid = p->args[0]; - req_pid = p->args[1]; + if (ncells == 1) { + req_qid = 0; + req_pid = p->args[0]; + } else { + req_qid = p->args[0]; + req_pid = p->args[1]; + } + + if (d->is_sproxy) { + if (req_pid > d->num_valid_queues) + goto err; + qinst = &inst->qinsts[req_pid]; + return qinst->chan; + } for (qinst = inst->qinsts, i = 0; i < inst->num_valid_queues; i++, qinst++) { @@ -448,6 +559,7 @@ static struct mbox_chan *ti_msgmgr_of_xlate(struct mbox_controller *mbox, return qinst->chan; } +err: dev_err(inst->dev, "Queue ID %d, Proxy ID %d is wrong on %s\n", req_qid, req_pid, p->np->name); return ERR_PTR(-ENOENT); @@ -474,6 +586,8 @@ static int ti_msgmgr_queue_setup(int idx, struct device *dev, struct ti_queue_inst *qinst, struct mbox_chan *chan) { + char *dir; + qinst->proxy_id = qd->proxy_id; qinst->queue_id = qd->queue_id; @@ -483,17 +597,38 @@ static int ti_msgmgr_queue_setup(int idx, struct device *dev, return -ERANGE; } - qinst->is_tx = qd->is_tx; - snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d_%03d", - dev_name(dev), qinst->is_tx ? "tx" : "rx", qinst->queue_id, - qinst->proxy_id); - - qinst->queue_buff_start = inst->queue_proxy_region + - Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, d->data_first_reg); - qinst->queue_buff_end = inst->queue_proxy_region + - Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, d->data_last_reg); - qinst->queue_state = inst->queue_state_debug_region + - Q_STATE_OFFSET(qinst->queue_id); + if (d->is_sproxy) { + qinst->queue_buff_start = inst->queue_proxy_region + + SPROXY_THREAD_DATA_OFFSET(qinst->proxy_id, + d->data_first_reg); + qinst->queue_buff_end = inst->queue_proxy_region + + SPROXY_THREAD_DATA_OFFSET(qinst->proxy_id, + d->data_last_reg); + qinst->queue_state = inst->queue_state_debug_region + + SPROXY_THREAD_STATUS_OFFSET(qinst->proxy_id); + qinst->queue_ctrl = inst->queue_ctrl_region + + SPROXY_THREAD_CTRL_OFFSET(qinst->proxy_id); + + /* XXX: DONOT read registers here!.. Some may be unusable */ + dir = "thr"; + snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d", + dev_name(dev), dir, qinst->proxy_id); + } else { + qinst->queue_buff_start = inst->queue_proxy_region + + Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, + d->data_first_reg); + qinst->queue_buff_end = inst->queue_proxy_region + + Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, + d->data_last_reg); + qinst->queue_state = + inst->queue_state_debug_region + + Q_STATE_OFFSET(qinst->queue_id); + qinst->is_tx = qd->is_tx; + dir = qinst->is_tx ? "tx" : "rx"; + snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d_%03d", + dev_name(dev), dir, qinst->queue_id, qinst->proxy_id); + } + qinst->chan = chan; /* Setup an error value for IRQ - Lazy allocation */ @@ -543,12 +678,29 @@ static const struct ti_msgmgr_desc k2g_desc = { .tx_polled = false, .valid_queues = k2g_valid_queues, .num_valid_queues = ARRAY_SIZE(k2g_valid_queues), + .is_sproxy = false, +}; + +static const struct ti_msgmgr_desc am654_desc = { + .queue_count = 190, + .num_valid_queues = 190, + .max_message_size = 60, + .data_region_name = "target_data", + .status_region_name = "rt", + .ctrl_region_name = "scfg", + .data_first_reg = 0, + .data_last_reg = 14, + .status_cnt_mask = SPROXY_THREAD_STATUS_COUNT_MASK, + .tx_polled = false, + .is_sproxy = true, }; static const struct of_device_id ti_msgmgr_of_match[] = { {.compatible = "ti,k2g-message-manager", .data = &k2g_desc}, + {.compatible = "ti,am654-secure-proxy", .data = &am654_desc}, { /* Sentinel */ } }; + MODULE_DEVICE_TABLE(of, ti_msgmgr_of_match); static int ti_msgmgr_probe(struct platform_device *pdev) @@ -599,6 +751,14 @@ static int ti_msgmgr_probe(struct platform_device *pdev) if (IS_ERR(inst->queue_state_debug_region)) return PTR_ERR(inst->queue_state_debug_region); + if (desc->is_sproxy) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + desc->ctrl_region_name); + inst->queue_ctrl_region = devm_ioremap_resource(dev, res); + if (IS_ERR(inst->queue_ctrl_region)) + return PTR_ERR(inst->queue_ctrl_region); + } + dev_dbg(dev, "proxy region=%p, queue_state=%p\n", inst->queue_proxy_region, inst->queue_state_debug_region); @@ -620,12 +780,29 @@ static int ti_msgmgr_probe(struct platform_device *pdev) return -ENOMEM; inst->chans = chans; - for (i = 0, queue_desc = desc->valid_queues; - i < queue_count; i++, qinst++, chans++, queue_desc++) { - ret = ti_msgmgr_queue_setup(i, dev, np, inst, - desc, queue_desc, qinst, chans); - if (ret) - return ret; + if (desc->is_sproxy) { + struct ti_msgmgr_valid_queue_desc sproxy_desc; + + /* All proxies may be valid in Secure Proxy instance */ + for (i = 0; i < queue_count; i++, qinst++, chans++) { + sproxy_desc.queue_id = 0; + sproxy_desc.proxy_id = i; + ret = ti_msgmgr_queue_setup(i, dev, np, inst, + desc, &sproxy_desc, qinst, + chans); + if (ret) + return ret; + } + } else { + /* Only Some proxies are valid in Message Manager */ + for (i = 0, queue_desc = desc->valid_queues; + i < queue_count; i++, qinst++, chans++, queue_desc++) { + ret = ti_msgmgr_queue_setup(i, dev, np, inst, + desc, queue_desc, qinst, + chans); + if (ret) + return ret; + } } mbox = &inst->mbox;