From patchwork Tue Jun 19 12:53:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 139112 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5170745lji; Tue, 19 Jun 2018 05:53:28 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLfcBy+eCf/7JEfTKb0vCj5f46luemw1IUtq1cAZjKAeGjuMMVbG7SKJqsJtZIrwSYJQPzd X-Received: by 2002:a17:902:622:: with SMTP id 31-v6mr18631937plg.135.1529412808485; Tue, 19 Jun 2018 05:53:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529412808; cv=none; d=google.com; s=arc-20160816; b=BlUUdVOeKzcS74gUH/sAFONm0kDvTN0ss2lmmV2dvqac1G3JK/wjDu/7W1DEBo+q5p tTYJ59IoCpfteGC3GnFTc2GXTQlKIpobT/RApmu+4TkwLR3O07aiVEX/TE/oy+d9lvRp 2seriB1IlCmjnEcPtaldq8PUFd1QWFESpwg8de5ZUgpG+HYMNQbNUvU9FKAv/fvFq4s4 dzQcUz4sffKWH4jN9W0brkMAJnq5SZIU9YWh4UHZdBRxIMnnzdBWMFOtgXjCrviC3Svw tEMt6bLNYU23fO96PdKGK5nLFwM3BwN1AmtO7L+6M9yJqaDLmebb0KysjUnmn/fLdra8 EiqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=k+s9Vf+IyzX9x6W5RPMjrhsY0/5nokEG/V7DA5yUK3k=; b=CWsHRD+N1k7Pt/rsVxiMGYNChFX7p7kdQ/Pe5uMYbCS1NckzlLJDtkl3NeBqxQSceB hU1ia50rxNcDnaW4qWtKc2xHzWiLFdClf1hR2ji84xWpNwrws2Mo6hkKei/32JkWuoMJ m1SHe1hyYehPVTKzxRfpSHslFZZnXR8BVQpJDVanufdEjoZtOzL56X4xBqYdwlagDvrE QD/tU5AUndleH12VTmrWszfpEHXTJ1lcbCeyAof3tta+fCKgDFX4NvctxD6k2XUk/y+L zuqkGTtqDS1bc/zvHRO7y7NXuhqZPptuw2ZrUoi5orHSxrZDTjQla7FoNphU5uVrxG0J yd/A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j13-v6si14169186pgc.288.2018.06.19.05.53.28; Tue, 19 Jun 2018 05:53:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937888AbeFSMwo (ORCPT + 30 others); Tue, 19 Jun 2018 08:52:44 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:49296 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937847AbeFSMwk (ORCPT ); Tue, 19 Jun 2018 08:52:40 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 290291596; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EF46C3F59C; Tue, 19 Jun 2018 05:52:39 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 854261AE0F4E; Tue, 19 Jun 2018 13:53:15 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon , Yoshinori Sato Subject: [RESEND PATCH v2 1/9] h8300: Don't include linux/kernel.h in asm/atomic.h Date: Tue, 19 Jun 2018 13:53:06 +0100 Message-Id: <1529412794-17720-2-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1529412794-17720-1-git-send-email-will.deacon@arm.com> References: <1529412794-17720-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org linux/kernel.h isn't needed by asm/atomic.h and will result in circular dependencies when the asm-generic atomic bitops are built around the tomic_long_t interface. Remove the broad include and replace it with linux/compiler.h for READ_ONCE() etc and asm/irqflags.h for arch_local_irq_save() etc. Cc: Yoshinori Sato Acked-by: Peter Zijlstra (Intel) Signed-off-by: Will Deacon --- arch/h8300/include/asm/atomic.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.1.4 diff --git a/arch/h8300/include/asm/atomic.h b/arch/h8300/include/asm/atomic.h index 941e7554e886..b174dec099bf 100644 --- a/arch/h8300/include/asm/atomic.h +++ b/arch/h8300/include/asm/atomic.h @@ -2,8 +2,10 @@ #ifndef __ARCH_H8300_ATOMIC__ #define __ARCH_H8300_ATOMIC__ +#include #include #include +#include /* * Atomic operations that C can't guarantee us. Useful for @@ -15,8 +17,6 @@ #define atomic_read(v) READ_ONCE((v)->counter) #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i)) -#include - #define ATOMIC_OP_RETURN(op, c_op) \ static inline int atomic_##op##_return(int i, atomic_t *v) \ { \ From patchwork Tue Jun 19 12:53:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 139111 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5170370lji; Tue, 19 Jun 2018 05:53:02 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKYrAKvjWy7vWoeimCVgMg6moYJLwkoNJgg7L20qhIkjp8saMRd4MPnCMqa8Fa584cTCEKH X-Received: by 2002:a62:e005:: with SMTP id f5-v6mr18149472pfh.88.1529412781861; Tue, 19 Jun 2018 05:53:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529412781; cv=none; d=google.com; s=arc-20160816; b=B/RTMVmYMCsUfoqEpDsTr4YptfA5XJGBHeh/1xbNBdQeiGkxDZfRLVuLFG/YFMuquY hOGPqQrcu54KuEL9Um3PnB/LcezxQH3I5M0mffF1vnUMryQHAeUJ4iUSK+IniEZsaxo/ xm3oCynVDcqmVJsGqmw4+1L7DYLz5atJR0fYT0CYe/5n30cK2Xm6cLpRRaa15nNaWIob 8IrVGpijIPg7ommvpZKQH0Y2OIkVwN/OCJdgsRUlkxZ2JGHmYxdnpiKjzNsFjiTjIc2N mU+soecuAwNfK7/j9JY/0IqvpaRTmyrGo1mnfCu8GAcRZkr5gsP0QnIMlZlvm/P6nuhA qa2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=PgUR7T1oloEwNNr9qJji2CAZyuQHiHeevFuByilgzoU=; b=k2Sj7tHCF63kzN1pyol7XK+pgyKjUD5tvZVimXsNgj2sKu5Jmo5e02IkgUKAvai8TW NFqFzGCD+PTfisZPx1DHGG+Z7UhuXzhlVaoYG/tG9ybM9Wlq45IyAJiktK+f1VW8nCYk ElD+pZJrRrlxN8udoTOS5zlSe/T1OjI0bPRCAbko4ClCPQoUlpmEwx0cSGca6FD6AfIe hV6yIdRKh4WmAE7vGMErrt5vG46hJx6vRJ5onPKocrUOVCauKpvMcTfFxj/gp0yGu1nB 1REhrPGnsnd0S7a4XKpOuJ0p/3Hn+Kl6v3aFzNi1ZcG54jUxInSxCaNwsQhrLCu56hcw LbBg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n3-v6si17286642pld.116.2018.06.19.05.53.01; Tue, 19 Jun 2018 05:53:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937901AbeFSMwp (ORCPT + 30 others); Tue, 19 Jun 2018 08:52:45 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:49306 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937848AbeFSMwk (ORCPT ); Tue, 19 Jun 2018 08:52:40 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 38D5C15BE; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0A51C3F5B6; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 9B7331AE3632; Tue, 19 Jun 2018 13:53:15 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RESEND PATCH v2 2/9] m68k: Don't use asm-generic/bitops/lock.h Date: Tue, 19 Jun 2018 13:53:07 +0100 Message-Id: <1529412794-17720-3-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1529412794-17720-1-git-send-email-will.deacon@arm.com> References: <1529412794-17720-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org asm-generic/bitops/lock.h is shortly going to be built on top of the atomic_long_* API, which introduces a nasty circular dependency for m68k where linux/atomic.h pulls in linux/bitops.h via: linux/atomic.h asm/atomic.h linux/irqflags.h asm/irqflags.h linux/preempt.h asm/preempt.h asm-generic/preempt.h linux/thread_info.h asm/thread_info.h asm/page.h asm-generic/getorder.h linux/log2.h linux/bitops.h Since m68k isn't SMP and doesn't support ACQUIRE/RELEASE barriers, we can just define the lock bitops in terms of the atomic bitops in the asm/bitops.h header. Acked-by: Geert Uytterhoeven Acked-by: Peter Zijlstra (Intel) Signed-off-by: Will Deacon --- arch/m68k/include/asm/bitops.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index 93b47b1f6fb4..18193419f97d 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -515,12 +515,16 @@ static inline int __fls(int x) #endif +/* Simple test-and-set bit locks */ +#define test_and_set_bit_lock test_and_set_bit +#define clear_bit_unlock clear_bit +#define __clear_bit_unlock clear_bit_unlock + #include #include #include #include #include -#include #endif /* __KERNEL__ */ #endif /* _M68K_BITOPS_H */ From patchwork Tue Jun 19 12:53:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 139110 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5170164lji; Tue, 19 Jun 2018 05:52:50 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKmbYiuYcw707JEbORPULPyG/nXR2YsZ8E5GWizGLKPMug3Bv7zVSLCEmE5WkJCZT+x6t8K X-Received: by 2002:a17:902:280b:: with SMTP id e11-v6mr18740144plb.298.1529412770064; Tue, 19 Jun 2018 05:52:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529412770; cv=none; d=google.com; s=arc-20160816; b=QZFyRquqAhg7gevGG92pshewQSPhgnyXl4c/7JhoxvTQ2ENL5JQwgFsR9hYQDFXQEM DZBDoItl8D44mMpXaXGLhV97kgt5ANBFbCG14hMch/T6KxmHulkihKErWa/YptxbE+hl gRj+zxwBm4zzSs7wD2P5TB+T6ICVtvXD0XZ1LVTqtc1ZuqeIrsuxQwF7ZgygBB90UfR1 AlQnDsox2T3ghxh94KY8HMRDPivK6r94xqtl5GiTenE9QysbGSpnpA9ObiHTP0EHhfkj iJ7iMymt7Jw3ZaEzJdNwtb/lkiuieQL2M+jdXp4uMi4PtPCsgplFXWm4FxvKdVwJP98F WANQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Y5nJSRHCmQMhRLBNBZo6Pv7oyT/JSD1eVdxM3H5iH1c=; b=maEc00BHrE/h6qRP1UbJOuPKLuWPjNPl2bbUK2Z2BZaS0cOEzQK0SvedwRTjW6XxtY fNUhJgt1KbYDr+xqZ2Y7QESJbDRk0bAEpMlvbEkRxCFgT9cfyynIiRijH/+Cw/OKbgDg Nht/cWOxC0awTMv6zLdeAVPe4bl8jXaTiBZ1S4YHUwwxGMJzZpiPvUt/mYcr4unU0lyW 9T2+Ynqli6O39GyJIRIzGYso1E9cLoFLQpmEhoxaxL8G0q2zEe+kq42Z0va+fL5/Faxg RNypPOA4ikahV5KzWcuSPkMpY6GiHL6XYYQwqb9quXENSrWBNCJvEzQ5c1dcJZCHyJcs Z5Mw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k91-v6si17768945pld.248.2018.06.19.05.52.49; Tue, 19 Jun 2018 05:52:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937913AbeFSMwr (ORCPT + 30 others); Tue, 19 Jun 2018 08:52:47 -0400 Received: from foss.arm.com ([217.140.101.70]:49316 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937849AbeFSMwk (ORCPT ); Tue, 19 Jun 2018 08:52:40 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 47DAC15BF; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 19E453F557; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id ABBBC1AE3638; Tue, 19 Jun 2018 13:53:15 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RESEND PATCH v2 3/9] asm-generic: Move some macros from linux/bitops.h to a new bits.h file Date: Tue, 19 Jun 2018 13:53:08 +0100 Message-Id: <1529412794-17720-4-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1529412794-17720-1-git-send-email-will.deacon@arm.com> References: <1529412794-17720-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation for implementing the asm-generic atomic bitops in terms of atomic_long_*, we need to prevent asm/atomic.h implementations from pulling in linux/bitops.h. A common reason for this include is for the BITS_PER_BYTE definition, so move this and some other BIT() and masking macros into a new header file, linux/bits.h Acked-by: Peter Zijlstra (Intel) Signed-off-by: Will Deacon --- include/linux/bitops.h | 22 +--------------------- include/linux/bits.h | 26 ++++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 21 deletions(-) create mode 100644 include/linux/bits.h -- 2.1.4 Signed-off-by: Chris Wilson Reviewed-by: Jani Nikula Signed-off-by: Andrew Morton diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 4cac4e1a72ff..af419012d77d 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -2,29 +2,9 @@ #ifndef _LINUX_BITOPS_H #define _LINUX_BITOPS_H #include +#include -#ifdef __KERNEL__ -#define BIT(nr) (1UL << (nr)) -#define BIT_ULL(nr) (1ULL << (nr)) -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) -#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) -#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) -#define BITS_PER_BYTE 8 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) -#endif - -/* - * Create a contiguous bitmask starting at bit position @l and ending at - * position @h. For example - * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. - */ -#define GENMASK(h, l) \ - (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) - -#define GENMASK_ULL(h, l) \ - (((~0ULL) - (1ULL << (l)) + 1) & \ - (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) extern unsigned int __sw_hweight8(unsigned int w); extern unsigned int __sw_hweight16(unsigned int w); diff --git a/include/linux/bits.h b/include/linux/bits.h new file mode 100644 index 000000000000..2b7b532c1d51 --- /dev/null +++ b/include/linux/bits.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_BITS_H +#define __LINUX_BITS_H +#include + +#define BIT(nr) (1UL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) +#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) +#define BITS_PER_BYTE 8 + +/* + * Create a contiguous bitmask starting at bit position @l and ending at + * position @h. For example + * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. + */ +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define GENMASK_ULL(h, l) \ + (((~0ULL) - (1ULL << (l)) + 1) & \ + (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + +#endif /* __LINUX_BITS_H */ From patchwork Tue Jun 19 12:53:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 139119 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5172980lji; Tue, 19 Jun 2018 05:55:52 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLdqfQA0EViw+6mvCuCGWB6tPt5FG7SH5aRKT46G7hl41onguV3uoatr4rbfE2XCI1GDqwk X-Received: by 2002:a65:5106:: with SMTP id f6-v6mr14664601pgq.122.1529412952420; Tue, 19 Jun 2018 05:55:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529412952; cv=none; d=google.com; s=arc-20160816; b=e0ges7hf8lmaIfB68kv7kcVUylJE0HjFlKbbeb5oKWFDtOQijd03bJF9mo0q7/ZH1k I4auvl5zxmwsncWCiJurPxUBsR/mVRIdLet7IBD4SxXehtb1kznrCgp4hTj3xnD+rcOY 2Ehre9ih8OLjbKHgeNsJUuyPXQv5SPr5oJ1dkdV90bYLySXfTauwfO9ZSx3bxybqRjAk eWNnHRm4JbyTQrQ+4A7yAzWvS0Eggsnpecq59uWUtuTOMZyblPe9SFVL0x11atnhW1Xw aO9f3MErixG6BAv3gy9iujCUtLBW4BNVHSX/NO0UXwJln/Trv3HeS1LPERUKRhc67wb6 oixA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=MHzLHwvig5B8V93F16//D3CklXT6WamK7UYUHkz7Yxg=; b=bQjLo+iii+ThDUHYmn9p8qDuisGpZosnX/77/seEn+gITB9NiynixCpx8MY67C0hg1 cfuoP6Ym0EFv8QZ99San8KJCC+sBHUzKF/JXONONS7q+ZUbI69hm8Jk3AHjVtIbn/I6x ZMNOti8DP3qn1DUe/KaZkFdIWUPUd0k+PvcBqiWsARjkMn/4oazQi93VEoCcimN6UaMa Uz8niBH69eO1gzIneTsP0mKaLXo3dabP3T9ayRiXN7w0FBFRrGkhwGe4Q9rXnluL3vEf /oP+B9osqZtZ48D/62zy2Zl9uS6qa24u/GYfLlPQGbnBNPGuUjR5Ev9r6y0j8UfRPDYR 04Tw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y20-v6si17620224plp.267.2018.06.19.05.55.52; Tue, 19 Jun 2018 05:55:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937960AbeFSMzs (ORCPT + 30 others); Tue, 19 Jun 2018 08:55:48 -0400 Received: from foss.arm.com ([217.140.101.70]:49326 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937853AbeFSMwk (ORCPT ); Tue, 19 Jun 2018 08:52:40 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 58EA8164F; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2B1AD3F59C; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id BA4381AE3692; Tue, 19 Jun 2018 13:53:15 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RESEND PATCH v2 4/9] openrisc: Don't pull in all of linux/bitops.h in asm/cmpxchg.h Date: Tue, 19 Jun 2018 13:53:09 +0100 Message-Id: <1529412794-17720-5-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1529412794-17720-1-git-send-email-will.deacon@arm.com> References: <1529412794-17720-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The openrisc implementation of asm/cmpxchg.h pulls in linux/bitops.h so that it can refer to BITS_PER_BYTE. It also transitively relies on this pulling in linux/compiler.h for READ_ONCE(). Replace the #include with linux/bits.h and linux/compiler.h Acked-by: Peter Zijlstra (Intel) Signed-off-by: Will Deacon --- arch/openrisc/include/asm/cmpxchg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/openrisc/include/asm/cmpxchg.h b/arch/openrisc/include/asm/cmpxchg.h index d29f7db53906..f9cd43a39d72 100644 --- a/arch/openrisc/include/asm/cmpxchg.h +++ b/arch/openrisc/include/asm/cmpxchg.h @@ -16,8 +16,9 @@ #ifndef __ASM_OPENRISC_CMPXCHG_H #define __ASM_OPENRISC_CMPXCHG_H +#include +#include #include -#include #define __HAVE_ARCH_CMPXCHG 1 From patchwork Tue Jun 19 12:53:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 139118 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5172706lji; Tue, 19 Jun 2018 05:55:35 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKvT9pif5xP8dInvaSH6tt8hzU2JXIL3RcgYI4XR9NbhuMsMYbGV4xAcEhKmv0t7DkGf3WL X-Received: by 2002:a65:4d08:: with SMTP id i8-v6mr14859911pgt.427.1529412935654; Tue, 19 Jun 2018 05:55:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529412935; cv=none; d=google.com; s=arc-20160816; b=Sxz1I/h8iOpHAUPlUtv5fnJsutOyZlbGzLhiOWUM2iVvpPCm9eLbLxncwKFeg5nV1d Z2CVhb+jH22qqDwqX06YRB218hEpk7waZ2ihB3bjBzJc1m9l2HOdDVUfj4KjZ1+wu2Wz 5HXcz3F8CN3Z45cCTH1xFsw3Fwae8A3rRVMqTYEv8La+oY/LFu2xmlpmRB3jc/P6xmnY h4ne5TKLdN1MD5oxNdJTqA/zumrm/FanFGZP/j/hWcMsqPZdhgyxO6ByVLQ5HaMnTHkO v9Y4KkrVUinhiI3UNU701j7CRX21eI69oYU1I4ysVVKYmGKbgSkzsk8I57owzJa53bvm UBxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=//QOMuPzMbUFU/Px57jKoaHSiE9SJM4w4mLtMoekew8=; b=FPaU7E6jdBVqdwk6p/PSWskLA45TFClntRW/3FHJ3uF8D0F6/zAhNkda9GQ6AUwcMl UIyh83RyY0JzvAM3VHeUUAdvemvsLtm6Mxf+iwU9XqwpP/VfighoDbdE2s+sknhc5QRM 88Fu9C1mFScMu7aYKmVdR3ZL312srJ9UuM0KXN6G3Y/rOHJ3uxk/Z/QzZFqi4tk8HqNm GKO5suMUz3+YuzqUU0e47+efKrjaQjvXagpRYDYJu+pktIdMxhKWJtcud2grcossed3F FPeGNEfCCEHwzaJ0cMH8MSngN8p2W1H6q9YKa5Ko2sY/EAghmU3nS3fKFpFTYsJeHzi0 rUgg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a76-v6si18919598pfk.35.2018.06.19.05.55.35; Tue, 19 Jun 2018 05:55:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937905AbeFSMzR (ORCPT + 30 others); Tue, 19 Jun 2018 08:55:17 -0400 Received: from foss.arm.com ([217.140.101.70]:49350 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937858AbeFSMwl (ORCPT ); Tue, 19 Jun 2018 08:52:41 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 09418165C; Tue, 19 Jun 2018 05:52:41 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CF18D3F59C; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id CC47F1AE36A0; Tue, 19 Jun 2018 13:53:15 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RESEND PATCH v2 5/9] sh: Don't pull in all of linux/bitops.h in asm/cmpxchg-xchg.h Date: Tue, 19 Jun 2018 13:53:10 +0100 Message-Id: <1529412794-17720-6-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1529412794-17720-1-git-send-email-will.deacon@arm.com> References: <1529412794-17720-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The sh implementation of asm/cmpxchg-xchg.h pulls in linux/bitops.h so that it can refer to BITS_PER_BYTE. It also transitively relies on this pulling in linux/compiler.h for READ_ONCE(). Replace the #include with linux/bits.h and linux/compiler.h Acked-by: Peter Zijlstra (Intel) Signed-off-by: Will Deacon --- arch/sh/include/asm/cmpxchg-xchg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/sh/include/asm/cmpxchg-xchg.h b/arch/sh/include/asm/cmpxchg-xchg.h index 1e881f5db659..593a9704782b 100644 --- a/arch/sh/include/asm/cmpxchg-xchg.h +++ b/arch/sh/include/asm/cmpxchg-xchg.h @@ -8,7 +8,8 @@ * This work is licensed under the terms of the GNU GPL, version 2. See the * file "COPYING" in the main directory of this archive for more details. */ -#include +#include +#include #include /* From patchwork Tue Jun 19 12:53:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 139117 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5172530lji; Tue, 19 Jun 2018 05:55:23 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLQv2FzkDho4GdQzc/OeSfqoG53XrwOmWkSFJ/OABOKreSlEpsi1W2lncY/f4dcow5yido+ X-Received: by 2002:a62:9419:: with SMTP id m25-v6mr17980184pfe.120.1529412923294; Tue, 19 Jun 2018 05:55:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529412923; cv=none; d=google.com; s=arc-20160816; b=rG+MjWJw07kk9m7RglTy7nIYpdLzLLC+0tARbEMncQrMx3vRQkx5Dmm9S72nLSEWwx wDqKwAqM1Aq2FhrW/peZ8hSX7tI+rJerOs7vBUih5zepMjSCQNxcnhHNLamYOXsH1rHh 52EGMn/JhrobKLq+kmlcFMg49pJ71q+ukEtICFfqWngNOYXc1zjbcnS/PEwA4SDpSc3L YGJXe3XyWgt6So8+t6bnsShXx6zDo7eOKbsxYz/c8/65yR8W+M/3DyUsun8Hlzhlsvdu oQEkiyhiOUSfQDRNNyc66Re6bBXx1hgcNNVy6Q7TxAHS7Tdn/XU1ds5L87isK26Tc3Rx PAfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Gg9C4/6ZRYAo92TROsVov7p7aoQbcWEtQ183Cq48cLA=; b=uW5Aq6TYh8wEitNo89wEUTSHimMuzmLUoc8+p5tO3CjOIMW1oifuCdvEhsVBUb+ZKf vKmVmvpRr/t80EyQZlYO9s6gHaB2J9KAMAUT5FFwxJ5tGFhbnW6ctAl05lR7g+3mv9dU iFxwqY7gUzR7W8vbIWGV6gVciPcsMr2uM5UwdLEBf4DSPeOHoRRQcmurKrsXCc1x2Ar1 qXvi5WucCU72Kuv0wkQ6YQ/FVOrNfrUnvhOEJNxOJUE+gucu6cvNG8IBsydVgpDKV2QC yo1fZrcmytBDzKDhsK7Cb2BzGfdfW1YUJ34Ozy0Ib4XY9eeJJnSRHMHYTfEbAM/qXIDH qmRQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n64-v6si17545306pfh.210.2018.06.19.05.55.23; Tue, 19 Jun 2018 05:55:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937931AbeFSMzT (ORCPT + 30 others); Tue, 19 Jun 2018 08:55:19 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:49346 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937854AbeFSMwl (ORCPT ); Tue, 19 Jun 2018 08:52:41 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F41EA15B2; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C626B3F557; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id DC99E1AE36FB; Tue, 19 Jun 2018 13:53:15 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RESEND PATCH v2 6/9] asm-generic/bitops/atomic.h: Rewrite using atomic_* Date: Tue, 19 Jun 2018 13:53:11 +0100 Message-Id: <1529412794-17720-7-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1529412794-17720-1-git-send-email-will.deacon@arm.com> References: <1529412794-17720-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The atomic bitops can actually be implemented pretty efficiently using the atomic_* ops, rather than explicit use of spinlocks. Cc: Peter Zijlstra Cc: Ingo Molnar Acked-by: Peter Zijlstra (Intel) Signed-off-by: Will Deacon --- include/asm-generic/bitops/atomic.h | 188 +++++++----------------------------- 1 file changed, 33 insertions(+), 155 deletions(-) -- 2.1.4 diff --git a/include/asm-generic/bitops/atomic.h b/include/asm-generic/bitops/atomic.h index 04deffaf5f7d..dd90c9792909 100644 --- a/include/asm-generic/bitops/atomic.h +++ b/include/asm-generic/bitops/atomic.h @@ -2,189 +2,67 @@ #ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_ #define _ASM_GENERIC_BITOPS_ATOMIC_H_ -#include -#include - -#ifdef CONFIG_SMP -#include -#include /* we use L1_CACHE_BYTES */ - -/* Use an array of spinlocks for our atomic_ts. - * Hash function to index into a different SPINLOCK. - * Since "a" is usually an address, use one spinlock per cacheline. - */ -# define ATOMIC_HASH_SIZE 4 -# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) - -extern arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; - -/* Can't use raw_spin_lock_irq because of #include problems, so - * this is the substitute */ -#define _atomic_spin_lock_irqsave(l,f) do { \ - arch_spinlock_t *s = ATOMIC_HASH(l); \ - local_irq_save(f); \ - arch_spin_lock(s); \ -} while(0) - -#define _atomic_spin_unlock_irqrestore(l,f) do { \ - arch_spinlock_t *s = ATOMIC_HASH(l); \ - arch_spin_unlock(s); \ - local_irq_restore(f); \ -} while(0) - - -#else -# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) -# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) -#endif +#include +#include +#include /* - * NMI events can occur at any time, including when interrupts have been - * disabled by *_irqsave(). So you can get NMI events occurring while a - * *_bit function is holding a spin lock. If the NMI handler also wants - * to do bit manipulation (and they do) then you can get a deadlock - * between the original caller of *_bit() and the NMI handler. - * - * by Keith Owens + * Implementation of atomic bitops using atomic-fetch ops. + * See Documentation/atomic_bitops.txt for details. */ -/** - * set_bit - Atomically set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * This function is atomic and may not be reordered. See __set_bit() - * if you do not require the atomic guarantees. - * - * Note: there are no guarantees that this function will not be reordered - * on non x86 architectures, so if you are writing portable code, - * make sure not to rely on its reordering guarantees. - * - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void set_bit(int nr, volatile unsigned long *addr) +static inline void set_bit(unsigned int nr, volatile unsigned long *p) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p |= mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + atomic_long_or(BIT_MASK(nr), (atomic_long_t *)p); } -/** - * clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and may not be reordered. However, it does - * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() - * in order to ensure changes are visible on other processors. - */ -static inline void clear_bit(int nr, volatile unsigned long *addr) +static inline void clear_bit(unsigned int nr, volatile unsigned long *p) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p &= ~mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + atomic_long_andnot(BIT_MASK(nr), (atomic_long_t *)p); } -/** - * change_bit - Toggle a bit in memory - * @nr: Bit to change - * @addr: Address to start counting from - * - * change_bit() is atomic and may not be reordered. It may be - * reordered on other architectures than x86. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void change_bit(int nr, volatile unsigned long *addr) +static inline void change_bit(unsigned int nr, volatile unsigned long *p) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p ^= mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + atomic_long_xor(BIT_MASK(nr), (atomic_long_t *)p); } -/** - * test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It may be reordered on other architectures than x86. - * It also implies a memory barrier. - */ -static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +static inline int test_and_set_bit(unsigned int nr, volatile unsigned long *p) { + long old; unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old | mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + if (READ_ONCE(*p) & mask) + return 1; - return (old & mask) != 0; + old = atomic_long_fetch_or(mask, (atomic_long_t *)p); + return !!(old & mask); } -/** - * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It can be reorderdered on other architectures other than x86. - * It also implies a memory barrier. - */ -static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +static inline int test_and_clear_bit(unsigned int nr, volatile unsigned long *p) { + long old; unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old & ~mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + if (!(READ_ONCE(*p) & mask)) + return 0; - return (old & mask) != 0; + old = atomic_long_fetch_andnot(mask, (atomic_long_t *)p); + return !!(old & mask); } -/** - * test_and_change_bit - Change a bit and return its old value - * @nr: Bit to change - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +static inline int test_and_change_bit(unsigned int nr, volatile unsigned long *p) { + long old; unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old ^ mask; - _atomic_spin_unlock_irqrestore(p, flags); - return (old & mask) != 0; + p += BIT_WORD(nr); + old = atomic_long_fetch_xor(mask, (atomic_long_t *)p); + return !!(old & mask); } #endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */ From patchwork Tue Jun 19 12:53:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 139115 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5171937lji; Tue, 19 Jun 2018 05:54:45 -0700 (PDT) X-Google-Smtp-Source: ADUXVKITKpxYIHHRG4liIdyV/lclkEa3xdv/5U8c6cDe/p9hdBJgUiSVNlpE7pnODX/6BUAr1FrB X-Received: by 2002:a62:c809:: with SMTP id z9-v6mr17864573pff.5.1529412885614; Tue, 19 Jun 2018 05:54:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529412885; cv=none; d=google.com; s=arc-20160816; b=MsxRRsy4mS9k5Z9rKVR/w0b8z6/wL7V6mMU7Hhs++0m1XQBWwnYt2HfjsHObuM5k/w Dtm9GjGrsdltJQeT+q/HDGPTfs/NfF/2FVTQms3xgpLvnrNJfBqiiuxu2mMOQ8KMtAy8 6LQ3zGUWfndmdFxVkfQecbjO+yYXYRh4EFIEEKhVfwNB1g5hwVuHnRGCBqFQcVx83+nC sfwCQ39T+24fMP1j9gtv5HmMgkXPiCuE6ql5pP/j3fyBP0B0V/zmGsCLSwrHqUheF/ss dn9OIhszGBk6A4IjaIzSd27vL6rPI6DCmGsvQt/qKkL8iH3oHABrosd2oLpbXJ38f2LM 0s0Q== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id e9-v6si14024571pgo.397.2018.06.19.05.54.45; Tue, 19 Jun 2018 05:54:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937902AbeFSMym (ORCPT + 30 others); Tue, 19 Jun 2018 08:54:42 -0400 Received: from foss.arm.com ([217.140.101.70]:49354 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937859AbeFSMwl (ORCPT ); Tue, 19 Jun 2018 08:52:41 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1368B1682; Tue, 19 Jun 2018 05:52:41 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D96163F5B6; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id ECDF91AE3700; Tue, 19 Jun 2018 13:53:15 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RESEND PATCH v2 7/9] asm-generic/bitops/lock.h: Rewrite using atomic_fetch_* Date: Tue, 19 Jun 2018 13:53:12 +0100 Message-Id: <1529412794-17720-8-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1529412794-17720-1-git-send-email-will.deacon@arm.com> References: <1529412794-17720-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The lock bitops can be implemented more efficiently using the atomic_fetch_* ops, which provide finer-grained control over the memory ordering semantics than the bitops. Cc: Peter Zijlstra Cc: Ingo Molnar Acked-by: Peter Zijlstra (Intel) Signed-off-by: Will Deacon --- include/asm-generic/bitops/lock.h | 68 ++++++++++++++++++++++++++++++++------- 1 file changed, 56 insertions(+), 12 deletions(-) -- 2.1.4 diff --git a/include/asm-generic/bitops/lock.h b/include/asm-generic/bitops/lock.h index 67ab280ad134..3ae021368f48 100644 --- a/include/asm-generic/bitops/lock.h +++ b/include/asm-generic/bitops/lock.h @@ -2,6 +2,10 @@ #ifndef _ASM_GENERIC_BITOPS_LOCK_H_ #define _ASM_GENERIC_BITOPS_LOCK_H_ +#include +#include +#include + /** * test_and_set_bit_lock - Set a bit and return its old value, for lock * @nr: Bit to set @@ -11,7 +15,20 @@ * the returned value is 0. * It can be used to implement bit locks. */ -#define test_and_set_bit_lock(nr, addr) test_and_set_bit(nr, addr) +static inline int test_and_set_bit_lock(unsigned int nr, + volatile unsigned long *p) +{ + long old; + unsigned long mask = BIT_MASK(nr); + + p += BIT_WORD(nr); + if (READ_ONCE(*p) & mask) + return 1; + + old = atomic_long_fetch_or_acquire(mask, (atomic_long_t *)p); + return !!(old & mask); +} + /** * clear_bit_unlock - Clear a bit in memory, for unlock @@ -20,11 +37,11 @@ * * This operation is atomic and provides release barrier semantics. */ -#define clear_bit_unlock(nr, addr) \ -do { \ - smp_mb__before_atomic(); \ - clear_bit(nr, addr); \ -} while (0) +static inline void clear_bit_unlock(unsigned int nr, volatile unsigned long *p) +{ + p += BIT_WORD(nr); + atomic_long_fetch_andnot_release(BIT_MASK(nr), (atomic_long_t *)p); +} /** * __clear_bit_unlock - Clear a bit in memory, for unlock @@ -37,11 +54,38 @@ do { \ * * See for example x86's implementation. */ -#define __clear_bit_unlock(nr, addr) \ -do { \ - smp_mb__before_atomic(); \ - clear_bit(nr, addr); \ -} while (0) +static inline void __clear_bit_unlock(unsigned int nr, + volatile unsigned long *p) +{ + unsigned long old; -#endif /* _ASM_GENERIC_BITOPS_LOCK_H_ */ + p += BIT_WORD(nr); + old = READ_ONCE(*p); + old &= ~BIT_MASK(nr); + atomic_long_set_release((atomic_long_t *)p, old); +} + +/** + * clear_bit_unlock_is_negative_byte - Clear a bit in memory and test if bottom + * byte is negative, for unlock. + * @nr: the bit to clear + * @addr: the address to start counting from + * + * This is a bit of a one-trick-pony for the filemap code, which clears + * PG_locked and tests PG_waiters, + */ +#ifndef clear_bit_unlock_is_negative_byte +static inline bool clear_bit_unlock_is_negative_byte(unsigned int nr, + volatile unsigned long *p) +{ + long old; + unsigned long mask = BIT_MASK(nr); + + p += BIT_WORD(nr); + old = atomic_long_fetch_andnot_release(mask, (atomic_long_t *)p); + return !!(old & BIT(7)); +} +#define clear_bit_unlock_is_negative_byte clear_bit_unlock_is_negative_byte +#endif +#endif /* _ASM_GENERIC_BITOPS_LOCK_H_ */ From patchwork Tue Jun 19 12:53:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 139114 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5171889lji; Tue, 19 Jun 2018 05:54:43 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLk9hx5RW1yFCX8BCvXktmKBgFPLnPTUe+Y2kRUDC3gAGiq99+vVhHIIChz+rzOTBpw1wC9 X-Received: by 2002:a62:dc98:: with SMTP id c24-v6mr18121814pfl.183.1529412883545; Tue, 19 Jun 2018 05:54:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529412883; cv=none; d=google.com; s=arc-20160816; b=QpcCTPHFekBUadbwGvf93fbmm5//iZMj4mRH6XHKcldPwIU3XjzioGQ/OVxMKNULBB TPpWejmcicLUC/loEu0iOPUxM7Fxvyt4EqilLDCkyl86rvjm4Djzoiw0LRWupuc0VCzZ msEtJJrlLv4EMA8If8+7XBH5ZhGufb0FNzDUrCZqKGXz4nZiW7qQGNtpFMg+JN38prlK +ZfF7K15gzcZ1gPMuY9K8c2HoyLXACJ5Eh9SF5hjjdSLSWTUGAfhmURT1RYgvIbccQlC 2va/i2gMMx2+K0ZA1v5VW32GH4V6wFbAV3nPIEjwdA1MfpO62wXaDKCrBUGAoxGRo2pY Iu/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=nDANHoxWslVF4ix7bIp/kIt2E+xkqlL3QMiTa72jHz4=; b=eSA3g0j70OzxteXtI3uJ1JxnweOwgqbz1uahbdgMxS91Dsm8/ZlPh9KFDb1M3JofdO Qq4gg+xTeWpxWYW1tRtYE8LslmMV5IzPt2M8URIQGM2Fps6awVrzD1Kd0PErStVxpk1T f6sTdFnROl1VKJpJQ/Qc0sD9KqLjG+ynG5O21mWnTAg2V6+CE+69jtzoReW6e1hEM6Ow pls5jxpft3VkWEka86hqK89KM4yBSP5wibXfAjDeCGgUOEmo4bszWZGsVyCiHhZTzt/A P3jaOV1LhGSQW0vrdEV0DLgb2KOq2B5jEfPAn6hTPSNlOAP4AzmMgzMSmqzMHUnCDYtc Tspw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e9-v6si14024571pgo.397.2018.06.19.05.54.43; Tue, 19 Jun 2018 05:54:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966345AbeFSMyl (ORCPT + 30 others); Tue, 19 Jun 2018 08:54:41 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:49358 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937860AbeFSMwl (ORCPT ); Tue, 19 Jun 2018 08:52:41 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1C8BD1684; Tue, 19 Jun 2018 05:52:41 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E2F913F7F3; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 112701AE3719; Tue, 19 Jun 2018 13:53:16 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RESEND PATCH v2 8/9] arm64: Replace our atomic/lock bitop implementations with asm-generic Date: Tue, 19 Jun 2018 13:53:13 +0100 Message-Id: <1529412794-17720-9-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1529412794-17720-1-git-send-email-will.deacon@arm.com> References: <1529412794-17720-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The asm-generic/bitops/{atomic,lock}.h implementations are built around the atomic-fetch ops, which we implement efficiently for both LSE and LL/SC systems. Use that instead of our hand-rolled, out-of-line bitops.S. Acked-by: Peter Zijlstra (Intel) Signed-off-by: Will Deacon --- arch/arm64/include/asm/bitops.h | 14 ++------ arch/arm64/lib/Makefile | 2 +- arch/arm64/lib/bitops.S | 76 ----------------------------------------- 3 files changed, 3 insertions(+), 89 deletions(-) delete mode 100644 arch/arm64/lib/bitops.S -- 2.1.4 diff --git a/arch/arm64/include/asm/bitops.h b/arch/arm64/include/asm/bitops.h index 9c19594ce7cb..13501460be6b 100644 --- a/arch/arm64/include/asm/bitops.h +++ b/arch/arm64/include/asm/bitops.h @@ -17,22 +17,11 @@ #define __ASM_BITOPS_H #include -#include #ifndef _LINUX_BITOPS_H #error only can be included directly #endif -/* - * Little endian assembly atomic bitops. - */ -extern void set_bit(int nr, volatile unsigned long *p); -extern void clear_bit(int nr, volatile unsigned long *p); -extern void change_bit(int nr, volatile unsigned long *p); -extern int test_and_set_bit(int nr, volatile unsigned long *p); -extern int test_and_clear_bit(int nr, volatile unsigned long *p); -extern int test_and_change_bit(int nr, volatile unsigned long *p); - #include #include #include @@ -44,8 +33,9 @@ extern int test_and_change_bit(int nr, volatile unsigned long *p); #include #include -#include +#include +#include #include #include diff --git a/arch/arm64/lib/Makefile b/arch/arm64/lib/Makefile index 137710f4dac3..68755fd70dcf 100644 --- a/arch/arm64/lib/Makefile +++ b/arch/arm64/lib/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -lib-y := bitops.o clear_user.o delay.o copy_from_user.o \ +lib-y := clear_user.o delay.o copy_from_user.o \ copy_to_user.o copy_in_user.o copy_page.o \ clear_page.o memchr.o memcpy.o memmove.o memset.o \ memcmp.o strcmp.o strncmp.o strlen.o strnlen.o \ diff --git a/arch/arm64/lib/bitops.S b/arch/arm64/lib/bitops.S deleted file mode 100644 index 43ac736baa5b..000000000000 --- a/arch/arm64/lib/bitops.S +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Based on arch/arm/lib/bitops.h - * - * Copyright (C) 2013 ARM Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -/* - * x0: bits 5:0 bit offset - * bits 31:6 word offset - * x1: address - */ - .macro bitop, name, llsc, lse -ENTRY( \name ) - and w3, w0, #63 // Get bit offset - eor w0, w0, w3 // Clear low bits - mov x2, #1 - add x1, x1, x0, lsr #3 // Get word offset -alt_lse " prfm pstl1strm, [x1]", "nop" - lsl x3, x2, x3 // Create mask - -alt_lse "1: ldxr x2, [x1]", "\lse x3, [x1]" -alt_lse " \llsc x2, x2, x3", "nop" -alt_lse " stxr w0, x2, [x1]", "nop" -alt_lse " cbnz w0, 1b", "nop" - - ret -ENDPROC(\name ) - .endm - - .macro testop, name, llsc, lse -ENTRY( \name ) - and w3, w0, #63 // Get bit offset - eor w0, w0, w3 // Clear low bits - mov x2, #1 - add x1, x1, x0, lsr #3 // Get word offset -alt_lse " prfm pstl1strm, [x1]", "nop" - lsl x4, x2, x3 // Create mask - -alt_lse "1: ldxr x2, [x1]", "\lse x4, x2, [x1]" - lsr x0, x2, x3 -alt_lse " \llsc x2, x2, x4", "nop" -alt_lse " stlxr w5, x2, [x1]", "nop" -alt_lse " cbnz w5, 1b", "nop" -alt_lse " dmb ish", "nop" - - and x0, x0, #1 - ret -ENDPROC(\name ) - .endm - -/* - * Atomic bit operations. - */ - bitop change_bit, eor, steor - bitop clear_bit, bic, stclr - bitop set_bit, orr, stset - - testop test_and_change_bit, eor, ldeoral - testop test_and_clear_bit, bic, ldclral - testop test_and_set_bit, orr, ldsetal From patchwork Tue Jun 19 12:53:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 139116 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5172276lji; Tue, 19 Jun 2018 05:55:07 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLqf/1g8sFoDUr/YyWNv0rcmB2J9zk7YFyPBWhDHGMh/4Rp8C2gfSTaP7xoNUnlOZtrbvsm X-Received: by 2002:a63:770f:: with SMTP id s15-v6mr15204761pgc.30.1529412907579; Tue, 19 Jun 2018 05:55:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529412907; cv=none; d=google.com; s=arc-20160816; b=FERBo9MY7lyINaR1Kkr6jL31eHUlGimuHK456nVAudVOTg+AGGPKsNKzogv8j0mh9e 1q2NMPYHZE6SFm+iyDGnhAydRxZLOxgydhibWvY0TvSg9KtdoLh/oZOls8Cn0/IDlwX+ Fonzo8zmstqZFpIJgNzI3Qun3mWk/j32P9DGmfO7V+WjqxHmrY+cgPBGKZJxLy4Aruy0 sDytqAYM2B/23WqhAWgDRQXNkIk5T1I2uw9ycgWMzox7/g274/ukzTtKXplF7LEnyNKs mkN6buYUsSeltqt+UB6FkWDwHirFDtT2Oun7OVREiU5cq/ZlWbMVJZTS9ZzQLekO7r/D 8OWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Z/XbD58FafxKZE8LGDDZ7F8R80r4uaO2CAfVYW1/FOY=; b=e0qM90dJ37GSow5Jhhumyze4wMKHqPZmfJHSh7hUogWUqlMmtke9g1JB4oQiN98Acq yJV/bYxEE1C+1bskhZj2ZcPMqiTS5VAJOohuhQt/3r4RkjqUSGh/WQCI9mfOv1WVr3Hv Bv7druPt3DDYGMTfqooi7bSG5aKRF0lWroZDtk6jxTqZu+QarrtJQEXczJ4GimN8S4su NwpvMq5+7Ug0N5esXCZBdxdhZZFwiDc7G4lULFkU1T9lsmFNktbcp4c0DP4biQpU8nw6 Szgkk8gTGx74PNM4fPftXB9TwimiXK21t04jJ7U57w7QtiRpz2/9hl2NPyHrR1ww9bN8 YAkw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v32-v6si17088272plb.273.2018.06.19.05.55.07; Tue, 19 Jun 2018 05:55:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966310AbeFSMyk (ORCPT + 30 others); Tue, 19 Jun 2018 08:54:40 -0400 Received: from foss.arm.com ([217.140.101.70]:49362 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937861AbeFSMwl (ORCPT ); Tue, 19 Jun 2018 08:52:41 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 251AF168F; Tue, 19 Jun 2018 05:52:41 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EB5D33F7F4; Tue, 19 Jun 2018 05:52:40 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 216471AE3797; Tue, 19 Jun 2018 13:53:16 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RESEND PATCH v2 9/9] arm64: bitops: Include Date: Tue, 19 Jun 2018 13:53:14 +0100 Message-Id: <1529412794-17720-10-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1529412794-17720-1-git-send-email-will.deacon@arm.com> References: <1529412794-17720-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org asm-generic/bitops/ext2-atomic-setbit.h provides the ext2 atomic bitop definitions, so we don't need to define our own. Acked-by: Peter Zijlstra (Intel) Signed-off-by: Will Deacon --- arch/arm64/include/asm/bitops.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/bitops.h b/arch/arm64/include/asm/bitops.h index 13501460be6b..10d536b1af74 100644 --- a/arch/arm64/include/asm/bitops.h +++ b/arch/arm64/include/asm/bitops.h @@ -38,11 +38,6 @@ #include #include #include - -/* - * Ext2 is defined to use little-endian byte ordering. - */ -#define ext2_set_bit_atomic(lock, nr, p) test_and_set_bit_le(nr, p) -#define ext2_clear_bit_atomic(lock, nr, p) test_and_clear_bit_le(nr, p) +#include #endif /* __ASM_BITOPS_H */