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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id t204-v6sm7857239oig.24.2018.06.18.18.45.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jun 2018 18:45:43 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2018 20:42:11 -0500 Message-Id: <20180619014319.28272-46-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180619014319.28272-1-mdroth@linux.vnet.ibm.com> References: <20180619014319.28272-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c0f::242 Subject: [Qemu-devel] [PATCH 045/113] arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXIT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-stable@nongnu.org, Victor Kamensky Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Victor Kamensky In OE project 4.15 linux kernel boot hang was observed under single cpu aarch64 qemu. Kernel code was in a loop waiting for vtimer arrival, spinning in TC generated blocks, while interrupt was pending unprocessed. This happened because when qemu tried to handle vtimer interrupt target had interrupts disabled, as result flag indicating TCG exit, cpu->icount_decr.u16.high, was cleared but arm_cpu_exec_interrupt function did not call arm_cpu_do_interrupt to process interrupt. Later when target reenabled interrupts, it happened without exit into main loop, so following code that waited for result of interrupt execution run in infinite loop. To solve the problem instructions that operate on CPU sys state (i.e enable/disable interrupt), and marked as DISAS_UPDATE, should be considered as DISAS_EXIT variant, and should be forced to exit back to main loop so qemu will have a chance processing pending CPU state updates, including pending interrupts. This change brings consistency with how DISAS_UPDATE is treated in aarch32 case. CC: Peter Maydell CC: Alex Bennée CC: qemu-stable@nongnu.org Suggested-by: Peter Maydell Signed-off-by: Victor Kamensky Reviewed-by: Richard Henderson Message-id: 1521526368-1996-1-git-send-email-kamensky@cisco.com Signed-off-by: Peter Maydell (cherry picked from commit a75a52d62418dafe462be4fe30485501d1010bb9) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.11.0 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 625ef2dfd2..c38109146f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11384,12 +11384,12 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) case DISAS_UPDATE: gen_a64_set_pc_im(dc->pc); /* fall through */ - case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(); - break; case DISAS_EXIT: tcg_gen_exit_tb(0); break; + case DISAS_JUMP: + tcg_gen_lookup_and_goto_ptr(); + break; case DISAS_NORETURN: case DISAS_SWI: break; From patchwork Tue Jun 19 01:42:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 139070 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4665629lji; Mon, 18 Jun 2018 19:50:44 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIL1FC07ORrCtnga5jc4GNop3r0XIwxMgBZMqhpGfx1MPXtAtePV05nOi5UOKCWlBsBng9U X-Received: by 2002:a0c:d2ee:: with SMTP id x43-v6mr12741129qvh.237.1529376644774; Mon, 18 Jun 2018 19:50:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529376644; cv=none; d=google.com; s=arc-20160816; b=YNZ/v+JbdaVurdvIjgj5TUxJjkqydvuo13aNALiGyHdFg0QzgdAWbPVUUtOvJw2P5P yuv8mXT1sjavreZVDOZKBHKHzA3wY9Vu7NgqXjnUVKbac651O94/+oMNcX+rkf4K7e5O tBJJNEjkcHygaIx3uCJ1rfXJNwTkqAEqgPQ7rkr19UTmQXfPKU9TnnK645nE/FUVMKhw x63HXLTUfXvRdFAtWQytrb/CbTMsDuSNmj9l2D+POOGP/Vv0U1bVHdS2I4jyJdguunLM MPGOT7eqXUJnEYeP1kqWwt08hUw74SH++cHv7OjxVOP/R1H/J8GN8UD97htjKYT5nDAe MU7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=EiedPMKIMDOxSC/Z0Tp6rpZSOKyu6ubrgDOJ4qs5lq8=; b=r42qa9HSe5RlxQsB6i3mo3YoGwLu1VTwsocIfa3ZFU7w3+j/QBS+7M2jopwrDC53MB I/Cmv2PrPYz4447kaVYn/OdENJGySpVQwTOWua829Z5IHuuhO/VD569r1ZAGVqUF2BYs DxyKfghwyon4vg6G1oIcOIxW0uA7uNPK/UfoDeBTYOIt3mbK/ctXTPlp7unSnkNI9q9z 3UvFV/LWQH1atoSx7IoTFgN+3g4EOnH4TkXLD4JNGIY594s5sjOMI35ZiUCUOeNq+IuP F2mLNoF2vGy//zzbggldmyFFg4y8TikTIfDQavq/I3Qyp2kSp8ZayJ61gFNzFZDT/7lH IgwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=ITe7V0k9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id o65-v6sm6629915oia.35.2018.06.18.18.45.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jun 2018 18:45:53 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2018 20:42:16 -0500 Message-Id: <20180619014319.28272-51-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180619014319.28272-1-mdroth@linux.vnet.ibm.com> References: <20180619014319.28272-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c0f::242 Subject: [Qemu-devel] [PATCH 050/113] tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Failure to do so results in the tcg optimizer sign-extending any constant fold from 32-bits. This turns out to be visible in the RISC-V testsuite using a host that emits these opcodes (e.g. any non-x86_64). Reported-by: Michael Clark Reviewed-by: Emilio G. Cota Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson (cherry picked from commit f2f1dde75160cac6ede330f3db50dc817d01a2d6) Signed-off-by: Michael Roth --- tcg/tcg-opc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.11.0 diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 956fb1e9f3..bb28b863ce 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -182,8 +182,8 @@ DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64)) DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64)) DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64)) DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64)) -DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64)) -DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64)) +DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64)) +DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64)) #define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2) #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) From patchwork Tue Jun 19 01:42:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 139069 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4663602lji; Mon, 18 Jun 2018 19:47:28 -0700 (PDT) X-Google-Smtp-Source: ADUXVKITdahIYm6ZYZQ3vvTSaHIrk8N8KMp4ZE1CSy6dWLKM1q/Jg5iFrwIzpEhZY3BtjNryp/UX X-Received: by 2002:a37:350a:: with SMTP id c10-v6mr12115417qka.388.1529376448536; Mon, 18 Jun 2018 19:47:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529376448; cv=none; d=google.com; s=arc-20160816; b=Z9QlIp0AMoXLcrdpW6helhhmky9vQ5CDPnpiQj1iLib21MM26dQNiHDDCMzsvCs/h2 7eGL5XG2sx/utobt8pK7fZ9PDldfY+MB0CMnWBTllEV0IFptjoB8Hfp/rw7cxwiSitSx DCFpJ2/phlplT7EOj0gT2ng+g1h9Y8tYZrQgYPKhP+lKYY7ITvuWALx//3z4YAB55aDW 2ulueMsIGYKta3OWa5He2zAEkzaiYCgerC2czhKl1qe/imN2vtcSa+3O3ObDOeWZVh+/ xnfNdYDZ487Zo95pW16vnuhxZT44Iq4YeH129ZZJKIs7mPVM9gaUtZCg/rGXxHn1clEH FnMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=rOuwpNiiE+JdCAHr4P1l3+or/iloZktTvGW4y9eDwtg=; b=qMSZer7b/izYhi1y12hYva/uM2n/uA6K1Fwj1/vmJOUgJXikIrQ7gTlvmIa7XIR1J3 /viKlJ/LiyJVUQc5hiM0fk63Mcs/DaBpgJTTMSVYk87uC8KDceKmM386GjkFygftV4g3 8s1PxRoNqHOYuacxbb+a28XITDxXLjYZ7UvllhiKLAJcrwirPKzbWstII1iOyStaxR7B MSisnYjhJgMhoEWzObWukrsL7NxLIWbTXlSQRLhhQRw5CorLmtjNwp6pRvkpx+u96bSB +mo3tepdFy6BHpId6nSS7L+6siR7glEGkcJkZqvglbFOCIbdGtEnR04dznAJJS9GA+9a GmOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=dthUBTIP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id t77-v6sm7294818oie.3.2018.06.18.18.46.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jun 2018 18:46:03 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2018 20:42:20 -0500 Message-Id: <20180619014319.28272-55-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180619014319.28272-1-mdroth@linux.vnet.ibm.com> References: <20180619014319.28272-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c0f::231 Subject: [Qemu-devel] [PATCH 054/113] cpus.c: ensure running CPU recalculates icount deadlines on timer expiry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell When we run in TCG icount mode, we calculate the number of instructions to execute using tcg_get_icount_limit(), which ensures that we stop execution at the next timer deadline. However there is a bug where currently we do not recalculate that limit if the guest reprograms a timer so that the next deadline moves closer, and so we will continue execution until the original limit and fire the timer later than we should. Fix this bug in qemu_timer_notify_cb(): if we are currently running a VCPU in icount mode, we simply need to kick it out of the main loop and back to tcg_cpu_exec(), where it will recalculate the icount limit. If we are not currently running a VCPU, then we retain the existing logic for waking up a halted CPU. Cc: qemu-stable@nongnu.org Fixes: https://bugs.launchpad.net/qemu/+bug/1754038 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Message-id: 20180406123838.21249-1-peter.maydell@linaro.org (cherry picked from commit c52e7132d7c885841500f5277f7305f62767fe1d) Signed-off-by: Michael Roth --- cpus.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) -- 2.11.0 diff --git a/cpus.c b/cpus.c index 114c29b6a0..96bb688d7b 100644 --- a/cpus.c +++ b/cpus.c @@ -843,11 +843,19 @@ void qemu_timer_notify_cb(void *opaque, QEMUClockType type) return; } - if (!qemu_in_vcpu_thread() && first_cpu) { + if (qemu_in_vcpu_thread()) { + /* A CPU is currently running; kick it back out to the + * tcg_cpu_exec() loop so it will recalculate its + * icount deadline immediately. + */ + qemu_cpu_kick(current_cpu); + } else if (first_cpu) { /* qemu_cpu_kick is not enough to kick a halted CPU out of * qemu_tcg_wait_io_event. async_run_on_cpu, instead, * causes cpu_thread_is_idle to return false. This way, * handle_icount_deadline can run. + * If we have no CPUs at all for some reason, we don't + * need to do anything. */ async_run_on_cpu(first_cpu, do_nothing, RUN_ON_CPU_NULL); } From patchwork Tue Jun 19 01:42:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 139071 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4667167lji; Mon, 18 Jun 2018 19:53:05 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIajX/VSjG0YNPX2LocMN919mlW3rtuX8cSm+QJ6MXrR1BR7j4pLCULyhOjOra81vdtX0ab X-Received: by 2002:a0c:b98a:: with SMTP id v10-v6mr12873192qvf.175.1529376785501; Mon, 18 Jun 2018 19:53:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529376785; cv=none; d=google.com; s=arc-20160816; b=zEo6laGvkWWQqDHyXChjk1jdYkw12CWYtKKElzj1Bir+CQfILCKwspmfXwQbIPslib q1GJAW4aPxCZUAl57IcEHZPNl+CsxyZpG5y3MhakyT+5Gv2CbZO/yh8vdnXSd9XvOq8h Ifdh0bfaJ56ckL/j1Gdufz7rlVuAKaXMfG5tuFPjQQGT6dArnPgus59eDiz4OPa3HihV MJGlHah2eDfJ4MY2eFL12N4C3Rz7CVxSp6Ofa1iCzIAq8VsZEI2bOdCE6bWN3lO13JFI D6i8E8TYU4CVbt5sQMUESL+Toihbfiw0fB19hMC0C33GELYL1jqdlCJ1GTWdXZOYJW0O D9Hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ezUafyHTkoYy5utYrpDUYrzLfAPSG5t+PRP0S/F5e6k=; b=IqtwN4qfN516kdR/QTXRaJ7oZeS0wpeLszrwc9bHG0XFRblfi6Y4gQijAPw/H6zgGa caSXlgzDOy9bTVY/Z5J0Z4br3rkWmCqdHuaFDuGklekVqLtJEG5hIQs9ZL7FYmjZlPyr +4j3xgWOj/TJ+eXZokTolyS9LE7JyNVIR9Qn4/RoVnbvRuy/Rq32zTTw7ttKPHj7+ZAL /0eJD12/DiQhlOLc6pwT55BCwla7by1shnbh3ucWzQOt39JXBt36tEN+Xdz8ZxDYvAiC f+HfNdocsy6XN936G6zXtDQdOWuhhENq5oJrgymzEgcJiP2VQlEMrZdjuTcu0R9OQAq3 oQRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=C0tu49ft; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4003:c06::22e Subject: [Qemu-devel] [PATCH 057/113] tcg: Introduce tcg_set_insn_start_param X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The parameters for tcg_gen_insn_start are target_ulong, which may be split into two TCGArg parameters for storage in the opcode on 32-bit hosts. Fixes the ARM target and its direct use of tcg_set_insn_param, which would set the wrong argument in the 64-on-32 case. Cc: qemu-stable@nongnu.org Reported-by: alarson@ddci.com Signed-off-by: Richard Henderson Message-id: 20180410003558.2470-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell (cherry picked from commit 9743cd5736263e90d312b2c33bd739ffe1eae70d) Conflicts: target/arm/translate.h tcg/tcg.h * rework to avoid functional dependency on 15fa08f Signed-off-by: Michael Roth --- target/arm/translate.h | 2 +- tcg/tcg.h | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) -- 2.11.0 diff --git a/target/arm/translate.h b/target/arm/translate.h index 410ba79c0d..0c6a24d287 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -118,7 +118,7 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) /* We check and clear insn_start_idx to catch multiple updates. */ assert(s->insn_start_idx != 0); - tcg_set_insn_param(s->insn_start_idx, 2, syn); + tcg_set_insn_start_param(s->insn_start_idx, 2, syn); s->insn_start_idx = 0; } diff --git a/tcg/tcg.h b/tcg/tcg.h index cb7b329876..d88d3520ac 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -783,6 +783,16 @@ static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) tcg_ctx->gen_op_buf[op_idx].args[arg] = v; } +static inline void tcg_set_insn_start_param(int op_idx, int arg, target_ulong v) +{ +#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS + tcg_set_insn_param(op_idx, arg, v); +#else + tcg_set_insn_param(op_idx, arg * 2, v); + tcg_set_insn_param(op_idx, arg * 2 + 1, v >> 32); +#endif +} + /* The number of opcodes emitted so far. */ static inline int tcg_op_buf_count(void) { From patchwork Tue Jun 19 01:42:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 139072 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4670813lji; Mon, 18 Jun 2018 19:58:20 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJummFDdQJSdVVntUZ9F5iu7SDOe5TK12vqwqqHaA1j/N9PK/73Sqhrda2T2howszppwEcd X-Received: by 2002:aed:3534:: with SMTP id a49-v6mr13408673qte.47.1529377100433; Mon, 18 Jun 2018 19:58:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529377100; cv=none; d=google.com; s=arc-20160816; b=k1+51G7NMbeF1161n4SgeUDTFmNZMOeb8rP5eYM2w6KEfM4uFnJNiA43VeXnRQ1qHp PbdnUyO/zuYfv9R7lwqjymQU+8BlsP6erJHSOHNplzb+wF/HYcz20IHDUecOeLX3xIaj vMBTbpNFXoBTJZn19tbyMloHpESXb3dsNQ9T//UpHMgL22jWOaErN4M0mmFx7qq25F0+ JJJtNAoRG1/jnBU/mQNVWWCcz4ASPIVSjI8nxSADVp4c2QBAfLhwmX8lnvg0aLV7c/zr 18j51doXTDAKZuwG0ZMhVKMEtv/ECdjNgZSdtNv/8uzSzuZI/mW2S3dwmZ/j782d2W55 yX5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=upoUpTUx54PoqmTgNon2saxWoWBtl1z80fkO6l8JrNA=; b=tugdPZD08+o4HBG+oeDPRthUBN3AMlbTayCcpJIyqNnAljT3Qtkn9PLaWa/7u1dy3R Sk4OI1J62TSCo1PXspRoS31D3iSC88O+R9lJBy00UhJR5tZTYJ0MbxfoE0zR/UCOPshI p55i1bBSASAVg/exzwYehWutU4/XYPJ7JitFh85fSOEenol3r1d6kFolAkhFvgNordIR N8iK3CNdgO5ERJYVZZ7SilwL29vO3lMURc+Fm2PvfK4VhR39U3tVCIBf6O8O5NuYKSQp l+biyoQI0eLZNsYrYY7wVQW9XPhIZ6r8sKWsCvIq5HwskwhYWGixRrAFFZI6eaXKmxvU 83+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=MoKqJaTg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id s22-v6sm10290687ote.14.2018.06.18.18.46.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jun 2018 18:46:11 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2018 20:42:24 -0500 Message-Id: <20180619014319.28272-59-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180619014319.28272-1-mdroth@linux.vnet.ibm.com> References: <20180619014319.28272-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c0f::22c Subject: [Qemu-devel] [PATCH 058/113] hw/char/cmsdk-apb-uart.c: Correctly clear INTSTATUS bits on writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell The CMSDK APB UART INTSTATUS register bits are all write-one-to-clear. We were getting this correct for the TXO and RXO bits (which need special casing because their state lives in the STATE register), but had forgotten to handle the normal bits for RX and TX which we do store in our s->intstatus field. Perform the W1C operation on the bits in s->intstatus too. Fixes: https://bugs.launchpad.net/qemu/+bug/1760262 Cc: qemu-stable@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell Message-id: 20180410134203.17552-1-peter.maydell@linaro.org (cherry picked from commit 6670b494fdb23f74ecd9be3d952c007f64e268f1) Signed-off-by: Michael Roth --- hw/char/cmsdk-apb-uart.c | 1 + 1 file changed, 1 insertion(+) -- 2.11.0 diff --git a/hw/char/cmsdk-apb-uart.c b/hw/char/cmsdk-apb-uart.c index 1ad1e14295..9c0929d8a2 100644 --- a/hw/char/cmsdk-apb-uart.c +++ b/hw/char/cmsdk-apb-uart.c @@ -274,6 +274,7 @@ static void uart_write(void *opaque, hwaddr offset, uint64_t value, * is then reflected into the intstatus value by the update function). */ s->state &= ~(value & (R_INTSTATUS_TXO_MASK | R_INTSTATUS_RXO_MASK)); + s->intstatus &= ~value; cmsdk_apb_uart_update(s); break; case A_BAUDDIV: From patchwork Tue Jun 19 01:42:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 139073 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4678430lji; Mon, 18 Jun 2018 20:08:12 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJW3EVPLgea3RE/DgyAn8mXzzRYrhYCV4uHp0s6trd/rXQwULRMLUXuDq+vBHpKZKss38zj X-Received: by 2002:a37:f713:: with SMTP id q19-v6mr12414084qkj.278.1529377692397; Mon, 18 Jun 2018 20:08:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529377692; cv=none; d=google.com; s=arc-20160816; b=QPsxCYDs7jj4C6vnC6fIOwFkrRLtfFd7yvSeZ9j4yG/XRqFqu1JnqdNoSZKrvKFcVK U3jNmYDgE7DpQ85lkG8h+xOvgoA/5/qvTg4zwqbz7Tj1+a3V+OtdC+JE5+wd6xGUGoKy VXgejdruRt7vH3nYCjYS5q7ujha1TqjVuIQ2AWKVvHDjAFncVbXI3xW6spczH63tovAS kt72AMgS8Syy0ErfTjDxphAkGjMPpLA5DYeBZZ29hT8Da5aqwo8ZmIwlEI2oBza6FU8F IvV1CcNOtygaXymv0KEOzEXdaza7JkljLgqIFu31I2e9MMohob3bqXKif3ZfneARy0Wu RAQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=8IvJppQ7K4e0ec4Tu1tPfeuKWzXeZ7Q12FRDR3t1nJw=; b=X1Nzxnat3JC068Jh1R5Z2G8JyCMtZpc3W9nSKpbHxY05jieHNTVkzj/a/cBM9kNedM iUQ+yU7D3U6I10ZX3j60OhLQ4JgSBHP7gKeWXERAbNOVQP0DN0D/PYKY0L/TQGTWsI7P ZrjyaoxfNCAWLbbXwuUT8lwAxFSxCXDd8UJnCA4OUjqxAxMosVlA8/qhnoT2wnlexPeW xPyJ2+8m7pdb1VvoyqIfaRmv50pv6CRR5bCuguhTqyad3gs0eZ77zlfzYZpY8aNoY5F1 V9bXaQyE6XWyMjIKjHMIJ07Ytif54ya4CizpmPqGe3pfHRZFf29RekWLXC/6gdgJBi3b sHjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=L4QRiqXB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a2-v6si9642078qka.10.2018.06.18.20.08.12 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 18 Jun 2018 20:08:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=L4QRiqXB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Received: from localhost ([::1]:38906 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fV707-00005u-P6 for patch@linaro.org; Mon, 18 Jun 2018 23:08:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46708) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fV5j6-0002fP-R2 for qemu-devel@nongnu.org; Mon, 18 Jun 2018 21:46:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fV5j5-0000Pa-Oi for qemu-devel@nongnu.org; Mon, 18 Jun 2018 21:46:32 -0400 Received: from mail-oi0-x22f.google.com ([2607:f8b0:4003:c06::22f]:37063) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fV5j5-0000PL-JQ; Mon, 18 Jun 2018 21:46:31 -0400 Received: by mail-oi0-x22f.google.com with SMTP id l22-v6so16718271oib.4; Mon, 18 Jun 2018 18:46:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=8IvJppQ7K4e0ec4Tu1tPfeuKWzXeZ7Q12FRDR3t1nJw=; b=L4QRiqXB+FpaCw0IcmN5CSFcAO4EF4kC13XkfJxi6TRH/okj6AMZcc4R127dKTWJmR vPV8xkSaWeUedSfxMVoi457VBBy4DK/6A40sZb9E6G1GYeoeXVIzVg0hpcC0Ek4E/StF q2Rg1b6cndV3AcNTftGozLYPRWxKwBqD4d5GfQtcuzUB/o4Zqa6FrMQMOso56R9s2lf5 gZ0C0GxaGtZtt5EsEFoFsdefKjyBAJ+J8WLZxSeChzdbKXxzP1p3qbwI4byC/Ub3KK6D q7krkfjLGio7kMXV5nwMpOFDPNp1G1EDUtx2fZC9KhjJChQM9DS2Y71pIekiDVQarvWf LVDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=8IvJppQ7K4e0ec4Tu1tPfeuKWzXeZ7Q12FRDR3t1nJw=; b=QV/VPtnaIpZLz/MB6KVYEE1knsVNxStpP4kJ7ueCVI63BZyP/cJjahvRhu/uxjI1YS g8bmnXcq12qHstkC4GkqXGzMRdB3eep+MmYGw1D1vHsUzde6GZk3WNwlC+o4Zfle3l6D 0fXaHe7TJtlwgiHVKtNZwhACWeq8myqsgtl/vAxrR44zsa0udrEXMkE1Unhwun95alHR WcLgh+cb+/UjHfAAFC501xYCICuwo7YFR43jqdBl3mXeCjlnvSIs7gO9aSF47E9zy5Je CeGUjkUrajHW44QodZKc+9rD0gDHtF4Qd4BMMAZ1mU3BkHo/oD66oFtz2PFawhcozzDi v+ew== X-Gm-Message-State: APt69E0auGY83e65oEuNaxSgftZOW+4dDtlziWbKTpEGWOZxqhRwHo2e RrmZNApn9xS9u7lSSYOVZSsj8U67sLU= X-Received: by 2002:aca:501:: with SMTP id 1-v6mr8584115oif.217.1529372790390; Mon, 18 Jun 2018 18:46:30 -0700 (PDT) Received: from localhost ([2600:1700:70:e488:b0ee:9bda:ee6f:91be]) by smtp.gmail.com with ESMTPSA id z44-v6sm9636236otc.46.2018.06.18.18.46.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jun 2018 18:46:29 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2018 20:42:31 -0500 Message-Id: <20180619014319.28272-66-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180619014319.28272-1-mdroth@linux.vnet.ibm.com> References: <20180619014319.28272-1-mdroth@linux.vnet.ibm.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::22f Subject: [Qemu-devel] [PATCH 065/113] target/arm: Implement v8M VLLDM and VLSTM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell For v8M the instructions VLLDM and VLSTM support lazy saving and restoring of the secure floating-point registers. Even if the floating point extension is not implemented, these instructions must act as NOPs in Secure state, so they can be used as part of the secure-to-nonsecure call sequence. Fixes: https://bugs.launchpad.net/qemu/+bug/1768295 Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180503105730.5958-1-peter.maydell@linaro.org (cherry picked from commit b1e5336a9899016c53d59eba53ebf6abcc21995c) Signed-off-by: Michael Roth --- target/arm/translate.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) -- 2.11.0 diff --git a/target/arm/translate.c b/target/arm/translate.c index f120932f44..a8e8168a06 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10511,8 +10511,23 @@ static int disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Coprocessor. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { /* We don't currently implement M profile FP support, - * so this entire space should give a NOCP fault. + * so this entire space should give a NOCP fault, with + * the exception of the v8M VLLDM and VLSTM insns, which + * must be NOPs in Secure state and UNDEF in Nonsecure state. */ + if (arm_dc_feature(s, ARM_FEATURE_V8) && + (insn & 0xffa00f00) == 0xec200a00) { + /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx + * - VLLDM, VLSTM + * We choose to UNDEF if the RAZ bits are non-zero. + */ + if (!s->v8m_secure || (insn & 0x0040f0ff)) { + goto illegal_op; + } + /* Just NOP since FP support is not implemented */ + break; + } + /* All other insns: NOCP */ gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(), default_exception_el(s)); break;