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Thu, 22 Apr 2021 20:30:55 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Apr 2021 13:30:54 -0700 Received: from skomatineni-linux.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Apr 2021 20:30:54 +0000 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH 2/4] cpuidle: menu: add idle_time to cpuidle_state Date: Thu, 22 Apr 2021 13:30:46 -0700 Message-ID: <1619123448-10138-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1619123448-10138-1-git-send-email-skomatineni@nvidia.com> References: <1619123448-10138-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 126974cf-5a15-410d-0358-08d905cd8811 X-MS-TrafficTypeDiagnostic: MWHPR12MB1951: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:826; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2021 20:30:55.7137 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 126974cf-5a15-410d-0358-08d905cd8811 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1951 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Some platforms use separate CPU firmware running in background to handle state transitions which may need runtime idle time of the corresponding target state from the kernel. This patch adds idle_time to cpuidle state to expose to cpuidle driver the idle time that the governor menu predicts based on next events and states target residency for selecting proper idle state. CPU idle driver passes this runtime state idle time to TF-A. Signed-off-by: Sowjanya Komatineni --- drivers/cpuidle/governors/menu.c | 7 ++++++- include/linux/cpuidle.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/cpuidle/governors/menu.c b/drivers/cpuidle/governors/menu.c index c3aa8d6..0da5bc5 100644 --- a/drivers/cpuidle/governors/menu.c +++ b/drivers/cpuidle/governors/menu.c @@ -382,8 +382,10 @@ static int menu_select(struct cpuidle_driver *drv, struct cpuidle_device *dev, * stuck in the shallow one for too long. */ if (drv->states[idx].target_residency_ns < TICK_NSEC && - s->target_residency_ns <= delta_tick) + s->target_residency_ns <= delta_tick) { + drv->states[idx].idle_time = delta_tick / NSEC_PER_USEC; idx = i; + } return idx; } @@ -393,6 +395,7 @@ static int menu_select(struct cpuidle_driver *drv, struct cpuidle_device *dev, idx = i; } + drv->states[idx].idle_time = predicted_ns / NSEC_PER_USEC; if (idx == -1) idx = 0; /* No states enabled. Must use 0. */ @@ -419,6 +422,8 @@ static int menu_select(struct cpuidle_driver *drv, struct cpuidle_device *dev, if (drv->states[i].target_residency_ns <= delta_tick) break; } + + drv->states[idx].idle_time = delta_tick / NSEC_PER_USEC; } } diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h index fce4762..12db2e9 100644 --- a/include/linux/cpuidle.h +++ b/include/linux/cpuidle.h @@ -55,6 +55,7 @@ struct cpuidle_state { unsigned int exit_latency; /* in US */ int power_usage; /* in mW */ unsigned int target_residency; /* in US */ + unsigned int idle_time; /* in US */ int (*enter) (struct cpuidle_device *dev, struct cpuidle_driver *drv, From patchwork Thu Apr 22 20:30:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 426055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40A9FC43617 for ; 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vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.32 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.32; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.32) by BN8NAM11FT011.mail.protection.outlook.com (10.13.176.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4065.21 via Frontend Transport; Thu, 22 Apr 2021 20:30:57 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Apr 2021 13:30:56 -0700 Received: from skomatineni-linux.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Apr 2021 20:30:56 +0000 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH 4/4] arm64: dts: tegra194: Add CPU idle states Date: Thu, 22 Apr 2021 13:30:48 -0700 Message-ID: <1619123448-10138-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1619123448-10138-1-git-send-email-skomatineni@nvidia.com> References: <1619123448-10138-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bb6b35f2-6993-41f6-dad8-08d905cd891e X-MS-TrafficTypeDiagnostic: DM6PR12MB2940: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:262; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2021 20:30:57.4832 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb6b35f2-6993-41f6-dad8-08d905cd891e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2940 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This patch adds CPU core and cluster idle states to Tegra194 device tree Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 9449156..c3b478e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2161,6 +2161,7 @@ device_type = "cpu"; reg = <0x000>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2175,6 +2176,7 @@ device_type = "cpu"; reg = <0x001>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2189,6 +2191,7 @@ device_type = "cpu"; reg = <0x100>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2203,6 +2206,7 @@ device_type = "cpu"; reg = <0x101>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2217,6 +2221,7 @@ device_type = "cpu"; reg = <0x200>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2231,6 +2236,7 @@ device_type = "cpu"; reg = <0x201>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2245,6 +2251,7 @@ device_type = "cpu"; reg = <0x300>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2259,6 +2266,7 @@ device_type = "cpu"; reg = <0x301>; enable-method = "psci"; + cpu-idle-states = <&C6>; i-cache-size = <131072>; i-cache-line-size = <64>; i-cache-sets = <512>; @@ -2343,6 +2351,17 @@ cache-line-size = <64>; cache-sets = <4096>; }; + + idle-states { + entry-method = "arm,psci"; + C6: c6 { + compatible = "arm,idle-state"; + wakeup-latency-us = <2000>; + min-residency-us = <30000>; + arm,psci-suspend-param = <0x6>; + status = "okay"; + }; + }; }; psci {