From patchwork Thu Apr 22 09:42:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasanna Vengateshan X-Patchwork-Id: 425944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B649C433ED for ; Thu, 22 Apr 2021 09:43:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 16AEF600EF for ; Thu, 22 Apr 2021 09:43:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235754AbhDVJnu (ORCPT ); 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d="scan'208";a="124117420" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Apr 2021 02:43:14 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 22 Apr 2021 02:43:13 -0700 Received: from CHE-LT-I21427LX.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 22 Apr 2021 02:43:07 -0700 From: Prasanna Vengateshan To: , , , CC: , , , , , , , , Subject: [PATCH v2 net-next 1/9] dt-bindings: net: dsa: dt bindings for microchip lan937x Date: Thu, 22 Apr 2021 15:12:49 +0530 Message-ID: <20210422094257.1641396-2-prasanna.vengateshan@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210422094257.1641396-1-prasanna.vengateshan@microchip.com> References: <20210422094257.1641396-1-prasanna.vengateshan@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Documentation in .yaml format and updates to the MAINTAINERS Also 'make dt_binding_check' is passed Signed-off-by: Prasanna Vengateshan --- .../bindings/net/dsa/microchip,lan937x.yaml | 142 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml new file mode 100644 index 000000000000..22128a52d699 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/microchip,lan937x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LAN937x Ethernet Switch Series Tree Bindings + +maintainers: + - UNGLinuxDriver@microchip.com + +allOf: + - $ref: dsa.yaml# + +properties: + compatible: + enum: + - microchip,lan9370 + - microchip,lan9371 + - microchip,lan9372 + - microchip,lan9373 + - microchip,lan9374 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 50000000 + + reset-gpios: + description: Optional gpio specifier for a reset line + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + //Ethernet switch connected via spi to the host + ethernet { + #address-cells = <1>; + #size-cells = <0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + + lan9374: switch@0 { + compatible = "microchip,lan9374"; + reg = <0>; + + spi-max-frequency = <44000000>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + label = "lan1"; + phy-handle = <&t1phy0>; + }; + port@1 { + reg = <1>; + label = "lan2"; + phy-handle = <&t1phy1>; + }; + port@2 { + reg = <2>; + label = "lan4"; + phy-handle = <&t1phy2>; + }; + port@3 { + reg = <3>; + label = "lan6"; + phy-handle = <&t1phy3>; + }; + port@4 { + reg = <4>; + phy-mode = "rgmii"; + ethernet = <ðernet>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + port@5 { + reg = <5>; + label = "lan7"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + port@6 { + reg = <6>; + label = "lan5"; + phy-handle = <&t1phy4>; + }; + port@7 { + reg = <7>; + label = "lan3"; + phy-handle = <&t1phy5>; + }; + }; + + mdio { + compatible = "microchip,lan937x-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + t1phy0: ethernet-phy@0{ + reg = <0x0>; + }; + t1phy1: ethernet-phy@1{ + reg = <0x1>; + }; + t1phy2: ethernet-phy@2{ + reg = <0x2>; + }; + t1phy3: ethernet-phy@3{ + reg = <0x3>; + }; + t1phy4: ethernet-phy@6{ + reg = <0x6>; + }; + t1phy5: ethernet-phy@7{ + reg = <0x7>; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index c3c8fa572580..a0fdfef8802a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11752,6 +11752,7 @@ M: UNGLinuxDriver@microchip.com L: netdev@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +F: Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml F: drivers/net/dsa/microchip/* F: include/linux/platform_data/microchip-ksz.h F: net/dsa/tag_ksz.c From patchwork Thu Apr 22 09:42:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasanna Vengateshan X-Patchwork-Id: 425943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18E8CC433B4 for ; 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IronPort-SDR: yH7+rjBX4k8Ro3fWb1riu30zuJ8VMsVaKHvoJG6MAJBAt6UdatJaN57BHFRT8ihXm803pgU2Tf e7an389QzQMO/OmffWrZD6KBriq4+Ig+KwXs3/A13OtRJRyiQYYJIvkR1HzVyrJQtDFkN4DdBw y28f4oDvqGrYigDI8XfHZ0MPY6FkJw73qfACiRm3YIWfLiOFLIKpi9SY95BDZ2t4AwqdpJ5SCS YAiw5ZHLwJmPl9Vy/Gdl7nPyk1r/ek9CXUDPTEbMCyhIa9w0fLUZnxxiBQU9Gmm23CoqeWDyyo j/8= X-IronPort-AV: E=Sophos;i="5.82,242,1613458800"; d="scan'208";a="111784867" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Apr 2021 02:43:27 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 22 Apr 2021 02:43:27 -0700 Received: from CHE-LT-I21427LX.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 22 Apr 2021 02:43:20 -0700 From: Prasanna Vengateshan To: , , , CC: , , , , , , , , Subject: [PATCH v2 net-next 3/9] net: dsa: tag_ksz: add tag handling for Microchip LAN937x Date: Thu, 22 Apr 2021 15:12:51 +0530 Message-ID: <20210422094257.1641396-4-prasanna.vengateshan@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210422094257.1641396-1-prasanna.vengateshan@microchip.com> References: <20210422094257.1641396-1-prasanna.vengateshan@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Microchip LAN937X switches have a tagging protocol which is very similar to KSZ tagging. So that the implementation is added to tag_ksz.c and reused common APIs Signed-off-by: Prasanna Vengateshan --- include/net/dsa.h | 2 ++ net/dsa/Kconfig | 4 ++-- net/dsa/tag_ksz.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+), 2 deletions(-) diff --git a/include/net/dsa.h b/include/net/dsa.h index 507082959aa4..98c1ab6dc4dc 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -50,6 +50,7 @@ struct phylink_link_state; #define DSA_TAG_PROTO_OCELOT_8021Q_VALUE 20 #define DSA_TAG_PROTO_SEVILLE_VALUE 21 #define DSA_TAG_PROTO_BRCM_LEGACY_VALUE 22 +#define DSA_TAG_PROTO_LAN937X_VALUE 23 enum dsa_tag_protocol { DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE, @@ -75,6 +76,7 @@ enum dsa_tag_protocol { DSA_TAG_PROTO_XRS700X = DSA_TAG_PROTO_XRS700X_VALUE, DSA_TAG_PROTO_OCELOT_8021Q = DSA_TAG_PROTO_OCELOT_8021Q_VALUE, DSA_TAG_PROTO_SEVILLE = DSA_TAG_PROTO_SEVILLE_VALUE, + DSA_TAG_PROTO_LAN937X = DSA_TAG_PROTO_LAN937X_VALUE, }; struct packet_type; diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig index cbc2bd643ab2..888eb79a85f2 100644 --- a/net/dsa/Kconfig +++ b/net/dsa/Kconfig @@ -97,10 +97,10 @@ config NET_DSA_TAG_MTK Mediatek switches. config NET_DSA_TAG_KSZ - tristate "Tag driver for Microchip 8795/9477/9893 families of switches" + tristate "Tag driver for Microchip 8795/937x/9477/9893 families of switches" help Say Y if you want to enable support for tagging frames for the - Microchip 8795/9477/9893 families of switches. + Microchip 8795/937x/9477/9893 families of switches. config NET_DSA_TAG_RTL4_A tristate "Tag driver for Realtek 4 byte protocol A tags" diff --git a/net/dsa/tag_ksz.c b/net/dsa/tag_ksz.c index 4820dbcedfa2..a67f21bdab8f 100644 --- a/net/dsa/tag_ksz.c +++ b/net/dsa/tag_ksz.c @@ -190,10 +190,68 @@ static const struct dsa_device_ops ksz9893_netdev_ops = { DSA_TAG_DRIVER(ksz9893_netdev_ops); MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_KSZ9893); +/* For xmit, 2 bytes are added before FCS. + * --------------------------------------------------------------------------- + * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|tag0(1byte)|tag1(1byte)|FCS(4bytes) + * --------------------------------------------------------------------------- + * tag0 : represents tag override, lookup and valid + * tag1 : each bit represents port (eg, 0x01=port1, 0x02=port2, 0x80=port8) + * + * For rcv, 1 byte is added before FCS. + * --------------------------------------------------------------------------- + * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|tag0(1byte)|FCS(4bytes) + * --------------------------------------------------------------------------- + * tag0 : zero-based value represents port + * (eg, 0x00=port1, 0x02=port3, 0x07=port8) + */ +#define LAN937X_INGRESS_TAG_LEN 2 + +#define LAN937X_TAIL_TAG_OVERRIDE BIT(11) +#define LAN937X_TAIL_TAG_LOOKUP BIT(12) +#define LAN937X_TAIL_TAG_VALID BIT(13) +#define LAN937X_TAIL_TAG_PORT_MASK 7 + +static struct sk_buff *lan937x_xmit(struct sk_buff *skb, + struct net_device *dev) +{ + struct dsa_port *dp = dsa_slave_to_port(dev); + __be16 *tag; + u8 *addr; + u16 val; + + tag = skb_put(skb, LAN937X_INGRESS_TAG_LEN); + addr = skb_mac_header(skb); + + val = BIT(dp->index); + + if (is_link_local_ether_addr(addr)) + val |= LAN937X_TAIL_TAG_OVERRIDE; + + /* Tail tag valid bit - This bit should always be set by the CPU*/ + val |= LAN937X_TAIL_TAG_VALID; + + *tag = cpu_to_be16(val); + + return skb; +} + +static const struct dsa_device_ops lan937x_netdev_ops = { + .name = "lan937x", + .proto = DSA_TAG_PROTO_LAN937X, + .xmit = lan937x_xmit, + .rcv = ksz9477_rcv, + .overhead = LAN937X_INGRESS_TAG_LEN, + .tail_tag = true, +}; + +DSA_TAG_DRIVER(lan937x_netdev_ops); +MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_LAN937X); + static struct dsa_tag_driver *dsa_tag_driver_array[] = { &DSA_TAG_DRIVER_NAME(ksz8795_netdev_ops), &DSA_TAG_DRIVER_NAME(ksz9477_netdev_ops), &DSA_TAG_DRIVER_NAME(ksz9893_netdev_ops), + &DSA_TAG_DRIVER_NAME(lan937x_netdev_ops), }; module_dsa_tag_drivers(dsa_tag_driver_array); From patchwork Thu Apr 22 09:42:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasanna Vengateshan X-Patchwork-Id: 425942 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB642C433ED for ; Thu, 22 Apr 2021 09:43:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4447261459 for ; Thu, 22 Apr 2021 09:43:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235865AbhDVJo3 (ORCPT ); Thu, 22 Apr 2021 05:44:29 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:52771 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235855AbhDVJoX (ORCPT ); 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d="scan'208";a="114490573" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Apr 2021 02:43:48 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 22 Apr 2021 02:43:47 -0700 Received: from CHE-LT-I21427LX.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 22 Apr 2021 02:43:41 -0700 From: Prasanna Vengateshan To: , , , CC: , , , , , , , , Subject: [PATCH v2 net-next 6/9] net: dsa: microchip: add support for ethtool port counters Date: Thu, 22 Apr 2021 15:12:54 +0530 Message-ID: <20210422094257.1641396-7-prasanna.vengateshan@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210422094257.1641396-1-prasanna.vengateshan@microchip.com> References: <20210422094257.1641396-1-prasanna.vengateshan@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Reused the KSZ common APIs for get_ethtool_stats() & get_sset_count() along with relevant lan937x hooks for KSZ common layer and added support for get_strings() Signed-off-by: Prasanna Vengateshan --- drivers/net/dsa/microchip/lan937x_main.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c index 93c392081423..573d2dd906f5 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -43,6 +43,21 @@ static int lan937x_phy_write16(struct dsa_switch *ds, int addr, int reg, return lan937x_internal_phy_write(dev, addr, reg, val); } +static void lan937x_get_strings(struct dsa_switch *ds, int port, + u32 stringset, uint8_t *buf) +{ + struct ksz_device *dev = ds->priv; + int i; + + if (stringset != ETH_SS_STATS) + return; + + for (i = 0; i < dev->mib_cnt; i++) { + memcpy(buf + i * ETH_GSTRING_LEN, lan937x_mib_names[i].string, + ETH_GSTRING_LEN); + } +} + static void lan937x_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) { @@ -372,6 +387,9 @@ const struct dsa_switch_ops lan937x_switch_ops = { .phy_read = lan937x_phy_read16, .phy_write = lan937x_phy_write16, .port_enable = ksz_enable_port, + .get_strings = lan937x_get_strings, + .get_ethtool_stats = ksz_get_ethtool_stats, + .get_sset_count = ksz_sset_count, .port_bridge_join = ksz_port_bridge_join, .port_bridge_leave = ksz_port_bridge_leave, .port_pre_bridge_flags = lan937x_port_pre_bridge_flags, From patchwork Thu Apr 22 09:42:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasanna Vengateshan X-Patchwork-Id: 425941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12856C43462 for ; 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IronPort-SDR: V5PHlqJXK4sMWYwFDeVPjmxgw5b3BSVjMysa8hEKW/6HTWEvOifzbWi/33CkHXaflKDser+1Ky VYPy91IMlUy4rNlbELD32cNDfL3iTsTaF7Lr6xvBjMIVCco4i1JBqL5scglFPnwUaDfMJmsZ7o B2kD+9TJyjDnOjX0bW2BymHU/aDBiruj1zMiQodQkgJkc5BgqEh8tyN+8OteDOkiVN4kJqwTze OR+YKljYYHKOGLyFV/6lYY73ttzNh7T3zpLgFa7/aSsmZqh0EyNkmGMHQFM+iq9D0yPJfg9p/O 2d4= X-IronPort-AV: E=Sophos;i="5.82,242,1613458800"; d="scan'208";a="117977918" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Apr 2021 02:43:55 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 22 Apr 2021 02:43:54 -0700 Received: from CHE-LT-I21427LX.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 22 Apr 2021 02:43:48 -0700 From: Prasanna Vengateshan To: , , , CC: , , , , , , , , Subject: [PATCH v2 net-next 7/9] net: dsa: microchip: add support for port mirror operations Date: Thu, 22 Apr 2021 15:12:55 +0530 Message-ID: <20210422094257.1641396-8-prasanna.vengateshan@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210422094257.1641396-1-prasanna.vengateshan@microchip.com> References: <20210422094257.1641396-1-prasanna.vengateshan@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Added support for port_mirror_add() and port_mirror_del operations Signed-off-by: Prasanna Vengateshan --- drivers/net/dsa/microchip/lan937x_main.c | 50 ++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c index 573d2dd906f5..bfce5098ea69 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -128,6 +128,54 @@ static void lan937x_port_stp_state_set(struct dsa_switch *ds, int port, mutex_unlock(&dev->dev_mutex); } +static int lan937x_port_mirror_add(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress) +{ + struct ksz_device *dev = ds->priv; + int rc; + + if (ingress) + rc = lan937x_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); + else + rc = lan937x_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); + + if (rc < 0) + return rc; + + rc = lan937x_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); + if (rc < 0) + return rc; + + /* configure mirror port */ + rc = lan937x_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, + PORT_MIRROR_SNIFFER, true); + if (rc < 0) + return rc; + + rc = lan937x_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); + + return rc; +} + +static void lan937x_port_mirror_del(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror) +{ + struct ksz_device *dev = ds->priv; + u8 data; + + if (mirror->ingress) + lan937x_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); + else + lan937x_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); + + lan937x_pread8(dev, port, P_MIRROR_CTRL, &data); + + if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) + lan937x_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, + PORT_MIRROR_SNIFFER, false); +} + static phy_interface_t lan937x_get_interface(struct ksz_device *dev, int port) { phy_interface_t interface; @@ -396,6 +444,8 @@ const struct dsa_switch_ops lan937x_switch_ops = { .port_bridge_flags = lan937x_port_bridge_flags, .port_stp_state_set = lan937x_port_stp_state_set, .port_fast_age = ksz_port_fast_age, + .port_mirror_add = lan937x_port_mirror_add, + .port_mirror_del = lan937x_port_mirror_del, .port_max_mtu = lan937x_get_max_mtu, .port_change_mtu = lan937x_change_mtu, .phylink_validate = lan937x_phylink_validate, From patchwork Thu Apr 22 09:42:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasanna Vengateshan X-Patchwork-Id: 425940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1420C433ED for ; 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IronPort-SDR: zItV1dLqdhrJBctnqfO8KwC7xooPwAEf3pL1ku88H2FR6X4s46K4vgmxjKV8ZdfiBsTb8KPD0B Hh3lksaWKvyr4lSFaWI54FlbE3vQrD0V3wDHlVPrUWao2oyz9Q+gCgfG+F7WDa4wSeYvz31RNL VmiVmxo8j1vQA4VSICdpGxSd4CcJCA4/zGCOxYVh+23hRDxgtTFldzdK0QXs7WM+MR1NVjrhn5 Lg/u2in2CuNc27In6Zw9jywTSUSjF+q1zEBgYc1CStBDF2ucOcV6RVnM56XCPhkXPlUpRYO/Xc 8KY= X-IronPort-AV: E=Sophos;i="5.82,242,1613458800"; d="scan'208";a="124117508" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Apr 2021 02:44:09 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 22 Apr 2021 02:44:08 -0700 Received: from CHE-LT-I21427LX.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 22 Apr 2021 02:44:02 -0700 From: Prasanna Vengateshan To: , , , CC: , , , , , , , , Subject: [PATCH v2 net-next 9/9] net: dsa: microchip: add support for vlan operations Date: Thu, 22 Apr 2021 15:12:57 +0530 Message-ID: <20210422094257.1641396-10-prasanna.vengateshan@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210422094257.1641396-1-prasanna.vengateshan@microchip.com> References: <20210422094257.1641396-1-prasanna.vengateshan@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Support for VLAN add, del, prepare and filtering operations. It aligns with latest update of removing switchdev transactional logic from VLAN objects Signed-off-by: Prasanna Vengateshan --- drivers/net/dsa/microchip/lan937x_main.c | 214 +++++++++++++++++++++++ 1 file changed, 214 insertions(+) diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c index 7f6183dc0e31..35f3456c3506 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -14,6 +14,103 @@ #include "ksz_common.h" #include "lan937x_dev.h" +static int lan937x_wait_vlan_ctrl_ready(struct ksz_device *dev) +{ + unsigned int val; + + return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, + val, !(val & VLAN_START), 10, 1000); +} + +static int lan937x_get_vlan_table(struct ksz_device *dev, u16 vid, + u32 *vlan_table) +{ + int rc; + + mutex_lock(&dev->vlan_mutex); + + rc = ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); + if (rc < 0) + goto exit; + + rc = ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); + if (rc < 0) + goto exit; + + /* wait to be cleared */ + rc = lan937x_wait_vlan_ctrl_ready(dev); + if (rc < 0) + goto exit; + + rc = ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); + if (rc < 0) + goto exit; + + rc = ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); + if (rc < 0) + goto exit; + + rc = ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); + if (rc < 0) + goto exit; + + rc = ksz_write8(dev, REG_SW_VLAN_CTRL, 0); + if (rc < 0) + goto exit; + +exit: + mutex_unlock(&dev->vlan_mutex); + + return rc; +} + +static int lan937x_set_vlan_table(struct ksz_device *dev, u16 vid, + u32 *vlan_table) +{ + int rc; + + mutex_lock(&dev->vlan_mutex); + + rc = ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); + if (rc < 0) + goto exit; + + rc = ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); + if (rc < 0) + goto exit; + + rc = ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); + if (rc < 0) + goto exit; + + rc = ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); + if (rc < 0) + goto exit; + + rc = ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); + if (rc < 0) + goto exit; + + /* wait to be cleared */ + rc = lan937x_wait_vlan_ctrl_ready(dev); + if (rc < 0) + goto exit; + + rc = ksz_write8(dev, REG_SW_VLAN_CTRL, 0); + if (rc < 0) + goto exit; + + /* update vlan cache table */ + dev->vlan_cache[vid].table[0] = vlan_table[0]; + dev->vlan_cache[vid].table[1] = vlan_table[1]; + dev->vlan_cache[vid].table[2] = vlan_table[2]; + +exit: + mutex_unlock(&dev->vlan_mutex); + + return rc; +} + static int lan937x_read_table(struct ksz_device *dev, u32 *table) { int rc; @@ -190,6 +287,120 @@ static void lan937x_port_stp_state_set(struct dsa_switch *ds, int port, mutex_unlock(&dev->dev_mutex); } +static int lan937x_port_vlan_filtering(struct dsa_switch *ds, int port, + bool flag, + struct netlink_ext_ack *extack) +{ + struct ksz_device *dev = ds->priv; + int rc; + + if (flag) { + rc = lan937x_port_cfg(dev, port, REG_PORT_LUE_CTRL, + PORT_VLAN_LOOKUP_VID_0, true); + if (rc < 0) + return rc; + + rc = lan937x_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); + } else { + rc = lan937x_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); + if (rc < 0) + return rc; + + rc = lan937x_port_cfg(dev, port, REG_PORT_LUE_CTRL, + PORT_VLAN_LOOKUP_VID_0, false); + } + + return rc; +} + +static int lan937x_port_vlan_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan, + struct netlink_ext_ack *extack) +{ + bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; + struct ksz_device *dev = ds->priv; + u32 vlan_table[3]; + int rc; + + rc = lan937x_get_vlan_table(dev, vlan->vid, vlan_table); + if (rc < 0) { + dev_err(dev->dev, "Failed to get vlan table\n"); + return rc; + } + + vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); + + /* set/clear switch port when updating vlan table registers */ + if (untagged) + vlan_table[1] |= BIT(port); + else + vlan_table[1] &= ~BIT(port); + vlan_table[1] &= ~(BIT(dev->cpu_port)); + + vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); + + rc = lan937x_set_vlan_table(dev, vlan->vid, vlan_table); + if (rc < 0) { + dev_err(dev->dev, "Failed to set vlan table\n"); + return rc; + } + + /* change PVID */ + if (vlan->flags & BRIDGE_VLAN_INFO_PVID) { + rc = lan937x_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); + + if (rc < 0) { + dev_err(dev->dev, "Failed to set pvid\n"); + return rc; + } + } + + return 0; +} + +static int lan937x_port_vlan_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; + struct ksz_device *dev = ds->priv; + u32 vlan_table[3]; + u16 pvid; + int rc; + + lan937x_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); + pvid &= 0xFFF; + + rc = lan937x_get_vlan_table(dev, vlan->vid, vlan_table); + + if (rc < 0) { + dev_err(dev->dev, "Failed to get vlan table\n"); + return rc; + } + /* clear switch port number */ + vlan_table[2] &= ~BIT(port); + + if (pvid == vlan->vid) + pvid = 1; + + if (untagged) + vlan_table[1] &= ~BIT(port); + + rc = lan937x_set_vlan_table(dev, vlan->vid, vlan_table); + if (rc < 0) { + dev_err(dev->dev, "Failed to set vlan table\n"); + return rc; + } + + rc = lan937x_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); + + if (rc < 0) { + dev_err(dev->dev, "Failed to set pvid\n"); + return rc; + } + + return 0; +} + static u8 lan937x_get_fid(u16 vid) { if (vid > ALU_FID_SIZE) @@ -955,6 +1166,9 @@ const struct dsa_switch_ops lan937x_switch_ops = { .port_bridge_flags = lan937x_port_bridge_flags, .port_stp_state_set = lan937x_port_stp_state_set, .port_fast_age = ksz_port_fast_age, + .port_vlan_filtering = lan937x_port_vlan_filtering, + .port_vlan_add = lan937x_port_vlan_add, + .port_vlan_del = lan937x_port_vlan_del, .port_fdb_dump = lan937x_port_fdb_dump, .port_fdb_add = lan937x_port_fdb_add, .port_fdb_del = lan937x_port_fdb_del,