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[209.132.180.131]) by mx.google.com with ESMTPS id 67-v6si8090965pla.475.2018.06.15.07.31.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 Jun 2018 07:31:33 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-479805-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=aKhsciov; spf=pass (google.com: domain of gcc-patches-return-479805-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-479805-patch=linaro.org@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=yamX3Yc24EIWKyENb6HvgICc2b8PpSCtfub1o9awSqFdr8 h+Sqx5AhUqkwlLLHyYBlhQLgcrqE41C4RbDGrD8vEGrcSRQhNYDGywJPP1IPxcVk YQNmlUf02E1IaE/hssDpeCqVN/7MAvtq1ETEV5tQdyXIYwjxdRn0L38Pe7qLY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=NVa5mH1vjcQXjFTiZUcnMczTOik=; b=aKhsciovDIBTSnsnh3ao 1e0y4R2EDBXZahfOWe6yWNngZiOKmBsou38r6xEFYz0MLmEyKUtbZ48AlyYKt6eq m4cmvRaz+qB8vkYi9KmFPPxUfVmtEI0u9n2XvT5wXYuq9heaITuBr4zX97tR3jRE VyxszcuXMOTpOEM3uKKgkAM= Received: (qmail 99362 invoked by alias); 15 Jun 2018 14:31:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 99265 invoked by uid 89); 15 Jun 2018 14:31:08 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=sk:armv8l-, reality, reminder, sk:armv8l X-HELO: mail-vk0-f41.google.com Received: from mail-vk0-f41.google.com (HELO mail-vk0-f41.google.com) (209.85.213.41) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 15 Jun 2018 14:31:03 +0000 Received: by mail-vk0-f41.google.com with SMTP id l64-v6so5780073vkl.12 for ; Fri, 15 Jun 2018 07:31:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=Eih8fGMJZtiUbpxL1b1kSUvfugaVJ3vGRauQV3c3XK4=; b=RF3Qtk4M9fMnRLIs3fEeyCrfnrLisIXY5PuPyxupkEcoW4/+yk9lx7FDoL6enxeP86 aanME7yxTmfd66JUlylKjLAhNnTFcZ7ZRFSn9XSaT6cGDyO1hSKvWWtqDDhMuxtu3sWO cOYZo2D5RFwxYRRxEe3dFe3kAp4CfM+s5qVc1vs0ZnEjZE+NZnIR/TBcNrwLlarfRKEE 1es9IFSy4eP3+94VuaXnnHB1J/0vXaZPzkj88Ncg/brE+KdqoIBPFZL/oENRS5XbKkMY e1i9sMbZLh343ADosO0VVA3B8fTPF4/AbMXL3q+sg5rFpzif32gzqwEFVKnxd0oJ9u3C RvWg== X-Gm-Message-State: APt69E2awzVSDX29z0WPa5g03c8OQy6ZIVsXAh+fg500Bqw2/SdZcpcm xlKFmbM3Mqh8lT+wLYAM3+wk+NV6FXClNN/Xr9u3ITaaLjI= X-Received: by 2002:a1f:58c:: with SMTP id 134-v6mr1084649vkf.55.1529073059636; Fri, 15 Jun 2018 07:30:59 -0700 (PDT) MIME-Version: 1.0 From: Christophe Lyon Date: Fri, 15 Jun 2018 16:30:48 +0200 Message-ID: Subject: [PATCH][ARM] Use __ARM_ARCH instead of __ARM_ARCH__ To: gcc Patches , Kyrylo Tkachov , Richard Earnshaw X-IsSubscribed: yes Hello, As suggested in [1], the attached patch removes all definitions and uses of __ARM_ARCH__ and uses __ARM_ARCH instead. The later is indeed defined by the preprocessor to the appropriate value. I ran make check on arm-none-eabi (with A-profile multilib), arm-none-linux-gnueabi, arm-none-linux-gnueabihf (with cortex-a9, a15, a5, a57 and armtdmi as --with-cpu), armeb-none-linux-gnueabihf and armv8l-linux-gnueabihf, and noticed no regression. OK for trunk? Thanks, Christophe [1] https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00445.html libatomic/ChangeLog: 2018-06-15 Christophe Lyon * config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use __ARM_ARCH instead. libgcc/ChangeLog: 2018-06-15 Christophe Lyon * config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use __ARM_ARCH instead. * config/arm/ieee754-df.S: Use __ARM_ARCH instead of __ARM_ARCH__. * config/arm/ieee754-sf.S: Likewise. * config/arm/libunwind.S: Likewise. diff --git a/libatomic/config/arm/arm-config.h b/libatomic/config/arm/arm-config.h index c0504be..ce8ff0e 100644 --- a/libatomic/config/arm/arm-config.h +++ b/libatomic/config/arm/arm-config.h @@ -23,57 +23,15 @@ . */ -#if defined(__ARM_ARCH_2__) -# define __ARM_ARCH__ 2 -#endif - -#if defined(__ARM_ARCH_3__) -# define __ARM_ARCH__ 3 -#endif - -#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ - || defined(__ARM_ARCH_4T__) -/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with - long multiply instructions. That includes v3M. */ -# define __ARM_ARCH__ 4 -#endif - -#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ - || defined(__ARM_ARCH_5TEJ__) -# define __ARM_ARCH__ 5 -#endif - -#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ - || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ - || defined(__ARM_ARCH_6M__) -# define __ARM_ARCH__ 6 -#endif - -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ - || defined(__ARM_ARCH_7EM__) -# define __ARM_ARCH__ 7 -#endif - -#if defined(__ARM_ARCH_8A__) -# define __ARM_ARCH__ 8 -#endif - -#ifndef __ARM_ARCH__ -#error Unable to determine architecture. -#endif - -#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__) +#if __ARM_ARCH >= 7 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__) # define HAVE_STREX 1 # define HAVE_STREXBHD 1 -#elif __ARM_ARCH__ == 6 +#elif __ARM_ARCH == 6 # define HAVE_STREX 1 #endif -#if __ARM_ARCH__ >= 7 +#if __ARM_ARCH >= 7 # define HAVE_DMB 1 -#elif __ARM_ARCH__ == 6 +#elif __ARM_ARCH == 6 # define HAVE_DMB_MCR 1 #endif diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 04c1b77..264d54a 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* Function end macros. Variants for interworking. */ -#if defined(__ARM_ARCH_2__) -# define __ARM_ARCH__ 2 -#endif - -#if defined(__ARM_ARCH_3__) -# define __ARM_ARCH__ 3 -#endif - -#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ - || defined(__ARM_ARCH_4T__) -/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with - long multiply instructions. That includes v3M. */ -# define __ARM_ARCH__ 4 -#endif - -#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ - || defined(__ARM_ARCH_5TEJ__) -# define __ARM_ARCH__ 5 -#endif - -#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ - || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ - || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ - || defined(__ARM_ARCH_6M__) -# define __ARM_ARCH__ 6 -#endif - -#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ - || defined(__ARM_ARCH_7EM__) -# define __ARM_ARCH__ 7 -#endif - -#if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \ - || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__) -# define __ARM_ARCH__ 8 -#endif - -#ifndef __ARM_ARCH__ -#error Unable to determine architecture. -#endif - /* There are times when we might prefer Thumb1 code even if ARM code is permitted, for example, the code might be smaller, or there might be interworking problems with switching to ARM state if interworking is @@ -135,13 +92,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* How to return from a function call depends on the architecture variant. */ -#if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) +#if (__ARM_ARCH > 4) || defined(__ARM_ARCH_4T__) # define RET bx lr # define RETc(x) bx##x lr /* Special precautions for interworking on armv4t. */ -# if (__ARM_ARCH__ == 4) +# if (__ARM_ARCH == 4) /* Always use bx, not ldr pc. */ # if (defined(__thumb__) || defined(__THUMB_INTERWORK__)) @@ -544,7 +501,7 @@ pc .req r15 /* ------------------------------------------------------------------------ */ .macro ARM_DIV_BODY dividend, divisor, result, curbit -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) #if defined (__thumb2__) clz \curbit, \dividend @@ -584,8 +541,8 @@ pc .req r15 .endr #endif -#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ -#if __ARM_ARCH__ >= 5 +#else /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ +#if __ARM_ARCH >= 5 clz \curbit, \divisor clz \result, \dividend @@ -595,7 +552,7 @@ pc .req r15 mov \curbit, \curbit, lsl \result mov \result, #0 -#else /* __ARM_ARCH__ < 5 */ +#else /* __ARM_ARCH < 5 */ @ Initially shift the divisor left 3 bits if possible, @ set curbit accordingly. This allows for curbit to be located @@ -626,7 +583,7 @@ pc .req r15 mov \result, #0 -#endif /* __ARM_ARCH__ < 5 */ +#endif /* __ARM_ARCH < 5 */ @ Division loop 1: cmp \dividend, \divisor @@ -651,13 +608,13 @@ pc .req r15 movne \divisor, \divisor, lsr #4 bne 1b -#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ +#endif /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ .endm /* ------------------------------------------------------------------------ */ .macro ARM_DIV2_ORDER divisor, order -#if __ARM_ARCH__ >= 5 +#if __ARM_ARCH >= 5 clz \order, \divisor rsb \order, \order, #31 @@ -687,7 +644,7 @@ pc .req r15 /* ------------------------------------------------------------------------ */ .macro ARM_MOD_BODY dividend, divisor, order, spare -#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) +#if __ARM_ARCH >= 5 && ! defined (__OPTIMIZE_SIZE__) clz \order, \divisor clz \spare, \dividend @@ -702,15 +659,15 @@ pc .req r15 subcs \dividend, \dividend, \divisor, lsl #shift .endr -#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ -#if __ARM_ARCH__ >= 5 +#else /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ +#if __ARM_ARCH >= 5 clz \order, \divisor clz \spare, \dividend sub \order, \order, \spare mov \divisor, \divisor, lsl \order -#else /* __ARM_ARCH__ < 5 */ +#else /* __ARM_ARCH < 5 */ mov \order, #0 @@ -732,7 +689,7 @@ pc .req r15 addlo \order, \order, #1 blo 1b -#endif /* __ARM_ARCH__ < 5 */ +#endif /* __ARM_ARCH < 5 */ @ Perform all needed substractions to keep only the reminder. @ Do comparisons in batch of 4 first. @@ -770,7 +727,7 @@ pc .req r15 subhs \dividend, \dividend, \divisor 5: -#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ +#endif /* __ARM_ARCH < 5 || defined (__OPTIMIZE_SIZE__) */ .endm /* ------------------------------------------------------------------------ */ @@ -1560,7 +1517,7 @@ LSYM(Lover12): @ EABI GNU/Linux call to cacheflush syscall. ARM_FUNC_START clear_cache do_push {r7} -#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__) +#if __ARM_ARCH >= 7 || defined(__ARM_ARCH_6T2__) movw r7, #2 movt r7, #0xf #else @@ -1701,8 +1658,8 @@ LSYM(Lover12): #if (__ARM_ARCH_ISA_THUMB == 2 \ || (__ARM_ARCH_ISA_ARM \ - && (__ARM_ARCH__ > 5 \ - || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB)))) + && (__ARM_ARCH > 5 \ + || (__ARM_ARCH == 5 && __ARM_ARCH_ISA_THUMB)))) #define HAVE_ARM_CLZ 1 #endif @@ -1887,7 +1844,7 @@ ARM_FUNC_START ctzsi2 not support Thumb instructions. (This can be a multilib option). */ #if defined __ARM_ARCH_4T__ || defined __ARM_ARCH_5T__\ || defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__ \ - || __ARM_ARCH__ >= 6 + || __ARM_ARCH >= 6 #if defined L_call_via_rX diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S index 570e5f6..7c5260e 100644 --- a/libgcc/config/arm/ieee754-df.S +++ b/libgcc/config/arm/ieee754-df.S @@ -245,7 +245,7 @@ LSYM(Lad_a): @ No rounding necessary since ip will always be 0 at this point. LSYM(Lad_l): -#if __ARM_ARCH__ < 5 +#if __ARM_ARCH < 5 teq xh, #0 movne r3, #20 @@ -656,7 +656,7 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3 orr yh, yh, #0x00100000 beq LSYM(Lml_1) -#if __ARM_ARCH__ < 4 +#if __ARM_ARCH < 4 @ Put sign bit in r6, which will be restored in yl later. and r6, r6, #0x80000000 diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S index dac3e2e..00a8d9c 100644 --- a/libgcc/config/arm/ieee754-sf.S +++ b/libgcc/config/arm/ieee754-sf.S @@ -175,7 +175,7 @@ LSYM(Lad_a): @ No rounding necessary since r1 will always be 0 at this point. LSYM(Lad_l): -#if __ARM_ARCH__ < 5 +#if __ARM_ARCH < 5 movs ip, r0, lsr #12 moveq r0, r0, lsl #12 @@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf subeq r3, r3, #(32 << 23) 2: sub r3, r3, #(1 << 23) -#if __ARM_ARCH__ < 5 +#if __ARM_ARCH < 5 mov r2, #23 cmp ip, #(1 << 16) @@ -460,7 +460,7 @@ LSYM(Lml_x): orr r0, r3, r0, lsr #5 orr r1, r3, r1, lsr #5 -#if __ARM_ARCH__ < 4 +#if __ARM_ARCH < 4 @ Put sign bit in r3, which will be restored into r0 later. and r3, ip, #0x80000000 diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S index 3302447..50c58dc 100644 --- a/libgcc/config/arm/libunwind.S +++ b/libgcc/config/arm/libunwind.S @@ -46,7 +46,7 @@ EQUIV SYM (\name), SYM (__\name) .endm -#if (__ARM_ARCH__ == 4) +#if (__ARM_ARCH == 4) /* Some coprocessors require armv5t. We know this code will never be run on other cpus. Tell gas to allow armv5t, but only mark the objects as armv4. */