From patchwork Sun Apr 18 14:44:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 423977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98197C43600 for ; Sun, 18 Apr 2021 14:44:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 770036135A for ; Sun, 18 Apr 2021 14:44:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231767AbhDROpP (ORCPT ); Sun, 18 Apr 2021 10:45:15 -0400 Received: from out28-121.mail.aliyun.com ([115.124.28.121]:35990 "EHLO out28-121.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230038AbhDROpO (ORCPT ); Sun, 18 Apr 2021 10:45:14 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.077516|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.00333635-0.000227116-0.996437; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047188; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=15; RT=15; SR=0; TI=SMTPD_---.K.sSkG._1618757074; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.K.sSkG._1618757074) by smtp.aliyun-inc.com(10.147.40.233); Sun, 18 Apr 2021 22:44:42 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linus.walleij@linaro.org, robh+dt@kernel.org, paul@crapouillou.net Cc: linux-gpio@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, hns@goldelico.com, paul@boddie.org.uk, andy.shevchenko@gmail.com, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sernia.zhou@foxmail.com, stable@vger.kernel.org Subject: [PATCH v6 01/12] pinctrl: Ingenic: Add missing pins to the JZ4770 MAC MII group. Date: Sun, 18 Apr 2021 22:44:22 +0800 Message-Id: <1618757073-1724-2-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618757073-1724-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1618757073-1724-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org The MII group of JZ4770's MAC should have 7 pins, add missing pins to the MII group. Fixes: 5de1a73e78ed ("Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780.") Cc: Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Andy Shevchenko Reviewed-by: Paul Cercueil --- Notes: v2: New patch. v2->v3: Add fixes tag. v3->v4: 1.Add Cc: . 2.Add Andy Shevchenko's Reviewed-by. 3.Add Paul Cercueil's Reviewed-by. v4->v5: No change. v5->v6: No change. drivers/pinctrl/pinctrl-ingenic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index f274612..05dfa0a 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -667,7 +667,9 @@ static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; static int jz4770_mac_rmii_pins[] = { 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, }; -static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, }; +static int jz4770_mac_mii_pins[] = { + 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, +}; static const struct group_desc jz4770_groups[] = { INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), From patchwork Sun Apr 18 14:44:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 424537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBEB6C4360C for ; Sun, 18 Apr 2021 14:44:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BAD6D613AC for ; Sun, 18 Apr 2021 14:44:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235024AbhDROpS (ORCPT ); Sun, 18 Apr 2021 10:45:18 -0400 Received: from out28-125.mail.aliyun.com ([115.124.28.125]:55388 "EHLO out28-125.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231861AbhDROpQ (ORCPT ); Sun, 18 Apr 2021 10:45:16 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1222198|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0547366-0.000210722-0.945053; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047204; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=15; RT=15; SR=0; TI=SMTPD_---.K.sSkG._1618757074; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.K.sSkG._1618757074) by smtp.aliyun-inc.com(10.147.40.233); Sun, 18 Apr 2021 22:44:43 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linus.walleij@linaro.org, robh+dt@kernel.org, paul@crapouillou.net Cc: linux-gpio@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, hns@goldelico.com, paul@boddie.org.uk, andy.shevchenko@gmail.com, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sernia.zhou@foxmail.com, stable@vger.kernel.org Subject: [PATCH v6 02/12] pinctrl: Ingenic: Add support for read the pin configuration of X1830. Date: Sun, 18 Apr 2021 22:44:23 +0800 Message-Id: <1618757073-1724-3-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618757073-1724-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1618757073-1724-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Add X1830 support in "ingenic_pinconf_get()", so that it can read the configuration of X1830 SoC correctly. Fixes: d7da2a1e4e08 ("pinctrl: Ingenic: Add pinctrl driver for X1830.") Cc: Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Andy Shevchenko Reviewed-by: Paul Cercueil --- Notes: v2: New patch. v2->v3: 1.Add fixes tag. 2.Adjust the code, simplify the ingenic_pinconf_get() function. v3->v4: 1.Add parentheses around the '%' to make it more obvious. 2.Add Cc: . 3.Add Andy Shevchenko's Reviewed-by. 4.Add Paul Cercueil's Reviewed-by. v4->v5: No change. v5->v6: No change. drivers/pinctrl/pinctrl-ingenic.c | 40 ++++++++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 05dfa0a..3de0f76 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -2109,26 +2109,48 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, enum pin_config_param param = pinconf_to_config_param(*config); unsigned int idx = pin % PINS_PER_GPIO_CHIP; unsigned int offt = pin / PINS_PER_GPIO_CHIP; - bool pull; + unsigned int bias; + bool pull, pullup, pulldown; - if (jzpc->info->version >= ID_JZ4770) - pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); - else - pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); + if (jzpc->info->version >= ID_X1830) { + unsigned int half = PINS_PER_GPIO_CHIP / 2; + unsigned int idxh = (pin % half) * 2; + + if (idx < half) + regmap_read(jzpc->map, offt * jzpc->info->reg_offset + + X1830_GPIO_PEL, &bias); + else + regmap_read(jzpc->map, offt * jzpc->info->reg_offset + + X1830_GPIO_PEH, &bias); + + bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN); + + pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx)); + pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx)); + + } else { + if (jzpc->info->version >= ID_JZ4770) + pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); + else + pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); + + pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx)); + pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx)); + } switch (param) { case PIN_CONFIG_BIAS_DISABLE: - if (pull) + if (pullup || pulldown) return -EINVAL; break; case PIN_CONFIG_BIAS_PULL_UP: - if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx))) + if (!pullup) return -EINVAL; break; case PIN_CONFIG_BIAS_PULL_DOWN: - if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx))) + if (!pulldown) return -EINVAL; break; @@ -2146,7 +2168,7 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, if (jzpc->info->version >= ID_X1830) { unsigned int idx = pin % PINS_PER_GPIO_CHIP; unsigned int half = PINS_PER_GPIO_CHIP / 2; - unsigned int idxh = pin % half * 2; + unsigned int idxh = (pin % half) * 2; unsigned int offt = pin / PINS_PER_GPIO_CHIP; if (idx < half) {