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X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [RISU PATCH v3 01/22] risu_reginfo_aarch64: include signal.h for FPSIMD_MAGIC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Building with the Bionic Beaver cross compilers fails which probably means we were getting this as a side effect before. Include the correct header to get at these bits. Signed-off-by: Alex Bennée --- risu_reginfo_aarch64.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index e3fadde..3bb4339 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -13,6 +13,7 @@ #include #include #include +#include /* for FPSIMD_MAGIC */ #include "risu.h" #include "risu_reginfo_aarch64.h" From patchwork Wed Jun 13 12:55:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138455 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp685452lji; Wed, 13 Jun 2018 05:56:38 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKuDbxFjryI03Soi1EDntkoHEMDC6xM3ciTKOuK4cmlr8vdBHJWqTFnQtZvOhH5SqTkLu4i X-Received: by 2002:a0c:e354:: with SMTP id a20-v6mr4170169qvm.229.1528894598227; Wed, 13 Jun 2018 05:56:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528894598; cv=none; d=google.com; s=arc-20160816; b=Wyel+ezvv338RRVJdrZEWorNhAolSp16242HTMUSkvREYeFg2kve8q0LSz6mRgRsA9 oRdfNB4Z4EBlmAGEBGAn/RoUZRWRInVavDIL2IpOBeKpJ/Xo4I/7z/tnQ4/PYi6se2y9 Ub9ABZCnv1AQ3irOHow43O9CqAB88YX//gQWyyvT77LJ9kK/J4WOtCgeaiZe2BRu+AHh 2NPxwHJpb9kmwQF74x63LN0Y2E1204gYIF2WZHRh3CSqASoYzKqe70ID+FN2TlvDnAaK d7yR2EyFZFuB36+zPSlsB6oDyqk0eviIXkuuEv2qNRiZ5V1xKrJb9nb/9rWLyjMg6t5i u0IA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=uPJGhUZMN9OICgRHF4EF6gY4Qz617Mu28M40KL4BiT8=; b=RGEYB4sZ7asvkx9FGeb2IRzcRWk7r72vJFc3QAWhcyOupjutMxAyLEREJUMVnvdQPQ tT1/KT0RiBSD+li9utUBJvE8ZTDi2BJWcAJ+00PtYWjA/ErypSuRE48moquY4OmKwwpR bc9T+e4DgLNf74V46oYkB527c+kahVYX6O3YC2TyEGVPeON4IkAkPDx4gSa85Brf5UTX +pwh+8KCNCHaymQB/NHEbMYYS+RodtekSUBJLsaFBsX/rlbHtxfLylSsiF9YsuxwKoSy 8IM7hwaycafn4HJxTkuwHus4yC6BqB0kKd86WSA3MaTv00wypmckTbEIE5Np5Cu7Pafw JgwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Au3urgvR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [RISU PATCH v3 02/22] comms: include header for writev X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The compiler complains about implicit declarations otherwise. Signed-off-by: Alex Bennée --- comms.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/comms.c b/comms.c index 2900c33..6946fd9 100644 --- a/comms.c +++ b/comms.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include From patchwork Wed Jun 13 12:55:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138456 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp685501lji; Wed, 13 Jun 2018 05:56:41 -0700 (PDT) X-Google-Smtp-Source: ADUXVKL/bMUXuyk1bO6r/fr/QTr9Jpold/ttYvJNjFy1LSAXmwlqy6YnvQGjAfBGap6DtRqQzCty X-Received: by 2002:ac8:313d:: with SMTP id g58-v6mr4286197qtb.321.1528894601117; Wed, 13 Jun 2018 05:56:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528894601; cv=none; d=google.com; s=arc-20160816; b=yEZ90mbbP7385/o0IQ4pcDqpbsDrX45KirCMHO4ih3lU+fxq9zp1luW23nbATv8DKZ TEMzVG08TXGmBmMiWtVn1WtLKMEEuQbq5nmPd8e2DIV+CPyYwaanw8ISImpy3fqhH6QA dwj7rLPT47C/f37A+pn+xWXjY3W8X84niy45aY2yfwx3us7vrQPy1Ir18cRUS+s8E6dF cxaZTCBlLGfqFv6HmIp9kMBAWP06pJTn8Mv6eZtHkYzq/jsldGAGdPh4GwDCMyjLHAFO 3EZjbfPPC8zik6mtQFzp62S2RqwBhQJaByqofgGcA1tvQPMqpw/1QTmIBrzPLqkmvPQQ AfRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=KPEpDniC/v0/LmqxJpn4p9Ffr05ugc4zTNV+MFf4kuI=; b=XKNi8GoKM+dgOL0S7n9wg7R1CmWvJ5TjAckprLcLfu47T+nls/fpel89SVBCibrXC9 rD8DjdAkGYTKu2YwgJ3CiFqqVQ1owpOmiGLI248Ca+QcT1LD9rn5ZuVE0bGsV3KoZdIP rGMurVaaVr9EKEjqw/iAWAb7a7IQghv06yLpI9Y3LmQTUfUhty7Za4A883DXlCHFofAb bqUCXeonFvT3ZFHzjS6lT+VxkaPxHQ/ywIqfr6DDadmFJI1rbOQ072wxrp3p0myE+HRe udwunihuJQjb11pF8Cil14QTKTiIEYov/8Oue4HleTDxzl59zywzKU+XN6WyYfTKdnSO krGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AUHW86as; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::229 Subject: [Qemu-devel] [RISU PATCH v3 03/22] build-all-arches: expand the range of docker images X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We won't actually want power, we want ppc64el for the 64 bit version. Also we will soon have m68k so include that as well. Signed-off-by: Alex Bennée --- build-all-archs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/build-all-archs b/build-all-archs index fa2ac90..a2f5cff 100755 --- a/build-all-archs +++ b/build-all-archs @@ -39,7 +39,7 @@ while [[ "$1" = -* ]]; do ;; --use-docker) if [ -z "$arg" ]; then - default_tags=$(docker images qemu --format "{{.Repository}}:{{.Tag}}" | grep "\(arm\|power\).*cross$") + default_tags=$(docker images qemu --format "{{.Repository}}:{{.Tag}}" | grep "\(arm\|ppc64el\|m68k\).*cross$") docker_tags=$(echo $default_tags | sed 's/\n/\s/g' ) else docker_tags="$arg" From patchwork Wed Jun 13 12:55:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138460 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp688463lji; Wed, 13 Jun 2018 05:59:43 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJ9SokTjwrIPRZUkOJII+wwDixFJBbi88OjTDNjoDuGBqc510et2ZgTt2jQOvqKI335j9q8 X-Received: by 2002:a37:2801:: with SMTP id o1-v6mr4114252qkh.319.1528894783005; Wed, 13 Jun 2018 05:59:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528894783; cv=none; d=google.com; s=arc-20160816; b=iFcUOCq+EwyMawdB4hhLdhfUJiqViNQ6+fFKgRIZSgSrmIfdq2zXfFiUd+ydfCRJ75 YambEuI9wxc+t47kvXO7DAA16xG3Syg8bGxCcNjiDE+xXFS+oKQATIUrPBjR1LAYf2N0 2IknvBAegW/3yNmrsbxiQjqULY/dPdvwj49aAXaL3FPF28UgFRgxkJC0DtDSbwsOYwgF KDDZtwrqF+wfvUSb6t3ChhoPSlVi3DVx5xXWmfNILtiKLvuGyRFrxj5d648kJ7KY1l30 31BSJT+FUMv2xcJxN8t5gxy8tlDPxcdtUWL60n+SOqLbGJnUY1HWRlPZtWRNMU8IsqZx QTUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=KCKIq+8OEady2Byjj4NMgletq2g04qOhocFOf1HWHBA=; b=jC0UMgRcamtNkQPWn3kX7mv7+tQE7jurv5AsLNNzgS58evOrBGL/PBwndADVY7OD3T ax/HMNvql0RLfrSaT2pvotBk0Zm5ODI6eUKsOxMNab8lkZ8LKTw6WKHJ7y/jAmlPnffT cTlfPbs2zulazU/uAIcjej2ZR0GCOtywpLJ3eto2430FkOkTNewpMHX83JPGZWKL+4bO LcU21qqlung+mBnHblxE+pn3PEJJ8TKntRfd+7c2DP0hl6RgdcB0szIdoBw1M5q8o6hI +aVdD/oJBP66+R+I3QUfyFKB9rayuQCzZ6T4EO8d/tSUUQVd6/pIx/OR7fhMfNxYVq5I Q1qQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=b9Y0L1Yh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [RISU PATCH v3 04/22] build-all-arches: do a distclean $(SRC) configured X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This can cause much confusion when you have been building in your source tree. I've added a distclean so we don't unexpectedly drop the config for normal make clean invocations. Signed-off-by: Alex Bennée --- Makefile | 3 +++ build-all-archs | 10 ++++++++++ 2 files changed, 13 insertions(+) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/Makefile b/Makefile index ca80eef..16e48a0 100644 --- a/Makefile +++ b/Makefile @@ -51,3 +51,6 @@ $(PROG): $(OBJS) clean: rm -f $(PROG) $(OBJS) $(BINS) + +distclean: clean + rm -f config.h Makefile.in diff --git a/build-all-archs b/build-all-archs index a2f5cff..a7cd7c2 100755 --- a/build-all-archs +++ b/build-all-archs @@ -54,6 +54,16 @@ while [[ "$1" = -* ]]; do esac done +# +# If you are developing your primary architecture directly out of the +# source tree you can confuse any out-of-tree builds thanks to random +# crap in your VPATH. Let's detect that and save some hair pulling. +# +if [ -e Makefile.in ]; then + echo "Cleaning in-src-tree build" + make distclean +fi + # Debian stretch and Ubuntu Xenial have cross compiler packages for # all of these: # gcc-arm-linux-gnueabihf gcc-aarch64-linux-gnu gcc-m68k-linux-gnu From patchwork Wed Jun 13 12:55:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138462 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp694413lji; Wed, 13 Jun 2018 06:03:22 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJ2Xuj+5nGomxKr3rCqldqzmq0W4UiYRO/0smbMcMDnz1Z2nrTJtn1drsXezgTlOtIEc6GM X-Received: by 2002:ac8:2ffc:: with SMTP id m57-v6mr4336035qta.212.1528895002794; Wed, 13 Jun 2018 06:03:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528895002; cv=none; d=google.com; s=arc-20160816; b=qtyjQPiOaU32CMtJ3Az8Krnl6kxKWzG2lpeSGq7YHp9JlWOEh0U566zNVbwoM+2Tx2 fR2iyKM4EMhSJkxg4dEuu+waTRIWSxGzTXOwnz/eN7oENfertOnuUJpp15jF8VAhRjvA laa+flPRTXriStbMSOtFwhxrz4izmDKyrJ11BZ8D4QcMMSYKQP2E4mB1LFl+8alI/O8Y i6vlS39Pp8taGJCZ5R4i0VU1Ny4ECHYVMSXSGp/cwB7VN0tHCVEi/NlLXj6pUhfwhelc LLZaFHCTWO8tBWZ2JekwJW/eSBfHqUbR1161dGc1+cy/+rDVOswdLuk9RSUD+6LRe+l3 zhOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=wxcfGsS86kcfjLCdS7LsJfrKrVdL+ITWHRqzI4GxmL0=; b=KTnz3FS5tcV7w/3G7XdyNcWPsamfZr9RgaHQHHRVUXVaHFTEOQ1jhekazLLddrC55w +A45PkOa3WgwnjT7PdI+hP4JzalOJC0hcJsIKURsxC7DC8ZHlp5jW8Aai9YAdpCDMqrg iLzS4lJw998O9RMvqlQ21wU+Wwp8gzZ0PWi/odd5RtQdlYuSn83N1EVfaDRVfHukB/RW Sr/N5F6eFrscFvl5df60g+7CZWuRpX44ITDG9X2f4WLD1LwWbBiLYCtXK1vAcQRedcEy iG8qunMze599/MwGXy+dzzq4veuR0FoT3CTQ95smppveBDloRFLL7PVaN2tmxoOf8PrV PUbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=e3Xgh41Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::22a Subject: [Qemu-devel] [RISU PATCH v3 05/22] risu: add zlib indication to help text X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a simple aide-memoir as it can be tricky to determine this with a simple statically compiled binary. Signed-off-by: Alex Bennée --- risu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/risu.c b/risu.c index 616fc33..c684c90 100644 --- a/risu.c +++ b/risu.c @@ -39,6 +39,9 @@ size_t signal_count; #ifdef HAVE_ZLIB #include gzFile gz_trace_file; +#define TRACE_TYPE "compressed" +#else +#define TRACE_TYPE "uncompressed" #endif sigjmp_buf jmpbuf; @@ -273,7 +276,7 @@ void usage(void) fprintf(stderr, "between master and apprentice risu processes.\n\n"); fprintf(stderr, "Options:\n"); fprintf(stderr, " --master Be the master (server)\n"); - fprintf(stderr, " -t, --trace=FILE Record/playback trace file\n"); + fprintf(stderr, " -t, --trace=FILE Record/playback " TRACE_TYPE " trace file\n"); fprintf(stderr, " -h, --host=HOST Specify master host machine (apprentice only)" "\n"); From patchwork Wed Jun 13 12:55:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138466 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp698364lji; Wed, 13 Jun 2018 06:06:03 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJIW9UDXcZRZqxNCpzZ567pDQ9lwgCcEd3m85P3yYbdgPu+dObhK7yX4ByFL4Z7wLaKQPiV X-Received: by 2002:a37:ac02:: with SMTP id e2-v6mr4063306qkm.222.1528895163162; Wed, 13 Jun 2018 06:06:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528895163; cv=none; d=google.com; s=arc-20160816; b=UIdAhcxMUQOMXSGewc4zI1M2bwrTyyz8/f57CyZdyoZ/DOVDxMSjUTQIrcUM71lXZh Mva6SzyJdafT2sA78e0QiKz60y3412bxqICSt8LnFmdElFkCzqif+pYZaN/P5/XhcvCu 2K7QJh+YH2rYMTCzaZZ+SMTPQVDa2y/R/HGmmUw4Acl3ffvvoae1MvAKgYVlnJ9IEw+l 8nwDzm66S5po1Ku5b88wQz7BQZYggMzmHQ5Fa5TD6wD+CNariehYR4jkZTZEHYmBB+Wn wyUeytdlgouN5cJC6QLrGTG1rgC01FATcyzbXJX80RjsnMPCbxHiQdgVmD5LmT4Jp/Gf zACQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=OMhZ8+l3oFZGLTz6NEd67UuqOdw7Hr+2pHEWznqZjqY=; b=HWi9/e7wv3aEdGEP35HkwgfYCIisgTgXPPKxXEdWzrnSQmsW8l1fKH75lz21tQu0BF u+5o3cHQpOxP2hWO+06+7In/1DLIhQCb5PiuqGThDL0eZ9MSqVcWXDG4dDurqeWDAWD3 a54BYmwNwQmBN6Mi3aRODU2lsQGdyTSgGCyyPeAib0r8cIoL4Ypx2DTTvQTCTraQrDbC fOfZ/97CVNQxmOgRFmHrkHwdZPYz1rqAnk2EKY2LUfCt/j+jN7UxfaBA2gtrIp1nCy4I AGmMpWbmIbePyMKPdUDkTEDxSDH5KLO7ksSDPKQ5H1G2pjf61WOQhxT3l+YCz9MIbssv vUIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IB9XvymX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [RISU PATCH v3 06/22] Makefile: include risu_reginfo_$(ARCH) in HDRS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Otherwise changes to reginfo don't cause the whole thing to be re-built causing much confusion when bisecting. Signed-off-by: Alex Bennée --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/Makefile b/Makefile index 16e48a0..4aad448 100644 --- a/Makefile +++ b/Makefile @@ -21,7 +21,7 @@ ALL_CFLAGS = -Wall -D_GNU_SOURCE -DARCH=$(ARCH) $(BUILD_INC) $(CFLAGS) $(EXTRA_C PROG=risu SRCS=risu.c comms.c reginfo.c risu_$(ARCH).c risu_reginfo_$(ARCH).c -HDRS=risu.h +HDRS=risu.h risu_reginfo_$(ARCH).h BINS=test_$(ARCH).bin # For dumping test patterns From patchwork Wed Jun 13 12:55:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138457 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp687824lji; Wed, 13 Jun 2018 05:59:05 -0700 (PDT) X-Google-Smtp-Source: ADUXVKK1XliFXue3tKYc3SB7XwDRrUUex88nHRUozvj9gKzkk+ymDUhjbt+o7ZS+2y66t7cD7RIx X-Received: by 2002:a37:b603:: with SMTP id g3-v6mr4306903qkf.208.1528894745385; Wed, 13 Jun 2018 05:59:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528894745; cv=none; d=google.com; s=arc-20160816; b=VlQS221saL5dwGYpOuPwpcWvE0SYwa4ByctqoAa7Pr4jO4NhOSLpYJYACdv9uaAdMT IGplFZe2wIQhXVqktaFESS5pVWX67HGLVtklPEculu8+W/2+iZWwM+7uLIsIqJ1TNKch 3mWtW3asYOrppFyBhOQtMWOsB8pVxuWiPdcdqIV6YNENFMZRqeidVsOGX9UX2wOkgY84 J81Ecw/sdGjJoyqoVRmsuTCHOI7406ND1iuLj/dwnR4p2luKbVlvzo9qG3ft0KuS3N0f mOR653yvKqNpq99dFZuOJmkBJm+YFFOwTAE3NflWIa+uEaE4R3pE+TAu15i5q1JtlQOE vSug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=IEGZXFnFNMOWMxKC/DUaSek0uOvs3FGzAO/YFETY3Ak=; b=P5rsNdqLWY0lEwbW6sqiKbJpF6SCH/I1bAy3ftbm4R2NjkPJ7SiHpoH5/bd979gFbn 5W3JUyNL6x/Yj5WUaFgZzb+9m/EqM/aGZKQ3g0oUZVxtoqMijXgix9tjgxpI4QrfdAbp JpvchTDCIMOiQLNxSQrIWXV4acS0T6+e9u5XETN2dGmVqZdPqyya/u/48UwQyZUyypB/ OZNpO3gftTrnnGOlRB+eoit7WX2VmFGXVa6F3B6PgFuD8Mp7rPTtDblnX2wPoPSZqlsv XMGYVGwL91GgNxfWNtzF/HNhxS6AWa/dTF9Cj1eCkPW4WuHDGgAhwfEDpaDpIZwaoloH 3FXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DN5YSijr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [RISU PATCH v3 07/22] risugen: add --sve support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is similar to the approach used by the FP/simd data in so far as we generate a block of random data and then load into it. The loading is actually done by the current vector length but that is implicit in the run anyway. Signed-off-by: Alex Bennée --- v2 - only one SIMD/FP/SVE block as they alias - move efficient loading as suggested by Dave --- risugen | 3 +++ risugen_arm.pm | 56 ++++++++++++++++++++++++++++++++++++++++++-------- 2 files changed, 50 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/risugen b/risugen index 488d804..de3f5ea 100755 --- a/risugen +++ b/risugen @@ -319,6 +319,7 @@ sub main() my $condprob = 0; my $fpscr = 0; my $fp_enabled = 1; + my $sve_enabled = 1; my $big_endian = 0; my ($infile, $outfile); @@ -336,6 +337,7 @@ sub main() }, "be" => sub { $big_endian = 1; }, "no-fp" => sub { $fp_enabled = 0; }, + "sve" => sub { $sve_enabled = 1; }, ) or return 1; # allow "--pattern re,re" and "--pattern re --pattern re" @pattern_re = split(/,/,join(',',@pattern_re)); @@ -363,6 +365,7 @@ sub main() 'fpscr' => $fpscr, 'numinsns' => $numinsns, 'fp_enabled' => $fp_enabled, + 'sve_enabled' => $sve_enabled, 'outfile' => $outfile, 'details' => \%insn_details, 'keys' => \@insn_keys, diff --git a/risugen_arm.pm b/risugen_arm.pm index 2f10d58..bb3ee90 100644 --- a/risugen_arm.pm +++ b/risugen_arm.pm @@ -472,14 +472,51 @@ sub write_random_aarch64_fpdata() } } -sub write_random_aarch64_regdata($) +sub write_random_aarch64_svedata() { - my ($fp_enabled) = @_; + # Load SVE registers + my $align = 16; + my $vq = 16; # quadwords per vector + my $datalen = (32 * $vq * 16) + $align; + + write_pc_adr(0, (3 * 4) + ($align - 1)); # insn 1 + write_align_reg(0, $align); # insn 2 + write_jump_fwd($datalen); # insn 3 + + # align safety + for (my $i = 0; $i < ($align / 4); $i++) { + # align with nops + insn32(0xd503201f); + }; + + for (my $rt = 0; $rt <= 31; $rt++) { + for (my $q = 0; $q < $vq; $q++) { + write_random_fpreg_var(4); # quad + } + } + + # Reset all the predicate registers to all true + for (my $p = 0; $p < 16; $p++) { + insn32(0x2518e3e0 | $p); + } + + for (my $rt = 0; $rt <= 31; $rt++) { + # ldr z$rt, [x0, #$rt, mul vl] + insn32(0x85804000 + $rt + (($rt & 7) << 10) + (($rt & 0x18) << 13)); + } +} + +sub write_random_aarch64_regdata($$) +{ + my ($fp_enabled, $sve_enabled) = @_; # clear flags insn32(0xd51b421f); # msr nzcv, xzr - if ($fp_enabled) { - # load floating point / SIMD registers + # Load floating point / SIMD registers + # (one or the other as they overlap) + if ($sve_enabled) { + write_random_aarch64_svedata(); + } elsif ($fp_enabled) { write_random_aarch64_fpdata(); } @@ -490,12 +527,12 @@ sub write_random_aarch64_regdata($) } } -sub write_random_register_data($) +sub write_random_register_data($$) { - my ($fp_enabled) = @_; + my ($fp_enabled, $sve_enabled) = @_; if ($is_aarch64) { - write_random_aarch64_regdata($fp_enabled); + write_random_aarch64_regdata($fp_enabled, $sve_enabled); } else { write_random_arm_regdata($fp_enabled); } @@ -893,6 +930,7 @@ sub write_test_code($$$$$$$$) my $fpscr = $params->{ 'fpscr' }; my $numinsns = $params->{ 'numinsns' }; my $fp_enabled = $params->{ 'fp_enabled' }; + my $sve_enabled = $params->{ 'sve_enabled' }; my $outfile = $params->{ 'outfile' }; my %insn_details = %{ $params->{ 'details' } }; @@ -918,7 +956,7 @@ sub write_test_code($$$$$$$$) write_memblock_setup(); } # memblock setup doesn't clean its registers, so this must come afterwards. - write_random_register_data($fp_enabled); + write_random_register_data($fp_enabled, $sve_enabled); write_switch_to_test_mode(); for my $i (1..$numinsns) { @@ -930,7 +968,7 @@ sub write_test_code($$$$$$$$) # Rewrite the registers periodically. This avoids the tendency # for the VFP registers to decay to NaNs and zeroes. if ($periodic_reg_random && ($i % 100) == 0) { - write_random_register_data($fp_enabled); + write_random_register_data($fp_enabled, $sve_enabled); write_switch_to_test_mode(); } progress_update($i); From patchwork Wed Jun 13 12:55:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138459 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp688291lji; Wed, 13 Jun 2018 05:59:34 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJEijK4x5yOJxOjcM4sfGCwBJzn8wKGbDqREffKrX9sB1oeu/iewy0A8GR7ZRHlng4zevvO X-Received: by 2002:a0c:f748:: with SMTP id e8-v6mr4290145qvo.174.1528894774245; Wed, 13 Jun 2018 05:59:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528894774; cv=none; d=google.com; s=arc-20160816; b=s6jVVUSjR6hKET77b3mtGKtljMuVnQ2MD6NnWBOPwbGoPYrvEG8HXoYqp1uTpx7EaL lRJplqkuK3tsQtzvwF/09Sm8yZCa00iGnx6cjRpTjX6AgQZx9Za3Evcjz/PxAHbUObCa 7E49AbviUwGavantiW9lXBiHknxVG+FuSEkDzX6WFvLtkDpKwxSUnHKF/w+aGHiRsbys qdlJoWtIaHM/9C4HTa2JjlIYQagIWzGvBCcDTSbgLmM7AR3BoqdIy1q0WBAwy5HAMT94 n1S1ipgL1FYtAO3HxhLwoMSLdARaZxUI1fD9zSiidha3hkgf9UuMxFsebahMz9yV9qm3 pU6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=0Xm+ER24biXy+jhU0foOUmeppdyuMIuvTildhLQkYKo=; b=P0JM2x3KTLzhPJUkugM3iQ12bwp+eFv60hoMj1xMyu93y3h7WEgkY4GRuXYfCPgQwl GXwc3ecguBa6qs+Y3xSQu1qKybbRi5CQiEwOUz+II6n5GdA/wK2TuIZUrdmttQ8mXdKs pSXqWPyk+HDufpPZUfwuEdQlmyQp/zTBXmteWJFGXs3vXZjVk3UiQa4heEC0KuJL0LYu xYra3w9BAaUwkflYUjl6nr24gctez26VAuXaSHUvw7PF+TOnhGx1wlR3+ItBMmajRUCJ QWWyRS1188UktLJ0cOANJofWjIbSdythv4V00m4yM0SbdJE/WnqJVJf9VKLxTNGy7OPP 46vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LyOaFe9V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [RISU PATCH v3 08/22] risugen: Initialize sve predicates with random data X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Using ptrue makes most of the uses of predicates trivial. Therefore, initialize them to something interesting. Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée --- risugen_arm.pm | 48 ++++++++++++++++++++++++++++++++++-------------- 1 file changed, 34 insertions(+), 14 deletions(-) -- 2.17.1 diff --git a/risugen_arm.pm b/risugen_arm.pm index bb3ee90..83e521d 100644 --- a/risugen_arm.pm +++ b/risugen_arm.pm @@ -174,6 +174,24 @@ sub write_sxt32($$) insn32(0x93407c00 | $rn << 5 | $rd); } +sub write_add_rri($$$) +{ + my ($rd, $rn, $i) = @_; + my $sh; + + die "write_add_rri: invalid operation for this arch.\n" if (!$is_aarch64); + + if ($i >= 0 && $i < 0x1000) { + $sh = 0; + } elsif (($i & 0xfff) || $i >= 0x1000000) { + die "invalid immediate for this arch,\n"; + } else { + $sh = 1; + $i >>= 12; + } + insn32(0x91000000 | ($rd << 0) | ($rn << 5) | ($i << 10) | ($sh << 22)); +} + sub write_sub_rrr($$$) { my ($rd, $rn, $rm) = @_; @@ -477,33 +495,35 @@ sub write_random_aarch64_svedata() # Load SVE registers my $align = 16; my $vq = 16; # quadwords per vector - my $datalen = (32 * $vq * 16) + $align; - - write_pc_adr(0, (3 * 4) + ($align - 1)); # insn 1 - write_align_reg(0, $align); # insn 2 - write_jump_fwd($datalen); # insn 3 + my $veclen = 32 * $vq * 16; + my $predlen = 16 * $vq * 2; + my $datalen = $veclen + $predlen; - # align safety - for (my $i = 0; $i < ($align / 4); $i++) { - # align with nops - insn32(0xd503201f); - }; + write_pc_adr(0, 2 * 4); # insn 1 + write_jump_fwd($datalen); # insn 2 for (my $rt = 0; $rt <= 31; $rt++) { for (my $q = 0; $q < $vq; $q++) { write_random_fpreg_var(4); # quad } } - - # Reset all the predicate registers to all true - for (my $p = 0; $p < 16; $p++) { - insn32(0x2518e3e0 | $p); + for (my $rt = 0; $rt <= 15; $rt++) { + for (my $q = 0; $q < $vq; $q++) { + insn16(rand(0xffff)); + } } for (my $rt = 0; $rt <= 31; $rt++) { # ldr z$rt, [x0, #$rt, mul vl] insn32(0x85804000 + $rt + (($rt & 7) << 10) + (($rt & 0x18) << 13)); } + + write_add_rri(0, 0, $veclen); + + for (my $rt = 0; $rt <= 15; $rt++) { + # ldr p$rt, [x0, #$pt, mul vl] + insn32(0x85800000 + $rt + (($rt & 7) << 10) + (($rt & 0x18) << 13)); + } } sub write_random_aarch64_regdata($$) From patchwork Wed Jun 13 12:55:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138463 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp694613lji; Wed, 13 Jun 2018 06:03:30 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKfnO/Vwgs12vRn2AEUOdBNQagVo+xeZ7BRB0eu8VK1l/w6nqXEvuRYSWVs+WIiZeK09rHm X-Received: by 2002:ac8:2ee5:: with SMTP id i34-v6mr4191337qta.390.1528895010123; Wed, 13 Jun 2018 06:03:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528895010; cv=none; d=google.com; s=arc-20160816; b=BTbGaDJqedGhNi3VHzXxHhE7aZYkx9nFEODuo6FaQE1H+GuQNHZEPi4A8W9cvbksCI yHatstNcu8wEc5PpNKc/LkYydb6PUQhZzPBYbw++ypyVlDdd84B2G9KthHfpXo6Rdb3d Gm3xsvDmTbMXhkMsL6J3lWndrYTcmuZS07x8zqLgVmnjyk0rzAqsYDZogkXQnvuZ9n5B 2yckxAXrifoPOf/WzCP81X8TEAZYpe+7JoK7rpQcxu1XzvVnPy4z6p7hv0WHueDPlkhG L9V6tWMShzy71Pf43NbYMVUgZLWc2+3zAnfmYcPHCa7BegMV2t8DES6z8yvUqs63TfMa HLtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=yGIXH0KQMm00dKEL2Etwd2IPZwUNEDVV+bNKLpa67ZE=; b=di78c/tqjKXIBS7z5kDa3kOYgaHGn6A4qDtZ1HSEyPxNmUDMlkcLa8hWx3Zgg5a7Re zvDIi7VtAD0aeiMJXOkMXrURQrQqQcq7TtDqShEq0FNcZ7duiVo3wEtoc/hq9CtMwpc9 P7OlRNcHe02IOX7SCfiphiNoksznWUXh7MkMTx0hesoCUGrjp5YKYQu/vNM3g8HTWQ1O MB06a3zwk5oIp6EnJxM4Hi/RsdQk4oyvAHkiAsoOluLPXXdz1lh6zTDUiA5fku7xfk0P xK502FuSfT4JY3Z5gfNRnsZ80FS+VmIpzjnyirfYMvkv8wwbIpfuN6G/CkUQd0FLWG6i liag== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=e8GmGeWV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::234 Subject: [Qemu-devel] [RISU PATCH v3 09/22] risugen: use fewer insns for aarch64 immediate load X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Alex Bennée --- risugen_arm.pm | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/risugen_arm.pm b/risugen_arm.pm index 83e521d..485e94e 100644 --- a/risugen_arm.pm +++ b/risugen_arm.pm @@ -261,15 +261,13 @@ sub write_mov_rr($$) sub write_mov_ri16($$$) { - # Write 16 bits of immediate to register, using either MOVW or MOVT + # Write 16 bits of immediate to register. my ($rd, $imm, $is_movt) = @_; - die "write_mov_ri16: immediate $imm out of range\n" if (($imm & 0xffff0000) != 0); - if ($is_aarch64) { - # Use MOVZ 0x52800000. is_movt means MOVK of high bits */ - insn32(0xd2800000 | ($is_movt << 29) | ($is_movt ? 16 << 17 : 0) | ($imm << 5) | $rd); + die "write_mov_ri16: invalid operation for this arch.\n" if ($is_aarch64); + die "write_mov_ri16: immediate $imm out of range\n" if (($imm & 0xffff0000) != 0); - } elsif ($is_thumb) { + if ($is_thumb) { # enc T3 my ($imm4, $i, $imm3, $imm8) = (($imm & 0xf000) >> 12, ($imm & 0x0800) >> 11, @@ -287,16 +285,24 @@ sub write_mov_ri16($$$) sub write_mov_ri($$) { - # We always use a MOVW/MOVT pair, for simplicity. - # on aarch64, we use a MOVZ/MOVK pair. my ($rd, $imm) = @_; - write_mov_ri16($rd, ($imm & 0xffff), 0); my $highhalf = ($imm >> 16) & 0xffff; - write_mov_ri16($rd, $highhalf, 1) if $highhalf; - if ($is_aarch64 && $imm < 0) { - # sign extend to allow small negative imm constants - write_sxt32($rd, $rd); + if ($is_aarch64) { + if ($imm < 0) { + # MOVN + insn32(0x92800000 | ((~$imm & 0xffff) << 5) | $rd); + # MOVK, LSL 16 + insn32(0xf2a00000 | ($highhalf << 5) | $rd) if $highhalf != 0xffff; + } else { + # MOVZ + insn32(0x52800000 | (($imm & 0xffff) << 5) | $rd); + # MOVK, LSL 16 + insn32(0xf2a00000 | ($highhalf << 5) | $rd) if $highhalf != 0; + } + } else { + write_mov_ri16($rd, ($imm & 0xffff), 0); + write_mov_ri16($rd, $highhalf, 1) if $highhalf; } } From patchwork Wed Jun 13 12:55:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138467 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp699001lji; Wed, 13 Jun 2018 06:06:29 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIQRnPgCknOLs+w/sfS+NP5ksiO1ejIMikIwp0u7ZJiTehLjG0g5C6kri3MSG3ZApf5tuFA X-Received: by 2002:a0c:93a2:: with SMTP id f31-v6mr4270812qvf.151.1528895189087; Wed, 13 Jun 2018 06:06:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528895189; cv=none; d=google.com; s=arc-20160816; b=nmz3n2yrGATEdsX8obVDm13jp5zpvcvGaVEvZCUb0qrGvksQLdHr0SAX51y831HNud vEkOOBgfB/P+jHilxUESTGyTCyKI+zj2LMiybn1A5MenBB14WlindMMMILBkiGQFyVnF KQJ0ZMJG4XfFD2xCeC32LLgZOuqKeilcwmNm8m1KWhKYavVL9arkzFw5lKZqG687O1Jm 3xBzmJqOFFgLum43Z6prFf12q5BdeHc3UbEooXna7zg6piPpfG0N12JMBsiLFl1RGHeW t4cWgKLzCN4HXwx6f20s2wGYsh4ZHbJ3q2shZIHPeFTCn/NcWab0/T1Rzmonm4n0nkRl xD4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=eUY/neGXdk4S8JqLBaT3aKaFiB1DXFXQWHVnmZJwCZM=; b=SsNLT6ogF01W28nRdfeoGTdB2tbkqBgFjfLT/7K3sIfGZikYAaZ0nF9lF+CCLynV18 GFu6GAcNRp6PARC25/3ETB1uUDrJRwfQNr0/R/RrBmKk8Hub5Tj+QAVY6D30z06KEIgX FzNSNxeJ1o6/KusUwAygnVXNhKyAknASq8nnQUnnhx+1W/rWyhZ3JDNzvSbGNX5jbnxb 0rCKJxlWbbv0WIakVAT+1CeB7i632J6HISpKyz6OxZrAj9aOZWAH9PABr0i0/Y+ydnWi e99nfoy85wAUc/eCbXpzQQw5VXxC8SHN/6DuyJrdyDMKER0Bcse/BOindqntP/vAZKAU qc/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NWF1PUaX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [RISU PATCH v3 10/22] risugen: add reg_plus_imm_pl and reg_plus_imm_vl address helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Alex Bennée --- risugen_arm.pm | 126 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) -- 2.17.1 diff --git a/risugen_arm.pm b/risugen_arm.pm index 485e94e..696bf5f 100644 --- a/risugen_arm.pm +++ b/risugen_arm.pm @@ -306,6 +306,52 @@ sub write_mov_ri($$) } } +sub write_addpl_rri($$$) +{ + my ($rd, $rn, $imm) = @_; + die "write_addpl: invalid operation for this arch.\n" if (!$is_aarch64); + + insn32(0x04605000 | ($rn << 16) | (($imm & 0x3f) << 5) | $rd); +} + +sub write_addvl_rri($$$) +{ + my ($rd, $rn, $imm) = @_; + die "write_addvl: invalid operation for this arch.\n" if (!$is_aarch64); + + insn32(0x04205000 | ($rn << 16) | (($imm & 0x3f) << 5) | $rd); +} + +sub write_rdvl_ri($$) +{ + my ($rd, $imm) = @_; + die "write_rdvl: invalid operation for this arch.\n" if (!$is_aarch64); + + insn32(0x04bf5000 | (($imm & 0x3f) << 5) | $rd); +} + +sub write_madd_rrrr($$$$) +{ + my ($rd, $rn, $rm, $ra) = @_; + die "write_madd: invalid operation for this arch.\n" if (!$is_aarch64); + + insn32(0x9b000000 | ($rm << 16) | ($ra << 10) | ($rn << 5) | $rd); +} + +sub write_msub_rrrr($$$$) +{ + my ($rd, $rn, $rm, $ra) = @_; + die "write_msub: invalid operation for this arch.\n" if (!$is_aarch64); + + insn32(0x9b008000 | ($rm << 16) | ($ra << 10) | ($rn << 5) | $rd); +} + +sub write_mul_rrr($$$) +{ + my ($rd, $rn, $rm) = @_; + write_madd_rrrr($rd, $rn, $rm, 31); +} + # write random fp value of passed precision (1=single, 2=double, 4=quad) sub write_random_fpreg_var($) { @@ -767,6 +813,86 @@ sub reg_plus_imm($$@) return $base; } +sub reg_plus_imm_pl($$@) +{ + # Handle reg + immediate addressing mode + my ($base, $imm, @trashed) = @_; + if ($imm == 0) { + return reg($base, @trashed); + } + write_get_offset(); + + # Now r0 is the address we want to do the access to, + # so set the basereg by doing the inverse of the + # addressing mode calculation, ie base = r0 - imm + # + # Note that addpl has a 6-bit immediate, but ldr has a 9-bit + # immediate, so we need to be able to support larger immediates. + + if (-$imm >= -32 && -$imm <= 31) { + write_addpl_rri($base, 0, -$imm); + } else { + # We borrow r1 and r2 as a temporaries (not a problem + # as long as we don't leave anything in a register + # which depends on the location of the memory block) + write_mov_ri(1, 0); + write_mov_ri(2, $imm); + write_addpl_rri(1, 1, 1); + write_msub_rrrr($base, 1, 2, 0); + } + if (grep $_ == $base, @trashed) { + return -1; + } + return $base; +} + +sub reg_plus_imm_vl($$@) +{ + # The usual address formulation is + # elements = VL DIV esize + # mbytes = msize DIV 8 + # addr = base + imm * elements * mbytes + # Here we compute + # scale = log2(esize / msize) + # base + (imm * VL) >> scale + my ($base, $imm, $scale, @trashed) = @_; + if ($imm == 0) { + return reg($base, @trashed); + } + write_get_offset(); + + # Now r0 is the address we want to do the access to, + # so set the basereg by doing the inverse of the + # addressing mode calculation, ie base = r0 - imm + # + # Note that rdvl/addvl have a 6-bit immediate, but ldr has a 9-bit + # immediate, so we need to be able to support larger immediates. + + use integer; + my $mul = 1 << $scale; + my $imm_div = $imm / $mul; + + if ($imm == $imm_div * $mul && -$imm_div >= -32 && -$imm_div <= 31) { + write_addvl_rri($base, 0, -$imm_div); + } elsif ($imm >= -32 && $imm <= 31) { + write_rdvl_ri(1, $imm); + write_sub_rrrs($base, 0, 1, $SHIFT_ASR, $scale); + } else { + write_rdvl_ri(1, 1); + write_mov_ri(2, $imm); + if ($scale == 0) { + write_msub_rrrr($base, 1, 2, 0); + } else { + write_mul_rrr(1, 1, 2); + write_sub_rrrs($base, 0, 1, $SHIFT_ASR, $scale); + } + } + if (grep $_ == $base, @trashed) { + return -1; + } + return $base; +} + sub reg_minus_imm($$@) { my ($base, $imm, @trashed) = @_; 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [RISU PATCH v3 11/22] risugen: add dtype_msz address helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée --- risugen_arm.pm | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 diff --git a/risugen_arm.pm b/risugen_arm.pm index 696bf5f..8d423b1 100644 --- a/risugen_arm.pm +++ b/risugen_arm.pm @@ -765,6 +765,15 @@ sub write_get_offset() write_risuop($OP_GETMEMBLOCK); } +# Return the log2 of the memory size of an operation described by dtype. +sub dtype_msz($) +{ + my ($dtype) = @_; + my $dth = $dtype >> 2; + my $dtl = $dtype & 3; + return $dtl >= $dth ? $dth : 3 - $dth; +} + sub reg($@) { my ($base, @trashed) = @_; From patchwork Wed Jun 13 12:55:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138476 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp721610lji; Wed, 13 Jun 2018 06:25:19 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKJAOxS9DcE5C8U5YBNlaxxkJ6LxJrtxYiQnv8WR31/UHsHsrWhP7oeBhic+1HG1Gno5fL0 X-Received: by 2002:ae9:c00f:: with SMTP id u15-v6mr4261028qkk.383.1528896319799; Wed, 13 Jun 2018 06:25:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528896319; cv=none; d=google.com; s=arc-20160816; b=YAVHtVT/cWPdzyb8O+Gd21MMAYm4LmmaALWj86TpM3na3Z0TbtfhFMrVIU6Uh0NVAU k+kszx/yTpYb23z9fbBwZJT6jFBW0iwrfNwvAhjdxNb56oVyBL898N4aG8LvPYh+KmRp n8sKOko2WJ5CkgBOp5AiUamWIJqB+nkO1bZZYRaMpr3Kd/yui9HgzVFpLgE/fQwOv7oF RIKGRCvdb33622RVp0B9DVbw08VaiAX8spRxARIFW7jCiMO7TjiTR5CDtaqLnAPTe0t1 hXAOACNFdj8bwLbrzyIcUY7V1u3V+o8mlKTfyxLdHKiS5twHuhIZzz5c56gLJ12HkugR jc3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=/IZQ4p0hwe86+xUxCaKvDsHzWjVNlBH8FOK7w9lXmkc=; b=cRI1c/Q4LgP2KMdC32mBGshZ7NeLxx68x/bdNM2VLhQnWPlmJ1zTOvKOqlZmZ8Vv6d usZL65g5kpfplAWlEDtE2GVuJvYvW7o+dD8DSUQF5fqLB83j1JaMc6jS1wZVGSkmhBCC VH3botuM5uFxT14pth6F88IXiJqiu7pD7eP4HWLbdUjdQKAwvG8PIvG0XCwoookN0y0y GxXETuvfo6Ly87/BUqgwB0mNbR0a/GdYwYQ80KmhIObNtyvrIF6FfvyUP96ugFThb3P6 yrUU2I5sTxC4nkGKtkExqesuoV2exGZoTdgdvGff6uNlwyoNJZzSLkDFjtqv/5T53Wws wGPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BVkbTQwi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::22a Subject: [Qemu-devel] [RISU PATCH v3 12/22] contrib/generate_all.sh: allow passing of arguments to risugen X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows us to use any new risugen options when generating all our test patterns. Signed-off-by: Alex Bennée --- contrib/generate_all.sh | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/contrib/generate_all.sh b/contrib/generate_all.sh index 1e6b847..651cb23 100755 --- a/contrib/generate_all.sh +++ b/contrib/generate_all.sh @@ -12,11 +12,11 @@ # Alex Bennée - initial implementation # # Usage: -# ./contrib/generate_all.sh +# ./contrib/generate_all.sh -- risugen args set -e -USAGE="Usage: `basename $0` [-h] [-n x] " +USAGE="Usage: `basename $0` [-h] [-n x] -- [risugen args]" SPLIT=4 RISUGEN=$(CDPATH= cd -- "$(dirname -- "$0")/.." && pwd -P)/risugen @@ -41,18 +41,24 @@ done # Remove the switches we parsed above. shift `expr $OPTIND - 1` -while [ $# -ne 0 ]; do +# Parse up to and including any -- +RISUGEN_ARGS="" +while [ $# -ne 0 ] && [ -z "$RISUGEN_ARGS" ]; do if [ -f $1 ]; then RISU_FILE=$1; elif [ -d $1 ]; then TARGET_DIR=$1; + elif [ "$1" = "--" ]; then + RISUGEN_ARGS=$1 elif [ ! -e $1 ]; then TARGET_DIR=$1 fi shift done +# anything left is for RISUGEN +RISUGEN_ARGS=$@ if test -z "${RISUGEN}" || test ! -x "${RISUGEN}"; then echo "Couldn't find risugen (${RISUGEN})" @@ -90,7 +96,7 @@ while test $# -gt 0 ; do fi done I_FILE="${I_FILE}_INC.risu.bin" - CMD="${RISUGEN} ${INSN_PATTERNS} ${RISU_FILE} ${I_FILE}" + CMD="${RISUGEN} ${RISUGEN_ARGS} ${INSN_PATTERNS} ${RISU_FILE} ${I_FILE}" echo "Running: $CMD" $CMD done From patchwork Wed Jun 13 12:55:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138477 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp723120lji; Wed, 13 Jun 2018 06:26:39 -0700 (PDT) X-Google-Smtp-Source: ADUXVKK4rcJ3Z9regQuSEck3pxgTuk+Kte7b9zz0i9nyN8bvehPCs+28x5vD83GTZngq9peyLJMS X-Received: by 2002:a37:4c47:: with SMTP id z68-v6mr4140099qka.233.1528896399340; Wed, 13 Jun 2018 06:26:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528896399; cv=none; d=google.com; s=arc-20160816; b=PxT0OhdshOrwwn4lVjmkKq5COOsygLndvJx38AnEF7vcrTA8d6NalnEgrweB3qjLrt AE4XPvDQOmRynyta8kwJuU/h5CUpLDcmqsq8QwSypYbyzd394UIt/erfEvqA1LAMhBXZ s1cdWEdNHht5EMPumeFEnuqPKJkpxZRlak8kz1+oxxa52eOBmPyVO7BIhOSDPpMxvUoH 657dcNxQS3ybG5sNvmvPOOIs9JCn/YaouZVUFjw9zRh5jPMSfjM47Fl7WWHevOWSqQip YTfhmoyxim0pfF0ylHswrlHtv+wc6bD8HPdI9htZAaIItD8v4XmXHrt/VOV4BF8cSdKA WD7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=jjUldyaKeKYrcB+Cm5ncCoScFYt4ewD1ApH+rdYho6Q=; b=uaVRbEAKR8XqB+K+pA5LneGBeGibwNQ6PClXgsdXVRK08R4XG07MntGIXmxFCquJJL MX5ZwwPdiZjRSrQJR4kd9/XJfo+qvs0jL6Nv50dIzcLGYmDiE+DyzIZavD7RNRztdKqy WOCERAKZ94X6NDoe5RTFS9HPmqkU4IHPCzjo4tqaAkv6FoTDDhggHx7QBX6Yx7k3rrAb A1whqVoQaCSW9DwWWm9SkhhZ+uCbCb9yow1bU3Juw8mmyD8ibm0iDdFeAkLFaCh1uB/z Auyh2Wc1ckl2QghlMCSKSgiCINABgMw+CY41e19cYOALXD7wF89+/9hvoVLpAqOAkpKh II4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UnL5ND9L; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::22e Subject: [Qemu-devel] [RISU PATCH v3 13/22] risu: move optional args to each architecture X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The key variables here are: *arch_long_opts and *arch_extra_help. If they are not NULL then we concatenate the extra options to appropriate structure to enable the support. Adding architecture short options is not supported. This also includes moving the ARM specific test_fp_exc/test-fp-exc into ARM specific code. Signed-off-by: Alex Bennée --- v2 - better concatenation of default and extra opts --- risu.c | 29 +++++++++++++++++++++++++---- risu.h | 6 ++++-- risu_reginfo_aarch64.c | 3 +++ risu_reginfo_arm.c | 11 +++++++++++ risu_reginfo_m68k.c | 3 +++ risu_reginfo_ppc64.c | 3 +++ 6 files changed, 49 insertions(+), 6 deletions(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/risu.c b/risu.c index c684c90..18de351 100644 --- a/risu.c +++ b/risu.c @@ -46,8 +46,7 @@ gzFile gz_trace_file; sigjmp_buf jmpbuf; -/* Should we test for FP exception status bits? */ -int test_fp_exc; +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) /* Master functions */ @@ -283,6 +282,9 @@ void usage(void) fprintf(stderr, " -p, --port=PORT Specify the port to connect to/listen on " "(default 9191)\n"); + if (arch_extra_help) { + fprintf(stderr, "%s", arch_extra_help); + } } struct option * setup_options(char **short_opts) @@ -293,12 +295,31 @@ struct option * setup_options(char **short_opts) {"host", required_argument, 0, 'h'}, {"port", required_argument, 0, 'p'}, {"trace", required_argument, 0, 't'}, - {"test-fp-exc", no_argument, &test_fp_exc, 1}, {0, 0, 0, 0} }; + struct option *lopts = &default_longopts[0]; *short_opts = "h:p:t:"; - return default_longopts; + + if (arch_long_opts) { + const size_t osize = sizeof(struct option); + const int default_count = ARRAY_SIZE(default_longopts); + struct option *dptr; + int extra_count = 0; + + /* count additional opts */ + dptr = arch_long_opts; + do {} while (dptr[extra_count++].name); + + lopts = calloc(default_count + extra_count, osize); + + /* Copy default opts + extra opts */ + memcpy(lopts, default_longopts, default_count * osize); + dptr = &lopts[default_count - 1]; + memcpy(dptr, arch_long_opts, extra_count * osize); + } + + return lopts; } int main(int argc, char **argv) diff --git a/risu.h b/risu.h index 1c8ecee..89811f4 100644 --- a/risu.h +++ b/risu.h @@ -17,6 +17,10 @@ #include #include +/* Extra option processing for architectures */ +extern void *arch_long_opts; +extern char *arch_extra_help; + /* GCC computed include to pull in the correct risu_reginfo_*.h for * the architecture. */ @@ -36,8 +40,6 @@ void send_response_byte(int sock, int resp); extern uintptr_t image_start_address; extern void *memblock; -extern int test_fp_exc; - /* Ops code under test can request from risu: */ #define OP_COMPARE 0 #define OP_TESTEND 1 diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 3bb4339..ab12270 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -18,6 +18,9 @@ #include "risu.h" #include "risu_reginfo_aarch64.h" +void *arch_long_opts; +char *arch_extra_help; + /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) { diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c index 6b9ee7b..5acad02 100644 --- a/risu_reginfo_arm.c +++ b/risu_reginfo_arm.c @@ -13,12 +13,23 @@ #include #include #include +#include #include "risu.h" #include "risu_reginfo_arm.h" extern int insnsize(ucontext_t *uc); +/* Should we test for FP exception status bits? */ +static int test_fp_exc; +static struct option extra_opts[] = { + {"test-fp-exc", no_argument, &test_fp_exc, 1}, + {0, 0, 0, 0} +}; + +void *arch_long_opts = &extra_opts[0]; +char *arch_extra_help = " --test-fp-exc Check FP exception bits when comparing\n"; + static void reginfo_init_vfp(struct reginfo *ri, ucontext_t *uc) { /* Read VFP registers. These live in uc->uc_regspace, which is diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c index 4ff0aa8..d429502 100644 --- a/risu_reginfo_m68k.c +++ b/risu_reginfo_m68k.c @@ -14,6 +14,9 @@ #include "risu.h" #include "risu_reginfo_m68k.h" +void *arch_long_opts; +char *arch_extra_help; + /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) { diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 5f33648..395111c 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -22,6 +22,9 @@ #define XER 37 #define CCR 38 +void *arch_long_opts; +char *arch_extra_help; + /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) { From patchwork Wed Jun 13 12:55:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138468 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp702253lji; Wed, 13 Jun 2018 06:08:57 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKEM06kg02ohNHEU3Q0WK3MBvbBJg8O5xcJvtdmkSRgxk/EneHTkwGlzuy6CAy2S9dP1cd4 X-Received: by 2002:a0c:bca9:: with SMTP id l41-v6mr4224720qvg.178.1528895337542; Wed, 13 Jun 2018 06:08:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528895337; cv=none; d=google.com; s=arc-20160816; b=hyW4khL57F4hOpmLg+CoNkafTTFOKr8s1H5pR9CkiiKbQVCom9JqIpKZn2IC41WTo+ i3/wl072hCq2efZyC1AqCt+ty5MhU9+hrU7RFxq36A3ejyEUY5hvhhl5uhlFeoax9+Sk r5OLrPQN8sWsjmAH98R5ZLvgj3q4p9Zx6yq7ywfV1x+uzqWRdjOOV6NuDPVh0OT6OuPE ChI1YMzceeWSKD/xuDhchHQ9YGRvOkUDzCNSuALZl0fAEy46+b4/e8KGGoosToc+BKOw GFX0sSfZE3eyel4NeYhA+nX8GMqVx0BPrcHQcbSBlWMHL4CmvncbZ96fF19rGNgSUUb8 c/fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Bp/1YbPML67ffji3kuZga7TLev+DhxX9wc1+8T4FSYo=; b=qAc+fsssLL9EfhrnNaVoLfg+1JBgm673ZBRDwGugvk5h8rGWkB4AJZuJ7Py9MJPj5j /ANwXyX+R2Sq7gA3Arte1TUlSlfMSX0BsWyNwpD5Fkx/ztLxkCsJcRb5wrtF4FLHM4k8 O48pOSmLsSMShtwy48fetD/kI8dLhpnOi2wCJq84/oqPt8fUL+HZxyn6z5/fTV2aOvtz MjQ8v7PzZrt/0GJ9RowizXqMddvpcR2m4xERhzOLtxP0K+pg138SFETjyKA9ZagSohaN Vv33C8ZzV+HjhFmS8ovBeedzxatogynBr+88PAjkSRkyR4Rs8z0+ObARBxg0sByLroUL ebsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ECj7tu4f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::236 Subject: [Qemu-devel] [RISU PATCH v3 14/22] risu: add process_arch_opt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Allows the backend to do more that just set a flag when it comes to processing options. Signed-off-by: Richard Henderson [AJB: tweaked order, added stdlib includes] Signed-off-by: Alex Bennée --- risu.c | 33 +++++++++++---------------------- risu.h | 7 +++++-- risu_reginfo_aarch64.c | 10 ++++++++-- risu_reginfo_arm.c | 14 ++++++++++---- risu_reginfo_m68k.c | 10 ++++++++-- risu_reginfo_ppc64.c | 10 ++++++++-- 6 files changed, 50 insertions(+), 34 deletions(-) -- 2.17.1 diff --git a/risu.c b/risu.c index 18de351..01525d2 100644 --- a/risu.c +++ b/risu.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -27,7 +26,6 @@ #include #include "config.h" - #include "risu.h" void *memblock; @@ -287,7 +285,7 @@ void usage(void) } } -struct option * setup_options(char **short_opts) +static struct option * setup_options(char **short_opts) { static struct option default_longopts[] = { {"help", no_argument, 0, '?'}, @@ -303,20 +301,19 @@ struct option * setup_options(char **short_opts) if (arch_long_opts) { const size_t osize = sizeof(struct option); - const int default_count = ARRAY_SIZE(default_longopts); - struct option *dptr; - int extra_count = 0; + const int default_count = ARRAY_SIZE(default_longopts) - 1; + int arch_count; /* count additional opts */ - dptr = arch_long_opts; - do {} while (dptr[extra_count++].name); + for (arch_count = 0; arch_long_opts[arch_count].name; arch_count++) { + continue; + } - lopts = calloc(default_count + extra_count, osize); + lopts = calloc(default_count + arch_count + 1, osize); /* Copy default opts + extra opts */ memcpy(lopts, default_longopts, default_count * osize); - dptr = &lopts[default_count - 1]; - memcpy(dptr, arch_long_opts, extra_count * osize); + memcpy(lopts + default_count, arch_long_opts, arch_count * osize); } return lopts; @@ -343,34 +340,26 @@ int main(int argc, char **argv) switch (c) { case 0: - { /* flag set by getopt_long, do nothing */ break; - } case 't': - { trace_fn = optarg; trace = 1; break; - } case 'h': - { hostname = optarg; break; - } case 'p': - { /* FIXME err handling */ port = strtol(optarg, 0, 10); break; - } case '?': - { usage(); exit(1); - } default: - abort(); + assert(c >= FIRST_ARCH_OPT); + process_arch_opt(c, optarg); + break; } } diff --git a/risu.h b/risu.h index 89811f4..48c50d9 100644 --- a/risu.h +++ b/risu.h @@ -16,10 +16,13 @@ #include #include #include +#include /* Extra option processing for architectures */ -extern void *arch_long_opts; -extern char *arch_extra_help; +extern const struct option * const arch_long_opts; +extern const char * const arch_extra_help; +void process_arch_opt(int opt, const char *arg); +#define FIRST_ARCH_OPT 0x100 /* GCC computed include to pull in the correct risu_reginfo_*.h for * the architecture. diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index ab12270..c270e0b 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -14,12 +14,18 @@ #include #include #include /* for FPSIMD_MAGIC */ +#include #include "risu.h" #include "risu_reginfo_aarch64.h" -void *arch_long_opts; -char *arch_extra_help; +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c index 5acad02..12ad0ef 100644 --- a/risu_reginfo_arm.c +++ b/risu_reginfo_arm.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include "risu.h" #include "risu_reginfo_arm.h" @@ -22,13 +22,19 @@ extern int insnsize(ucontext_t *uc); /* Should we test for FP exception status bits? */ static int test_fp_exc; -static struct option extra_opts[] = { +static const struct option extra_opts[] = { {"test-fp-exc", no_argument, &test_fp_exc, 1}, {0, 0, 0, 0} }; -void *arch_long_opts = &extra_opts[0]; -char *arch_extra_help = " --test-fp-exc Check FP exception bits when comparing\n"; +const struct option * const arch_long_opts = &extra_opts[0]; +const char * const arch_extra_help = + " --test-fp-exc Check FP exception bits when comparing\n"; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} static void reginfo_init_vfp(struct reginfo *ri, ucontext_t *uc) { diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c index d429502..7a1c5a9 100644 --- a/risu_reginfo_m68k.c +++ b/risu_reginfo_m68k.c @@ -10,12 +10,18 @@ #include #include #include +#include #include "risu.h" #include "risu_reginfo_m68k.h" -void *arch_long_opts; -char *arch_extra_help; +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 395111c..4b70460 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "risu.h" #include "risu_reginfo_ppc64.h" @@ -22,8 +23,13 @@ #define XER 37 #define CCR 38 -void *arch_long_opts; -char *arch_extra_help; +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) From patchwork Wed Jun 13 12:55:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138464 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp695608lji; Wed, 13 Jun 2018 06:04:08 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKwbfa7yEMoPYefB0SDzF1rd43AiS5+S+GIHiILO636D1QuZWlGUb+psAsTRchD16610kv0 X-Received: by 2002:a37:5687:: with SMTP id k129-v6mr4339812qkb.163.1528895048090; Wed, 13 Jun 2018 06:04:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528895048; cv=none; d=google.com; s=arc-20160816; b=ypjC5+wMNfE7xh1jUgMSp1LF6cLdt7QmcVCUfOXLEf7FDb2S1XJIPBgbBlFDRoaFGn OsjMrsGm09rOEIXRpIfk0uWsVdFiDHdXmGj4l454GH85tRHPfmdkOKLuH4+CVlnAEam6 G2XnDmGXzSTZegXBNHZAONII8GjeWZMAnM3aeCrLK+iAG1+kNXBCpdaawqDGkm12vsFU qxJuA4OkJrsmEj2M4va6zOKptZ6Bzb58EIT1UKkUZODan15glmO5WCTwjVorvkz8zFRi +unluMbEQDvE3deuHq0IiBuPH2S4VLOCl0LoRXhLryQgxtgeBWA1hEYF6pVAm256cBGr zP/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=8h3p2bJmRYKdvQUyRXUZ12mtlfZfXctrDwETVGrxqLc=; b=qb/Sexx08sQk7GQY5gfGh1YAdNYg6izwNBeJfd0qjfm7XmJ3J+rmm4wh2RM6HwJ3MW 1DeNr/BiqJq1pVWij18CsbEW6ri4cQRYuZxFZTLlFrD16vpngTIkfoXZDSpxQZ1amKMC cWoA9J2ZbwaRZ+xDNQPJlwiJzKgVpMgHb/uNGY+h3CA5pExk8XCcoV4OrJ+es+LP9KOM DuKrYRBzJSc/xCVxc6f/YROWoEndReXYb3SsvgzdZVw4/JHMsBkZQMnDnsuOdBMiERzk DDnkmxN1EBPxfyaYMkJeepteREpveIgi8oyZULsILzSEe4zb372RyjaeDbRHxiwBjXoP JS9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kPxj2ymZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [RISU PATCH v3 15/22] risu_reginfo_aarch64: drop stray ; X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- risu_reginfo_aarch64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index c270e0b..34dd9af 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -66,7 +66,7 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) for (i = 0; i < 32; i++) { ri->vregs[i] = fp->vregs[i]; } -}; +} /* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2) From patchwork Wed Jun 13 12:55:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138471 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp706481lji; Wed, 13 Jun 2018 06:12:23 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLJ/JZGIY57f9IPOEWMaD9FUroPSfQRGWO7S/v1E7BDhULIm4KoDDpRhPvxFRmVCC07I2Hw X-Received: by 2002:a0c:e74c:: with SMTP id g12-v6mr4297676qvn.203.1528895543505; Wed, 13 Jun 2018 06:12:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528895543; cv=none; d=google.com; s=arc-20160816; b=fUkVsZwXKF2kYhnSzBdnOb8rm8qHHhUvSdAgmmvY7AeB0qNhBafzwNZNNwkDci8O+E 3dnf0TZkTxFDGMZ5sK6ZV8ptes6pR4qlWPuMVovrk8RhFj9aUJXfMKYf5VkYPqXJWtYO v59odz2qIZ8nd3+nYEERvnlGGL1TC2omAL91dvid4c8oEuWE2YZpKD2koh2FEaJCHFpq fX3Xtu6WaK/N1KUW0dKeWOfCb3gGVcMhMvP9gyR6oWBdcpiFvg7slUIz65A+mN0bgz+r TCQEcwZkkM4nRxl4n2C0fM/ou3dylN9s9y4NDwplkUL98VQ+yHUWMFOtPy9U8/QW0SLj T5SQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=lbCPrENDXodqYySnVETQzfGuSpf+E0XwrnRGSzM1nmE=; b=etHJZT3eb2JWsFO+DvmrbiOMdj5fABCdz9ymTqM7XB9Ej03VktHde8whjiHDnhL6zo 72fj8p6BH3bThQHE21bKo1/LXV9uK0GS7jSkP9YkMyTBbTnZ3xV8jwZS/E4WwPdBF/36 dh5bfPssSJoYZ2wNP3li35eCiLvY/vENTbyPfwnaRFSjq2qg4ti33cR2yfCnvCkepXlQ NnnyWkUIawgyc0EMDZRU0738d+k67iv2ksjuQhG8C/sI+hb68c6qD3JatQtF5EI3KXak V75R/NDqVA2ZgtoVgH6/NC2wru1tNK7DC6nWcZNqRSvigsSwQfN1mbzdiR/s0xDOL7cc dWcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IufAp4Ap; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::235 Subject: [Qemu-devel] [RISU PATCH v3 16/22] risu_reginfo_aarch64: unionify VFP regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is preparation for the SVE work as we won't want to be carrying around both VFP and SVE registers at the same time as they overlap. Signed-off-by: Alex Bennée --- risu_reginfo_aarch64.c | 16 ++++++++-------- risu_reginfo_aarch64.h | 9 ++++++++- 2 files changed, 16 insertions(+), 9 deletions(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 34dd9af..62a5599 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -64,7 +64,7 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) ri->fpcr = fp->fpcr; for (i = 0; i < 32; i++) { - ri->vregs[i] = fp->vregs[i]; + ri->simd.vregs[i] = fp->vregs[i]; } } @@ -92,8 +92,8 @@ int reginfo_dump(struct reginfo *ri, FILE * f) for (i = 0; i < 32; i++) { fprintf(f, " V%2d : %016" PRIx64 "%016" PRIx64 "\n", i, - (uint64_t) (ri->vregs[i] >> 64), - (uint64_t) (ri->vregs[i] & 0xffffffffffffffff)); + (uint64_t) (ri->simd.vregs[i] >> 64), + (uint64_t) (ri->simd.vregs[i] & 0xffffffffffffffff)); } return !ferror(f); @@ -138,14 +138,14 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) } for (i = 0; i < 32; i++) { - if (m->vregs[i] != a->vregs[i]) { + if (m->simd.vregs[i] != a->simd.vregs[i]) { fprintf(f, " V%2d : " "%016" PRIx64 "%016" PRIx64 " vs " "%016" PRIx64 "%016" PRIx64 "\n", i, - (uint64_t) (m->vregs[i] >> 64), - (uint64_t) (m->vregs[i] & 0xffffffffffffffff), - (uint64_t) (a->vregs[i] >> 64), - (uint64_t) (a->vregs[i] & 0xffffffffffffffff)); + (uint64_t) (m->simd.vregs[i] >> 64), + (uint64_t) (m->simd.vregs[i] & 0xffffffffffffffff), + (uint64_t) (a->simd.vregs[i] >> 64), + (uint64_t) (a->simd.vregs[i] & 0xffffffffffffffff)); } } diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h index a05fb4e..a1c708b 100644 --- a/risu_reginfo_aarch64.h +++ b/risu_reginfo_aarch64.h @@ -13,6 +13,10 @@ #ifndef RISU_REGINFO_AARCH64_H #define RISU_REGINFO_AARCH64_H +struct simd_reginfo { + __uint128_t vregs[32]; +}; + struct reginfo { uint64_t fault_address; uint64_t regs[31]; @@ -24,7 +28,10 @@ struct reginfo { /* FP/SIMD */ uint32_t fpsr; uint32_t fpcr; - __uint128_t vregs[32]; + + union { + struct simd_reginfo simd; + }; }; #endif /* RISU_REGINFO_AARCH64_H */ From patchwork Wed Jun 13 12:55:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138465 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp698173lji; Wed, 13 Jun 2018 06:05:54 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJWrE6Dp7bEzzO7n0LLjgxnZ6gVm36pAiQGxAU3aveeArt+Ct3JT55nBdfbhk8mlKaEg+yG X-Received: by 2002:aed:3541:: with SMTP id b1-v6mr4440587qte.68.1528895154876; Wed, 13 Jun 2018 06:05:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528895154; cv=none; d=google.com; s=arc-20160816; b=erGskPY7mKRTaT8Ub0erj7eKuzS6PuufLyYpSCTKBYI2Dtztk4NmdGn/+Lfh2lRzRN bYn8Eu7mR1Vrxzg/CgU5BKF5hLMd3VmnU3zHTF04zrzdndUxGnYJPD2kjnewQnNLAUPg Fb2gnwXfe8FdxSg1SXR11WNc8KhBRPW019vYfZX3Sef5iuStS2KN6PX9mN9ShOfRpXO0 vgraXbHDv4dLX0KwgQuBvcyPAlX624keJ0PTE6aERLW0/cMscNzoGovGDpVc1HQ1xpIW btGWucd9Znc9TOrfOeIxpdRXk0Gao9x9IVrZA4EcaFuIYOPzRX2JxJ1Qc9qVQckJG/mj /UhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=HAIX9tTUSqBJuCs9MaUHymal6G4zj6ophHdsDwTVexY=; b=DJiFYvukAzFs7ataiU4ePePi6HP6qxOy/Yk1b2ip5uy8B1uQCsYzj0CTobpJ7Xwd86 tftrGDVfCBIEJHug+7ZpKe2OTAVpCpC17ft6Njc+3vw9Y9+e3/HqUVWLaNNB4CIuM3XT PCnKiKHvuOGpIwzvHcsH5gQ4bqHGmfWspYZFA8C844Ys5BB9TThJYnJuPAxqYJgLPJ+N 1CkMKyk4MNysagIFQsaU1dSwRbWQh4ccfc+ftcSitHTxRowKE1lAYhEBFYeyadGKd3XF S6k597ZmL6fVByFIIs7+rwBKs/VdLDsX9AsmhsS6HZcFOMHKWsyVRJTEAGy5xORINdDn Z2Jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hcoBddz2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::234 Subject: [Qemu-devel] [RISU PATCH v3 17/22] risu_reginfo: introduce reginfo_size() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for conditionally supporting SVE we need to be able to have different sized reginfos. This introduces reginfo_size() to abstract the size away to the code the actually knows. For aarch64 we also use this while initialising the block. Signed-off-by: Alex Bennée --- reginfo.c | 6 +++--- risu.h | 3 +++ risu_reginfo_aarch64.c | 11 ++++++++++- risu_reginfo_aarch64.h | 1 + risu_reginfo_arm.c | 5 +++++ risu_reginfo_m68k.c | 5 +++++ risu_reginfo_ppc64.c | 5 +++++ 7 files changed, 32 insertions(+), 4 deletions(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/reginfo.c b/reginfo.c index 1f55d06..dd42ae2 100644 --- a/reginfo.c +++ b/reginfo.c @@ -39,7 +39,7 @@ int send_register_info(write_fn write_fn, void *uc) switch (op) { case OP_TESTEND: - write_fn(&ri, sizeof(ri)); + write_fn(&ri, reginfo_size()); /* if we are tracing write_fn will return 0 unlike a remote end, hence we force return of 1 here */ return 1; @@ -58,7 +58,7 @@ int send_register_info(write_fn write_fn, void *uc) /* Do a simple register compare on (a) explicit request * (b) end of test (c) a non-risuop UNDEF */ - return write_fn(&ri, sizeof(ri)); + return write_fn(&ri, reginfo_size()); } return 0; } @@ -101,7 +101,7 @@ int recv_and_compare_register_info(read_fn read_fn, /* Do a simple register compare on (a) explicit request * (b) end of test (c) a non-risuop UNDEF */ - if (read_fn(&apprentice_ri, sizeof(apprentice_ri))) { + if (read_fn(&apprentice_ri, reginfo_size())) { packet_mismatch = 1; resp = 2; } else if (!reginfo_is_eq(&master_ri, &apprentice_ri)) { diff --git a/risu.h b/risu.h index 48c50d9..8d2d646 100644 --- a/risu.h +++ b/risu.h @@ -133,4 +133,7 @@ int reginfo_dump(struct reginfo *ri, FILE * f); /* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero=ok */ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f); +/* return size of reginfo */ +const int reginfo_size(void); + #endif /* RISU_H */ diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 62a5599..5da9e39 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -15,6 +15,8 @@ #include #include /* for FPSIMD_MAGIC */ #include +#include +#include #include "risu.h" #include "risu_reginfo_aarch64.h" @@ -27,6 +29,13 @@ void process_arch_opt(int opt, const char *arg) abort(); } +const int reginfo_size(void) +{ + const int size = offsetof(struct reginfo, simd.end); + assert(sizeof(struct reginfo)==size); + return size; +} + /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) { @@ -71,7 +80,7 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) /* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2) { - return memcmp(r1, r2, sizeof(*r1)) == 0; + return memcmp(r1, r2, reginfo_size()) == 0; } /* reginfo_dump: print state to a stream, returns nonzero on success */ diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h index a1c708b..ef97622 100644 --- a/risu_reginfo_aarch64.h +++ b/risu_reginfo_aarch64.h @@ -15,6 +15,7 @@ struct simd_reginfo { __uint128_t vregs[32]; + char end[0]; }; struct reginfo { diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c index 12ad0ef..3662f12 100644 --- a/risu_reginfo_arm.c +++ b/risu_reginfo_arm.c @@ -36,6 +36,11 @@ void process_arch_opt(int opt, const char *arg) abort(); } +const int reginfo_size(void) +{ + return sizeof(struct reginfo); +} + static void reginfo_init_vfp(struct reginfo *ri, ucontext_t *uc) { /* Read VFP registers. These live in uc->uc_regspace, which is diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c index 7a1c5a9..32b28c8 100644 --- a/risu_reginfo_m68k.c +++ b/risu_reginfo_m68k.c @@ -23,6 +23,11 @@ void process_arch_opt(int opt, const char *arg) abort(); } +const int reginfo_size(void) +{ + return sizeof(struct reginfo); +} + /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) { diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 4b70460..f9d2f0d 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -31,6 +31,11 @@ void process_arch_opt(int opt, const char *arg) abort(); } +const int reginfo_size(void) +{ + return sizeof(struct reginfo); +} + /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) { From patchwork Wed Jun 13 12:55:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138472 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp711722lji; Wed, 13 Jun 2018 06:16:49 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIYyp6UmCcwrafqYro514igCfqEer6ma4Ygio87pReFQAte/Qd97XNRuGMyVjQD2Zy7vAvu X-Received: by 2002:ac8:327c:: with SMTP id y57-v6mr4462738qta.14.1528895809308; Wed, 13 Jun 2018 06:16:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528895809; cv=none; d=google.com; s=arc-20160816; b=YGo7d704yTDy7CoTjehgY0wLSWZQ7oc03Xu4pa1Z6bOSAl6JQo//8hL+6Td6ClImLV CAy7uxORJZk4yoV3C1CN5PTGOQhvRCz1IE+6c0JlLFbQbQ9Uh73xQjCMDH8OZRgm8tDM ly4XJD5qha7L5M9ZtcrdYEv2qnjRrxPjpXtGCv9X4P6g8rJCsVY+JQEoBcDGjiUOdt9Z u0yl4i0xMe0Za05maLkDlZFqgdfoCfkoPxiJ6ZOyBGPkK7lmxnrYwd8+dM61WW2Sropr lxctmUevsLuxr0GNAwYrQBgCfl3r3/V9rxbP812D+YHezllnqpMi1ITXMd5eRisaNtYG DStA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=3GZt6zmPPRz/Cc8Er05snigjnuvB2tXpXhI9lbDLCgQ=; b=s8u9MfwOpDaEyZooOWBbU0UzX2B/lXATpnSCi+EKXXQoO7UcgXdIJqaQzPIUtirOrw PF1vT0xFqxL+Kb9FQ/RjEg7Gtcv3j8GbDDDXRnFjuarP+zHAUYN+xKeiXquOz2HG6Re4 UzVfIAQP6nU6EXL61D7chif/YTdcGg/QcM4rJ7j3si/Kv5zhzZALK41u5hUitfIIOUix NPIT5gexhAtDQ1Y6xPZOMDcBmFgZLleOt/k+L/CCNnfLUdU0cJb438qtVixwz2AeV+BQ 8UGf7i+/jTeimOjfMwleKLTjHMM5V3kRg6IEPJEUmKNa0OaZ4YoTPPAM/SM6QnSYHQ32 fAVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bWv0ExrI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [RISU PATCH v3 18/22] risu_reginfo_aarch64: left justify regnums and drop masks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Left justification is more pleasing to the eye than the default. We also drop the masking which isn't needed as we are casting to a smaller size anyway. This was split out of Richard's re-factoring work for SVE. Signed-off-by: Alex Bennée --- risu_reginfo_aarch64.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 5da9e39..3ccaf0e 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -90,7 +90,7 @@ int reginfo_dump(struct reginfo *ri, FILE * f) fprintf(f, " faulting insn %08x\n", ri->faulting_insn); for (i = 0; i < 31; i++) { - fprintf(f, " X%2d : %016" PRIx64 "\n", i, ri->regs[i]); + fprintf(f, " X%-2d : %016" PRIx64 "\n", i, ri->regs[i]); } fprintf(f, " sp : %016" PRIx64 "\n", ri->sp); @@ -100,9 +100,9 @@ int reginfo_dump(struct reginfo *ri, FILE * f) fprintf(f, " fpcr : %08x\n", ri->fpcr); for (i = 0; i < 32; i++) { - fprintf(f, " V%2d : %016" PRIx64 "%016" PRIx64 "\n", i, + fprintf(f, " V%-2d : %016" PRIx64 "%016" PRIx64 "\n", i, (uint64_t) (ri->simd.vregs[i] >> 64), - (uint64_t) (ri->simd.vregs[i] & 0xffffffffffffffff)); + (uint64_t) (ri->simd.vregs[i])); } return !ferror(f); @@ -119,7 +119,7 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) } for (i = 0; i < 31; i++) { if (m->regs[i] != a->regs[i]) { - fprintf(f, " X%2d : %016" PRIx64 " vs %016" PRIx64 "\n", + fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n", i, m->regs[i], a->regs[i]); } } @@ -148,13 +148,13 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) for (i = 0; i < 32; i++) { if (m->simd.vregs[i] != a->simd.vregs[i]) { - fprintf(f, " V%2d : " + fprintf(f, " V%-2d : " "%016" PRIx64 "%016" PRIx64 " vs " "%016" PRIx64 "%016" PRIx64 "\n", i, (uint64_t) (m->simd.vregs[i] >> 64), - (uint64_t) (m->simd.vregs[i] & 0xffffffffffffffff), + (uint64_t) m->simd.vregs[i], (uint64_t) (a->simd.vregs[i] >> 64), - (uint64_t) (a->simd.vregs[i] & 0xffffffffffffffff)); + (uint64_t) a->simd.vregs[i]); } } From patchwork Wed Jun 13 12:55:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138470 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp704942lji; Wed, 13 Jun 2018 06:11:09 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKVU4HoyUa8P4Kz0ZWw+lJ/PvyopgfWUGO7xw4N2RG8o+ALD23GTagg58uLX1rt7GTnflbE X-Received: by 2002:a37:4c47:: with SMTP id z68-v6mr4089077qka.233.1528895468995; Wed, 13 Jun 2018 06:11:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528895468; cv=none; d=google.com; s=arc-20160816; b=wOVqSiPBitrOyozyOZNASeRkvzN/BOn1N92GtOZi9XEfOQvGbWCq9jit0JQtsMYC/s WtnWLijVHvrcIJau0rLOlKe6FA5IKr7A5FeJwvMDLJIgOf8V48uvXN0FFKJFWageVLHb yr3WfQSCp2eqwyaY8rmo/8d7zO0bFLfmphh1o2vMT2YIe+PAqNxzrSG7aJdvKkIaaIGH 9ypiL4RsIsDANXj7lgG++dQ4lqqAyoFHiGi39vN35ik/9lhKP2hQv+jc4ddaU9j5h/08 WYlFeDNrCNBC+g0MF+5VBG6GDFLWpmXguE83x7fl1DMAUPuVcvORA9Hugbu1ENOdveMl PM/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=7LijovdmKNV9kAq+uRPzeOm1CxkfeVzs8McFFxEKX1M=; b=x1UgZGU0S+qO8fuw/SvU0xIVE9pm6urO46/zB4GXj1SyXrVL0ZXxSmc+VaLpLaCyF3 OldCRP7HqiqtDYqRl0ETeWsTfXJt+N1hLoQC8NZRgUIZuxI03zVMyGfZTgHU1xiSRvcm ot+xP2OlNFQBaZDmoMJolYhy2j9SDkDFWgvojfQ8fGvHx+pdZ85eWELLtHKWU4fIklHs /Fp52H2E2iXr0ad7fC/H5AEm7eOqvXJre+l5oyJCy8pMvK648dbkMH7GZDF30DYTStoZ W0ubFXthXEaJxT0uCRkjlcheAAT/USUEiQtZNuD8+wGGmGX5bfrucFfVKEaP+YbwcLNM PyCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ka3j0sG+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [RISU PATCH v3 19/22] risu_reginfo_aarch64: add support for copying SVE register state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add the ability to save SVE registers from the signal context. This is controlled with an optional flag --test-sve. The whole thing is conditionally compiled when SVE support is in the sigcontext headers. Signed-off-by: Alex Bennée --- v2 - support EXTRA_MAGIC contexts v3 - handle conditional bits - include in reginfo.h - move from helper function to main init function - (void *) cast for memcpy - additional ifdef SVE_MAGIC stuff --- risu_reginfo_aarch64.c | 107 ++++++++++++++++++++++++++++++++++++----- risu_reginfo_aarch64.h | 16 ++++++ 2 files changed, 110 insertions(+), 13 deletions(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 3ccaf0e..79db5dd 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -16,13 +16,26 @@ #include /* for FPSIMD_MAGIC */ #include #include -#include +#include #include "risu.h" #include "risu_reginfo_aarch64.h" +#ifndef SVE_MAGIC const struct option * const arch_long_opts; const char * const arch_extra_help; +#else + +/* Should we test SVE register state */ +static int test_sve; +static const struct option extra_opts[] = { + {"test-sve", no_argument, &test_sve, 1}, + {0, 0, 0, 0} +}; + +const struct option * const arch_long_opts = &extra_opts[0]; +const char * const arch_extra_help = " --test-sve Compare SVE registers\n"; +#endif void process_arch_opt(int opt, const char *arg) { @@ -31,8 +44,12 @@ void process_arch_opt(int opt, const char *arg) const int reginfo_size(void) { - const int size = offsetof(struct reginfo, simd.end); - assert(sizeof(struct reginfo)==size); + int size = offsetof(struct reginfo, simd.end); +#ifdef SVE_MAGIC + if (test_sve) { + size = offsetof(struct reginfo, sve.end); + } +#endif return size; } @@ -40,8 +57,12 @@ const int reginfo_size(void) void reginfo_init(struct reginfo *ri, ucontext_t *uc) { int i; - struct _aarch64_ctx *ctx; - struct fpsimd_context *fp; + struct _aarch64_ctx *ctx, *extra = NULL; + struct fpsimd_context *fp = NULL; +#ifdef SVE_MAGIC + struct sve_context *sve = NULL; +#endif + /* necessary to be able to compare with memcmp later */ memset(ri, 0, sizeof(*ri)); @@ -57,21 +78,81 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.pc); ctx = (struct _aarch64_ctx *) &uc->uc_mcontext.__reserved[0]; - - while (ctx->magic != FPSIMD_MAGIC && ctx->size != 0) { - ctx += (ctx->size + sizeof(*ctx) - 1) / sizeof(*ctx); + while (ctx) { + switch (ctx->magic) { + case FPSIMD_MAGIC: + fp = (void *)ctx; + break; +#ifdef SVE_MAGIC + case SVE_MAGIC: + sve = (void *)ctx; + break; + case EXTRA_MAGIC: + extra = (void *)((struct extra_context *)(ctx))->datap; + break; +#endif + case 0: + /* End of list. */ + ctx = extra; + extra = NULL; + continue; + default: + /* Unknown record -- skip it. */ + break; + } + ctx = (void *)ctx + ctx->size; } - if (ctx->magic != FPSIMD_MAGIC || ctx->size != sizeof(*fp)) { - fprintf(stderr, - "risu_reginfo_aarch64: failed to get FP/SIMD state\n"); + if (!fp || fp->head.size != sizeof(*fp)) { + fprintf(stderr, "risu_reginfo_aarch64: failed to get FP/SIMD state\n"); return; } - - fp = (struct fpsimd_context *) ctx; ri->fpsr = fp->fpsr; ri->fpcr = fp->fpcr; +#ifdef SVE_MAGIC + if (test_sve) { + int vq = sve_vq_from_vl(sve->vl); /* number of quads for whole vl */ + + if (sve == NULL) { + fprintf(stderr, "risu_reginfo_aarch64: failed to get SVE state\n"); + return; + } + + ri->sve.vl = sve->vl; + + if (sve->head.size < SVE_SIG_CONTEXT_SIZE(vq)) { + if (sve->head.size == sizeof(*sve)) { + /* SVE state is empty -- not an error. */ + } else { + fprintf(stderr, "risu_reginfo_aarch64: " + "failed to get complete SVE state\n"); + } + return; + } + + /* Copy ZREG's one at a time */ + for (i = 0; i < SVE_NUM_ZREGS; i++) { + memcpy(&ri->sve.zregs[i], + (void *)sve + SVE_SIG_ZREG_OFFSET(vq, i), + SVE_SIG_ZREG_SIZE(vq)); + } + + /* Copy PREG's one at a time */ + for (i = 0; i < SVE_NUM_PREGS; i++) { + memcpy(&ri->sve.pregs[i], + (void *)sve + SVE_SIG_PREG_OFFSET(vq, i), + SVE_SIG_PREG_SIZE(vq)); + } + + /* Finally the FFR */ + memcpy(&ri->sve.ffr,(void *)sve + SVE_SIG_FFR_OFFSET(vq), + SVE_SIG_FFR_SIZE(vq)); + + return; + } +#endif + for (i = 0; i < 32; i++) { ri->simd.vregs[i] = fp->vregs[i]; } diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h index ef97622..b3701b3 100644 --- a/risu_reginfo_aarch64.h +++ b/risu_reginfo_aarch64.h @@ -13,11 +13,24 @@ #ifndef RISU_REGINFO_AARCH64_H #define RISU_REGINFO_AARCH64_H +#include /* for SVE_MAGIC */ + struct simd_reginfo { __uint128_t vregs[32]; char end[0]; }; +#ifdef SVE_MAGIC +struct sve_reginfo { + /* SVE */ + uint16_t vl; /* current VL */ + __uint128_t zregs[SVE_NUM_ZREGS][SVE_VQ_MAX]; + uint16_t pregs[SVE_NUM_PREGS][SVE_VQ_MAX]; + uint16_t ffr[SVE_VQ_MAX]; + char end[0]; +}; +#endif + struct reginfo { uint64_t fault_address; uint64_t regs[31]; @@ -32,6 +45,9 @@ struct reginfo { union { struct simd_reginfo simd; +#ifdef SVE_MAGIC + struct sve_reginfo sve; +#endif }; }; From patchwork Wed Jun 13 12:55:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138475 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp720037lji; Wed, 13 Jun 2018 06:23:56 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKcAPx2Uppvzzcz5lsHtkUfFKzBu9yJm+dVa0YUmb+VzNu8ZXSl3sk4yXP/8JxubNRk/Y+S X-Received: by 2002:a37:8e87:: with SMTP id q129-v6mr4314764qkd.76.1528896236471; Wed, 13 Jun 2018 06:23:56 -0700 (PDT) ARC-Seal: i=1; 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X-Received-From: 2a00:1450:400c:c0c::231 Subject: [Qemu-devel] [RISU PATCH v3 20/22] risu_reginfo_aarch64: add SVE support to reginfo_dump_mismatch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- v2 - include ffr in comparison - mild re-factor of preg cmp/diff v3 - re-factoring --- risu_reginfo_aarch64.c | 74 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) -- 2.17.1 diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 79db5dd..a352b4c 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "risu.h" #include "risu_reginfo_aarch64.h" @@ -164,6 +165,35 @@ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2) return memcmp(r1, r2, reginfo_size()) == 0; } +#ifdef SVE_MAGIC +static int sve_zreg_is_eq(struct reginfo *r1, struct reginfo *r2, int z) +{ + return memcmp(r1->sve.zregs[z], r2->sve.zregs[z], sizeof(*r1->sve.zregs[z])) == 0; +} + +static int sve_preg_is_eq(uint16_t const (*p1)[SVE_VQ_MAX], + uint16_t const (*p2)[SVE_VQ_MAX]) +{ + return memcmp(p1, p2, sizeof *p1) == 0; +} + +static void sve_dump_preg_diff(FILE *f, int vq, + uint16_t const (*p1)[SVE_VQ_MAX], + uint16_t const (*p2)[SVE_VQ_MAX]) +{ + int q; + + for (q = 0; q < vq; q++) { + fprintf(f, "%#04x", *p1[q]); + } + fprintf(f, " vs "); + for (q = 0; q < vq; q++) { + fprintf(f, "%#04x", *p2[q]); + } + fprintf(f, "\n"); +} +#endif + /* reginfo_dump: print state to a stream, returns nonzero on success */ int reginfo_dump(struct reginfo *ri, FILE * f) { @@ -227,6 +257,50 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) fprintf(f, " fpcr : %08x vs %08x\n", m->fpcr, a->fpcr); } +#ifdef SVE_MAGIC + if (test_sve) { + struct sve_reginfo *ms = &m->sve; + struct sve_reginfo *as = &a->sve; + + if (ms->vl != as->vl) { + fprintf(f, " SVE VL : %d vs %d\n", ms->vl, as->vl); + } + + if (!sve_preg_is_eq(&ms->ffr, &as->ffr)) { + fprintf(f, " FFR : "); + sve_dump_preg_diff(f, sve_vq_from_vl(ms->vl), + &ms->pregs[i], &as->pregs[i]); + } + for (i = 0; i < SVE_NUM_PREGS; i++) { + if (!sve_preg_is_eq(&ms->pregs[i], &as->pregs[i])) { + fprintf(f, " P%2d : ", i); + sve_dump_preg_diff(f, sve_vq_from_vl(ms->vl), + &ms->pregs[i], &as->pregs[i]); + } + } + for (i = 0; i < SVE_NUM_ZREGS; i++) { + if (!sve_zreg_is_eq(m, a, i)) { + int q; + char *pad=""; + fprintf(f, " Z%2d : ", i); + for (q = 0; q < sve_vq_from_vl(ms->vl); q++) { + if (ms->zregs[i][q] != as->zregs[i][q]) { + fprintf(f, "%sq%02d: %016" PRIx64 "%016" PRIx64 + " vs %016" PRIx64 "%016" PRIx64"\n", pad, q, + (uint64_t) (ms->zregs[i][q] >> 64), + (uint64_t) ms->zregs[i][q], + (uint64_t) (as->zregs[i][q] >> 64), + (uint64_t) as->zregs[i][q]); + pad = " "; + } + } + } + } + + return !ferror(f); + } +#endif + for (i = 0; i < 32; i++) { if (m->simd.vregs[i] != a->simd.vregs[i]) { fprintf(f, " V%-2d : " From patchwork Wed Jun 13 12:56:00 2018 Content-Type: text/plain; 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [RISU PATCH v3 21/22] risu_reginfo_aarch64: limit SVE_VQ_MAX to current architecture X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The kernel headers optimistically assume it's going to grow but as we are never going to use that many on current hardware we limit SVE_VQ_MAX to what we will. Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée --- risu_reginfo_aarch64.h | 5 +++++ 1 file changed, 5 insertions(+) -- 2.17.1 diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h index b3701b3..c33b86f 100644 --- a/risu_reginfo_aarch64.h +++ b/risu_reginfo_aarch64.h @@ -31,6 +31,11 @@ struct sve_reginfo { }; #endif +/* The kernel headers set this based on future arch extensions. + The current arch maximum is 16. Save space below. */ +#undef SVE_VQ_MAX +#define SVE_VQ_MAX 16 + struct reginfo { uint64_t fault_address; uint64_t regs[31]; From patchwork Wed Jun 13 12:56:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 138474 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp719814lji; Wed, 13 Jun 2018 06:23:42 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLz7YurPjLgZqUc8yw0fCz61MU40eVtg0pg/JI3FCCiR80EAEFGIK2xE1+xFJvt7XOyECiM X-Received: by 2002:a37:678b:: with SMTP id b133-v6mr4349213qkc.54.1528896222250; Wed, 13 Jun 2018 06:23:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528896222; cv=none; d=google.com; s=arc-20160816; b=hysuC0I7gN0RZv5AOchmvbfKsjhF883otYFTC7yOl/SxVxF9wKQFvIk06kwUN7T2HF 3pTS0/N35torWG1ZF52irci6Z1wrcF0eTVsbDSrYSYIYYLxO/wy9zTxk05gZaTry4xni ai6gjgF0TrdkgZo3RRtfBR5faJK7ep7eCgUxXYSp5cNRHQ6wLUJUbAJIQIco2BUMRFxE zCY7drNe3Yl4Dug/Kr9rHMgWDGVbZmzWh3c1Tt0eYQqqwLlxH9RFLILMvDqAGcMUB7+N egoPoswHht7TdckabbuH73IpxUmj9lYbWxZwbpFeEXrYYQUAEDSlW34sfJ2YrqqPePf0 6w2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=LgQ7v8FSvW3rYAYloOho4U2Wg8+IrRIeB0BXVRYCzj0=; b=eKf7NbtJVuilKKxVszbhtRgDG84cSKGlGpE9wI+/1i+STEDTrF73WCduXKer6Ww7xO MDuPxd5IkRkW6q7aJSadL6pLxbj7SN3Dj+iiwLanhwT+zW68igAid6REWFC4WSz3GqSp vwXRQD5c8Z3ZaLrVxcdjp1ZdiVjwvICbmCsKMa//yujJtQjInajTy42ersXOlhgPduMO joGQMfzhsv02SH/VszhkFOwgD+wzzFC4yiHcFggPN9ZBYzvOup99UlBaH9YNnOPV2cUq 3iPF9A9ToxbYOWyEuzhptnKu4UJ/f7hVi7tozVTv6Ra3mS5LH4cSTFh1+0CQTGS0Z3pC 6kqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cL6XUzg4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::22d Subject: [Qemu-devel] [RISU PATCH v3 22/22] risu_reginfo_aarch64: handle variable VQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This involves parsing the command line parameter and calling the kernel to set the VQ limit. We also add dumping of the register state in the main register dump. Signed-off-by: Alex Bennée --- risu_reginfo_aarch64.c | 164 +++++++++++++++++++++++++++++------------ 1 file changed, 115 insertions(+), 49 deletions(-) -- 2.17.1 diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index a352b4c..71c57b9 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include "risu.h" #include "risu_reginfo_aarch64.h" @@ -30,17 +32,41 @@ const char * const arch_extra_help; /* Should we test SVE register state */ static int test_sve; static const struct option extra_opts[] = { - {"test-sve", no_argument, &test_sve, 1}, + {"test-sve", required_argument, NULL, FIRST_ARCH_OPT }, {0, 0, 0, 0} }; const struct option * const arch_long_opts = &extra_opts[0]; -const char * const arch_extra_help = " --test-sve Compare SVE registers\n"; +const char * const arch_extra_help + = " --test-sve= Compare SVE registers with VQ\n"; #endif void process_arch_opt(int opt, const char *arg) { +#ifdef SVE_MAGIC + long want, got; + + assert(opt == FIRST_ARCH_OPT); + test_sve = strtol(arg, 0, 10); + + if (test_sve <= 0 || test_sve > SVE_VQ_MAX) { + fprintf(stderr, "Invalid value for VQ (1-%d)\n", SVE_VQ_MAX); + exit(1); + } + want = sve_vl_from_vq(test_sve); + got = prctl(PR_SVE_SET_VL, want); + if (want != got) { + if (got < 0) { + perror("prctl PR_SVE_SET_VL"); + } else { + fprintf(stderr, "Unsupported value for VQ (%d != %d)\n", + test_sve, (int)sve_vq_from_vl(got)); + } + exit(1); + } +#else abort(); +#endif } const int reginfo_size(void) @@ -113,12 +139,18 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) #ifdef SVE_MAGIC if (test_sve) { - int vq = sve_vq_from_vl(sve->vl); /* number of quads for whole vl */ + int vq = test_sve; if (sve == NULL) { fprintf(stderr, "risu_reginfo_aarch64: failed to get SVE state\n"); return; } + if (sve->vl != sve_vl_from_vq(vq)) { + fprintf(stderr, "risu_reginfo_aarch64: " + "unexpected SVE state: %d != %d\n", + sve->vl, sve_vl_from_vq(vq)); + return; + } ri->sve.vl = sve->vl; @@ -147,12 +179,12 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) } /* Finally the FFR */ - memcpy(&ri->sve.ffr,(void *)sve + SVE_SIG_FFR_OFFSET(vq), + memcpy(&ri->sve.ffr, (void *)sve + SVE_SIG_FFR_OFFSET(vq), SVE_SIG_FFR_SIZE(vq)); return; } -#endif +#endif /* SVE_MAGIC */ for (i = 0; i < 32; i++) { ri->simd.vregs[i] = fp->vregs[i]; @@ -166,32 +198,49 @@ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2) } #ifdef SVE_MAGIC -static int sve_zreg_is_eq(struct reginfo *r1, struct reginfo *r2, int z) +static int sve_zreg_is_eq(int vq, const void *z1, const void *z2) { - return memcmp(r1->sve.zregs[z], r2->sve.zregs[z], sizeof(*r1->sve.zregs[z])) == 0; + return memcmp(z1, z2, vq * 16) == 0; } -static int sve_preg_is_eq(uint16_t const (*p1)[SVE_VQ_MAX], - uint16_t const (*p2)[SVE_VQ_MAX]) +static int sve_preg_is_eq(int vq, const void *p1, const void *p2) { - return memcmp(p1, p2, sizeof *p1) == 0; + return memcmp(p1, p2, vq * 2) == 0; } -static void sve_dump_preg_diff(FILE *f, int vq, - uint16_t const (*p1)[SVE_VQ_MAX], - uint16_t const (*p2)[SVE_VQ_MAX]) +static void sve_dump_preg(FILE *f, int vq, const uint16_t *p) { int q; - - for (q = 0; q < vq; q++) { - fprintf(f, "%#04x", *p1[q]); + for (q = vq - 1; q >= 0; q--) { + fprintf(f, "%04x", p[q]); } +} + +static void sve_dump_preg_diff(FILE *f, int vq, const uint16_t *p1, + const uint16_t *p2) +{ + sve_dump_preg(f, vq, p1); fprintf(f, " vs "); - for (q = 0; q < vq; q++) { - fprintf(f, "%#04x", *p2[q]); - } + sve_dump_preg(f, vq, p2); fprintf(f, "\n"); } + +static void sve_dump_zreg_diff(FILE *f, int vq, const __uint128_t *z1, + const __uint128_t *z2) +{ + const char *pad = ""; + int q; + + for (q = 0; q < vq; ++q) { + if (z1[q] != z2[q]) { + fprintf(f, "%sq%02d: %016" PRIx64 "%016" PRIx64 + " vs %016" PRIx64 "%016" PRIx64"\n", pad, q, + (uint64_t)(z1[q] >> 64), (uint64_t)z1[q], + (uint64_t)(z2[q] >> 64), (uint64_t)z2[q]); + pad = " "; + } + } +} #endif /* reginfo_dump: print state to a stream, returns nonzero on success */ @@ -210,6 +259,36 @@ int reginfo_dump(struct reginfo *ri, FILE * f) fprintf(f, " fpsr : %08x\n", ri->fpsr); fprintf(f, " fpcr : %08x\n", ri->fpcr); +#ifdef SVE_MAGIC + if (test_sve) { + int q, vq = test_sve; + + fprintf(f, " vl : %d\n", ri->sve.vl); + + for (i = 0; i < 32; i++) { + fprintf(f, " Z%-2d q%-2d: %016" PRIx64 "%016" PRIx64 "\n", i, 0, + (uint64_t)(ri->sve.zregs[i][0] >> 64), + (uint64_t)ri->sve.zregs[i][0]); + for (q = 1; q < vq; ++q) { + fprintf(f, " q%-2d: %016" PRIx64 "%016" PRIx64 "\n", q, + (uint64_t)(ri->sve.zregs[i][q] >> 64), + (uint64_t)ri->sve.zregs[i][q]); + } + } + + for (i = 0; i < 16; i++) { + fprintf(f, " P%-2d : ", i); + sve_dump_preg(f, vq, &ri->sve.pregs[i][0]); + fprintf(f, "\n"); + } + fprintf(f, " FFR : "); + sve_dump_preg(f, vq, &ri->sve.ffr[0]); + fprintf(f, "\n"); + + return !ferror(f); + } +#endif + for (i = 0; i < 32; i++) { fprintf(f, " V%-2d : %016" PRIx64 "%016" PRIx64 "\n", i, (uint64_t) (ri->simd.vregs[i] >> 64), @@ -259,42 +338,29 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) #ifdef SVE_MAGIC if (test_sve) { - struct sve_reginfo *ms = &m->sve; - struct sve_reginfo *as = &a->sve; + int vq = sve_vq_from_vl(m->sve.vl); - if (ms->vl != as->vl) { - fprintf(f, " SVE VL : %d vs %d\n", ms->vl, as->vl); + if (m->sve.vl != a->sve.vl) { + fprintf(f, " vl : %d vs %d\n", m->sve.vl, a->sve.vl); } - if (!sve_preg_is_eq(&ms->ffr, &as->ffr)) { - fprintf(f, " FFR : "); - sve_dump_preg_diff(f, sve_vq_from_vl(ms->vl), - &ms->pregs[i], &as->pregs[i]); + for (i = 0; i < SVE_NUM_ZREGS; i++) { + if (!sve_zreg_is_eq(vq, &m->sve.zregs[i], &a->sve.zregs[i])) { + fprintf(f, " Z%-2d : ", i); + sve_dump_zreg_diff(f, vq, &m->sve.zregs[i][0], + &a->sve.zregs[i][0]); + } } for (i = 0; i < SVE_NUM_PREGS; i++) { - if (!sve_preg_is_eq(&ms->pregs[i], &as->pregs[i])) { - fprintf(f, " P%2d : ", i); - sve_dump_preg_diff(f, sve_vq_from_vl(ms->vl), - &ms->pregs[i], &as->pregs[i]); - } + if (!sve_preg_is_eq(vq, &m->sve.pregs[i], &a->sve.pregs[i])) { + fprintf(f, " P%-2d : ", i); + sve_dump_preg_diff(f, vq, &m->sve.pregs[i][0], + &a->sve.pregs[i][0]); + } } - for (i = 0; i < SVE_NUM_ZREGS; i++) { - if (!sve_zreg_is_eq(m, a, i)) { - int q; - char *pad=""; - fprintf(f, " Z%2d : ", i); - for (q = 0; q < sve_vq_from_vl(ms->vl); q++) { - if (ms->zregs[i][q] != as->zregs[i][q]) { - fprintf(f, "%sq%02d: %016" PRIx64 "%016" PRIx64 - " vs %016" PRIx64 "%016" PRIx64"\n", pad, q, - (uint64_t) (ms->zregs[i][q] >> 64), - (uint64_t) ms->zregs[i][q], - (uint64_t) (as->zregs[i][q] >> 64), - (uint64_t) as->zregs[i][q]); - pad = " "; - } - } - } + if (!sve_preg_is_eq(vq, &m->sve.ffr, &a->sve.ffr)) { + fprintf(f, " FFR : "); + sve_dump_preg_diff(f, vq, &m->sve.pregs[i][0], &a->sve.pregs[i][0]); } return !ferror(f);