From patchwork Fri Apr 16 18:59:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422559 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp646917jaf; Fri, 16 Apr 2021 12:02:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw7LN30r080AYbWENEhRf4EOYnpdBpGJUCSkkKDCQUrfJIdOpi5XW7634Wm9sAouWq4RrP5 X-Received: by 2002:a05:6512:131c:: with SMTP id x28mr3913215lfu.638.1618599722095; Fri, 16 Apr 2021 12:02:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618599722; cv=none; d=google.com; s=arc-20160816; b=Ci6zEauLx3/wAPX4kCbK8P5/OzfqUZTHhKYO+EZCvnpmOmMLdErtEfYspkVhqV0ff4 zNZUm+ojrKXwRYMwzfMSkoIsXu7M87BzATzoiM9jhEd+5muk7rzaDaDMl4YN3+AofNA5 8h9hmh2rdJY49iPpYCs6SxtWbDao7kLdSvyTlM47Ga+H2fEEDTMwGbq9La8rrf99TSpJ LkAuZJaf7Kv4IS6DeV6kWHSvtUYmXyJg7iUXL0jyS4jee+/7rBsgqqj/B0SLOFZuavRs 5b8s+weK2k5QWxoBjGODgsC8ErWFqnPKnB+aidq2Ztfxuy68aXwzoUbVrbSoI1FYksQS zQmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8XIA/+X37AvNazV2jisISm3ZiIWDvYr5zvekcj4Rlqc=; b=Q9bENeg4xwNBhhTlWWLmHcCEzRqXxh+8c6a/OPN5L8wtGx3LyDQir4zHlohxq2BiV8 A7k2GFVJ9kVuxSsJH16DMu68IKy00iwn4Fm35Uc6cJ5qQrhIPrYd6pA5z9muD5dm7Qkq ebLoABkKFkYX5rnRbqoqgkPOy6/HdqjrRA/OU/Y5WG3J3ihnHqYwWQkT/7epDt3GyHIG 69QrxO3AgZM9TRcm0bSfyB7PPCI1MBcXQ+gjAKKk0VLKMakrYNCe/97tId1F+i98Hn+O QJENYsUqY1/jrUMQ6+sbrB5STIFv+cGSuC7Sgcc5tghHqijCgRyqYg1Mb0tTF/mJvEf0 eg9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mqcwaLZi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n4si6718112lft.332.2021.04.16.12.02.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:02:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mqcwaLZi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTj6-0003Pv-Ic for patch@linaro.org; Fri, 16 Apr 2021 15:02:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49880) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThK-0003PD-J0 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:10 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:37499) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThD-0004Bz-6k for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:09 -0400 Received: by mail-pg1-x533.google.com with SMTP id p2so4354150pgh.4 for ; Fri, 16 Apr 2021 12:00:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8XIA/+X37AvNazV2jisISm3ZiIWDvYr5zvekcj4Rlqc=; b=mqcwaLZi+d0arlLA76I0vNPvphyZbetckfBnxaXTcWRftAQ2HzZJ9PqkWxg4SRPlaN ECBpjIC4VE+g/A+TitNpkDchAKtSmvBiV6gbSq8HMSqTFUF/yTlNy8xUis0hi51HBkRq zvYon89rXn/aqgB80ArZPQ+YyCgnDF3PG6RR+iLwAI8kTQ/jAzE55darLNtnZIT6Wy3G 5kFmj0DgViXe8tjDT9dsR/dbUC2MYRDL81xlypJC47FQ82oQ8VDWKR2XTQfIs+QQpU2m 7VM0RCVY9Vkgt5h3HzuzUKCMJbJkebF88GjXtkz+ietmoWwG1sxhPcKBrSfndUrEBM/E xATQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8XIA/+X37AvNazV2jisISm3ZiIWDvYr5zvekcj4Rlqc=; b=h+0/duOYFUmqYO8RobVExAnO92mR30+t461QgO6Ag3rw2dTqRrSs2yO9hYkJFMrI7V XduKYT6PYHN+d9qwkjvmF2abIxwHcCq1ljqln8gGzPBc3qn1zKXEyN3Zz5NGul87J6TX JYLUfLjZC3r2jpT7jGOvTig+N7VGDiwpXrSeOJ6e749UOJgBb30er9qjEOTkwlDFgcvQ ly6PXOZlC7tSJdcfRBWxHSEgYikwxDh8BzBLLquR9wIbqiPHNL0oiZLgg+z4wYwq282R GiX8vrz7JWkcGCWJY3a1wjXdaSJF3zVDkE6M2rs4soNB3Pd7zA7F0R8ScjjD8wOOwSHg oZTQ== X-Gm-Message-State: AOAM531LiIWNu399p7oKdAxXMisY/wlJsjVN+83MEyN9TfZ4RIEtK7Cw jzLyCKHfOeVr5X6+hhKEWfK8/EVXthHGxA== X-Received: by 2002:aa7:8c57:0:b029:246:730a:5607 with SMTP id e23-20020aa78c570000b0290246730a5607mr9355991pfd.74.1618599601816; Fri, 16 Apr 2021 12:00:01 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/30] target/arm: Fix decode of align in VLDST_single Date: Fri, 16 Apr 2021 11:59:30 -0700 Message-Id: <20210416185959.1520974-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The encoding of size = 2 and size = 3 had the incorrect decode for align, overlapping the stride field. This error was hidden by what should have been unnecessary masking in translate. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/neon-ls.decode | 4 ++-- target/arm/translate-neon.c.inc | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode index c17f5019e3..0a2a0e15db 100644 --- a/target/arm/neon-ls.decode +++ b/target/arm/neon-ls.decode @@ -46,7 +46,7 @@ VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \ VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \ vd=%vd_dp size=0 stride=1 -VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \ +VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 . align:1 rm:4 \ vd=%vd_dp size=1 stride=%imm1_5_p1 -VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \ +VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 . align:2 rm:4 \ vd=%vd_dp size=2 stride=%imm1_6_p1 diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index f6c68e30ab..0e5828744b 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -606,7 +606,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) switch (nregs) { case 1: if (((a->align & (1 << a->size)) != 0) || - (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) { + (a->size == 2 && (a->align == 1 || a->align == 2))) { return false; } break; @@ -621,7 +621,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) } break; case 4: - if ((a->size == 2) && ((a->align & 3) == 3)) { + if (a->size == 2 && a->align == 3) { return false; } break; From patchwork Fri Apr 16 18:59:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422562 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp649120jaf; Fri, 16 Apr 2021 12:04:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzGUGK8cX5Lhkbeg/nugN6t4IqydxHkGahn0LQzFa//VPTtuwgmaVSzx5ueXy6AXND+9CvA X-Received: by 2002:a92:d092:: with SMTP id h18mr8283422ilh.62.1618599886556; Fri, 16 Apr 2021 12:04:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618599886; cv=none; d=google.com; s=arc-20160816; b=xNoms+DlLRjWtWa83oIUNm9ll89c0kzIzrq3wircT3U9b7Yy6XPHKd3mta7B1P6Xkv JZzxjbcqRYcge/ngOaFK73D4FxtsAHb3pC1OeaUzgmpc9mULEYpsJz7HykWTUWEYDm6C f5zdja/pcW7wfpqoe24ez/jpkJGuYDryDgbuhpLaMM3nR/M6kagGC9mUma9VmlTUv4iQ MiD3GHUzOUP9urWDBKpR2mRfoAsYTKv3QapXylsqyAiLar5QTFgrua3ZeeTqF6nQ8N1H ewgBLhwK/xTXgkzJrVSJel6CQC1eEDXz2VteUz+PO1bbapJNNo9GeAu1SKl/EhZOKHkQ BrkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AAT589pnDxjsejZEwpNb+hvhHMZiaAtFUTqs+quVzLQ=; b=C/EcxiK7gsaT5D8kEfTbVifvVdl+YxIQvYRzAPHx/bY0mDC9TbHsC1/uW8QJDGCA2V NwdHF7GV1Hy/xx9NcRUI3ybjcOMlHmzcMOm4Lm/1NdOFFe8Sw3eZPIlmPmVX3tBxghZc WT9fpgoXjSzjLhyjYPJjVwp0TSWKotrRUeczbN2Mbqbs8dsSBbAM5nyt7oa6tnDxAEWK QGnm2qWNFvrgd5kKchbcmy07uju+b+W7GgD4ISfIns1BmckxnDrvbz7EgXv+QUqgezs/ CuSSEMglGwD/lYPJFbeqZRAWS8Q4lWCdWmfag/DxYV+/teu3fsE/b+HlTyeHYZviK2W9 MuHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wV7ePzSd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n18si6625120ioj.75.2021.04.16.12.04.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:04:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wV7ePzSd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41578 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTlm-0007Jl-0q for patch@linaro.org; Fri, 16 Apr 2021 15:04:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49830) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThH-0003Od-Ry for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:08 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:45813) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThE-0004DG-2D for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:07 -0400 Received: by mail-pg1-x52e.google.com with SMTP id d10so19803572pgf.12 for ; Fri, 16 Apr 2021 12:00:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AAT589pnDxjsejZEwpNb+hvhHMZiaAtFUTqs+quVzLQ=; b=wV7ePzSdvnHVQJmO4USWdwfZ9xtnaLJ46EirDvOQ+qx2EOuTiPuDTKWLrDvKXEK2XG v4RL8Z+OPeJGMFQOfS4uDYaoJIBytDabgsPZIlfj66uE0BsF3uginvJ9VPFj5YP9bu+o 5bzUOe4pgOKAK+zryPLNGjSFTEUYZHxDXgPW6mRxjns/ZpYfSui8HTpS+Za5DygE5P6V Zn7Ig7/N/jqYX+Cp6qoeJAxW7nKZbAf3YaWU338d5GLF3W4MkAwqx6OHN5Ne6tpCn2ql Bw9218ipWDTBm1B1au9NEpyuVbx3C1+gVtjAtvSwEwEyQORtf+3xhdIgBc+WdBE7592b +/1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AAT589pnDxjsejZEwpNb+hvhHMZiaAtFUTqs+quVzLQ=; b=TgoZGGn5SZdP8dQqiAVE3ZrWYlA7qwr9NhjdqPOi4sx3LQXTVi2unTQSa5N7GnuLZ2 zMg7N5Yj6YDtWcwXWLnCrU1QqcJEMSVSJl01lgZxuRO/o0u7k7ROfrzT7AicjOQYylPO Wo5uxROQg1Isz8yRgY2nhUJllVV+iQae0q5DXFnGv89KnJvNpmnEcXCmXc+Qz+464uWM Byx+h3CLQbtuhpkblX3s3PJ0hKMm7WbLLxgWKyqZ6xTTNGUdvkHosbmGxH7aui7hjSgF SrBCNIYg6ehsFyG9OH295Br3pqTYUmQtds+rUjrxw1rK+r3HsM8RyIkKnhE26rQVPVtM 0NZQ== X-Gm-Message-State: AOAM530h2MhdyCb2tTaXfUF9jfSVbMdQsJrWTiPNXuFWir3uFVQD+HtF 5MoLfxKQXPS9M9THHSJ0tilB/RvwXtNRjw== X-Received: by 2002:a65:4481:: with SMTP id l1mr494882pgq.42.1618599602664; Fri, 16 Apr 2021 12:00:02 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/30] target/arm: Rename TBFLAG_A32, SCTLR_B Date: Fri, 16 Apr 2021 11:59:31 -0700 Message-Id: <20210416185959.1520974-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're about to rearrange the macro expansion surrounding tbflags, and this field name will be expanded using the bit definition of the same name, resulting in a token pasting error. So SCTLR_B -> SCTLR__B in the 3 uses, and document it. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 +- target/arm/helper.c | 2 +- target/arm/translate.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 193a49ec7f..304e0a6af3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3423,7 +3423,7 @@ FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ */ FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */ -FIELD(TBFLAG_A32, SCTLR_B, 15, 1) +FIELD(TBFLAG_A32, SCTLR__B, 15, 1) /* Cannot overlap with SCTLR_B */ FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) /* * Indicates whether cp register reads and writes by guest code should access diff --git a/target/arm/helper.c b/target/arm/helper.c index d9220be7c5..556b9d4f0a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13003,7 +13003,7 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, bool sctlr_b = arm_sctlr_b(env); if (sctlr_b) { - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1); + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR__B, 1); } if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); diff --git a/target/arm/translate.c b/target/arm/translate.c index 62b1c2081b..9feb572792 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8879,7 +8879,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); - dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); + dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR__B); dc->hstr_active = FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE); dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS); dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); From patchwork Fri Apr 16 18:59:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422558 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp646264jaf; Fri, 16 Apr 2021 12:01:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx9Ehc7q6GhxOwwcu+m9htgg0yN760b2iBpTzINVzu0XTRtW6X+KXN1kGhVCWnPzWMxD8kV X-Received: by 2002:aca:b787:: with SMTP id h129mr7594444oif.58.1618599669782; Fri, 16 Apr 2021 12:01:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618599669; cv=none; d=google.com; s=arc-20160816; b=IsGVpa1AGTDOv7AWr5IqZ0b5M1ttKqQauNuJDMjChtbOzVho9hQkluqDouY4Dwpwal /kFzkNNwXiK6OqMy+x9W5YTqXIiNG1uatfzwJLL70ISQeKQSpoJ5jCtCku4629ASKB1p OcgDZNAJ5JRDZCz2wCeuj1KJPuH3CxZvIcrm2FJ0DyGRoUZBucVw5uyHZls4wUeVKzmo U5CmbnHZkHyPA3f5obkgHkmwRJua5ZKK3GOziXu4Hlck0w7y5x8DX0VcSnLdoXqmNJQK JcVX4Sg3V741yGTup9NtQQWFFiEpThVHQ8TlRLSekDERWSDXDxFamQXeYUzsGppW5lkt JLaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pMgL2a+prtbBPdSaIs5ct/RTVDgGVnnynJ69Tr1rM+o=; b=FQ71F9qKqBlHdQrNwnrYESe4LcwVue9DH4/AYwqOvkrhYUOAqGPoAXva1w8BcVGoU3 STmvitTbYGuGdjkGzLacB3/UKMpCyMaedcxQVX7wbfo6e4qbdrF1rQ1s9AK9knHIbkSu KudBHJP4bIhU6qEXv3hZBZoqEXX8lmoCq+UGdBa0YwuIGvmq7ew/Fe57a+h4tR1/tr5d qbbYf52FdPXEusJJuDFr5wD1vUG16UncDMcTPEnabZyTg4M93yLalSg5KUct543QNERh iXsDN7w7vAd9DZOcg+BwzZ1TAZ/o0AVhcIe0SEX6ndBDAMXa7i+oTz0mYu4wqeQqz2Ks V1BA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NJ8l0cHR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p5si7698382oib.96.2021.04.16.12.01.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:01:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NJ8l0cHR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60984 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTiH-0003QJ-2T for patch@linaro.org; Fri, 16 Apr 2021 15:01:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49874) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThK-0003PC-Gs for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:10 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:44896) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThF-0004E9-3N for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:09 -0400 Received: by mail-pg1-x52c.google.com with SMTP id y32so19807024pga.11 for ; Fri, 16 Apr 2021 12:00:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pMgL2a+prtbBPdSaIs5ct/RTVDgGVnnynJ69Tr1rM+o=; b=NJ8l0cHRm5UHxiRi092lgHcoMuwyF2SZu569arSzfd6gfcf1Z/22kg9xqJcGe1nlfL sqPEsTj/hlQEz3vgRWZBL8vQPkyXgzpCxkA+dBz4/CLF7B71iTu1WOjw4w3+783i8trI ODvlYIDpv1J9gCEFVa5fCoiGBYta6iugewsh7lOCpXF9c26Z5lH/S+SCudemU0Tkgq/5 jegPIndNjG1atOTGZ9+4K23n5Y58w8thTKUrpmtkmJmPqze4PJasYgrIdSTvlFghq2Ah rdPXahM95Pr3AUzfqntQ+gAJhCplSuOrzQyw2A5mpoanjBzxPle3bhGS+sFtGvKJuI3/ lBrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pMgL2a+prtbBPdSaIs5ct/RTVDgGVnnynJ69Tr1rM+o=; b=KsJPs3Z1kYi0Gab3udZJPs1CeNnHH10UIbVxNxJIsowPd6lABahWf+8LK/WlIUdYR5 LM/ZAV7bLanOOxGn7fGPdePOElKG6sL4WMZrZcDvIwETWNBz6+QPdUzVzoC+PBySSyWT XBuwLNipvzhyPlTbs5TqPrxxRKJ/9NV0U8qZO3k4G7RFRf68bwBnk6tgojcDLknyTAkz 34f42+hafHDG2n4FXfXC55z99ylFsG7/XcM2/Jxh2qw5QY/HvcdrlxOZq9mInJ+yReFF BnjRQEO6fR5WpY1YIPU90hLi0PgRpS/OGCXoEtsJO0yOjIQr6auWgy19nSRy23p1dXAl QIhg== X-Gm-Message-State: AOAM530GSkXzhUSwhWDoquUzF0KKHz1vgBeg24YANWICFt0E66VwQ/n0 u3F6ZkUI+xgkXiet6HiXwCwY+JhykExgGA== X-Received: by 2002:a62:f210:0:b029:24a:c8f:c1bf with SMTP id m16-20020a62f2100000b029024a0c8fc1bfmr8927789pfh.47.1618599603497; Fri, 16 Apr 2021 12:00:03 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/30] target/arm: Rename TBFLAG_ANY, PSTATE_SS Date: Fri, 16 Apr 2021 11:59:32 -0700 Message-Id: <20210416185959.1520974-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're about to rearrange the macro expansion surrounding tbflags, and this field name will be expanded using the bit definition of the same name, resulting in a token pasting error. So PSTATE_SS -> PSTATE__SS in the uses, and document it. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 +- target/arm/helper.c | 4 ++-- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 304e0a6af3..4cbf2db3e3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3396,7 +3396,7 @@ typedef ARMCPU ArchCPU; */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, PSTATE__SS, 29, 1) /* Not cached. */ FIELD(TBFLAG_ANY, BE_DATA, 28, 1) FIELD(TBFLAG_ANY, MMUIDX, 24, 4) /* Target EL if we take a floating-point-disabled exception */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 556b9d4f0a..cd8dec126f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13333,11 +13333,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 0 x Inactive (the TB flag for SS is always 0) * 1 0 Active-pending * 1 1 Active-not-pending - * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. + * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. */ if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE__SS, 1); } *pflags = flags; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f35a5e8174..64b3a5200c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14733,7 +14733,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, * end the TB */ dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); - dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); + dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS); dc->is_ldex = false; dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); diff --git a/target/arm/translate.c b/target/arm/translate.c index 9feb572792..45e320f4b3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8909,7 +8909,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) * end the TB */ dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); - dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); + dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS); dc->is_ldex = false; dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK; From patchwork Fri Apr 16 18:59:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422560 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp646952jaf; Fri, 16 Apr 2021 12:02:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyu9Jo1QSkvVQoEEK8nO9L1zvFTaO4P/rjoE0KSvOAHpDmLoyyaqKrDRSkaD7AsdGPFeDw9 X-Received: by 2002:a1c:98d3:: with SMTP id a202mr9589079wme.178.1618599723753; Fri, 16 Apr 2021 12:02:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618599723; cv=none; d=google.com; s=arc-20160816; b=XzOo9P+lJ1yMmCvSdOSVGHVY6mCNF6lfRROpAu79h9x/Fs/b7fpvWABWJg4Eskcper 75w/smaAUdXCudZ2MCj2NfSeffq28IQZhPUlbbXfH9JVS2HAPE/E4g5C3gd9OfYq6TKv QbY82xBxHZZPVGjcxniuCWXjBxi6HKsbBC8qbKHAHvYnOZEPu+UTSvahgu8ZjliHyWps PDyL7NVdP+gmLVYB3KlRwl3JRqR25J5Umh3N7ORQO49+p88g0OwEgnyOJJL+Ft1vetYj wgNItZDEiKQPVx4s1R3WCoJVKah0iOUK3y/JhuaAHyS2G8Fcoc2za/uLncA4a6DjIclu UthQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lyEZ23rEJ0ybvWabyWlgigAm5pXAYsoEK50osfBHHkY=; b=ZB+fD//c2QTPf62CeObq/o5xvO3ONX3o9Oo/hRGQIzJjs6p/e1yPxHovnfu8U9g7Gw TFqiIDaDrIBSK3vhxI943pd6T4ESz04neqxq7Va6ExUWaHX+bxOChZprVO44YZT27MVN h3tPKG4bENY5KsoLNm9ngyoQ67Pz2rrQor5asZQVeiixuqAmeDVVYJaMyu+y24KL6ezw MaYa7ouXRnq2Re1wtp0QHhFNKqAGXQT5BpcSLABEUvSDxDDKxQW913AGMfLPf/DyLQA9 S7vkG3TtPa+aLGwqc6iYhLm8yKIafJJLn9GG4iHDU64d6NRi5Dp1SAJMk4g3es2EX0Hx Bq4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PekFZlzI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g82si8063956wmg.155.2021.04.16.12.02.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:02:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PekFZlzI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35582 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTj8-0004ro-9I for patch@linaro.org; Fri, 16 Apr 2021 15:02:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50052) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThW-0003Rg-Ja for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:23 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:41816) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThG-0004FJ-5s for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:21 -0400 Received: by mail-pl1-x62b.google.com with SMTP id e2so10169078plh.8 for ; Fri, 16 Apr 2021 12:00:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lyEZ23rEJ0ybvWabyWlgigAm5pXAYsoEK50osfBHHkY=; b=PekFZlzIjnq841djhS+jJWS71bo8KJ7AfB4caHtY9JEqlR0rurhN10EnEH1BM8sI4F tAmL84E4hYMhbAsm5Nsg7z6HsiZRNCh7oPYk0VEg08rPSaUUk9lfzTRxSXt0tH1TKfk+ FgsGDjDZ+GCIZ6yuROnEKv3DuyRF/7B9cGlrEWPILsmjVnJB8eYo7hM8i60z+s6dtn0v KKfBNe+0nMsIHKkgVBFnRf0kanIrjvrf1We+vmeHUuLjtV1QqFmTpymROVOjKl/RwfhF EVeYYE/tTDyfv+m/GVqLtb9Zh9YqCZiUTblqf2lCKwkmL6P8bloyWYQC9zFNZbfKy6Nt 46AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lyEZ23rEJ0ybvWabyWlgigAm5pXAYsoEK50osfBHHkY=; b=cR9c+j38h+HyS6FPUHd3ET/GrQti+PouwefExVz0RDhqzZmmQrabgJqGpTAzZZcHok sRHN0LQ63rPIx146jjqFulUGLmH2gVt8OgzQTc1wFXGLEw1I4XdCSa6dLzdtE0lKXwxi AC9YbptNphNEiENsS17bzsY3/5HAVswUhRw7sI/1aNAvlngNepR+U/yQzQTzdcmRXGqm +eyDxqDxKpQCNQ+SFxTunZ9rmGlkQ5ab9J7wlbHOBhEHqTi+XmINvGyHL2GMAkB6if+U CQGTpq0MN1VsX0L1Akk/0E0iCcYhTFiDecx483VNi+upjmmPEGzu3yCcF8Ub9WpO3AMF tbUw== X-Gm-Message-State: AOAM533oox371Gcjd8R7NbHx+I+E+WBo50iXT/DwLu/b10lrFchtr2Qa bz7RWcK625PbeiF0flKOCRIRGJlPfajvIQ== X-Received: by 2002:a17:902:9b97:b029:eb:7a1b:5b88 with SMTP id y23-20020a1709029b97b02900eb7a1b5b88mr9906152plp.77.1618599604532; Fri, 16 Apr 2021 12:00:04 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/30] target/arm: Add wrapper macros for accessing tbflags Date: Fri, 16 Apr 2021 11:59:33 -0700 Message-Id: <20210416185959.1520974-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're about to split tbflags into two parts. These macros will ensure that the correct part is used with the correct set of bits. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 22 +++++++++- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 85 +++++++++++++++++--------------------- target/arm/translate-a64.c | 36 ++++++++-------- target/arm/translate.c | 48 ++++++++++----------- 5 files changed, 101 insertions(+), 92 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4cbf2db3e3..b798ff8115 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3462,6 +3462,26 @@ FIELD(TBFLAG_A64, TCMA, 16, 2) FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) +/* + * Helpers for using the above. + */ +#define DP_TBFLAG_ANY(DST, WHICH, VAL) \ + (DST = FIELD_DP32(DST, TBFLAG_ANY, WHICH, VAL)) +#define DP_TBFLAG_A64(DST, WHICH, VAL) \ + (DST = FIELD_DP32(DST, TBFLAG_A64, WHICH, VAL)) +#define DP_TBFLAG_A32(DST, WHICH, VAL) \ + (DST = FIELD_DP32(DST, TBFLAG_A32, WHICH, VAL)) +#define DP_TBFLAG_M32(DST, WHICH, VAL) \ + (DST = FIELD_DP32(DST, TBFLAG_M32, WHICH, VAL)) +#define DP_TBFLAG_AM32(DST, WHICH, VAL) \ + (DST = FIELD_DP32(DST, TBFLAG_AM32, WHICH, VAL)) + +#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN, TBFLAG_ANY, WHICH) +#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN, TBFLAG_A64, WHICH) +#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN, TBFLAG_A32, WHICH) +#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN, TBFLAG_M32, WHICH) +#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN, TBFLAG_AM32, WHICH) + /** * cpu_mmu_index: * @env: The cpu environment @@ -3472,7 +3492,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) */ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) { - return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX); + return EX_TBFLAG_ANY(env->hflags, MMUIDX); } static inline bool bswap_code(bool sctlr_b) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 061c8ff846..9cc3b066e2 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1020,7 +1020,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) * the hflags rebuild, since we can pull the composite TBII field * from there. */ - tbii = FIELD_EX32(env->hflags, TBFLAG_A64, TBII); + tbii = EX_TBFLAG_A64(env->hflags, TBII); if ((tbii >> extract64(new_pc, 55, 1)) & 1) { /* TBI is enabled. */ int core_mmu_idx = cpu_mmu_index(env, false); diff --git a/target/arm/helper.c b/target/arm/helper.c index cd8dec126f..2769e6fd35 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12987,12 +12987,11 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, uint32_t flags) { - flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); - flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, - arm_to_core_mmu_idx(mmu_idx)); + DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); + DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); if (arm_singlestep_active(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); } return flags; } @@ -13003,12 +13002,12 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, bool sctlr_b = arm_sctlr_b(env); if (sctlr_b) { - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR__B, 1); + DP_TBFLAG_A32(flags, SCTLR__B, 1); } if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + DP_TBFLAG_ANY(flags, BE_DATA, 1); } - flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); + DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } @@ -13019,7 +13018,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, uint32_t flags = 0; if (arm_v7m_is_handler_mode(env)) { - flags = FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1); + DP_TBFLAG_M32(flags, HANDLER, 1); } /* @@ -13030,7 +13029,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, if (arm_feature(env, ARM_FEATURE_V8) && !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags = FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1); + DP_TBFLAG_M32(flags, STACKCHECK, 1); } return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); @@ -13040,8 +13039,7 @@ static uint32_t rebuild_hflags_aprofile(CPUARMState *env) { int flags = 0; - flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, - arm_debug_target_el(env)); + DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); return flags; } @@ -13051,12 +13049,12 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, uint32_t flags = rebuild_hflags_aprofile(env); if (arm_el_is_aa64(env, 1)) { - flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + DP_TBFLAG_A32(flags, VFPEN, 1); } if (arm_current_el(env) < 2 && env->cp15.hstr_el2 && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { - flags = FIELD_DP32(flags, TBFLAG_A32, HSTR_ACTIVE, 1); + DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); @@ -13071,14 +13069,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, uint64_t sctlr; int tbii, tbid; - flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); /* Get control bits for tagged addresses. */ tbid = aa64_va_parameter_tbi(tcr, mmu_idx); tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); - flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); - flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); + DP_TBFLAG_A64(flags, TBII, tbii); + DP_TBFLAG_A64(flags, TBID, tbid); if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { int sve_el = sve_exception_el(env, el); @@ -13093,14 +13091,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } else { zcr_len = sve_zcr_len_for_el(env, el); } - flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); - flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); + DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); + DP_TBFLAG_A64(flags, ZCR_LEN, zcr_len); } sctlr = regime_sctlr(env, stage1); if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + DP_TBFLAG_ANY(flags, BE_DATA, 1); } if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { @@ -13111,14 +13109,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, * The decision of which action to take is left to a helper. */ if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { - flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); } } if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { - flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); + DP_TBFLAG_A64(flags, BT, 1); } } @@ -13130,7 +13128,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, case ARMMMUIdx_SE10_1: case ARMMMUIdx_SE10_1_PAN: /* TODO: ARMv8.3-NV */ - flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + DP_TBFLAG_A64(flags, UNPRIV, 1); break; case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: @@ -13141,7 +13139,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, * gated by HCR_EL2. == '11', and so is LDTR. */ if (env->cp15.hcr_el2 & HCR_TGE) { - flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + DP_TBFLAG_A64(flags, UNPRIV, 1); } break; default: @@ -13159,24 +13157,23 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, * 4) If no Allocation Tag Access, then all accesses are Unchecked. */ if (allocation_tag_access_enabled(env, el, sctlr)) { - flags = FIELD_DP32(flags, TBFLAG_A64, ATA, 1); + DP_TBFLAG_A64(flags, ATA, 1); if (tbid && !(env->pstate & PSTATE_TCO) && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { - flags = FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1); + DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); } } /* And again for unprivileged accesses, if required. */ - if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV) + if (EX_TBFLAG_A64(flags, UNPRIV) && tbid && !(env->pstate & PSTATE_TCO) && (sctlr & SCTLR_TCF0) && allocation_tag_access_enabled(env, 0, sctlr)) { - flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1); + DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); } /* Cache TCMA as well as TBI. */ - flags = FIELD_DP32(flags, TBFLAG_A64, TCMA, - aa64_va_parameter_tcma(tcr, mmu_idx)); + DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); } return rebuild_hflags_common(env, fp_el, mmu_idx, flags); @@ -13272,10 +13269,10 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *cs_base = 0; assert_hflags_rebuild_correctly(env); - if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { + if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { *pc = env->pc; if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { - flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); + DP_TBFLAG_A64(flags, BTYPE, env->btype); } } else { *pc = env->regs[15]; @@ -13284,7 +13281,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { - flags = FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1); + DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); } if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && @@ -13296,12 +13293,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * active FP context; we must create a new FP context before * executing any FP insn. */ - flags = FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED, 1); + DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); } bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - flags = FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1); + DP_TBFLAG_M32(flags, LSPACT, 1); } } else { /* @@ -13309,21 +13306,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * Note that VECLEN+VECSTRIDE are RES0 for M-profile. */ if (arm_feature(env, ARM_FEATURE_XSCALE)) { - flags = FIELD_DP32(flags, TBFLAG_A32, - XSCALE_CPAR, env->cp15.c15_cpar); + DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); } else { - flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, - env->vfp.vec_len); - flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, - env->vfp.vec_stride); + DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); + DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { - flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + DP_TBFLAG_A32(flags, VFPEN, 1); } } - flags = FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb); - flags = FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_bits); + DP_TBFLAG_AM32(flags, THUMB, env->thumb); + DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); } /* @@ -13335,9 +13329,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 1 1 Active-not-pending * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. */ - if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && - (env->pstate & PSTATE_SS)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE__SS, 1); + if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { + DP_TBFLAG_ANY(flags, PSTATE__SS, 1); } *pflags = flags; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 64b3a5200c..05d83a5f7a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14684,28 +14684,28 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, !arm_el_is_aa64(env, 3); dc->thumb = 0; dc->sctlr_b = 0; - dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; + dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; dc->condexec_mask = 0; dc->condexec_cond = 0; - core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); + core_mmu_idx = EX_TBFLAG_ANY(tb_flags, MMUIDX); dc->mmu_idx = core_to_aa64_mmu_idx(core_mmu_idx); - dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); - dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID); - dc->tcma = FIELD_EX32(tb_flags, TBFLAG_A64, TCMA); + dc->tbii = EX_TBFLAG_A64(tb_flags, TBII); + dc->tbid = EX_TBFLAG_A64(tb_flags, TBID); + dc->tcma = EX_TBFLAG_A64(tb_flags, TCMA); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); - dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); - dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; - dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); - dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); - dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); - dc->unpriv = FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV); - dc->ata = FIELD_EX32(tb_flags, TBFLAG_A64, ATA); - dc->mte_active[0] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); - dc->mte_active[1] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE0_ACTIVE); + dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); + dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); + dc->sve_len = (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16; + dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); + dc->bt = EX_TBFLAG_A64(tb_flags, BT); + dc->btype = EX_TBFLAG_A64(tb_flags, BTYPE); + dc->unpriv = EX_TBFLAG_A64(tb_flags, UNPRIV); + dc->ata = EX_TBFLAG_A64(tb_flags, ATA); + dc->mte_active[0] = EX_TBFLAG_A64(tb_flags, MTE_ACTIVE); + dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; @@ -14732,10 +14732,10 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, * emit code to generate a software step exception * end the TB */ - dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); - dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS); + dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE); + dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS); dc->is_ldex = false; - dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); + dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); /* Bound the number of insns to execute to those left on the page. */ bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; diff --git a/target/arm/translate.c b/target/arm/translate.c index 45e320f4b3..6774d17e8f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8848,46 +8848,42 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) */ dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb = FIELD_EX32(tb_flags, TBFLAG_AM32, THUMB); - dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; - condexec = FIELD_EX32(tb_flags, TBFLAG_AM32, CONDEXEC); + dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB); + dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; + condexec = EX_TBFLAG_AM32(tb_flags, CONDEXEC); dc->condexec_mask = (condexec & 0xf) << 1; dc->condexec_cond = condexec >> 4; - core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); + core_mmu_idx = EX_TBFLAG_ANY(tb_flags, MMUIDX); dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); + dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled = 1; dc->be_data = MO_TE; - dc->v7m_handler_mode = FIELD_EX32(tb_flags, TBFLAG_M32, HANDLER); + dc->v7m_handler_mode = EX_TBFLAG_M32(tb_flags, HANDLER); dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && regime_is_secure(env, dc->mmu_idx); - dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_M32, STACKCHECK); - dc->v8m_fpccr_s_wrong = - FIELD_EX32(tb_flags, TBFLAG_M32, FPCCR_S_WRONG); + dc->v8m_stackcheck = EX_TBFLAG_M32(tb_flags, STACKCHECK); + dc->v8m_fpccr_s_wrong = EX_TBFLAG_M32(tb_flags, FPCCR_S_WRONG); dc->v7m_new_fp_ctxt_needed = - FIELD_EX32(tb_flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED); - dc->v7m_lspact = FIELD_EX32(tb_flags, TBFLAG_M32, LSPACT); + EX_TBFLAG_M32(tb_flags, NEW_FP_CTXT_NEEDED); + dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT); } else { - dc->be_data = - FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; - dc->debug_target_el = - FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); - dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR__B); - dc->hstr_active = FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE); - dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS); - dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); + dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); + dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B); + dc->hstr_active = EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE); + dc->ns = EX_TBFLAG_A32(tb_flags, NS); + dc->vfp_enabled = EX_TBFLAG_A32(tb_flags, VFPEN); if (arm_feature(env, ARM_FEATURE_XSCALE)) { - dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); + dc->c15_cpar = EX_TBFLAG_A32(tb_flags, XSCALE_CPAR); } else { - dc->vec_len = FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); - dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); + dc->vec_len = EX_TBFLAG_A32(tb_flags, VECLEN); + dc->vec_stride = EX_TBFLAG_A32(tb_flags, VECSTRIDE); } } dc->cp_regs = cpu->cp_regs; @@ -8908,8 +8904,8 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) * emit code to generate a software step exception * end the TB */ - dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); - dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS); + dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE); + dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS); dc->is_ldex = false; dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK; @@ -9353,11 +9349,11 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns) DisasContext dc = { }; const TranslatorOps *ops = &arm_translator_ops; - if (FIELD_EX32(tb->flags, TBFLAG_AM32, THUMB)) { + if (EX_TBFLAG_AM32(tb->flags, THUMB)) { ops = &thumb_translator_ops; } #ifdef TARGET_AARCH64 - if (FIELD_EX32(tb->flags, TBFLAG_ANY, AARCH64_STATE)) { + if (EX_TBFLAG_ANY(tb->flags, AARCH64_STATE)) { ops = &aarch64_translator_ops; } #endif From patchwork Fri Apr 16 18:59:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422563 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp649145jaf; Fri, 16 Apr 2021 12:04:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxdmbJ609b3a3iQFvOTSlhfe1e4JNY0H91SnaOVJ88mV+AV9eBr2v2lHSKS8dHB6z4JnqyR X-Received: by 2002:a92:d684:: with SMTP id p4mr8386624iln.150.1618599887948; Fri, 16 Apr 2021 12:04:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618599887; cv=none; d=google.com; s=arc-20160816; b=MChSNjh/LFLFhHJYLQklruKacv7s1m8b+5QI6QYG/CTZfUKH+j7sjDk4zIbPMEKaTC EX4jpu8LDm78eJciL+pqmDwyM+4nIDH4lN/xxM2OEZiol6a0Nsv8Hi3m9JqRxzXfTQUI Nybami8Lmt1voG/73i0JuGoqlFE0BTlasb72EbnVir/NowXJRcXiUeHqDX7V7t9/cAe7 tP0qCe08TaLV7IiOqFmigGDTxX1TJ8i35SEhsHdmUuGyQdJZJlka1GArX32xloJQMlHO U9yXPDAiYSEPK/HyneElJb0Y1H0a7TuaNGNLEGr2Vc+tQT8xpHsOojvXpyUWFH1qpDk9 runw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bDMvl+749g2gHgGetA4XPQIS7uWfkEL7qLXDdrTbRa4=; b=HWYe4ppJj+qsgg4icRf78F7J7omAtXNlmP60THyxWQGyOJCurShsDI06pYdxnRclyl oVb/YWzy4Ksp7v8Pat9ygmABl4Gv0Uj4OoJTFW07QqL+hIryhCqASSVxXU8YwgnHXaao EHn6KWhsuCfKqEJNL2qPkvUEf4QjaXpxqTvlcmfs8BmSJ9XogKnmZcX0umHw2RU43SMX N5s/9Wy63KrCBjm3ARLfO/3j6LCArngYa7pSd0BLZGcUIlNGa91SUYQDXxSl2wvN6aAd W3SzJmc3mpeNqoazrUjjIqpOPk11gyYYhydTP15D4iXBD2bg0/eFbhkyu+rb9Oy38UwN dYeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Wed6EZOs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p15si4604774ilo.83.2021.04.16.12.04.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:04:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Wed6EZOs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41658 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTln-0007Li-Bf for patch@linaro.org; Fri, 16 Apr 2021 15:04:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49932) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThP-0003Py-9z for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:17 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:45818) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThG-0004FS-Iy for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:11 -0400 Received: by mail-pg1-x533.google.com with SMTP id d10so19803684pgf.12 for ; Fri, 16 Apr 2021 12:00:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bDMvl+749g2gHgGetA4XPQIS7uWfkEL7qLXDdrTbRa4=; b=Wed6EZOsZy1yKcS98o9YTbBK75ky/cFMBa6fnpUIWByC1KzcRluLfH2+0zbGiEKFnn xI52qEaP5vLOx4qTsDegmKwYJ9BCy+h4z3lT98lIVQ2jWa4TZrBvNIS6QRJiuYRWumQD X/WYF/NZe/KcjF4BVsPAkPgPXLmfKnMcI0bxfrING/y9MCDruTrcFSBGaptM7RxSgnmv DW9F1pRcBl1dVHClSiTV+0NFzoIhEl28AEEWrjriRKvbcYjIIDAGHRhedPvqzrNyjqSI wta2uOt2v6pz7aTz5+nmh3Q9eEwIkRWMr6/7W802qTYNQzDlxxkA7BRL5AZg/cWVyO2L I7CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bDMvl+749g2gHgGetA4XPQIS7uWfkEL7qLXDdrTbRa4=; b=jse/D4Spp1htuxrnPXe/UUbvtVO8iAJwz81hCRNrOJB6b6mfC00WJvLq93ahUfrzzV XuohOrUiQTxYUKTMlkBFqRTAd7LzZvolvKn68Vk76TciHEcoiU7tBTV62nKU9nfam73R gZNUgdDUZ85AAJ8WpTFC7n6PN4Jh1AMCsES3IGYgjRfUtGp6HN6AQGwYwnfGB73J3TdL CHWmDoplTRoIqmAcF9+ZbcC9r/mLkinIvpN7s/5NWVyUcgiUHysqnwHi4Z5MCUODRQk6 TlGYfi98k57ccawwUj9cyNqR+UaaVdNyCc7eMJCagnn+Z1JuFwaVLZXFSKH+sPGfk8+l M6gw== X-Gm-Message-State: AOAM531DV+QTeoRba9GcXvAHzUu843CCJ3WvO0Rk/Y7YbbTeW5JH2p0o sf4ZA2sPQHxJightcLB2PpWEcV0rVN3Y7g== X-Received: by 2002:a05:6a00:212b:b029:259:73ac:7217 with SMTP id n11-20020a056a00212bb029025973ac7217mr5750045pfj.20.1618599605313; Fri, 16 Apr 2021 12:00:05 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/30] target/arm: Introduce CPUARMTBFlags Date: Fri, 16 Apr 2021 11:59:34 -0700 Message-Id: <20210416185959.1520974-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for splitting tb->flags across multiple fields, introduce a structure to hold the value(s). So far this only migrates the one uint32_t and fixes all of the places that require adjustment to match. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 26 +++++++++++--------- target/arm/translate.h | 11 +++++++++ target/arm/helper.c | 50 +++++++++++++++++++++----------------- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 7 +++--- 5 files changed, 59 insertions(+), 37 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b798ff8115..79af9a7c62 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -225,6 +225,10 @@ typedef struct ARMPACKey { } ARMPACKey; #endif +/* See the commentary above the TBFLAG field definitions. */ +typedef struct CPUARMTBFlags { + uint32_t flags; +} CPUARMTBFlags; typedef struct CPUARMState { /* Regs for current mode. */ @@ -253,7 +257,7 @@ typedef struct CPUARMState { uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ /* Cached TBFLAGS state. See below for which bits are included. */ - uint32_t hflags; + CPUARMTBFlags hflags; /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access @@ -3466,21 +3470,21 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) * Helpers for using the above. */ #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ - (DST = FIELD_DP32(DST, TBFLAG_ANY, WHICH, VAL)) + (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) #define DP_TBFLAG_A64(DST, WHICH, VAL) \ - (DST = FIELD_DP32(DST, TBFLAG_A64, WHICH, VAL)) + (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A64, WHICH, VAL)) #define DP_TBFLAG_A32(DST, WHICH, VAL) \ - (DST = FIELD_DP32(DST, TBFLAG_A32, WHICH, VAL)) + (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A32, WHICH, VAL)) #define DP_TBFLAG_M32(DST, WHICH, VAL) \ - (DST = FIELD_DP32(DST, TBFLAG_M32, WHICH, VAL)) + (DST.flags = FIELD_DP32(DST.flags, TBFLAG_M32, WHICH, VAL)) #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ - (DST = FIELD_DP32(DST, TBFLAG_AM32, WHICH, VAL)) + (DST.flags = FIELD_DP32(DST.flags, TBFLAG_AM32, WHICH, VAL)) -#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN, TBFLAG_ANY, WHICH) -#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN, TBFLAG_A64, WHICH) -#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN, TBFLAG_A32, WHICH) -#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN, TBFLAG_M32, WHICH) -#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN, TBFLAG_AM32, WHICH) +#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) +#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A64, WHICH) +#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A32, WHICH) +#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_M32, WHICH) +#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_AM32, WHICH) /** * cpu_mmu_index: diff --git a/target/arm/translate.h b/target/arm/translate.h index 423b0e08df..f30287e554 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -394,6 +394,17 @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); +/** + * arm_tbflags_from_tb: + * @tb: the TranslationBlock + * + * Extract the flag values from @tb. + */ +static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) +{ + return (CPUARMTBFlags){ tb->flags }; +} + /* * Enum for argument to fpstatus_ptr(). */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 2769e6fd35..9070b773a9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12984,8 +12984,9 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif -static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx, uint32_t flags) +static CPUARMTBFlags +rebuild_hflags_common(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, CPUARMTBFlags flags) { DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); @@ -12996,8 +12997,9 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, return flags; } -static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx, uint32_t flags) +static CPUARMTBFlags +rebuild_hflags_common_32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, CPUARMTBFlags flags) { bool sctlr_b = arm_sctlr_b(env); @@ -13012,10 +13014,10 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } -static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags +rebuild_hflags_m32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - uint32_t flags = 0; + CPUARMTBFlags flags = {}; if (arm_v7m_is_handler_mode(env)) { DP_TBFLAG_M32(flags, HANDLER, 1); @@ -13035,18 +13037,19 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } -static uint32_t rebuild_hflags_aprofile(CPUARMState *env) +static CPUARMTBFlags +rebuild_hflags_aprofile(CPUARMState *env) { - int flags = 0; + CPUARMTBFlags flags = {}; DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); return flags; } -static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags +rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - uint32_t flags = rebuild_hflags_aprofile(env); + CPUARMTBFlags flags = rebuild_hflags_aprofile(env); if (arm_el_is_aa64(env, 1)) { DP_TBFLAG_A32(flags, VFPEN, 1); @@ -13060,10 +13063,10 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } -static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags +rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { - uint32_t flags = rebuild_hflags_aprofile(env); + CPUARMTBFlags flags = rebuild_hflags_aprofile(env); ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint64_t sctlr; @@ -13179,7 +13182,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } -static uint32_t rebuild_hflags_internal(CPUARMState *env) +static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) { int el = arm_current_el(env); int fp_el = fp_exception_el(env, el); @@ -13208,6 +13211,7 @@ void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) int el = arm_current_el(env); int fp_el = fp_exception_el(env, el); ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); } @@ -13228,6 +13232,7 @@ void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) int el = arm_current_el(env); int fp_el = fp_exception_el(env, el); ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); } @@ -13250,12 +13255,12 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) static inline void assert_hflags_rebuild_correctly(CPUARMState *env) { #ifdef CONFIG_DEBUG_TCG - uint32_t env_flags_current = env->hflags; - uint32_t env_flags_rebuilt = rebuild_hflags_internal(env); + CPUARMTBFlags c = env->hflags; + CPUARMTBFlags r = rebuild_hflags_internal(env); - if (unlikely(env_flags_current != env_flags_rebuilt)) { + if (unlikely(c.flags != r.flags)) { fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", - env_flags_current, env_flags_rebuilt); + c.flags, r.flags); abort(); } #endif @@ -13264,10 +13269,11 @@ static inline void assert_hflags_rebuild_correctly(CPUARMState *env) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - uint32_t flags = env->hflags; + CPUARMTBFlags flags; *cs_base = 0; assert_hflags_rebuild_correctly(env); + flags = env->hflags; if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { *pc = env->pc; @@ -13333,7 +13339,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, DP_TBFLAG_ANY(flags, PSTATE__SS, 1); } - *pflags = flags; + *pflags = flags.flags; } #ifdef TARGET_AARCH64 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 05d83a5f7a..b32ff56666 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14670,7 +14670,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; ARMCPU *arm_cpu = env_archcpu(env); - uint32_t tb_flags = dc->base.tb->flags; + CPUARMTBFlags tb_flags = arm_tbflags_from_tb(dc->base.tb); int bound, core_mmu_idx; dc->isar = &arm_cpu->isar; diff --git a/target/arm/translate.c b/target/arm/translate.c index 6774d17e8f..5cec3966d6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8836,7 +8836,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cs->env_ptr; ARMCPU *cpu = env_archcpu(env); - uint32_t tb_flags = dc->base.tb->flags; + CPUARMTBFlags tb_flags = arm_tbflags_from_tb(dc->base.tb); uint32_t condexec, core_mmu_idx; dc->isar = &cpu->isar; @@ -9348,12 +9348,13 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns) { DisasContext dc = { }; const TranslatorOps *ops = &arm_translator_ops; + CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb); - if (EX_TBFLAG_AM32(tb->flags, THUMB)) { + if (EX_TBFLAG_AM32(tb_flags, THUMB)) { ops = &thumb_translator_ops; } #ifdef TARGET_AARCH64 - if (EX_TBFLAG_ANY(tb->flags, AARCH64_STATE)) { + if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) { ops = &aarch64_translator_ops; } #endif From patchwork Fri Apr 16 18:59:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422566 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp651398jaf; Fri, 16 Apr 2021 12:07:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxkkdUv95U60lAV7uVx4lo8yDS0eSbyUxg01you8w3wCILLaApJRjPMxu+0kcs7Ebw0MUlv X-Received: by 2002:a02:77d6:: with SMTP id g205mr5460509jac.44.1618600075849; Fri, 16 Apr 2021 12:07:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600075; cv=none; d=google.com; s=arc-20160816; b=uqtcn/RB0sHCgn/+sY6odo9J699rVG9kOIYrUAu4UZj9QjdY0ZNgfAMqUAfWzw7G4N gZVhAOvjkENtqs7iuQ+QIVTNS7Nx1Dqh91JcT4ylj62S7fS8zaKyMq1lpMwBWy0fuWMg 7FK7QYP3prtPEbHzQFCYjLOtsr01H1KsnDTbxuPxb9qC5/63TsAdVAVQNTOV2J2gheCI 9M3zj4eGATZnodVyGWQYjxm8N+/2dMUwgOvipK9byOY5qOvQe56XjFSayzf3cqjWQlRT AEp0o0huntij5YjCzdENmV9CYi+YqEQATr2rTo6tB4qvfgKRP0bBfxr/vcgewxM+Aqrp NafA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=L/RYbqAiFAcdBNCHFx5fvkgfYEDJ6jX69rjW9+yXFZA=; b=Bd3cnZa3LcsXwuF+rhadECCJZwIAZleJjEyUcICBVlmqDpqsG63LEuFIKVS06iSPyD rtOG1wMA6y+XXbh+OFTo3tcyyWzugBQZkQWPFhxhwp5zLM2UTDGES9kaZQBCDEQ0uyeb DDRDsiw/b5FilTKd/wlCduZHU0OkOP7M/flLzTb2yF4/g/OkwYXf6r9mHS3LUaJMgeLx W7RoVfg951CiP/ayyZn2SyiBsB8jvZFHDo5FlLzzh0WJxHn7x4Q2+y+x/lAPslwNp+/1 WnBPmQyKvjLAVMqQHiM+bGkyqZl1PcMfqoqFfy7bANe20nv1mY2m82JJ1RunCc8xVQB2 ekAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HA4IRj2b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r12si6608460jao.41.2021.04.16.12.07.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:07:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HA4IRj2b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTop-0002fS-8U for patch@linaro.org; Fri, 16 Apr 2021 15:07:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThU-0003Qi-RT for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:22 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:34717) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThH-0004Gg-Iz for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:20 -0400 Received: by mail-pg1-x533.google.com with SMTP id z16so19807724pga.1 for ; Fri, 16 Apr 2021 12:00:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L/RYbqAiFAcdBNCHFx5fvkgfYEDJ6jX69rjW9+yXFZA=; b=HA4IRj2bqRw/IZm0L+FQakcyO/pIAfpOjeEdaAbNQymJATjvxxk05+yJjnDqwIMQIe vrCLHvHFY5f5lm95QO9FOZOLgkg4XHFGy2oQY4Qa/6fJBF7I7xMKVk3lQC5kssbAOJeM hzJeUP4X4jtBGfDze5m5kP7KCBxtK+TgQoaiQqeJsXiXTgEfVIptnc9xGFID0eQNxmgU /I1Pf0JiBSZw6ss93NYilbnmeYU9E9EwE+kH/1kjUCv7lbhSdBnxENtrYcw2Ci0FwRiL 0sLx5z47aGXDa9QYFCimPYt3lVfQYsRpYWeFz/XXjGXvjsDYL5tlAPiALxcP7GuK2YaJ s/uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L/RYbqAiFAcdBNCHFx5fvkgfYEDJ6jX69rjW9+yXFZA=; b=kqJ5mEpnq2QzemKqy1Eil8Ymun47m0gcC21LOXK2qtEd2N4pbgu1vgq19MuOS8Jnsb 22fbte4RmVBE4Mk6f1vDByuJiHzoguWhcaZexqMgRt8kNzC3iPypbijRhBHLg01OTlwb vWzflwX4Fn5K4OVRHvmQiusS3Wbr+KJc9vGt6Nm7UEmxXVdqwNB6EoN8Yp+FsC+CkLiz wLbZlkg1f6iEdB9Hik+tBas3g5ccmVnxE0y/TsOhqPEmuJ1BCARlbAm3L8sM21mew5Ez Ha39kkiWwxMwY9/s2UHTQb1A8HPHGkh02+vzs1RalNRFuSVVr7JXFm4y6Rpe5oL0jM6o KzyQ== X-Gm-Message-State: AOAM530/GzZGsPoFC3/dmbXfVIbbJVPjgQ1nTSFwIWz6IbEVozSJ97NZ Og+VCyhSsBxHeeA31IBbeIhiGToB7sPG0Q== X-Received: by 2002:a65:4202:: with SMTP id c2mr480869pgq.282.1618599606265; Fri, 16 Apr 2021 12:00:06 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/30] target/arm: Move mode specific TB flags to tb->cs_base Date: Fri, 16 Apr 2021 11:59:35 -0700 Message-Id: <20210416185959.1520974-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that we have all of the proper macros defined, expanding the CPUARMTBFlags structure and populating the two TB fields is relatively simple. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 49 ++++++++++++++++++++++++------------------ target/arm/translate.h | 2 +- target/arm/helper.c | 2 +- 3 files changed, 30 insertions(+), 23 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 79af9a7c62..a8da7c55a6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -228,6 +228,7 @@ typedef struct ARMPACKey { /* See the commentary above the TBFLAG field definitions. */ typedef struct CPUARMTBFlags { uint32_t flags; + target_ulong flags2; } CPUARMTBFlags; typedef struct CPUARMState { @@ -3381,20 +3382,26 @@ typedef ARMCPU ArchCPU; #include "exec/cpu-all.h" /* - * Bit usage in the TB flags field: bit 31 indicates whether we are - * in 32 or 64 bit mode. The meaning of the other bits depends on that. - * We put flags which are shared between 32 and 64 bit mode at the top - * of the word, and flags which apply to only one mode at the bottom. + * We have more than 32-bits worth of state per TB, so we split the data + * between tb->flags and tb->cs_base, which is otherwise unused for ARM. + * We collect these two parts in CPUARMTBFlags where they are named + * flags and flags2 respectively. * - * 31 20 18 14 9 0 - * +--------------+-----+-----+----------+--------------+ - * | | | TBFLAG_A32 | | - * | | +-----+----------+ TBFLAG_AM32 | - * | TBFLAG_ANY | |TBFLAG_M32| | - * | +-----------+----------+--------------| - * | | TBFLAG_A64 | - * +--------------+-------------------------------------+ - * 31 20 0 + * The flags that are shared between all execution modes, TBFLAG_ANY, + * are stored in flags. The flags that are specific to a given mode + * are stores in flags2. Since cs_base is sized on the configured + * address size, flags2 always has 64-bits for A64, and a minimum of + * 32-bits for A32 and M32. + * + * The bits for 32-bit A-profile and M-profile partially overlap: + * + * 18 9 0 + * +----------------+--------------+ + * | TBFLAG_A32 | | + * +-----+----------+ TBFLAG_AM32 | + * | |TBFLAG_M32| | + * +-----+----------+--------------+ + * 14 9 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3472,19 +3479,19 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) #define DP_TBFLAG_A64(DST, WHICH, VAL) \ - (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A64, WHICH, VAL)) + (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) #define DP_TBFLAG_A32(DST, WHICH, VAL) \ - (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A32, WHICH, VAL)) + (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) #define DP_TBFLAG_M32(DST, WHICH, VAL) \ - (DST.flags = FIELD_DP32(DST.flags, TBFLAG_M32, WHICH, VAL)) + (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ - (DST.flags = FIELD_DP32(DST.flags, TBFLAG_AM32, WHICH, VAL)) + (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) -#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A64, WHICH) -#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A32, WHICH) -#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_M32, WHICH) -#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_AM32, WHICH) +#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) +#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) +#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) +#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) /** * cpu_mmu_index: diff --git a/target/arm/translate.h b/target/arm/translate.h index f30287e554..50c2aba066 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -402,7 +402,7 @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); */ static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) { - return (CPUARMTBFlags){ tb->flags }; + return (CPUARMTBFlags){ tb->flags, tb->cs_base }; } /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 9070b773a9..85b7d6add0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13271,7 +13271,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, { CPUARMTBFlags flags; - *cs_base = 0; assert_hflags_rebuild_correctly(env); flags = env->hflags; @@ -13340,6 +13339,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } *pflags = flags.flags; + *cs_base = flags.flags2; } #ifdef TARGET_AARCH64 From patchwork Fri Apr 16 18:59:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422570 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp653508jaf; Fri, 16 Apr 2021 12:11:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz7SE+NIEOMUm7tq7hKvE4rgkPpTVmkpAfutmolTTB8pHtyQxcydchpb2lN9PlMjqnKq5bj X-Received: by 2002:a7b:c10e:: with SMTP id w14mr9482535wmi.8.1618600288278; Fri, 16 Apr 2021 12:11:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600288; cv=none; d=google.com; s=arc-20160816; b=hpyonpujZNHI2EtBsH33MrWjUIegmbEhSWS+2SRDNUQ/nVPOJZEiJ+FM5PLYRpvvwl Cyj1U8AAhG3FEk5AgoC8Qh5UjolgeM5opN64Yls/75pe8qpq3y4GCNjpHHUFHrHIwTAf 3Z5pKlHMeLWgM1VSQLTt+Z2U86ZNGlP4dLn3C0CbLjzhybP9/CZU4fOLQyjgZ5VfpCt9 0qnm9y1bJSKP87QYvA1/UZXvzzm3JpdsstAywetyGXqAUSq1P+JBu/3ZYuIslmFkxoWI fXBGgV28bPMs+Y6FBJ97D3tGobZ2K+79seZwtA+3uc5DhlJYRFirFtS8IgYCckT5596c VmiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cT3QO7VItfU2VrQhqJUimeA2gkAab7Ike6sYupHt1Ns=; b=vTBpwbDU2FICNC/rgCRSOvM3cQ7xx1atFfEhRuOpqh+xCbmv3aWP9ivsI8e4yrqGlr jPNlOCdxdJRAip2o9KFVFa180cxL4p2tixa6mZQyHDuBgfH2BGIB2a74W4EKqFdi22Av kx0s6l9a7ntzR3kOcKq6+3n3wpyEjsJBu4DkRs6M3BTea0yq/uR3kaAVJvdJJdh5TY8C k+d3xAn8rCHmjRLChXl49cIm4t1wDlb6Q6LzNJMMB/gl0jOkSUCcRdJMTrHShMuI1fme stESqtzOZ7OlCKNHEM3uINGsQNFD6Mke3Egp4Bb0j8vuTnPTxLdHZwnETW8TN/uhjmtN SB/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OfrSZ+OM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c10si1163858wrr.68.2021.04.16.12.11.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:11:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OfrSZ+OM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60172 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTsD-0006w4-67 for patch@linaro.org; Fri, 16 Apr 2021 15:11:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXTha-0003Tj-LX for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:28 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:36424) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThI-0004H8-HC for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:26 -0400 Received: by mail-pl1-x62f.google.com with SMTP id z22so9349577plo.3 for ; Fri, 16 Apr 2021 12:00:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cT3QO7VItfU2VrQhqJUimeA2gkAab7Ike6sYupHt1Ns=; b=OfrSZ+OMHSbYGaGqVds/CA0XLpHG8fQUkcOxqjtCIRNJvla5b0ZpPGx698A9KZv1RX 9Lko5708APj3y2qm6pVVPSpJ2R2oqPApUidWVyeQcma9ZOrPreUoMXfmdsx4y5kRVofy 1LhY1AHZHMY/vQwsFJdjaYwrn6akSs5DgehiaCX9Vdzpu8McgoLyWZtuT7N+u3UjE720 K0jE4Pi6M8QMcgKYe8YE1aM8TN3Zszi40+D/DKI57nLhmUYxafJyUasLw4fGX/o/JDAc pVDU5DZQ0/6MwvVTVFnzSpmbQWmOpzu72LmX8ToH6/dzmZfFIGZ95/iFUrXe/BkFA50x jjQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cT3QO7VItfU2VrQhqJUimeA2gkAab7Ike6sYupHt1Ns=; b=izBddjLQiF7uSquc4eLQJDrLNqdHfNnBlzsnBraPzjaYpVQTupHnO9cYw/H5o431Zx aMAKUE1PZEoM/4LiVtG/msE/Yu+sKTCQ+J9w0yLYoudGyKZjn8543JRUfRbvrw9dELo7 i0N1ICTRQun+Ku7g4Y+opZwO0gO1+lfdT8hdm2Xsl7zh9W2keZ5HlwmO5kxZZMKluxgX tjChqMuEC1HQx/7zHnFJtIfzCPAuZyx4DaOyxJLHIwJQlyjXvsXmaL8xwkCay063OSj5 6vp2FUOcLB/I7qgLMuRFrYrFf8gZlggqaf0GLTR+RABB9GX02xz3IcS80shXo9hPbYrG nunw== X-Gm-Message-State: AOAM530cUQwR3/hTHHJwL2lIOV1Pj52tW8wvfaW9p17K5xGrP3b/pOjc L+LMSqXCvUru4ceLNmmOIkqYvci/8yu4BQ== X-Received: by 2002:a17:90a:a22:: with SMTP id o31mr11466660pjo.127.1618599607144; Fri, 16 Apr 2021 12:00:07 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/30] target/arm: Move TBFLAG_AM32 bits to the top Date: Fri, 16 Apr 2021 11:59:36 -0700 Message-Id: <20210416185959.1520974-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that these bits have been moved out of tb->flags, where TBFLAG_ANY was filling from the top, move AM32 to fill from the top, and A32 and M32 to fill from the bottom. This means fewer changes when adding new bits. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a8da7c55a6..15104e1440 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3395,13 +3395,13 @@ typedef ARMCPU ArchCPU; * * The bits for 32-bit A-profile and M-profile partially overlap: * - * 18 9 0 - * +----------------+--------------+ - * | TBFLAG_A32 | | - * +-----+----------+ TBFLAG_AM32 | - * | |TBFLAG_M32| | - * +-----+----------+--------------+ - * 14 9 0 + * 31 23 11 10 0 + * +-------------+----------+----------------+ + * | | | TBFLAG_A32 | + * | TBFLAG_AM32 | +-----+----------+ + * | | |TBFLAG_M32| + * +-------------+----------------+----------+ + * 31 23 5 4 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3418,44 +3418,44 @@ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) /* * Bit usage when in AArch32 state, both A- and M-profile. */ -FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ -FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */ +FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ +FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ /* * Bit usage when in AArch32 state, for A-profile only. */ -FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ -FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ +FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. * Not cached, because VECLEN+VECSTRIDE are not cached. */ -FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) -FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */ -FIELD(TBFLAG_A32, SCTLR__B, 15, 1) /* Cannot overlap with SCTLR_B */ -FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) +FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ +FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ +FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) /* * Indicates whether cp register reads and writes by guest code should access * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -FIELD(TBFLAG_A32, NS, 17, 1) +FIELD(TBFLAG_A32, NS, 10, 1) /* * Bit usage when in AArch32 state, for M-profile only. */ /* Handler (ie not Thread) mode */ -FIELD(TBFLAG_M32, HANDLER, 9, 1) +FIELD(TBFLAG_M32, HANDLER, 0, 1) /* Whether we should generate stack-limit checks */ -FIELD(TBFLAG_M32, STACKCHECK, 10, 1) +FIELD(TBFLAG_M32, STACKCHECK, 1, 1) /* Set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */ +FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ /* Set if we must create a new FP context */ -FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */ +FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ /* Set if FPCCR.S does not match current security state */ -FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */ +FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ /* * Bit usage when in AArch64 state From patchwork Fri Apr 16 18:59:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422564 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp650268jaf; Fri, 16 Apr 2021 12:06:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwUHRNoj2nfHUbS5T4mF4mDLnnn95s52s7jJdp/R7VZogAweAPWIUnNrAFXkxHD/6YsMFcq X-Received: by 2002:a05:6638:2605:: with SMTP id m5mr5252779jat.97.1618599979940; Fri, 16 Apr 2021 12:06:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618599979; cv=none; d=google.com; s=arc-20160816; b=VclBXGVfz0UbAjqVBn1Zbsn+W9eAzPcNNCPyOfeVZZKnE1iztqHlxb4vSj/aYxymFw kWFZy9VubGiRMENabyXqOSXtNBqVKHzMKWYTy7bf0/PViXyYmrLTXCeaBtZQ5lWZXak+ aA+aZnCy0h+7+0EtnhvhkmoV3i9NBj2e2Eu/w318xUafoxW8yOa6qSunzCXYncHQRv1o cr7IuO+sqDF8CV+se+z3sDcFQhsMXAlYn9Mj2i5giu9OggK3/patsfl92h6nnN2bFpVR X6xhIqqgNKlXyWvWe6tnJFNFQ+/j0x9fHM13vjnZBvD6v9A6lMfw3b7l73AafK4sh0uJ tUSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=M4Ye/q/NQMpivvWde1aRm1kTY6gKWaOpl13EHd3UchY=; b=pl6m2wV+RvoX85otSQJT87I8JfEILLo+KTE8/pl3OhbQrVn/vxrrPVMFeHED9/yrBO K9av367NuQZzJD20It/U9sBr8OngIuswQw9VxuPMb1i8W2f7F6aNXuABugMceSR5wSBy BbvC2bwVK/468vyn9cCuevj219OQJYV6MmDXHfqq1eGDR2MNuquHKlxwd42WmMTF/5g8 3sj53FvelHIaBHRHsh2jMyMz0ZbD5pUmJW5XBhKceWqBR8mSOIkB/4gu7ekoIx3H59dX kWiSJaGHoKh0Pj/la1SvimKje/SVkKe272B/tOREiskjQQImTfH5IwauT2fULCrU/3GH bQSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eGtD80B8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v20si3822265jal.8.2021.04.16.12.06.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:06:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eGtD80B8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTnH-0000cm-BN for patch@linaro.org; Fri, 16 Apr 2021 15:06:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThc-0003Ty-Pb for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:28 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:35630) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThK-0004HZ-Rj for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:28 -0400 Received: by mail-pj1-x1034.google.com with SMTP id j21-20020a17090ae615b02901505b998b45so1587728pjy.0 for ; Fri, 16 Apr 2021 12:00:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M4Ye/q/NQMpivvWde1aRm1kTY6gKWaOpl13EHd3UchY=; b=eGtD80B8SK/We0er8fyLcUX+80k4fRcPW5KyDxgoy6/UtBfHUcCuJqqyhq+pDOFzi6 NtuKh0R+dfzaQYm8LrT34QtVrVITxW5TiyPQ2Kp9kv5hbvN5hTSBQDcTRD0AqSmyUo+T Eg0/UIrifYor0ubm5kya0auCbZ9MjS8nGBXEa26CfKRYNqxF+8UVZg70LwxjNPil1eh2 lGexOP/8biV9sYqGDkn2Bnem1F5kb01U3dLsCu6di/49V5D85vjraapvrO3PjrFjYWDA DuJ0uKahxL006xcnN5ZcdtPXNdRxjUHhriNvs6jzDHF66BKtvDI+pAgoxXQVb94YV2Cg W9/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M4Ye/q/NQMpivvWde1aRm1kTY6gKWaOpl13EHd3UchY=; b=PIs541IsWvFRbvCPfcukmQFGt0lNwROnkQy/frwrkACajJBW5k8XLcFF5eLLuQglov xrKj7D7ukLVGpbKyD7N6QtWbdQ2RbX3GpStw2HjKYCjOfLgKlH5Fq4yKeViQm3ffh7yl Nac31jymSlL0g7dY52DP7T16ug413eazGftL3RZxWDHxo5oJBnHTjtcbOqRw7cd1cIZ0 3nh9c+vwPEp5I/eJCoEGoTDiPzCoMxHLBix/+MB2ZW8Z9phxBiXRc/2QzSANJ4dXgiFD wsS9CzicrsWAvVS1f5lSV4oBO+5fBl+X+f/APcjlTgNlI6KLuk8ZsKfXfos83/P5/NML Tv6Q== X-Gm-Message-State: AOAM532xb1I9pbQz5dQQHamJM8Hyn6tUljkmS3FFpldiDSa7I/WNKvyR PakP6ZC4Ja8fV+z/nGWPYrp6VK+tbyUpHg== X-Received: by 2002:a17:90a:9503:: with SMTP id t3mr10141909pjo.220.1618599608167; Fri, 16 Apr 2021 12:00:08 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/30] target/arm: Move TBFLAG_ANY bits to the bottom Date: Fri, 16 Apr 2021 11:59:37 -0700 Message-Id: <20210416185959.1520974-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that other bits have been moved out of tb->flags, there's no point in filling from the top. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 15104e1440..5e0131be1a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3405,15 +3405,15 @@ typedef ARMCPU ArchCPU; * * Unless otherwise noted, these bits are cached in env->hflags. */ -FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) -FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) -FIELD(TBFLAG_ANY, PSTATE__SS, 29, 1) /* Not cached. */ -FIELD(TBFLAG_ANY, BE_DATA, 28, 1) -FIELD(TBFLAG_ANY, MMUIDX, 24, 4) +FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) +FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) +FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, BE_DATA, 3, 1) +FIELD(TBFLAG_ANY, MMUIDX, 4, 4) /* Target EL if we take a floating-point-disabled exception */ -FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) +FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) /* For A-profile only, target EL for debug exceptions. */ -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) +FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) /* * Bit usage when in AArch32 state, both A- and M-profile. From patchwork Fri Apr 16 18:59:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422573 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp654634jaf; Fri, 16 Apr 2021 12:13:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwsKerDlkC7gOrRP2mTyynk0z71slZXi6q+TdXHBByv3oFx5M0CsVrX4ahLwExxXlZL+lc5 X-Received: by 2002:a02:a38f:: with SMTP id y15mr5473513jak.106.1618600386840; Fri, 16 Apr 2021 12:13:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600386; cv=none; d=google.com; s=arc-20160816; b=FOIPTLbSZ9VTZKXNhG49vNqk+ukY41aZlQEYPIp75VEGGAqvz9EaB0TlsBYkUAgOku E3T9PsXG0UZRaN+oijKNAO3cTs8dLktmFcuBLvaNKpNlXs7Vt+NWFFHBKmhtoflL72+d c10MX9Zq0b772ry3sdV9XplWbKGkCbsI4ssg4+4fie0Ch9KM8XvTV+xR0OxoNn4m+MRN 0DkjS6WrkX72L1YEV7ou8ewfYquVCDGNtYdmIF+Z8Rm44lL3NDXGyC+dbgFSrgnhfcz1 aWo4TYWkuFQKMcL8qW+hpXfQlzqzQOhj4LwynNE605R6itnxjnoq7x/xIQWu8XxeIMbz FsnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QHXjEWeEZoO88te/rMgSkF0yOBhiok3uM+pUtZ6x5+A=; b=J0xCCdomK5EhO5Ca1VHWX6FEQKDXmKAQyKGXv7+PuSIzw4fLjyJnkBoC7xNJBTWNU3 G52yvls7c4F4YNJM1yjxmULEMK3SYkWjJ7wC4VuWkevN/mIM06nUKhMvkZ2WJfEK+3RC 8bl9qvUVAgxx0VOsypUW14uqsavj0Bbk0GyXgR1Vs3rrcZyVaNEuNHv5/9Pk7jcUHmAW ldGhzn9HfbYoRWRoCbhGumcbQChbJuMRjWXYN7ZcZ3uL917UxqooB642LCTHoKKbjTm7 qw3l5QTDSLzCpewqabzlNo55ql8wx+5uiErgD7Oe3xuzy7uf/z9jZ8bwHyKBe/YLo8JH mwWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sAEtib0E; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s1si4333286iob.72.2021.04.16.12.13.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:13:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sAEtib0E; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTtq-0002TX-Au for patch@linaro.org; Fri, 16 Apr 2021 15:13:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50180) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThd-0003X7-T8 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:29 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:34720) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThN-0004Hv-TC for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:29 -0400 Received: by mail-pg1-x536.google.com with SMTP id z16so19807841pga.1 for ; Fri, 16 Apr 2021 12:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QHXjEWeEZoO88te/rMgSkF0yOBhiok3uM+pUtZ6x5+A=; b=sAEtib0EZTLF04Gml9jvd12EvCw4TpiecJtqtvHj8t3lao2DAixQdIPuDfmKyIaiy/ 4/ikXR/5q2Ak2LWRhyPMY05vTFfQnbAPT1GzVqIiA9ZDgFihraFw1yCrSsonBFvMmbjW eMr4XE84Awb5VlrY+ziZQHY001Kd7LIxgz0dnoVizUNJ2sGz2CBp9AZDNG5CFrpTTEKI 9upwx8HAc9jDCrh7f6Q81EPwGUBz7e2Cw7NTuyfPMaKa/Nj+r20dDSyfpte8tqhlXyhy kZY0giHlcxi6Xq0Xixgfd7A/zZwoUm6gq3qx+uuN8CS4AV2QvaimqYJcD6AjnxUD4Zz+ HB6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QHXjEWeEZoO88te/rMgSkF0yOBhiok3uM+pUtZ6x5+A=; b=OvWT8biv+YFRS+HZMJnyWwYW6Qh77VyGjEQJdfWKLlAIWKFlrBFPUSzWqG+3JIBdX5 AiUC8kf21Waj6UnZV+AG2Y/muMoKNpz/F5yL6BKX6vBe0t8z+xKNh0ZxhFZMH3dPlH6B aK4KqfvG9d97pB2G5o86VrLBB2WOwXuSgbatc7IRbotjizopreEQGQ+cnU74+haSN3sH M4quz3RtM9h6gfWzhHADNn5JngKXcrJkugq0gzd73i7bRoEWoLQcRUYhHRH9+1dMi4Sz ILm/VIKGyQjOqFO7ZERAKdSZ+q/r0YzCvEcyobKjcdBcWHP0cm5+5uq2bhXrFMKYdvtU ihFQ== X-Gm-Message-State: AOAM533LCZfV1ymsS1eRIYio4iDxB631RPYCL4kklBHtSEb7YP04ZAkG YNsTlMCIoYyLn5QQFu5EhcuPEFxzvLeGbw== X-Received: by 2002:a62:6883:0:b029:220:4426:449c with SMTP id d125-20020a6268830000b02902204426449cmr8860757pfc.14.1618599609034; Fri, 16 Apr 2021 12:00:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/30] target/arm: Add ALIGN_MEM to TBFLAG_ANY Date: Fri, 16 Apr 2021 11:59:38 -0700 Message-Id: <20210416185959.1520974-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use this to signal when memory access alignment is required. This value comes from the CCR register for M-profile, and from the SCTLR register for A-profile. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 2 ++ target/arm/helper.c | 19 +++++++++++++++++-- target/arm/translate-a64.c | 1 + target/arm/translate.c | 7 +++---- 5 files changed, 25 insertions(+), 6 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5e0131be1a..616b393253 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3414,6 +3414,8 @@ FIELD(TBFLAG_ANY, MMUIDX, 4, 4) FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) /* For A-profile only, target EL for debug exceptions. */ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) +/* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ +FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/translate.h b/target/arm/translate.h index 50c2aba066..b185c14a03 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -87,6 +87,8 @@ typedef struct DisasContext { bool bt; /* True if any CP15 access is trapped by HSTR_EL2 */ bool hstr_active; + /* True if memory operations require alignment */ + bool align_mem; /* * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index 85b7d6add0..cd92a22689 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13018,6 +13018,12 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { CPUARMTBFlags flags = {}; + uint32_t ccr = env->v7m.ccr[env->v7m.secure]; + + /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ + if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); + } if (arm_v7m_is_handler_mode(env)) { DP_TBFLAG_M32(flags, HANDLER, 1); @@ -13030,7 +13036,7 @@ rebuild_hflags_m32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) */ if (arm_feature(env, ARM_FEATURE_V8) && !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && - (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { + (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { DP_TBFLAG_M32(flags, STACKCHECK, 1); } @@ -13050,12 +13056,17 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { CPUARMTBFlags flags = rebuild_hflags_aprofile(env); + int el = arm_current_el(env); + + if (arm_sctlr(env, el) & SCTLR_A) { + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); + } if (arm_el_is_aa64(env, 1)) { DP_TBFLAG_A32(flags, VFPEN, 1); } - if (arm_current_el(env) < 2 && env->cp15.hstr_el2 && + if (el < 2 && env->cp15.hstr_el2 && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } @@ -13100,6 +13111,10 @@ rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) sctlr = regime_sctlr(env, stage1); + if (sctlr & SCTLR_A) { + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); + } + if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { DP_TBFLAG_ANY(flags, BE_DATA, 1); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b32ff56666..92a62b1a75 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14697,6 +14697,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->user = (dc->current_el == 0); #endif dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); + dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sve_len = (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16; dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); diff --git a/target/arm/translate.c b/target/arm/translate.c index 5cec3966d6..51897a5113 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -933,8 +933,7 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, { TCGv addr; - if (arm_dc_feature(s, ARM_FEATURE_M) && - !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { + if (s->align_mem) { opc |= MO_ALIGN; } @@ -948,8 +947,7 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, { TCGv addr; - if (arm_dc_feature(s, ARM_FEATURE_M) && - !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { + if (s->align_mem) { opc |= MO_ALIGN; } @@ -8861,6 +8859,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->user = (dc->current_el == 0); #endif dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); + dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled = 1; From patchwork Fri Apr 16 18:59:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422581 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp657917jaf; Fri, 16 Apr 2021 12:18:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwYW3FgewgwLHMutBHeOrAfqmmWtFRHdsJWPGQx7g3rBZYeYcNDnvJc7jMwer2vvILbNIql X-Received: by 2002:a05:6638:238c:: with SMTP id q12mr5565212jat.114.1618600697132; Fri, 16 Apr 2021 12:18:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600697; cv=none; d=google.com; s=arc-20160816; b=ZXsWHbJgfxtKb2biCWJPMdj608q15zgOwkIZG/b3ebfq/dcNhh+gVnra42tULuE98V Tg7X/b+OuN3Dkj/rLmfptGxG6TutaPftKFiDAbs6QqC8KHg3hVMG45BdhifIWH1qpUqH shNlbWoiUrV+RZ0pLWFFHgjjeDncKDDeeSYgwiGI142ulQZyy9ySvD4EMA2Cifd23XWq YaFlth0aaI3wQ+Pt9I5Q4wZMB2v5XN/bGE8yLnFdfyH6kl58E+4tvGMaPnE07xSTPt4G ivKu3CB+lyHaOmTvpbwg4WZM8daPa7eYQvExJo26juKcVUGKIGMaHmQOXBS/BaSda5x+ zjww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=k4GoMuhnLHA2vh1yco9VQy1DoNTZgPa1ywK70BmOAqY=; b=uPE234qqsZ6y4fSd/q2z+GgZOf4Sb2WV01p8WZcrrx916WRwRS3M7JIA+kQu/Bqb1Z ackgzYCShiaAqHVqkIg84dY+rKIJPFFqyg0S1IcX7WkptqQEP3Y766GmCoaQbuWZf9hz woIpw1j0cYS9l6c+i0QB/dM9BCDhUB1ug5qeWRDfBlzx6xg33kvgUlzSBoqPCGlfWM2H fgM332NIS0A5x8EtwLm3IT5hYuvCYE9V9XvkZHfxcOCGgezbmdtmkOlFMQd0WgkxpI0e ZnbOxE/oZIyBBIRqfgm3TD/wmSsJSiA/+xUIVXL2v+E7A9bGblsWt/3hqwviylJot4nV +PBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GnzWIBTW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i12si6335812ilu.162.2021.04.16.12.18.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:18:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GnzWIBTW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTyq-0001uj-G3 for patch@linaro.org; Fri, 16 Apr 2021 15:18:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50322) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThj-0003l6-Vg for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:36 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:46754) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThP-0004J3-7z for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:35 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d124so18912010pfa.13 for ; Fri, 16 Apr 2021 12:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k4GoMuhnLHA2vh1yco9VQy1DoNTZgPa1ywK70BmOAqY=; b=GnzWIBTWXqAzByjbNPgKQLnXeZu6PbtAWI69mugXofwcu0Wb8joJE3pjSqslecNGaq B9Kz5Ianwgf3GcK7gOFbB9WiehrsaZ2YCKK9LWPelUvBZVhxGFnWTbmrpUJxP8zs1y4c YBV5UXpQXOgcbXe/7P2xP1jEHZ6ZSeqAFOfkLhJK+GouL664GaEmS5EHyZpXxcBtMxLi KcoMnbV0rwczM2r+s4Nbo+6s+uX7jXJ+4o2tfXj3L2+WhwfyRXGF6RUxboHBQUh0K6ny AaJH1Thu9hRXCa5pVD+V9c+wGbrMqXSMbg6Eo7u/c/3vt8yVNooeBN5CzsluYxGEjQZM F/FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k4GoMuhnLHA2vh1yco9VQy1DoNTZgPa1ywK70BmOAqY=; b=k+E1F+GNH2b5rJJbW/ysgm7AukT8JZvOGhteheJ1vtUcdSgnYz5Hky259cIOySbTuM BwC2EV64C8yHuo5bgsHdbYY7JU43LRHkmocZ5nGmNc7JieofF0BiMwgrCuhFZDavGGlE CxZtRSTC+1aJwBKEFNuGVRUoePnD9Ung07DwyfubwKDj4eBpxYQNlSlLd4Rlc0kA7o0G EdW7bCaQdVmB0TF2UEdJ6DMq2n4EuqXLnTSx6q9PI19WvR/FBKT0cGb/Zeh7p9GicVr1 0kdHVkE3rgzg7lCU33HGCwhqAxKUt6zwKP+rLeDSMMw0LAdZdJdjod9WKUdRUwlw80pw VFTw== X-Gm-Message-State: AOAM530KXFeWGFGnZ575Of/g9O0yPpIfId93ALzlWUO6Q5HgZGzB6RRl Zi0j9CePcnCI4AncMeMF/xDiWkkjbrKSVQ== X-Received: by 2002:a62:1409:0:b029:25a:4158:1c9 with SMTP id 9-20020a6214090000b029025a415801c9mr3457417pfu.61.1618599609920; Fri, 16 Apr 2021 12:00:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/30] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Date: Fri, 16 Apr 2021 11:59:39 -0700 Message-Id: <20210416185959.1520974-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a finalize_memop function that computes alignment and endianness and returns the final MemOp for the operation. Split out gen_aa32_{ld,st}_internal_i32 which bypasses any special handling of endianness or alignment. Adjust gen_aa32_{ld,st}_i32 so that s->be_data is not added by the callers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.h | 24 ++++++++ target/arm/translate.c | 100 +++++++++++++++++--------------- target/arm/translate-neon.c.inc | 9 +-- 3 files changed, 79 insertions(+), 54 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.h b/target/arm/translate.h index b185c14a03..0c60b83b3d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -459,4 +459,28 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) return statusptr; } +/** + * finalize_memop: + * @s: DisasContext + * @opc: size+sign+align of the memory operation + * + * Build the complete MemOp for a memory operation, including alignment + * and endianness. + * + * If (op & MO_AMASK) then the operation already contains the required + * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally + * unaligned operation, e.g. for AccType_NORMAL. + * + * In the latter case, there are configuration bits that require alignment, + * and this is applied here. Note that there is no way to indicate that + * no alignment should ever be enforced; this must be handled manually. + */ +static inline MemOp finalize_memop(DisasContext *s, MemOp opc) +{ + if (s->align_mem && !(opc & MO_AMASK)) { + opc |= MO_ALIGN; + } + return opc | s->be_data; +} + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 51897a5113..5e6c40022f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -908,7 +908,8 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var) #define IS_USER_ONLY 0 #endif -/* Abstractions of "generate code to do a guest load/store for +/* + * Abstractions of "generate code to do a guest load/store for * AArch32", where a vaddr is always 32 bits (and is zero * extended if we're a 64 bit core) and data is also * 32 bits unless specifically doing a 64 bit access. @@ -916,7 +917,7 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var) * that the address argument is TCGv_i32 rather than TCGv. */ -static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) +static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) { TCGv addr = tcg_temp_new(); tcg_gen_extu_i32_tl(addr, a32); @@ -928,47 +929,51 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) return addr; } +/* + * Internal routines are used for NEON cases where the endianness + * and/or alignment has already been taken into account and manipulated. + */ +static void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr = gen_aa32_addr(s, a32, opc); + tcg_gen_qemu_ld_i32(val, addr, index, opc); + tcg_temp_free(addr); +} + +static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr = gen_aa32_addr(s, a32, opc); + tcg_gen_qemu_st_i32(val, addr, index, opc); + tcg_temp_free(addr); +} + static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr; - - if (s->align_mem) { - opc |= MO_ALIGN; - } - - addr = gen_aa32_addr(s, a32, opc); - tcg_gen_qemu_ld_i32(val, addr, index, opc); - tcg_temp_free(addr); + gen_aa32_ld_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr; + gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); +} - if (s->align_mem) { - opc |= MO_ALIGN; +#define DO_GEN_LD(SUFF, OPC) \ + static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_ld_i32(s, val, a32, index, OPC); \ } - addr = gen_aa32_addr(s, a32, opc); - tcg_gen_qemu_st_i32(val, addr, index, opc); - tcg_temp_free(addr); -} - -#define DO_GEN_LD(SUFF, OPC) \ -static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ - TCGv_i32 a32, int index) \ -{ \ - gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ -} - -#define DO_GEN_ST(SUFF, OPC) \ -static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ - TCGv_i32 a32, int index) \ -{ \ - gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ -} +#define DO_GEN_ST(SUFF, OPC) \ + static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_st_i32(s, val, a32, index, OPC); \ + } static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) { @@ -6456,7 +6461,7 @@ static bool op_load_rr(DisasContext *s, arg_ldst_rr *a, addr = op_addr_rr_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); /* @@ -6477,7 +6482,7 @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, addr = op_addr_rr_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); tcg_temp_free_i32(tmp); @@ -6500,13 +6505,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) addr = op_addr_rr_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, a->rt, tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, a->rt + 1, tmp); /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6529,13 +6534,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) addr = op_addr_rr_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = load_reg(s, a->rt + 1); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); op_addr_rr_post(s, a, addr, -4); @@ -6600,7 +6605,7 @@ static bool op_load_ri(DisasContext *s, arg_ldst_ri *a, addr = op_addr_ri_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); /* @@ -6621,7 +6626,7 @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, addr = op_addr_ri_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); tcg_temp_free_i32(tmp); @@ -6637,13 +6642,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) addr = op_addr_ri_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, a->rt, tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, rt2, tmp); /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6676,13 +6681,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) addr = op_addr_ri_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = load_reg(s, rt2); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); op_addr_ri_post(s, a, addr, -4); @@ -6908,7 +6913,7 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop) addr = load_reg(s, a->rn); tmp = load_reg(s, a->rt); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); tcg_temp_free_i32(tmp); @@ -7064,7 +7069,7 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop) addr = load_reg(s, a->rn); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); tcg_temp_free_i32(addr); @@ -8248,8 +8253,7 @@ static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) addr = load_reg(s, a->rn); tcg_gen_add_i32(addr, addr, tmp); - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - half ? MO_UW | s->be_data : MO_UB); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), half ? MO_UW : MO_UB); tcg_temp_free_i32(addr); tcg_gen_add_i32(tmp, tmp, tmp); diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index 0e5828744b..c82aa1412e 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -559,8 +559,7 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) addr = tcg_temp_new_i32(); load_reg_var(s, addr, a->rn); for (reg = 0; reg < nregs; reg++) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - s->be_data | size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), size); if ((vd & 1) && vec_size == 16) { /* * We cannot write 16 bytes at once because the @@ -650,13 +649,11 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) */ for (reg = 0; reg < nregs; reg++) { if (a->l) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - s->be_data | a->size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), a->size); neon_store_element(vd, a->reg_idx, a->size, tmp); } else { /* Store */ neon_load_element(tmp, vd, a->reg_idx, a->size); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), - s->be_data | a->size); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), a->size); } vd += a->stride; tcg_gen_addi_i32(addr, addr, 1 << a->size); From patchwork Fri Apr 16 18:59:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422565 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp651011jaf; Fri, 16 Apr 2021 12:07:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxk4dcW5Kq//F+Yq8jv7HiQD4zn5NqTyMYQlgSHqmgFSOQJ694jH8CucMWC/NJPZqepASQi X-Received: by 2002:a05:6638:130b:: with SMTP id r11mr5385376jad.135.1618600038083; Fri, 16 Apr 2021 12:07:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600038; cv=none; d=google.com; s=arc-20160816; b=aQFzzTcHmgTHrvaLekYMZnoRTr033GJVf5gem26rtc3shTuGGWsaMMiTcTKLneYWU2 jvAIIFN84Fsav9tI6FQz6bWAwkF7EuKDYd2Ru1bpOeAWFOBysxaLLCtkyBzsVigFNb3t FI4gv80tflqZPiWiQkA5WjhIdV+ntYTxk1Y66gGUFDF4tWZmks2O8y0y/LaygAjc14x/ bpt8UKrm5KiREZmqoY6GCu5vzztT5UZpSP5SNWgE+5MnP2yCCOgyVzh/vRVqBxbBAlL5 PuIXTGQ4t/gDXOXmxbsmDBnY2rBJd7RZzK82SSck09ein3MvRRE1b5F0s4pKrs0N1lHI MuQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MMkcYruCLlbuVyp3rgi2e1FgoVe00zt1vg+jkG6WDEw=; b=N7RHZ5KiXhUc9aiO7XAIn7REYIVYynLElOf+oIPuaeDaHhEa5khlh4nujYY53ikWkz /4+ISMZUyHs1UvwN9fqxpCg/JZsMs/hmQJF0hx33uCUDZmv3ieCGo3Nyo9bEEPGmWjnz c4uH3Zxf5ddXOo7G1RrP90fsQUOqiLnOH1BB2iWtsaRZ461Dzt2n4TFEyqWZlgh/GWsy nipyCev1mJwwooToBSfmMuOX+IFpmXVwoGjQ6GEwfXpQZO0W2RAEiZoW4jQCf0PYf2/g uO2m9uktLk0ySMh1qEYjbe4yCsWro07TXdLP6wxehFs1tZAj7AtwbSyv6pHlLiZ6xmEr SmkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WtAMmV4l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d8si3831155ioe.12.2021.04.16.12.07.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:07:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WtAMmV4l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48778 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXToD-00022M-GB for patch@linaro.org; Fri, 16 Apr 2021 15:07:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50208) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThf-0003aU-Ag for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:31 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:41548) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThP-0004K4-2y for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:30 -0400 Received: by mail-pj1-x1030.google.com with SMTP id z22-20020a17090a0156b029014d4056663fso15127995pje.0 for ; Fri, 16 Apr 2021 12:00:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MMkcYruCLlbuVyp3rgi2e1FgoVe00zt1vg+jkG6WDEw=; b=WtAMmV4l3G0pRz/bHX9xRlPZxa4CxzSjCeXCOAerdN1F4fDiPyiU66bhe434NmvhRn BZzr+8RhhpehBdEr6+xoyeOkDrYrlyOjbjQLo8tvXUrwjVDvfLZL4MaKBaam4/isA5Ow 01mymTYpFrYTKZlF1phS2wqez+BMhwhYPqURsk123nHebZwNFSsNa9XhRcxBYyEbSQZP 0TWt0adHz9ZspSWOHHKR+QohxsAz4LF+pxRKJ/XsWEk+duNWpjRUbQZglqrwrIdDCBAZ vrDOSihVlLwa3rTd3upwggmyL+WGO54mpwQayHwXhha1n2NuOc6iSMAp9YX/M6Q6ziAm jY4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MMkcYruCLlbuVyp3rgi2e1FgoVe00zt1vg+jkG6WDEw=; b=fB/eD8zMED7k7Dj7OkGyAiIL+hq/2F8zwCDq8xdlZ7aS71RKN13A8LcupGWkeZzWBm QabFcn/KWlYhNYlqah4iytTkVtnvwIxUMk2SxsC9KE0YrwNdmxDk7lwM1JOMQHYdIaLv bRuWt7xfW9EJWpyzAodjC3EoosINkxApFPBzqAJrxn796rZ3ZusbldMzjNKZJc4t4Y8U Lb3LmviNMRgtH98LSXGbl5WxEEPJxK6Nh5n0INfQVh66WpBg5F0yy9wixlqpnAKopF9Q uyaUAzNIU1uqDsyqy5g4UTyV0cCWWukZHLhuKMNKopD4yYyuQ8wtovdLQkQh8oWuWWGj dZgw== X-Gm-Message-State: AOAM532C9nSrifMu+sFXjdnY7Fa/Mgj7Py4XH0L2gy8fA2oawBjOUjyN kUGEXy9NK5v40HrVMANteeUiHV0P3FvBdA== X-Received: by 2002:a17:90b:4384:: with SMTP id in4mr8258671pjb.188.1618599611076; Fri, 16 Apr 2021 12:00:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/30] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Date: Fri, 16 Apr 2021 11:59:40 -0700 Message-Id: <20210416185959.1520974-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the only caller. Adjust some commentary to talk about SCTLR_B instead of the vanishing function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 37 ++++++++++++++++--------------------- 1 file changed, 16 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 5e6c40022f..91a19bc4f4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -975,20 +975,17 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, gen_aa32_st_i32(s, val, a32, index, OPC); \ } -static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) -{ - /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b) { - tcg_gen_rotri_i64(val, val, 32); - } -} - static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index, MemOp opc) { TCGv addr = gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i64(val, addr, index, opc); - gen_aa32_frob64(s, val); + + /* Not needed for user-mode BE32, where we use MO_BE instead. */ + if (!IS_USER_ONLY && s->sctlr_b) { + tcg_gen_rotri_i64(val, val, 32); + } + tcg_temp_free(addr); } @@ -4987,16 +4984,13 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i32 tmp2 = tcg_temp_new_i32(); TCGv_i64 t64 = tcg_temp_new_i64(); - /* For AArch32, architecturally the 32-bit word at the lowest + /* + * For AArch32, architecturally the 32-bit word at the lowest * address is always Rt and the one at addr+4 is Rt2, even if * the CPU is big-endian. That means we don't want to do a - * gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if - * for an architecturally 64-bit access, but instead do a - * 64-bit access using MO_BE if appropriate and then split - * the two halves. - * This only makes a difference for BE32 user-mode, where - * frob64() must not flip the two halves of the 64-bit data - * but this code must treat BE32 user-mode like BE32 system. + * gen_aa32_ld_i64(), which checks SCTLR_B as if for an + * architecturally 64-bit access, but instead do a 64-bit access + * using MO_BE if appropriate and then split the two halves. */ TCGv taddr = gen_aa32_addr(s, addr, opc); @@ -5056,14 +5050,15 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, TCGv_i64 n64 = tcg_temp_new_i64(); t2 = load_reg(s, rt2); - /* For AArch32, architecturally the 32-bit word at the lowest + + /* + * For AArch32, architecturally the 32-bit word at the lowest * address is always Rt and the one at addr+4 is Rt2, even if * the CPU is big-endian. Since we're going to treat this as a * single 64-bit BE store, we need to put the two halves in the * opposite order for BE to LE, so that they end up in the right - * places. - * We don't want gen_aa32_frob64() because that does the wrong - * thing for BE32 usermode. + * places. We don't want gen_aa32_st_i64, because that checks + * SCTLR_B as if for an architectural 64-bit access. */ if (s->be_data == MO_BE) { tcg_gen_concat_i32_i64(n64, t2, t1); From patchwork Fri Apr 16 18:59:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422578 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp656701jaf; Fri, 16 Apr 2021 12:16:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyu2douqh2lIvoFfhkqpdocMtGnfi0qG9KBIbTnmySj/bgEVriF7aPktsS+m+5VZB9+9FVO X-Received: by 2002:a92:cd8a:: with SMTP id r10mr8383701ilb.282.1618600578138; Fri, 16 Apr 2021 12:16:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600578; cv=none; d=google.com; s=arc-20160816; b=e5YsxepBTlvO60O/TFDkXW5v5ib1RVLE7UrwtYCX4J66NWLdFMhX8FsaYk3hbUh/uI Xujbci5WyJWZrkV+alKke1MZgEZ5zMlNmP19DkNiBVyV/9ky3FBdLhZUF3GR6hZcQiCl Y0Fp2UhIzFPGGjtusfsuCt+/pcKCooTRY4tICax391M3kuG58W+B/xVRznmeCvk/Os7W CKtm5Ts8+uBE6aqVU03BG2mLvlFAq3MH+po3CfcIk8003dV6Kz+PUJ1yDm0M5Xlyt1Nc HzYsWlcMz5kTgG60Qj3NBcJFtEW+VKr3+qhayLUU/JCsb1dY6tAzwnva2p7bxUVZqy+W N5Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+FqQpeZX2hPehb5y76ZqDzt7hc+HNgslVIaYOGp2C88=; b=hpWtR5wLYkWsKXxF87UdXJhJzRi8tBJkGCz0C8AAqE7MLz3nNVyLTrNIBNIQ8CkrHD VJO15PNgF3E9gOczFkGhfkGKqrWR4c81SRVgPtcq1nqoOLvFPOyDw+rK1k3XtUit/oDD zLF4Hxkhjxm9rKWbpHqYUwsMQt930lWSgJh4GjBVDTutZ4BnfrXPZO2cltlNiQgglrPw QSh0OuEbfbjAS5lTZ2fjxjxOPYJUR78a2KA9iL4VcJOOrkO+bpc7YE+fiFexKX9F3gU1 ib/1BUYPUWhGbECg2lpMFej9cG64EVmFX35oGFEWcbBZuJwv/CvsejqKl88Q5KeaMiLV F9ZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VYMlRlb9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h10si6420317ilo.148.2021.04.16.12.16.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:16:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VYMlRlb9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTwv-00061c-I3 for patch@linaro.org; Fri, 16 Apr 2021 15:16:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThi-0003hW-Ar for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:34 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:46758) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThR-0004KF-Rl for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:33 -0400 Received: by mail-pf1-x431.google.com with SMTP id d124so18912077pfa.13 for ; Fri, 16 Apr 2021 12:00:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+FqQpeZX2hPehb5y76ZqDzt7hc+HNgslVIaYOGp2C88=; b=VYMlRlb9R+lOpaDUhAl9oTRyFpcqb9ok7Ddxa7eEr4DRVjxjskH/dA7evgvGytDWml 6D6F2WqNSjK6MDxh6jIkXdncxg3SbI+/UUCEq2Gwa85Cmm3bTQ3Il6MdVTutLrH6xQHO OU2VhmO0ef5/DWehCPF8VDkAHbhpDloKt95iSebHL4L+IHPqywdmLEV76PbM1ZRn/Sf5 YAW8e5mzmr1xaaBAFirmwMKGBM8AAOoQnxEz8pyB/ZY3o6RoYOGmS5dfg1BWsgF3PYWr ydTo49zGEsY3Xp6/XKsEGRl0vguR0eAuVzoA3Slspb6/Er9TU0AZ65nexFp+tF54frm6 ByrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+FqQpeZX2hPehb5y76ZqDzt7hc+HNgslVIaYOGp2C88=; b=qNvmc/qzAyJwxSsBTWhh92laRvJfJnVwf+SHcO2+oZli5Xxne5C+UcEauhkKuBpqmz x0Mk5vxbhjzg3q2Qzu9GFAVX2KQ9u4t2AxfsI2RX2dbixRhdSRmObtyubJhMghiMN2Nv UNHq6DC6PfGUfyjcSrooHItllSxq8CQBGdG2lXJpyiXRTByIr+8V2XSM/xKTJXdLjNmy uUQlWbSqMpIZSynbxRRZGeYmdJhyZEvAz71Ab3GZrNxO5/jLvj/ac4jRFfjTGTCi4ipF jsb78jcooW7g4dmzS6hF9hZk1NxRY/Ns3zsuO+2K/xw8l+jfFwsITRc/779fsFJcyE7E Jyxw== X-Gm-Message-State: AOAM530NMAywUX54GcRauO+/cZVSHieZP7D+/Dpv0AMncknLKjwLHhxH 1Q+nnrYgG/iwT+sNwG7Mm/11qMd+5kwTOA== X-Received: by 2002:a63:f715:: with SMTP id x21mr440994pgh.399.1618599612108; Fri, 16 Apr 2021 12:00:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/30] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Date: Fri, 16 Apr 2021 11:59:41 -0700 Message-Id: <20210416185959.1520974-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Just because operating on a TCGv_i64 temporary does not mean that we're performing a 64-bit operation. Restrict the frobbing to actual 64-bit operations. This bug is not currently visible because all current users of these two functions always pass MO_64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 91a19bc4f4..52b9ca502e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -982,7 +982,7 @@ static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, tcg_gen_qemu_ld_i64(val, addr, index, opc); /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b) { + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { tcg_gen_rotri_i64(val, val, 32); } @@ -1001,7 +1001,7 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, TCGv addr = gen_aa32_addr(s, a32, opc); /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b) { + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { TCGv_i64 tmp = tcg_temp_new_i64(); tcg_gen_rotri_i64(tmp, val, 32); tcg_gen_qemu_st_i64(tmp, addr, index, opc); From patchwork Fri Apr 16 18:59:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422567 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp652583jaf; Fri, 16 Apr 2021 12:09:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzr87Hf2Z6CD7zYUJl97oQx+/bDNzBUvZskHRHJbc9z0g9ZLiRXif2/En93IVkuFiZTmP4u X-Received: by 2002:aca:39d6:: with SMTP id g205mr7622126oia.81.1618600192052; Fri, 16 Apr 2021 12:09:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600192; cv=none; d=google.com; s=arc-20160816; b=P1J2D9QaByVGwqMlxHa9RifK5gQK2omgtkyfzStIh2MqNytUpbZqBq+Mf9Eqkrc84I jnsl9FmhLMKQZeKMDp/cMmntqEz7wguQuJe/IJFcJwTXCfP97grcxwn1Hn4r+nV4zvgQ DvnYBAuYRtYMWmcRr744eAFUxRwEhQldPNswTDK6rg0HYY+xomEflYHzdXLroE9RtPGM Wn8TMam+Vfjvvjb8EoASPmTsU7z6bjqAl7dx5KDgYJWSAjTEdbGYMwPsIqxDy+zd3xtH wzVzw6Ff6NYwCVsesc88vafBJeotAjlbhyXsat+S44kjRGyiv48X972l5QTISwf3iBsl 2IBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4JYXrsziQJ+2kkGBxoTfc1nhhgeCmFg+itswQ++dMS0=; b=ltiJTDnQ2/O4PJroSqmsKtH9x3MRBSXk1lOhpSYdwigP08Dkws/hNYY8gfl+rmYTcF Mt6N5b1ODXROJfyLNQ9RR8bBU9Y/fUTAMeSVGFzX57smc0aO750z9ruSpFh0UjZ6kTqZ KL0laoL3y6fWJ4o6JJaBh+iYpez6Ol4cr6hmZ7soo8Hm0c8nHkfnnnPEvWd8aUvKqYvB TJTAnYoA0nShSlvK+f3/QiAsrOczQIEz4NbfTdESKstXPUUtK3kPBclX+hhEjkgilRpk MPwvy9kwmaj1q5qhaFamG8bzX2QbeofzTH9/QylO5nxIOTh/Lr4w0yw0MCqpctVhWA5r S36w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MMXATsoT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u11si1552943oth.140.2021.04.16.12.09.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:09:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MMXATsoT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTqh-0004zh-4f for patch@linaro.org; Fri, 16 Apr 2021 15:09:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThj-0003jH-88 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:35 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:41526) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThQ-0004Kd-BK for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:34 -0400 Received: by mail-pg1-x532.google.com with SMTP id f29so19813372pgm.8 for ; Fri, 16 Apr 2021 12:00:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4JYXrsziQJ+2kkGBxoTfc1nhhgeCmFg+itswQ++dMS0=; b=MMXATsoTqhVtFU/Z+UvY//C4A0uGt6ec7aguA5lEu7IbdJt6zRnP2KqrYQQYdaQHN2 +AUks5fcaGEyoLgKW97iRMRkskzLzrmuJmYy0uwRMPtgaF/jvu5bAt9iJokz7P936Eel Wt8MngAmP6zsg1Pm5q4NUJ9igeO8aVcE2cFWcn/8gkce8HslWsgKjy+IQJtaAwEjg7D0 GIMHoV5eoG4x6rWYWKnTRWSWNYek5/hVmyU13eeNW9eQBMX9mUh62LZGc205N2Y1u64/ hBN4X8993EzPQuggOiE3ihsCiPW9zd7i9+AUwKQ0hYFfPKsO5QnadQF/L3L4ujTOGR9O IhMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4JYXrsziQJ+2kkGBxoTfc1nhhgeCmFg+itswQ++dMS0=; b=rHbxGKyAz8YGCgrEE25RnR3xx+6dmwzRBQmL4+3o94ahlITvChjZ1NdGj2Pug4Uycd l88qaNgm6GnwA53Wy0Lt1hB0VulE+eRQ12phRxF7sUO5tp+vf1cpFDGI6S3KNpBh8bDG 4Z8OhWTk1qQR8kUmYpH17Rgnx4CYrLnZhRjTAWkE+dLYVwpqhQa4nsjbthydJxRSqrt9 2OZUpPl+dS0vW0tSuOZHgZUZhZ0HuVQVSV7l6JSplMlbbHRSTZLKKhAWkk3gzN1C1JJ+ jfEwJ+/3UU/9s3x/vN3mIk2zACxQCm5nNu/bFw15eEmZr2LoE+3pxOhGRYAkx3DL1v/+ cETQ== X-Gm-Message-State: AOAM53341q8lmUPZusn06d70oATlJ6Hd7hbW1tariXJygVC7s5TpFrGq kzwGBbZPOPRGx1ryBrbvKiOChKtLuj7ixg== X-Received: by 2002:a65:6095:: with SMTP id t21mr456207pgu.383.1618599613146; Fri, 16 Apr 2021 12:00:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/30] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Date: Fri, 16 Apr 2021 11:59:42 -0700 Message-Id: <20210416185959.1520974-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Adjust the interface to match what has been done to the TCGv_i32 load/store functions. This is less obvious, because at present the only user of these functions, trans_VLDST_multiple, also wants to manipulate the endianness to speed up loading multiple bytes. Thus we retain an "internal" interface which is identical to the current gen_aa32_{ld,st}_i64 interface. The "new" interface will gain users as we remove the legacy interfaces, gen_aa32_ld64 and gen_aa32_st64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 78 +++++++++++++++++++-------------- target/arm/translate-neon.c.inc | 6 ++- 2 files changed, 49 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 52b9ca502e..7472e98f09 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -949,6 +949,37 @@ static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, tcg_temp_free(addr); } +static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr = gen_aa32_addr(s, a32, opc); + + tcg_gen_qemu_ld_i64(val, addr, index, opc); + + /* Not needed for user-mode BE32, where we use MO_BE instead. */ + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { + tcg_gen_rotri_i64(val, val, 32); + } + tcg_temp_free(addr); +} + +static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr = gen_aa32_addr(s, a32, opc); + + /* Not needed for user-mode BE32, where we use MO_BE instead. */ + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_rotri_i64(tmp, val, 32); + tcg_gen_qemu_st_i64(tmp, addr, index, opc); + tcg_temp_free_i64(tmp); + } else { + tcg_gen_qemu_st_i64(val, addr, index, opc); + } + tcg_temp_free(addr); +} + static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { @@ -961,6 +992,18 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } +static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) +{ + gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc)); +} + +static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) +{ + gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc)); +} + #define DO_GEN_LD(SUFF, OPC) \ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 a32, int index) \ @@ -975,47 +1018,16 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, gen_aa32_st_i32(s, val, a32, index, OPC); \ } -static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) -{ - TCGv addr = gen_aa32_addr(s, a32, opc); - tcg_gen_qemu_ld_i64(val, addr, index, opc); - - /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { - tcg_gen_rotri_i64(val, val, 32); - } - - tcg_temp_free(addr); -} - static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index) { - gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data); -} - -static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) -{ - TCGv addr = gen_aa32_addr(s, a32, opc); - - /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_rotri_i64(tmp, val, 32); - tcg_gen_qemu_st_i64(tmp, addr, index, opc); - tcg_temp_free_i64(tmp); - } else { - tcg_gen_qemu_st_i64(val, addr, index, opc); - } - tcg_temp_free(addr); + gen_aa32_ld_i64(s, val, a32, index, MO_Q); } static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index) { - gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data); + gen_aa32_st_i64(s, val, a32, index, MO_Q); } DO_GEN_LD(8u, MO_UB) diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index c82aa1412e..18d9042130 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -494,11 +494,13 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) int tt = a->vd + reg + spacing * xs; if (a->l) { - gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size); + gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, + endian | size); neon_store_element64(tt, n, size, tmp64); } else { neon_load_element64(tmp64, tt, n, size); - gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size); + gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, + endian | size); } tcg_gen_add_i32(addr, addr, tmp); } From patchwork Fri Apr 16 18:59:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422584 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp659391jaf; Fri, 16 Apr 2021 12:20:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxruetZZEjymreX1ObkUFcs98z12bncDzXk1HAkqVcBLmVTwFKyEX0MP4Hx2qp6aNddRYW1 X-Received: by 2002:a92:5204:: with SMTP id g4mr8361049ilb.84.1618600840782; Fri, 16 Apr 2021 12:20:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600840; cv=none; d=google.com; s=arc-20160816; b=BG4EGuLjUxAQB/rmNAr9RdpwhOfHss9KL+lKY7wrsnqakdOX8Ajpiums/PdyVp9HIm wKvsSWXS0l/w0VQQhcZcl4I5sKtSuYxnxkdYErf/SrwdIEgnBegbzWHQkktPmK6AVbya +f8CxIMNq27mWz3vRak0xlYhaq4JOcqDrUdaQmC4p6HK3D3yMw0tVoc/TTziXT3oYuxr Iki7ZIE2dUyHgbJ9HVWG2p7lVA3rtlP2OwNhMQ9djfBkLxLMMXAAnAYcfrkNtcfREDcg zGpApKYTwbmdTYUePETaGowmWqiUGWOtLC81LrJi1dNh0d/bONfQxhYcotP3xZsViUYa O2yQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DHk5nVHWEzvUPbJqkpxdTXVHC+WlIvNKPTV6ov5dVNQ=; b=aVcFTmDCtcyDhqpNUs5UUp8387bNvjbZgUov7qotE8SSUHxrfPaelryxjpE8QsfScR LDjYauBhtHvbJ6Y3TMloju6eHRr4xjheWUPPOU7N5GnE3y7miCJlJte/gWwUdJKhmhjb mGxFj60W3kqF0U3EW7+2qst+IY+VLVn9DFwy7hf3qyQHTS+cJcvVeExa0i09KW7gsY6I OPqoeJfV1dJ+KAKg2E9dq1J6wy1cCfjjufvPEm5o9Ll8+Xj2tY/yIqkIFkwu4Bo+xHf8 w0JjfQXddjHJdyEsp1/emkAr3u/yYIiUCys+B8De1/snSP+9H5xm7xKDOIJkHJGSpClS GbLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tVFp49xi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q3si5008574ios.60.2021.04.16.12.20.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:20:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tVFp49xi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXU1A-0005X6-6l for patch@linaro.org; Fri, 16 Apr 2021 15:20:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50384) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThm-0003qY-6R for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:38 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:38806) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThS-0004LI-PE for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:37 -0400 Received: by mail-pg1-x533.google.com with SMTP id w10so19823024pgh.5 for ; Fri, 16 Apr 2021 12:00:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DHk5nVHWEzvUPbJqkpxdTXVHC+WlIvNKPTV6ov5dVNQ=; b=tVFp49xi/mYyOMV0Pgrbax8MhuVM3A8UD6UCyYg07pTfJmNGXHUmJp7K6j5P41x5NK 18vL3YVnVj3M7/HEA8ZWcLMYXBVQrxA8tNhMwIjfboX9hZQcmwPxYzR3uzobjAuU8y97 Bl2MvIZiyPV53SCMB1ojjCrKrkXirQcuo0/UHHd68Kuox6fPJO9L+blkRbzohjO9cKur ZA99/WDcrViuxWt4oFI/lE2CWPfhUU1veuAvFEu3MH6CaScxu+38X0rjY10yvaz5WLhT agCBjVY9ESfxPbBtFf9X3hvin6rcGBtrzhvGfeX5nL3w1afqe6S4I+2MmUYRo35yuzj7 5ldg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DHk5nVHWEzvUPbJqkpxdTXVHC+WlIvNKPTV6ov5dVNQ=; b=sTExbzrbrWGwNVKVB8sKgj1lMfEpQTNs0gRMhCwfzIjwmio1fHMoE8ACh8Xm901siJ 9/tQ076M0qMMo7Db/m5jX7+Oq2d/M8NQ6kKzxCoh0TIF4TfusCoTbbvp9PhzPHIVB+AY XPM6n/sWOV8sQVDQ8Ln1pmVNAOuudUmtEzcJ4uVehPTbSctGzuYY1bwmj+15ZeTAdcIV KWLhkLC7y1FbI8XYiQtc+n0cBuv1CVVd8NIn5NSXaY7plkHTDBrLt6xpby/0bOFiDvsE Mi2YFE0f2hZ1vhIG/lqYkFPQAquHJuFQQVrdSHWKUMM0MM48MoFLi+SlSfffQfh9buE2 ADmg== X-Gm-Message-State: AOAM531+tOOOrrxHPAmA7KmF1xYP26sKAOi+3s0PvvNVo0M86gTpy/Wn 7Qm5Awsu4zHMaaBVX/v+QOH3NgWHPswqxA== X-Received: by 2002:a63:1a48:: with SMTP id a8mr469017pgm.81.1618599614010; Fri, 16 Apr 2021 12:00:14 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/30] target/arm: Enforce word alignment for LDRD/STRD Date: Fri, 16 Apr 2021 11:59:43 -0700 Message-Id: <20210416185959.1520974-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Buglink: https://bugs.launchpad.net/qemu/+bug/1905356 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 7472e98f09..63c665fb4e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6512,13 +6512,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) addr = op_addr_rr_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); store_reg(s, a->rt, tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); store_reg(s, a->rt + 1, tmp); /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6541,13 +6541,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) addr = op_addr_rr_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = load_reg(s, a->rt + 1); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); op_addr_rr_post(s, a, addr, -4); @@ -6649,13 +6649,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) addr = op_addr_ri_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); store_reg(s, a->rt, tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); store_reg(s, rt2, tmp); /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6688,13 +6688,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) addr = op_addr_ri_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = load_reg(s, rt2); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); op_addr_ri_post(s, a, addr, -4); From patchwork Fri Apr 16 18:59:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422568 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp653008jaf; Fri, 16 Apr 2021 12:10:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkg5xz8S1LxS6fylWfq1vDhogCvUBOQSIHjMSyi4j6dKhzE0woJPEC13kjlh6VIoMH3jiR X-Received: by 2002:aca:f486:: with SMTP id s128mr7478698oih.148.1618600233595; Fri, 16 Apr 2021 12:10:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600233; cv=none; d=google.com; s=arc-20160816; b=n432VsXd0coK8WGh6GYZRDxcm3+OXVX137e9Xu24dxP1zkvBwZIf4ojhdfTvJKeUoe JRZchfnj5Z/EB3F2sHZ0T/i2d1eH1VBIbWDC6W4MpXKpo7D/b9W06OWF6n4VbFHWyS2i 0IfNKJk9Jq/NA1ydQFzNnJ/g0gCFYeSgPIMQrOz42JXfA925gRi9W2UcqQ5JSm+NmnND 5vlSk5p4x6hJm5kloevMp3Y/eOMr6RFGQaZbNzBORJ6QjgMM94Gvy67A7dodrMpeizqP DbDsNoDpZ41iG9Ql3c/gmSuAZLkjzJTVG9iPvWd5yoHbcsgYb7PIVGD15I5qs7y8GDLz 9gcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vnaM4h0EcMHKhRnS4BkVBJaWLGLyH535AsBhLPRK9ZE=; b=yZeD0haakixxLkjwqcANpzyqJoyAJIaJ5iFlAk82O3JzCH5YTGfdQGP/Abcp7GL1oe trXiXjYh6uVe6tgNIZZSfJR769vbsdn8N7VSj1l5AC6HMrrwoy3BQsupsUD65KUr3ZeU 1SQ7++wDIDSIG0lUKQ6yAJuqhYwI7nFXYSKg6DQoNlz+P5bXexzf2ZIaAy5oX/UpbAAK Q236HxohlamIfq3t91Pa2qadLqS/5D9ataETIwIkFxsi9ZKk3qJSFKRzVICZENih6tB4 axPkCGBPAhFuUdnlxYV5BgzhcRPAAKbIahIPbwg/A7g/lGg9aUOcQ4voyQhAZfWxdwoB 8ILw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fyMqfRVt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s17si5920417otk.70.2021.04.16.12.10.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:10:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fyMqfRVt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57292 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTrM-0005dG-Sz for patch@linaro.org; Fri, 16 Apr 2021 15:10:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThn-0003sb-4X for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:39 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:40809) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThU-0004Ls-Gq for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:38 -0400 Received: by mail-pf1-x42b.google.com with SMTP id a12so18935151pfc.7 for ; Fri, 16 Apr 2021 12:00:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vnaM4h0EcMHKhRnS4BkVBJaWLGLyH535AsBhLPRK9ZE=; b=fyMqfRVt+kJN1zvcl0EdCtE9q5DZV92iiX5KVIKAfJ2o3GEt/L8LFygYg85Wtkhk6+ +D5bkPsggnx9/Cep6+r0kVTNU7C4uGgkJWmVm+UPdkfUg1FKMjwpYyu6qzlD7d8uTr2B za927vJJyU34pTDxH07Z512/Wozh5qaSrkwgstuZ9UQUKMX71FbEe+fJ5EmSyZ+TaZ9J Ik1KusqLx/AplH4v4UDlu0hYlV3ju+0DxSUXrvNmyVXz13JMJCbP8ubstsUmTT/bSV0h /6RwRoeoiJi6bUyVhM1mK94OGXeocrl3nQpQxN5XGXOskwvI4H/neSokXb25DpZfoDlG 9sBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vnaM4h0EcMHKhRnS4BkVBJaWLGLyH535AsBhLPRK9ZE=; b=RmWJAwmKOMehuvS7pMoseqSjAmF3FGFtNLNsX2KS7xDb6MqKUlSdINuy57mbdRFruU whEgTStWSXpJqztE71K9gLeIQxm7Fj+0Re+ZjawZ5sopeZbEP9iD0HXNx3xsmtrmUkfE jeERJiMU1HUkaHEUC/+hvLXc/0n+OTgNIhp7oXo6nrNE1d4hMnCgGMe3zvreX9rLIj00 iXoSqpToNK9tsZ5fR3QUWPhih9oS3th9ZwBC3or2t67nUKkvFg9SttIJWgMSnlL1mrJd hUQ+mji4V0dcEpVT1Jow6MlydW4VkPKfE8jWwTzMx4M3sS8zv0SJ2NiTH/esllru2qrn KmyQ== X-Gm-Message-State: AOAM532eHrt7aG8EjYYspEpPoH9EPWuH3S618mMStGBK6pPwwmSjcvPA s6rh+hc6mJFSrItutc1Z5aFoZJ5r3lDEmQ== X-Received: by 2002:a63:ed58:: with SMTP id m24mr508629pgk.248.1618599615611; Fri, 16 Apr 2021 12:00:15 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Date: Fri, 16 Apr 2021 11:59:44 -0700 Message-Id: <20210416185959.1520974-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 63c665fb4e..270b10f83a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6920,7 +6920,7 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop) addr = load_reg(s, a->rn); tmp = load_reg(s, a->rt); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); tcg_temp_free_i32(tmp); @@ -7076,7 +7076,7 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop) addr = load_reg(s, a->rn); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); tcg_temp_free_i32(addr); From patchwork Fri Apr 16 18:59:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422571 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp654438jaf; Fri, 16 Apr 2021 12:12:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwiNwFUA/rwXlXNJLPZmInsGBJNGoOUt2+rlMM0DEjUdH49Mx61GiJH+SuN79Tty0+sQdCz X-Received: by 2002:aca:1119:: with SMTP id 25mr127907oir.124.1618600370337; Fri, 16 Apr 2021 12:12:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600370; cv=none; d=google.com; s=arc-20160816; b=B1s4n8G6YrIG6vJ8Lq6jdcx5L/gLo5uwU56yTKYIkUKR/AnKQBTVJlVk+EV30eIfYz jXaso4tCnWAixBwCcL0r1j8jOWcroTYau8kAKb8eGDzXBraYJOTVeJaBOmdngRm9UgcB 4rGzR9JbzyAAYxqMx30cWn3HTpzbdRtzlMQjBQZoPPHmeMvpKrhAPkiyWkFDOLqdCSPK zuby5bSqV9fhKuy+AbedaNZOvEwDXaGVM7elcl1SIte8xzGPJp5k7td4lRzrrfKPO7qL CxhwA0iBig4Ykh2tNIXVBG0/bEVbdsHOkV8DTIHs/nUkWAXcRA307h2Yvma8cBY1AC4Z jQqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ltuTQwf3YJkQ09A/ilMOxMZEVgxXZ+bcwwZi4bHmuUg=; b=yyFTTAHqPhWMsoB1ZLtQ34Vs+5DqMrk0ppexYYpDapgZCudU5s3JglBOnDPY4MpNw2 6K0bOSdEsRMNRIXedwrqPiJN1JjoAFufd80DLWtIDZmwRzUNTCt1RcR8YlyawjwjI1Dr AO30HHBK33jgQqgwDf+ekP0PUOgeWHXrQ9FlxtvLx/AueAIe77Pvo3ooJS75SoIJDhRC fP7t3UjKnZk/qxw0peqKkMFKhRKVOuQkVCcUOkumCgfOrh9B95WCRYtW0Wp1/yOhiWBl dxhmaOJbaFQ74BSHMLwVTNnWxMyphi/FczYsnukj1wc6I/KgtGqOwSKq4W5fdK0ub7M3 3VLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dnH5fpaj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g2si7097337oiy.145.2021.04.16.12.12.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:12:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dnH5fpaj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39216 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTtZ-0001kH-Lf for patch@linaro.org; Fri, 16 Apr 2021 15:12:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50380) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThm-0003qU-6A for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:38 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:41521) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThU-0004NR-G9 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:37 -0400 Received: by mail-pg1-x52c.google.com with SMTP id f29so19813472pgm.8 for ; Fri, 16 Apr 2021 12:00:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ltuTQwf3YJkQ09A/ilMOxMZEVgxXZ+bcwwZi4bHmuUg=; b=dnH5fpajtitNw3WFYD9LEBeUWDBw8hlrnvfVWArNxaQxStXftkCJLUzelaU2ufZziT t7VncRQ6Ps1wblUbqeaJnnw9oqkpCgJ3PeGqyYIo+IRp7C+xV0VMDjl0U49Arnogxl5f 9Y+WcG7gdpVGMPJL0bhJ2P4x2VOQ/VApaJBh+HyuXQBK/GCuTjFGerUBYSfLC7WTelRF ofMXhwc9Eg/twkaF3l7eYF0bL8oUTTfKk4jP9P/8tb9DO1pmTPtYpRJTiqR8mze6asbR 3QzeYi3Eg/4aiNyo2KEyQyyfJNkHt24YkFxPXxDbPANJuqpW+ymvf1j9ljAa95K5i2rm cPeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ltuTQwf3YJkQ09A/ilMOxMZEVgxXZ+bcwwZi4bHmuUg=; b=cuPJcEUM2lT5QWitclQN/yvhU5agCJ+Pz0YtUDOw2ZvP6HZKul95ay9L+1OkaDvgMf VgkXssqfAfFJw58xwFCoHFdq6Pgfq3sajckqfpROxwkeOH/b9m4gUxT0PlJfu/u5x4bo NI3OWRVVMhtseLsgwdG95qxYlanHVQ5wroBoJvOIsNx0Wntw6z6D+MiFtP9xFLyxp6qd CHG38vbCF/OcVxrg2hd7qMcSeSD7cd1xrFj/JYxb1zlag0eaTIYHPuCZDufZH8/N5AfC w5CPSEUAEgrTR9VEchbQuEeT/ES6xoNw9809aELPVhVI6K76zmm+bCWm6WlqWeZ+P9m0 AGWw== X-Gm-Message-State: AOAM533hfGe+QRlVvXYNXlvJ/wcqR9IxezsQH0m/Z9st86y89MIUfz5e kGZFBNmFhxQoU9R9JkujnVM232xVrVvKTA== X-Received: by 2002:aa7:989c:0:b029:253:a2c7:9b29 with SMTP id r28-20020aa7989c0000b0290253a2c79b29mr8994857pfl.39.1618599616406; Fri, 16 Apr 2021 12:00:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/30] target/arm: Enforce alignment for LDM/STM Date: Fri, 16 Apr 2021 11:59:45 -0700 Message-Id: <20210416185959.1520974-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 270b10f83a..1ddfce9dfe 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7868,7 +7868,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) } else { tmp = load_reg(s, i); } - gen_aa32_st32(s, tmp, addr, mem_idx); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); /* No need to add after the last transfer. */ @@ -7943,7 +7943,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) } tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, mem_idx); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); if (user) { tmp2 = tcg_const_i32(i); gen_helper_set_user_reg(cpu_env, tmp2, tmp); From patchwork Fri Apr 16 18:59:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422572 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp654562jaf; Fri, 16 Apr 2021 12:13:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw4ScXfthvlFZMmYh7KOR9I4kKnAc7LBP+sCK6yIhWfDStvN7FLLWxYJfh8xAXbwpyv/Vky X-Received: by 2002:a05:6638:218b:: with SMTP id s11mr5403256jaj.81.1618600380943; Fri, 16 Apr 2021 12:13:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600380; cv=none; d=google.com; s=arc-20160816; b=B9sSFSRVbY4wmlquAyNpyk6sxdoFE/jXk4S4C2v0E5gIDWFmYabNQAyCYFi/TuJs9v YLNmdMNe2KmET6008kUfhhu1+MOG0eckwCsiecRjNlzAIeW+KrbVLIbggGnHHNcOSCu5 W6KCOg+QFrCqsb5VQ9mbIAzLZtF4IKKIGolVV4kzY/ag/eqHE7GZOcfrgL5L5fNcKRVj aRgdbVb2i2/HZhzJOiAgWyU0iZFha3nUZ/jQRbax9Bw6ULFZXyv+3LVCzpEpO2AOU4/N qyFbTaZB0UbnawARGcWgouzoVwmFhDPS+9SGiGq58pO/nxB4zVh/fqvUQwIzUkVU9OdG LWoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZY8Z6GuKFk2peBpwdwT6RL45PsoJHkRVCx8Ex73fZxw=; b=eoJioNW/xiKkox1/NP7ReqIDPwkYu4R1GGgHVkgz24c801yKl0q3rfC/55tNNSawsM R0g1LylqtFjOgYlaqCcstH+adqivESu7LQXuD1AtGWd71FYWXAuPmM8qOvXm5I75Mg3d 3AhS83xAaCdLNQ1QVjt53g7BT2V6n2XRfraOufuJ8DWeQZ0SCodaoys15YGRhFrPoANK h0fM91J2CUvF2kKiCQGFgUss5XDc9ashF5Ju/WwZrVdzibJJCEvpO4U8nK7fNXkxlPTY aqBDrmVT/1/cy5qR3gZ/e+w1lHIK/28VSQcXJjumICh60ms/SUjWvJmsU9rq+yXX2FiD u0Bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kwLpd8dg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i24si7124266jav.54.2021.04.16.12.13.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:13:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kwLpd8dg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTtk-000179-Ds for patch@linaro.org; Fri, 16 Apr 2021 15:13:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThp-0003uq-Bh for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:41 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:44579) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThW-0004Qh-C0 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:41 -0400 Received: by mail-pl1-x630.google.com with SMTP id d8so14467653plh.11 for ; Fri, 16 Apr 2021 12:00:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZY8Z6GuKFk2peBpwdwT6RL45PsoJHkRVCx8Ex73fZxw=; b=kwLpd8dgEvQNJ9rF8MSlXupicLAGUdi7PM3EPvG8Y5ckjqrYjqpk6IyOo+5sEoNbbw rjwUC5sRnXhzQ2DRGI1GKzMMhA9ec3l2F9HTl7ybAcTugbaqlsh0cA0F1frcrQOA2CAz Voa5Gwiqg48R77jhYc8MlVkOEpdc9Bih3QEZg9xJJOUFoVyQnbz/6XcizqAQeKpTudN+ YOuz/837HaJc4tVrh0sdHqRxjAE8+ps0a29L9ON3juchafgMfIO8S7YWUyCIRcid19RM 15Vf2+bRxA08H55yUcKDzAohQ2ve0Ga5Tntt9w2Ecxr3nEglJMqWmFlSeNdVndhrIYHY A4MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZY8Z6GuKFk2peBpwdwT6RL45PsoJHkRVCx8Ex73fZxw=; b=AKB8Uye1MIMqKFOxo8w3le6T1+JoA+ceoUQB6P0tiUexV1s2sbWXhjMkxtMg+XBKcs wF198j2urX51IJ1XfJn/KYl6Uezcn86e0/vANhUn3Dt6+KorvPKb4ijiyL/c/IPnjWHl SDNAI9hRTt8so8zj/qHAkgtlWWGgC2qa53mUFbNuihewjvDzLLo3M7R5c4BUTPpzsXFW EXsePVcLw9nWySVKN+P1lLnoVZ20a3UCzuHrf4wCaaoNxbZjGOUplF9M7TrjhVn3NmeJ tgBjAuauSxzsrSlsMMpH3/K4JgjaQouNvpU05nMkLbETz4FE3XVv20RFJ2Zc0/waiLd2 67Hg== X-Gm-Message-State: AOAM532uX5suuz7V46bNvWkk8HxiyIptHj9FGfqYarvchFl/wYpYzcBS QkP1vh2IyiKDjdkp/N2H/S8jJ/E86rj6xQ== X-Received: by 2002:a17:902:bd41:b029:e6:933a:f3ef with SMTP id b1-20020a170902bd41b02900e6933af3efmr10966839plx.19.1618599617511; Fri, 16 Apr 2021 12:00:17 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 17/30] target/arm: Enforce alignment for RFE Date: Fri, 16 Apr 2021 11:59:46 -0700 Message-Id: <20210416185959.1520974-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 1ddfce9dfe..6d2339ebad 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8341,10 +8341,10 @@ static bool trans_RFE(DisasContext *s, arg_RFE *a) /* Load PC into tmp and CPSR into tmp2. */ t1 = tcg_temp_new_i32(); - gen_aa32_ld32u(s, t1, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, t1, addr, get_mem_index(s), MO_UL | MO_ALIGN); tcg_gen_addi_i32(addr, addr, 4); t2 = tcg_temp_new_i32(); - gen_aa32_ld32u(s, t2, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, t2, addr, get_mem_index(s), MO_UL | MO_ALIGN); if (a->w) { /* Base writeback. */ From patchwork Fri Apr 16 18:59:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422569 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp653158jaf; Fri, 16 Apr 2021 12:10:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy+3bm0/OuS4m7bAjcjem5LxazNyBbJSl1CnCSz54ucfIzqfeeC49te8s6bUA6XpAJzk8Wd X-Received: by 2002:a9d:1b62:: with SMTP id l89mr4991361otl.307.1618600250052; Fri, 16 Apr 2021 12:10:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600250; cv=none; d=google.com; s=arc-20160816; b=M66sTFUG4kCVk3+O+Qp5sORWJthWzezxMIuq3sH99s27Tk63yRFIZ0r0MT18TKo5IL PW4VXvauxZP9IVw7EjB7hcC8f7V5KTaJvW39p0NNxFv7uWeuIVJm9S8rut4D+STzTcXt /ELG1pNlaBtUWF21G3SXh72EZqJaOIKqsAjr5abZuAqmeGg6pqR1uOP3eUg2jDP3hqqW I2veZkBigmITElyOphWfR/X9mtDwluQ40ikFPEthtw5GLDakvVssTI7yk/1x97T92CRH AR/vpnCE1hgNzjCU/twZ2m6r6UF4lazMvfnGGpinlCeYSYmgKOLlp5k2ANCAqzERuQDw qjNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=I2U8YEM62/D08WuqUDIDv71u1YA11N1lnaYze760LqI=; b=d1pnUl6AslvjgMb3kBO4KG9lt7+8h4gSCe98ANcAlE4moMADhn6n3kFadWX+zFL0ki hFAT3WrKKq99COcFhtYikSJ6Ip7vchiPglJrxIpm5Y4Ig0i4c2SSTvkgbivFfrsBgQ/Y uTUWpFfHJ3sst0npqxhsuLou/cFMLRUfkeykR0Jaq1ITP5emTZ01sQtTUVLOJ9DtQFR7 mMDe6taBOAzHhig6imseFDRok10gmglOC95JUbKeqcaE/P9YmdQ2wlbQhd8D2nXEesrn G7Jv/AZ3R6nG6H6qeL1rC5ifXYw+aDpW2B3xLgfYJq4gX3wUCKA2ILb63GInESPJFx1G uLEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=V+77bUFw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y10si5872637otq.318.2021.04.16.12.10.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:10:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=V+77bUFw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTrd-0006Ls-Bw for patch@linaro.org; Fri, 16 Apr 2021 15:10:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50354) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThl-0003nr-04 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:37 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:38532) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThU-0004P1-G7 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:36 -0400 Received: by mail-pj1-x102b.google.com with SMTP id k23-20020a17090a5917b02901043e35ad4aso16901393pji.3 for ; Fri, 16 Apr 2021 12:00:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I2U8YEM62/D08WuqUDIDv71u1YA11N1lnaYze760LqI=; b=V+77bUFwuTA+ecu4Ft7TtYrNKuDVCGQ9KVIHBWbAbLb0nImCFggps2RiC9mgXnn0sw SoUdtzj0070FnvTHMaTjYIZ/hwGy9KXCBGnc9sGt+kjYMpwrPaUh2TL0Ehz6MuU6hPO1 gk2wnQZVhxg+uuAMtgMFY/9Z/KO4ZOcNgfDyOESsM4L+isXRvJbcIrHU2Qw2kHaHyF4o knQBEx8Th3r/Nj2RwyXTIBeISJqYtyIoxcyWfwfn5WQNqC1RGW7b0DQj150K09DeLFW0 pk9KK+p88BJHjXMAN0od0eQ3GoYOn4sGFEef2COSWoYviBUejgIGuXSyhhLX1C8AmlaX BISQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I2U8YEM62/D08WuqUDIDv71u1YA11N1lnaYze760LqI=; b=drUNFeq1LieAjK0m4oVOyYItScyhHvrfPcGoMz1OtK6UxLEOfeCd6P+LExMne7zplk Kf+r0FIFGleG69k42qkXtGXG51c5+5CqP7V1yKsFeSxO++jFMPgJva26VYsknwpm3rAx le684so+ejQWRAZailiPmdOSPC32cNITxvLarMLMx+Nrj8ErdJ61oSpGrs4ThQkinqfK CM2eoEvogYkx8XjIF7gNunkVz5OcFq/Mt2mAMnEh4hnYoANydPVN8yD4e0ntb76UypgA 8xaUtVluEKH46zRMVvlnApx3e0/ySGonOdL3GOJxV7lBuZ9DDbFYILrNZh3XuwHzi9L1 SN8A== X-Gm-Message-State: AOAM531NBndbAXvvnsdixwdIkvOe/FUMjPTWhNvu1HvJN2//10N6AKhD CNAZGFlKLFtXr7dnX95VtF4kGv4oK8pQ2A== X-Received: by 2002:a17:90a:d983:: with SMTP id d3mr3455339pjv.99.1618599618727; Fri, 16 Apr 2021 12:00:18 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 18/30] target/arm: Enforce alignment for SRS Date: Fri, 16 Apr 2021 11:59:47 -0700 Message-Id: <20210416185959.1520974-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 6d2339ebad..c2970521c0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5200,11 +5200,11 @@ static void gen_srs(DisasContext *s, } tcg_gen_addi_i32(addr, addr, offset); tmp = load_reg(s, 14); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); tmp = load_cpu_field(spsr); tcg_gen_addi_i32(addr, addr, 4); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); if (writeback) { switch (amode) { From patchwork Fri Apr 16 18:59:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422575 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp655574jaf; Fri, 16 Apr 2021 12:14:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwx1qbRl0s61/Y64RkzySQlK8hDI3RHUb5I8yo3vgKUCzzCpy7zxseV3virnyqMpErY/2Q0 X-Received: by 2002:a6b:b4d1:: with SMTP id d200mr3831519iof.162.1618600470064; Fri, 16 Apr 2021 12:14:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600470; cv=none; d=google.com; s=arc-20160816; b=N7BETGRGTBQTfLF1G/DuJ87EZFawW0MmlaBP71dTjib9/PXncwE+vTtbnJ5C0jU+yy xwYTkTpYO7RdfTZiLKJNxgSQLWrMz2ysuaLwmJxOVaaa3jXWMshcijV8qq99zrCvHiHd shoJxxMCGbB3U2z2fMHTCRnBPoCs94SKY0D+FhQT/YLVKttvVDgYAAkd0v8wNxseTCWk F/XbAMAvrru29uoMfNkFNr3fgrY896+s0WhMtFwX2MwqklpXlHRmThPOLId/IyWnYwGB 8CmxDBDjIPPkj+na7PpIhox/tUC5SftlG4FxBJQF9NqFClhNhe2EFReyWfZ5WdnYSHHU jQTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KALA1eSooGUfBo7CGQXBooa38v23DHVbjR3um2cG8+w=; b=qPIq6mgss2uQTcfVvL4iNeEDtoHzNxRPheiA96B3gunss36ik52y37j/SPtK0VTzsw 5J0Ukog97+bYy2xMUfSdfJBEWVQEkVoNlAzlbfa0NhuZf64QyF+ZPjGhhwCr5N3+Ag5Y aJD31NeVjKd43J+0lVtUA2xc/EbVn5HfURwKOhy3C9XG6cMQbdB7nXzldrKiycrhHYAK r97Q7H9iIa0mCpS2WYvdcsBgcb/6TqatmO0KfwmWcSBXv67Zs/dKJ9kptTXaB369LR9D /MqisN2tE4GrxFj4+UMcZSTOqkNh0pzkhFact74qFtlofcsfUHLlu6IOCPi+JZfJZnIz 9Yvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=df7qR45v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g5si6665439ild.106.2021.04.16.12.14.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:14:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=df7qR45v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46492 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTvB-0004kj-F4 for patch@linaro.org; Fri, 16 Apr 2021 15:14:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50486) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThr-0003yR-Ih for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:43 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:42858) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThY-0004Pv-0C for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:42 -0400 Received: by mail-pj1-x1035.google.com with SMTP id j6-20020a17090adc86b02900cbfe6f2c96so15117465pjv.1 for ; Fri, 16 Apr 2021 12:00:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KALA1eSooGUfBo7CGQXBooa38v23DHVbjR3um2cG8+w=; b=df7qR45v3HbO40nbnKm+iajt4hX5QOAn1rOdywRK2LRqEDBhLqDd6W6l5o2fUKiwSu SVikwL6aUloRzn0zM5AzMI3MkGYNlMQpyhxwDnGbFDPXQHvdBC1uV+ubAUqg8c5rX1Ak B3TjDC0Sw0WMb0uxmX4ItwLRfJd83hGVzf9BD4c82ZTkNg+7r3qGC5v3KrV2TlXnQX4p 4L7UvS2xsNWZwMwP0ERdjXET/9UUhmYF0FlU0djrLw7Z2ka4rpvwhNKl1y3nGW5GQIfS b/GKSM92hnib5bOz5Fc08DLpyCKyTeCk5GolYn4JfnLU1JeV1Mzr2MiKRpznFAxEroBo wNWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KALA1eSooGUfBo7CGQXBooa38v23DHVbjR3um2cG8+w=; b=SMxaKEl1CxJ059sr7G2i80aWA+/DYoKlAaQeWxK+Nnd80ik6b6odmHEAwgweCT1cCP QJDBJJ8nK+R6MIaVbAb2zb5wFacIMhEGCnmvtC+yDL/BD3QzEtMD3tYdH2lPpuSgNBUR UVwfEACqR/3HpXvXfmvAZ40vmu302ozydtF815WqcGfrW2gjMfdgSygCTrZRFm5atOr6 5Pb26xUBBjSdb7RIEmhQcRwXT6bNETbIe+4N+ftdh42Z26I0CqSzs31GYh7UtAanFki1 3IsuL9TiRGfajkhoOsk+9LC3f0jJJPPh8NtUWqozzfUDCoSKMXhX+/4Yl1ln5FhrjlZ5 0HBA== X-Gm-Message-State: AOAM533Kbh1J6+WcSFhO/ROq94Nw8+SayKLwAM2WfDuOLjlq+T2sE/rC s7XrxsHcJTosclgxq2CiOPzIpkJu7ucX8A== X-Received: by 2002:a17:90a:cc0d:: with SMTP id b13mr11122306pju.219.1618599619640; Fri, 16 Apr 2021 12:00:19 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 19/30] target/arm: Enforce alignment for VLDM/VSTM Date: Fri, 16 Apr 2021 11:59:48 -0700 Message-Id: <20210416185959.1520974-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-vfp.c.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 10766f210c..f50afb23e7 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -1503,12 +1503,12 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) for (i = 0; i < n; i++) { if (a->l) { /* load */ - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); vfp_store_reg32(tmp, a->vd + i); } else { /* store */ vfp_load_reg32(tmp, a->vd + i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); } tcg_gen_addi_i32(addr, addr, offset); } @@ -1586,12 +1586,12 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) for (i = 0; i < n; i++) { if (a->l) { /* load */ - gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); vfp_store_reg64(tmp, a->vd + i); } else { /* store */ vfp_load_reg64(tmp, a->vd + i); - gen_aa32_st64(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); } tcg_gen_addi_i32(addr, addr, offset); } From patchwork Fri Apr 16 18:59:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422577 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp656511jaf; Fri, 16 Apr 2021 12:15:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz18yiwWtBR1g1ZbVOuWnBjZYNs+CGbnk7LEBGhscM0/NREIVHRrUASJLgPQHTpi29PZ8aF X-Received: by 2002:a6b:3118:: with SMTP id j24mr4632874ioa.205.1618600558850; Fri, 16 Apr 2021 12:15:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600558; cv=none; d=google.com; s=arc-20160816; b=gdOXGZ65veHHndWe3ldjOfEvPWx/KIR2ud60JN7qZ9vilM7uLs+V4eIKSsVtjAUlU3 BeqH9Z2GD7SDtlTXa/5YZagrTjoJlqS7Be8T8yRuJTMmYzWj3bfjcrbvKnBJzqfaDSRM DRdBQtgB/EralrTGcrApXIkR0BmZa30ePij2qiE/vEK0wnmF78V+F4IHRevtU14CJqAP 8YfAsDlVL1QfsJWgaROPk9fLveQApJw2Ao1y4L2ox+YVRpltdNmla6vVBzBem/gDcOjZ VQayOmoOASZ5XEwEBH+NOOb84OusFMbf6aNXzgTIxxrtSv/evLvW4ScKJJ+qBnDgogwM cIFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GPy6lM+lGGlDdnIcWgrCcXPOg/hgKZHwQM+u/2SzIUE=; b=FHkMQBJOFfzuWzxCmmwu4jkzhowPaDtPS2u39+pyX/yOkUPDEFqds1NEVGFRpF1W/e DBT3573BJ6PNUKvIgtpBAkeMOwMoZ+37JsYl2DuqLbWgaKogLOCrERFpxDQSHdBOBZgA EQE2dhvF/pVhvZTXJoCAiDMxBgC7BIXW5cLT2fFqZYD005TIRFRlhF7YZhCNF/l6yhFu pMI0BxoMB3zLPNnaZm8S4LYc77IcIWK6ikebY/DI2wyw71vk2StrybehTfPRSL/eqBOr x+zz3wZ2Ac3N9Dp53qDgY9UInnttVc6QezuFFfAazCXKzRzPcGZ3WGANeFcovbI8vNoA DRXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=B4LOV82q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h13si2170855ild.132.2021.04.16.12.15.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:15:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=B4LOV82q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49012 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTwc-0005m0-Al for patch@linaro.org; Fri, 16 Apr 2021 15:15:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50500) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThs-00040G-Te for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:45 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:35586) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThW-0004Qb-Bf for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:44 -0400 Received: by mail-pf1-x42c.google.com with SMTP id h15so1257679pfv.2 for ; Fri, 16 Apr 2021 12:00:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GPy6lM+lGGlDdnIcWgrCcXPOg/hgKZHwQM+u/2SzIUE=; b=B4LOV82qPNJQsvpB5aw3HxiFRhYA6LA0K602UhIr5GiIbz0d90mOgkhb5OKP/SIFSB JRnCHhjyTUAILmJg0vykBFbls9DSYb/nX+cGPQuuoOJwT4/c5BPOBGEb0iD7sbmjYaP0 Dx/tuIr8L41575PnlTnGp6Rdru0I5jbiWz8fRxwW8Cyt1RqXQ3H6QFesIwIHmADThznz yJ1I/B5zPwFABrrZwQh/irdhGYn9HRWMsKFCHCeT0tPu7EKe5bXZ9+GmGezOjGUSji1E emJ0bCT0hWs/L0x0bjOhSXUf0Ow9wF37CZTPB4agvV8PXaSST8cOEbs52uzOoAqV5XLW JFVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GPy6lM+lGGlDdnIcWgrCcXPOg/hgKZHwQM+u/2SzIUE=; b=UPHVcVnA2vWAjgjrN7JYaMuGnpkbcFj9zSuzptQHIEJFUdsal2/rANNW0xZuPrsU62 sooebE3EmR22BMPB2c0jsRFm0///x+tTIvhjgGBckL9cwarqTrY7dkqfkT1Nd3d1jqMp GfaTR+GE1oWMjtxb+b3A1pJraFF9iwUweTKVDW0x1zHU0PL7uBITqNR5LXXKaHVxIZk9 CHkQouYYmxuWXdBTNm2qKTINAEMVlj/rtKva2Md3SdgTijsdihrWs0tM+alqzO99oBSG HB/p9hfzEQFL5FcSyOHaNucx0tG+SfqS0WuoJqtWM+BGE6h6O79DaxhiR0gyBBZrmi9y DiSg== X-Gm-Message-State: AOAM5313YfmcfYDqn5c0/FJqkVXy7jUvqWeztRwCmnUdjeQoftoDWXqs IPZnsCOwsKl+4uo1akRnGW0bJ3TmsrwQZw== X-Received: by 2002:a63:cd01:: with SMTP id i1mr495292pgg.262.1618599620607; Fri, 16 Apr 2021 12:00:20 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 20/30] target/arm: Enforce alignment for VLDR/VSTR Date: Fri, 16 Apr 2021 11:59:49 -0700 Message-Id: <20210416185959.1520974-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-vfp.c.inc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index f50afb23e7..e20d9c7ba6 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -1364,11 +1364,11 @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a) addr = add_reg_for_lit(s, a->rn, offset); tmp = tcg_temp_new_i32(); if (a->l) { - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UW | MO_ALIGN); vfp_store_reg32(tmp, a->vd); } else { vfp_load_reg32(tmp, a->vd); - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UW | MO_ALIGN); } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); @@ -1398,11 +1398,11 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) addr = add_reg_for_lit(s, a->rn, offset); tmp = tcg_temp_new_i32(); if (a->l) { - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); vfp_store_reg32(tmp, a->vd); } else { vfp_load_reg32(tmp, a->vd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); @@ -1439,11 +1439,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) addr = add_reg_for_lit(s, a->rn, offset); tmp = tcg_temp_new_i64(); if (a->l) { - gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); vfp_store_reg64(tmp, a->vd); } else { vfp_load_reg64(tmp, a->vd); - gen_aa32_st64(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); } tcg_temp_free_i64(tmp); tcg_temp_free_i32(addr); From patchwork Fri Apr 16 18:59:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422579 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp657547jaf; Fri, 16 Apr 2021 12:17:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyFkftKEtYl9t97NoYz3nv28NPTlkwtaHvnBb/3DIgF9fTaxvhFP9+EbGo2v+hodjlqTtJG X-Received: by 2002:a05:6638:134e:: with SMTP id u14mr5549131jad.119.1618600662889; Fri, 16 Apr 2021 12:17:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600662; cv=none; d=google.com; s=arc-20160816; b=JIzGOpe2DzupLxGFx1+p0yOuFILX+3HcosawDa6IPOHH2eTKWYDx/YEe8d710nfItu /Z3nNXuxf4qi9g4zJimkllkOHWTg8fEulJ+UAf03kM4xI+GdnzVhpxM216BRS0wK+Eaw PHrExQiuew06uT2hobhdCzdCZuo7Hupv34wX+XJipOmsfu3AQ0hpn20k0aHjaY9w/T2O dM70wROM8MxtPex71vuSxY+rUSyqpRlFK+gE3eeREdL5zpNRa3Il7bdcHRVSxi5E3zGi aIKMvjUZOTZAYks1iL7bpUrnvkTSjF2gfm6HxngnGV/xiPUMDQ05/5s0sN9tnIxWr0Z5 WhBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+sb1OiK3PXbPdK4EXbSsWp1dZgv4+0of5bsvTMZpO2o=; b=kKs1QdK421SPnE+FbBIY46yMDZXJzJPxPq1fmBPUcCQChqWmV4B2e0FQN/Tl0OZVnJ yT3vOD7AojUKtwarx1gqjw3oXCj2bUn39DIniqvmK4F+ij2vyLxapuJURSzP9xtVF+fV mATCik8MUu/fgtrga1GxfpfCud57TtatB7LzVr+kaiQv7caV0cmeLZLgFxGSySwUz4vm BbPChOIhA688W1f/Go3v75gKJK4rGp3fee35idgwxpvjai4oDvYkV83nl9GedFWBxXhd Xm13ngaUu5h1xxh9aY4xqMEaZwgQBLVbQKuhZQk6ISy3eu5HLzQcSKpn8+esPsHyGXcr f3Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=crx4Egj6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j19si3264297ila.26.2021.04.16.12.17.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:17:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=crx4Egj6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55064 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTyH-00009j-Vy for patch@linaro.org; Fri, 16 Apr 2021 15:17:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50490) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThr-0003yV-KY for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:43 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:53106) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThY-0004RU-18 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:43 -0400 Received: by mail-pj1-x102d.google.com with SMTP id r13so10725167pjf.2 for ; Fri, 16 Apr 2021 12:00:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+sb1OiK3PXbPdK4EXbSsWp1dZgv4+0of5bsvTMZpO2o=; b=crx4Egj6hYxckLtJLYC7oOPbYhoUB+moSqF5lyTy3vFl6U7fnrbPgJzdmxEdrYfHAk UIiJjJsyMmz4dCkoIXex8DVGtzcSHGNmeTl1adL1ApMBtB2Zav/avtzDRBSL+Q37zrXz xzYhZhIy50JjgBmGQNOrFLZY4lVT3bsIcGhKsOQ/e2aLmmqBTHce//NgNMXhjhnAOXbz Z+uPAq1zavW1yjqYJTfBb/zivRbYpNWa3gIN1Dg+PDOnNevg3+25P5R6aMO4k24hH19i f4P0aW8oy3XYWN1V6YSy92iJQbh0IsDWJRFr/FYqERBuxvgPuUnBVHI+gfwDp3TisUh/ KOvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+sb1OiK3PXbPdK4EXbSsWp1dZgv4+0of5bsvTMZpO2o=; b=qr4ytU55XTBtoDqH9EZQzGGMlS9mMak64J2KgBq1sbY2B7DfVgU9Xdnu1GLTqOBCCL l+CgN5RHYLnnoaBtBeBbd+ewEdf4RXSS2o8Lra1s5tjQAGjr4zNS0joeDQcMLogIhhA6 FM25jObGkGMUDR1efM1DcmqvzZF0L3mFiets/jy5dBjTjEaGEO9Aa5ING2D8VVF3gzLg GY4xbZHfrkxr+sUjwMFuS4Fsr/8JgEnYRfgIKIFh3zaq6Y+tS3rTVlAn7cdr+8ajPsXB 90waE6ElS2x0EdPI75lCQQYoh4e3za8FTTXwSH/+N0OnATsphxQBbPW+J1bItUvZ+ZjM rN+w== X-Gm-Message-State: AOAM531cI52J23FMi0nuq8YA6tUHjT9/PpYBwZYqJDx2j4Q/b5MHwv0C kPPdvC7bQAL9gbI6ys2TwlQpO6ECqCLFxg== X-Received: by 2002:a17:90a:f0d5:: with SMTP id fa21mr11168701pjb.59.1618599621788; Fri, 16 Apr 2021 12:00:21 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 21/30] target/arm: Enforce alignment for VLDn (all lanes) Date: Fri, 16 Apr 2021 11:59:50 -0700 Message-Id: <20210416185959.1520974-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v2: Fix alignment for n in {2, 4}. --- target/arm/translate.h | 1 + target/arm/translate.c | 15 +++++++++++++ target/arm/translate-neon.c.inc | 37 +++++++++++++++++++++++++-------- 3 files changed, 44 insertions(+), 9 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.h b/target/arm/translate.h index 0c60b83b3d..ccf60c96d8 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -204,6 +204,7 @@ void arm_test_cc(DisasCompare *cmp, int cc); void arm_free_cc(DisasCompare *cmp); void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); +MemOp pow2_align(unsigned i); /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/translate.c b/target/arm/translate.c index c2970521c0..0420c0b0ce 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -908,6 +908,21 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var) #define IS_USER_ONLY 0 #endif +MemOp pow2_align(unsigned i) +{ + static const MemOp mop_align[] = { + 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, + /* + * FIXME: TARGET_PAGE_BITS_MIN affects TLB_FLAGS_MASK such + * that 256-bit alignment (MO_ALIGN_32) cannot be supported: + * see get_alignment_bits(). Enforce only 128-bit alignment for now. + */ + MO_ALIGN_16 + }; + g_assert(i < ARRAY_SIZE(mop_align)); + return mop_align[i]; +} + /* * Abstractions of "generate code to do a guest load/store for * AArch32", where a vaddr is always 32 bits (and is zero diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index 18d9042130..9c2b076027 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -522,6 +522,7 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) int size = a->size; int nregs = a->n + 1; TCGv_i32 addr, tmp; + MemOp mop, align; if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -532,18 +533,33 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) return false; } + align = 0; if (size == 3) { if (nregs != 4 || a->a == 0) { return false; } /* For VLD4 size == 3 a == 1 means 32 bits at 16 byte alignment */ - size = 2; - } - if (nregs == 1 && a->a == 1 && size == 0) { - return false; - } - if (nregs == 3 && a->a == 1) { - return false; + size = MO_32; + align = MO_ALIGN_16; + } else if (a->a) { + switch (nregs) { + case 1: + if (size == 0) { + return false; + } + align = MO_ALIGN; + break; + case 2: + align = pow2_align(size + 1); + break; + case 3: + return false; + case 4: + align = pow2_align(size + 2); + break; + default: + g_assert_not_reached(); + } } if (!vfp_access_check(s)) { @@ -556,12 +572,12 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) */ stride = a->t ? 2 : 1; vec_size = nregs == 1 ? stride * 8 : 8; - + mop = size | align; tmp = tcg_temp_new_i32(); addr = tcg_temp_new_i32(); load_reg_var(s, addr, a->rn); for (reg = 0; reg < nregs; reg++) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); if ((vd & 1) && vec_size == 16) { /* * We cannot write 16 bytes at once because the @@ -577,6 +593,9 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) } tcg_gen_addi_i32(addr, addr, 1 << size); vd += stride; + + /* Subsequent memory operations inherit alignment */ + mop &= ~MO_AMASK; } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); From patchwork Fri Apr 16 18:59:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422580 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp657555jaf; Fri, 16 Apr 2021 12:17:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwsatC4THwftyLJmvjwb4/MawQ+ciT2y7a3aVs1ozxijl9K6ega7IUqmR0diWYy7wmwygK0 X-Received: by 2002:a05:6e02:e0a:: with SMTP id a10mr7945142ilk.271.1618600663482; Fri, 16 Apr 2021 12:17:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600663; cv=none; d=google.com; s=arc-20160816; b=m2UvI1f0LxbEHZBVs02fS3Lmlqs/edc9Vz4C7nje4kCezG4lzEnO6A/mJ4c+Ij+cRo PhU9jOu8n4L2o9GWjCudlKuST/HuZux5+zmvJxzhY+jH189mYUhTPfjZSM2lt9p0xpru c1eeut9MN2QuK5RXtqLoSUgyKQxF3gPGmvRVjU8go5vFphP7CybSu9v9ZvKpluCZPiT2 ZWrMZ1groDLU5BreWF3B7GM6m6iJwchEWX4OE6eBWTJFVrPUNlkUEpizYgJ3WnAzf3Zc khoOb7Gp7k1EcNEdqp63wjWTMtZ1bOTRrQxEXp9Wa41lxkP16Vs/8NkdFegx0AH2Yrye yCpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kFpRdpzIBHPgybwqUXYjnSl/F8QbD35R7VDxiD3dIh0=; b=kM0UOQf095yUwLJpAxgnPzHPJBOI5BGHKuIBJqz6x8GaKHW530HF7iHu0aFSqhNYbn Jr8shywNhudBo9ZfHzh5Qq8lXaIMru0MiCQq9wfIUXBAPXP1HYlkRMuqQ0DDxfDXAX7B gx7fxqvLdXUnYpg682sW85kip0pTHzILVsiVraZvZZEo0VuYwo/x62UlycLqZsNZgH17 usjSUzWKQXv94qSikZD0JzJPEtZZiEVzeXAtbCTeMCgwMX+6qdoWqE54oMrQ/CLOaBfe ab0WifODQayObqK58isW+BGJ3oBOQHPcTp8Y6MkWUPyaelw/R7pHSsoR2INL/YJBZZ4R bVbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dK5vU8r1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o2si3999447iop.0.2021.04.16.12.17.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:17:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dK5vU8r1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57666 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTyJ-0001CW-0E for patch@linaro.org; Fri, 16 Apr 2021 15:17:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50514) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXTht-00040X-Ae for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:47 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:39523) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThY-0004S3-2M for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:44 -0400 Received: by mail-pl1-x631.google.com with SMTP id u7so12665431plr.6 for ; Fri, 16 Apr 2021 12:00:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kFpRdpzIBHPgybwqUXYjnSl/F8QbD35R7VDxiD3dIh0=; b=dK5vU8r1ytZLQgQHxf64w+EzZze2eOmH3UjyvumWGf8cu/yaxjnwhMMcHQKcS6jQu9 u6hkDNzWT3PF+2SoPdk62aU9r1gGQcyUYACA2A+lnQ3u9AIkToSqYoF30+tNn3zS1bsy T1R67UDMo6s2bzirTriAzvDCtkgWif2aU+A/CC3+VyWS2TFAHKiR2Y6AYxcCUU+y9PiC tN/JzDIn8dQjXdbACGIv0stCwI0eAZNbbMcGcnQtKVqb6eRjM5YoNB/y2Ue4YPCD4Qi/ 1Hp90ulhZJudoIEWDAJJ2tQ73uhmRgeyLsXXSV9Qs26dLCwTNITJws7xhI9kkjy2hplG FxKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kFpRdpzIBHPgybwqUXYjnSl/F8QbD35R7VDxiD3dIh0=; b=l2ub08+eLbTAEo1S2Vn1i4/HR+MyuEpUDo365WrttgTSEUvM/pBygdXq1H1zKuc5ps 0MWoH+FDQBz/pvP7bKu5uuCgZnGvwb+mZVYR40KaKOls1u8r+vZQVkx3QMxU+eFJLGia gOaA98jmIqdbq34032ThCR+bDQeAv0b9/2TxA57IPez13E+Dzrg7GGSCo+90w4nNGCpg jTZa6qu1BO5UHhnPuXB3By15fWPVguXVU7NKAsiMLxtxBnbyTa25y4Z9s5m4YeINHg2O yzNfz10LFwyqB8X/KgfdBGJgIGlmdfFC/SZJQ5CZMj2ioCnzUcWmdzKP0aYpDBqY0Cqy 6T+A== X-Gm-Message-State: AOAM531Us1xv20bAIw5zMPUTk5C4EuwYBRLDHCMSh3xfKdQMZ1seN/o3 Kt/oAs+8XMPW1VNyVuNHQMIf8+1RalYWDA== X-Received: by 2002:a17:90a:5b0b:: with SMTP id o11mr11186341pji.18.1618599622561; Fri, 16 Apr 2021 12:00:22 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 22/30] target/arm: Enforce alignment for VLDn/VSTn (multiple) Date: Fri, 16 Apr 2021 11:59:51 -0700 Message-Id: <20210416185959.1520974-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-neon.c.inc | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index 9c2b076027..e706c37c80 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -429,7 +429,7 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) { /* Neon load/store multiple structures */ int nregs, interleave, spacing, reg, n; - MemOp endian = s->be_data; + MemOp mop, align, endian; int mmu_idx = get_mem_index(s); int size = a->size; TCGv_i64 tmp64; @@ -473,20 +473,36 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) } /* For our purposes, bytes are always little-endian. */ + endian = s->be_data; if (size == 0) { endian = MO_LE; } + + /* Enforce alignment requested by the instruction */ + if (a->align) { + align = pow2_align(a->align + 2); /* 4 ** a->align */ + } else { + align = s->align_mem ? MO_ALIGN : 0; + } + /* * Consecutive little-endian elements from a single register * can be promoted to a larger little-endian operation. */ if (interleave == 1 && endian == MO_LE) { + /* Retain any natural alignment. */ + if (align == MO_ALIGN) { + align = pow2_align(size); + } size = 3; } + tmp64 = tcg_temp_new_i64(); addr = tcg_temp_new_i32(); tmp = tcg_const_i32(1 << size); load_reg_var(s, addr, a->rn); + + mop = endian | size | align; for (reg = 0; reg < nregs; reg++) { for (n = 0; n < 8 >> size; n++) { int xs; @@ -494,15 +510,16 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) int tt = a->vd + reg + spacing * xs; if (a->l) { - gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, - endian | size); + gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, mop); neon_store_element64(tt, n, size, tmp64); } else { neon_load_element64(tmp64, tt, n, size); - gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, - endian | size); + gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, mop); } tcg_gen_add_i32(addr, addr, tmp); + + /* Subsequent memory operations inherit alignment */ + mop &= ~MO_AMASK; } } } From patchwork Fri Apr 16 18:59:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422583 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp658315jaf; Fri, 16 Apr 2021 12:19:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzE/nlZZngehpB2zDA9s/59xqJKVh7R3ktQdHqxW7LKq2CaW4TUvnh3TONnL9XVy5rs/wwa X-Received: by 2002:a92:1a0a:: with SMTP id a10mr8352630ila.195.1618600741576; Fri, 16 Apr 2021 12:19:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600741; cv=none; d=google.com; s=arc-20160816; b=hghHoxTjnYmuRdkJsnv/8+7ju62U9j/W4HT9ogydKIKl6I92lpjS3uphyv46VTVKo0 3tIcs1bVEF/GkpDuaDUSBzd0BkZJk+GQSPlkrd6WrMavkP4mYJ59Vmcd0Jz8rUdp4oE5 GDXhP467pJ/itwGdYXg1nQjANjMSWAU9DRc8fspiWj2oxiWJeByT25XKI+952bmuSYY+ AICXT1PrhdBS7iQmQzTQl/swUCRzSiBSOlB3bFWiQiLcSMjIc1fJFgFXaWOrs0GaRdNa OcUG5KkF0fk7aZhbvAP4Yb/R5NBP1fhEJNVyWHZ+C6pbzGI7O8S+Nq6lnyXgv6ERUR8a f6tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZxTe0vrdv36w4KUhkfdQi48uXdXMfkmKMdEHX8Xoc08=; b=BOWWccoEvRrxzxAFz+/z2ZCewPgFJTgFUlw9DegXX7umCR+Zg2fdhBot1Gl8hcnbXc 1+zVfMBazOnUh6jZQmGF02h7CVbmRBN1EBz/HfsxYeTlMi5LZCXgjzyNazeSG0Lbsi4w LOJbzyxJR908h0hvG7ZFbZvlT9CWAcJWEV/ph6SHdSkb1MjUyBuM/Qr3lyVNfVamULuL 6OZ1FAfxSPvdO2X+QEVX7yxZsMhKdVfIn0zJ2yP9wtJ9cQj0hivNyiPHwPIfcLJXM9wb iC8MKX+RluHMHHFgp3GcHoJaDMZROy4p22Z0sDRIHGu2mN++GUso8uRf8dvsWs7VSUKJ mIWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ltAYMOAt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t12si2658434iof.82.2021.04.16.12.19.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:19:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ltAYMOAt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35568 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTzZ-0003g2-2D for patch@linaro.org; Fri, 16 Apr 2021 15:19:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50590) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThz-00042x-IS for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:55 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:43554) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThZ-0004SS-2H for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:50 -0400 Received: by mail-pj1-x1033.google.com with SMTP id x21-20020a17090a5315b029012c4a622e4aso15104865pjh.2 for ; Fri, 16 Apr 2021 12:00:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZxTe0vrdv36w4KUhkfdQi48uXdXMfkmKMdEHX8Xoc08=; b=ltAYMOAt86lv/kmqVDsSgs7r/fplbUiH7CHIQvfEob9VCNhNGMUH71QwSfCGDJ4KVS f+3EfUd2SDe71jLl105Km2G8Wfq9ob33dnPVRedreDdkD1wb3JsoCbRbBXZA06b16Ixp bEaxJmQ6zFbGn7ZYHjRBNqIr/+D10cEh8ktfYSmcJhF7BLPpcv39HkkJrr3Y492es2pr DZPYpT0aSfgrqw9KV1BntVqTIvQFnpU4XDbCwU+j7NZKt1u8EBQX8ro1MQbq+JFBr5ve Uk3U700QurPN2mSi4Fc53AzofS3GhGfv3fAlQd8EuVQqX1p68GaUcJfLJ+gtVokDgx6i T53w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZxTe0vrdv36w4KUhkfdQi48uXdXMfkmKMdEHX8Xoc08=; b=S9CBEobv2gFLgDMNnNzU/wx7VU+aVAz6SuTVMmr0s+3J6/zykhiY3+IDT7J4sQlw18 wLDl+qW/h1vLYaKx07vIulDk6F5BLIw2qYGU3mGvd2bytUd7vQjlAWZJhl+gVoSqjivw mzAty0T8SSwywbNcSyo93h5pxaaDtI4a6soTtdhCZq5vCQD24Ih/xet/0EO0sZl4qlvV 0e59wiMczYeEw9lnsWBEX+Z0cEmPbAjKT4LMX5p8gzXYQTx0I8Fappq9CUXqfUT8FdLy wYJaf1lTWWj4XlhhNf67UK0s2XSFKMb4rXq2ZzhGfCUxjcGYtJyBJ8Z0nCPwjhyFNaAV 9HkA== X-Gm-Message-State: AOAM532q/ivfT9QmvN+QvFfcPl/p4RX83ZF+l3HjZYJ9BLlc5J2KGLvL LQ+0qilr5jVLoQP+p+PBVtGs0O0O8KM6Yw== X-Received: by 2002:a17:90b:30d2:: with SMTP id hi18mr10960343pjb.94.1618599623561; Fri, 16 Apr 2021 12:00:23 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 23/30] target/arm: Enforce alignment for VLDn/VSTn (single) Date: Fri, 16 Apr 2021 11:59:52 -0700 Message-Id: <20210416185959.1520974-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-neon.c.inc | 48 ++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index e706c37c80..a02b8369a1 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -629,6 +629,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) int nregs = a->n + 1; int vd = a->vd; TCGv_i32 addr, tmp; + MemOp mop; if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -678,23 +679,58 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) return true; } + /* Pick up SCTLR settings */ + mop = finalize_memop(s, a->size); + + if (a->align) { + MemOp align_op; + + switch (nregs) { + case 1: + /* For VLD1, use natural alignment. */ + align_op = MO_ALIGN; + break; + case 2: + /* For VLD2, use double alignment. */ + align_op = pow2_align(a->size + 1); + break; + case 4: + if (a->size == MO_32) { + /* + * For VLD4.32, align = 1 is double alignment, align = 2 is + * quad alignment; align = 3 is rejected above. + */ + align_op = pow2_align(a->size + a->align); + } else { + /* For VLD4.8 and VLD.16, we want quad alignment. */ + align_op = pow2_align(a->size + 2); + } + break; + default: + /* For VLD3, the alignment field is zero and rejected above. */ + g_assert_not_reached(); + } + + mop = (mop & ~MO_AMASK) | align_op; + } + tmp = tcg_temp_new_i32(); addr = tcg_temp_new_i32(); load_reg_var(s, addr, a->rn); - /* - * TODO: if we implemented alignment exceptions, we should check - * addr against the alignment encoded in a->align here. - */ + for (reg = 0; reg < nregs; reg++) { if (a->l) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), a->size); + gen_aa32_ld_internal_i32(s, tmp, addr, get_mem_index(s), mop); neon_store_element(vd, a->reg_idx, a->size, tmp); } else { /* Store */ neon_load_element(tmp, vd, a->reg_idx, a->size); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), a->size); + gen_aa32_st_internal_i32(s, tmp, addr, get_mem_index(s), mop); } vd += a->stride; tcg_gen_addi_i32(addr, addr, 1 << a->size); + + /* Subsequent memory operations inherit alignment */ + mop &= ~MO_AMASK; } tcg_temp_free_i32(addr); tcg_temp_free_i32(tmp); From patchwork Fri Apr 16 18:59:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422587 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp660877jaf; Fri, 16 Apr 2021 12:23:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzw+qsLsuCXvZQPq4pgaw3kzaMv9cn/hMa5qRZgBEeRwVr7Ky5AprxdnQdMc54phIPnoip1 X-Received: by 2002:a92:c5c1:: with SMTP id s1mr8473575ilt.295.1618600999646; Fri, 16 Apr 2021 12:23:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600999; cv=none; d=google.com; s=arc-20160816; b=dPmJTbK+5DQcMsy83dY0pwvatFrJOXkv4yk7nikTGT8iJXzHDL6uy4mBZKD0pMw5V3 ywRxE5ZIoncUlarxjZVt/1dbdLJ+q8/4jjX2sc6BSqyNBEvj5kPsgHp/BZK+T1OGup7N e1FZQS032IDA+vnWJDl03YEos2Vl08QoNrbnza9XFkR3eKITj1ggKmIBcQ5csPpuKj02 Mkz3PcLMWCHzYndF+Jpi8R5Yh5SU3j7IHDF+qX2s22LLRlLQE+6muUWnNmi22s/huVyX GoqEG1ovum6X8SpZGGtoslakXLI06gq7sCynN1ZroOYdWzG1ecsZ+pQOGSVw+ivhjN/3 CUxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3RCCb6g/8oqZVVFrzfzAA8xyWzyQtEiKHnjFMLf0Q3g=; b=PUAeTEBDRwPxHEZLUdSYxgiLU8okzPEXbGmEDxd8uRyo497Fqdnq8yIowYBkCYUkR2 IxMxuDdhRiEcMydvNHKEI3DTZK1VXYckUYOrUDTxWL4/1jqa9Y2NkFt+2v1TO/GW9Ovj QMf2CiBrQtwnp7HF6hs6SHyWBPNNguU01v2/H8AmXcN645eaa/Hdgu6tifEdompILKIa fURBL5uvDGBOu8HjQ31Pd+8h3eOpC79es12kLFwQo4y+ECrQhNbqkaDE/9FD9MrajBP1 M0/Bm9+RzfN6XRK86qJKDOXtsvKoSRlBZM0FfMb7dbShBfAm1WAvPIZnSanCEV8KHBWk 0R5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YI2gHcmu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c3si6371802ilk.51.2021.04.16.12.23.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:23:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YI2gHcmu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXU3j-0001fM-2T for patch@linaro.org; Fri, 16 Apr 2021 15:23:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXTi5-00043t-L8 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:59 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:40749) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXTha-0004TB-1k for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:55 -0400 Received: by mail-pj1-x1029.google.com with SMTP id b8-20020a17090a5508b029014d0fbe9b64so16891247pji.5 for ; Fri, 16 Apr 2021 12:00:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3RCCb6g/8oqZVVFrzfzAA8xyWzyQtEiKHnjFMLf0Q3g=; b=YI2gHcmuO/DcWLVSy7GKxYtY9Y5P7rgi720e5JOgFvEvZ++VO0TlbRPUHlCxbazjt3 NuVedm0okFwnjmMlIx69T8gmAqEIeHaoZrLSls+ReDiKw0r0Stru0ijNWnHPJbbFiSUJ PLhmR8ob+/OXWTwV9TaM1p7hJuPgqjU4nsQs/oOQ8zpXhuJ5Xp8CfoysxcM29X7V22i1 Nz9S9ozJMlMn7ImeqdydKlTQUv20SgJXCw4u5rP3V8cQlz7OaFXArNmozLM5yJ2gdOEJ yXTcsEJtiQpAzfHmHiZ46YilMypxyKRMctwAlBFJ9wUZuozzisH9jlP2xxa0szlU5Cst gD7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3RCCb6g/8oqZVVFrzfzAA8xyWzyQtEiKHnjFMLf0Q3g=; b=bkqxJmevepWsMHRevpUl2QAxv3mFhUNkiYjFzYPOSVzKvY5um6vUBeqUzpm0+vPBsH KGchqOTD62EZneFnno38Q9TZUqQr18vOhBcLn06pBrDgQj6/yr9v/DOYxqnnwGjQJ80E 1xe91ouT1CP1fb+Ner0oiE858ug89S3rhCGKRTclKrS8/dDNmOLrnvyE/t1cIOtYAu71 w5F/PGzyN+bZPA5iOVq3RFDgZsgNAWWEtotKPvpKrEGRt0GWUwnJP0h+CATO2N+hWShO 0GKdBVFvgLZW0WhoKhExNrDJXVEeZnjqVtnKJBU0doXhArlN8Uy3zg36eVzYenITDH6q 37Jg== X-Gm-Message-State: AOAM532+TtWzFgv4m0SSPjdkf63Xu0mq/7NXx9kUVjWanHEhbqHeOcmQ 7LvSJW1dWOsnvnJzRpzauIIMjrUtxyoeQQ== X-Received: by 2002:a17:90b:2305:: with SMTP id mt5mr11480353pjb.198.1618599624553; Fri, 16 Apr 2021 12:00:24 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 24/30] target/arm: Use finalize_memop for aa64 gpr load/store Date: Fri, 16 Apr 2021 11:59:53 -0700 Message-Id: <20210416185959.1520974-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the case of gpr load, merge the size and is_signed arguments; otherwise, simply convert size to memop. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 78 ++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 45 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 92a62b1a75..f2995d2b74 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -886,19 +886,19 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) * Store from GPR register to memory. */ static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, - TCGv_i64 tcg_addr, int size, int memidx, + TCGv_i64 tcg_addr, MemOp memop, int memidx, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - g_assert(size <= 3); - tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size); + memop = finalize_memop(s, memop); + tcg_gen_qemu_st_i64(source, tcg_addr, memidx, memop); if (iss_valid) { uint32_t syn; syn = syn_data_abort_with_iss(0, - size, + (memop & MO_SIZE), false, iss_srt, iss_sf, @@ -909,37 +909,28 @@ static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, } static void do_gpr_st(DisasContext *s, TCGv_i64 source, - TCGv_i64 tcg_addr, int size, + TCGv_i64 tcg_addr, MemOp memop, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s), + do_gpr_st_memidx(s, source, tcg_addr, memop, get_mem_index(s), iss_valid, iss_srt, iss_sf, iss_ar); } /* * Load from memory to GPR register */ -static void do_gpr_ld_memidx(DisasContext *s, - TCGv_i64 dest, TCGv_i64 tcg_addr, - int size, bool is_signed, - bool extend, int memidx, +static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, + MemOp memop, bool extend, int memidx, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - MemOp memop = s->be_data + size; - - g_assert(size <= 3); - - if (is_signed) { - memop += MO_SIGN; - } - + memop = finalize_memop(s, memop); tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); - if (extend && is_signed) { - g_assert(size < 3); + if (extend && (memop & MO_SIGN)) { + g_assert((memop & MO_SIZE) <= MO_32); tcg_gen_ext32u_i64(dest, dest); } @@ -947,8 +938,8 @@ static void do_gpr_ld_memidx(DisasContext *s, uint32_t syn; syn = syn_data_abort_with_iss(0, - size, - is_signed, + (memop & MO_SIZE), + (memop & MO_SIGN) != 0, iss_srt, iss_sf, iss_ar, @@ -957,14 +948,12 @@ static void do_gpr_ld_memidx(DisasContext *s, } } -static void do_gpr_ld(DisasContext *s, - TCGv_i64 dest, TCGv_i64 tcg_addr, - int size, bool is_signed, bool extend, +static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, + MemOp memop, bool extend, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend, - get_mem_index(s), + do_gpr_ld_memidx(s, dest, tcg_addr, memop, extend, get_mem_index(s), iss_valid, iss_srt, iss_sf, iss_ar); } @@ -2717,7 +2706,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) } clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, size); - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -2830,8 +2819,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) /* Only unsigned 32bit loads target 32bit registers. */ bool iss_sf = opc != 0; - do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false, - true, rt, iss_sf, false); + do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + false, true, rt, iss_sf, false); } tcg_temp_free_i64(clean_addr); } @@ -2989,11 +2978,11 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) /* Do not modify tcg_rt before recognizing any exception * from the second load. */ - do_gpr_ld(s, tmp, clean_addr, size, is_signed, false, - false, 0, false, false); + do_gpr_ld(s, tmp, clean_addr, size + is_signed * MO_SIGN, + false, false, 0, false, false); tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); - do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false, - false, 0, false, false); + do_gpr_ld(s, tcg_rt2, clean_addr, size + is_signed * MO_SIGN, + false, false, 0, false, false); tcg_gen_mov_i64(tcg_rt, tmp); tcg_temp_free_i64(tmp); @@ -3124,8 +3113,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, iss_valid, rt, iss_sf, false); } else { - do_gpr_ld_memidx(s, tcg_rt, clean_addr, size, - is_signed, is_extended, memidx, + do_gpr_ld_memidx(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + is_extended, memidx, iss_valid, rt, iss_sf, false); } } @@ -3229,9 +3218,8 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, do_gpr_st(s, tcg_rt, clean_addr, size, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, clean_addr, size, - is_signed, is_extended, - true, rt, iss_sf, false); + do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + is_extended, true, rt, iss_sf, false); } } } @@ -3314,8 +3302,8 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, do_gpr_st(s, tcg_rt, clean_addr, size, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, - true, rt, iss_sf, false); + do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + is_extended, true, rt, iss_sf, false); } } } @@ -3402,7 +3390,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, * full load-acquire (we only need "load-acquire processor consistent"), * but we choose to implement them as full LDAQ. */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), true); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -3475,7 +3463,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, is_wback || rn != 31, size); tcg_rt = cpu_reg(s, rt); - do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, + do_gpr_ld(s, tcg_rt, clean_addr, size, /* extend */ false, /* iss_valid */ !is_wback, /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); @@ -3560,8 +3548,8 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) * Load-AcquirePC semantics; we implement as the slightly more * restrictive Load-Acquire. */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend, - true, rt, iss_sf, true); + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size + is_signed * MO_SIGN, + extend, true, rt, iss_sf, true); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } } From patchwork Fri Apr 16 18:59:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422585 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp659393jaf; Fri, 16 Apr 2021 12:20:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwcGP47+Wxk5/Oyq9udWtCpm+oZJBB3ZC0UGtTSYAr179Qrx6NLP+oBlnLG9VA19G3L3cFG X-Received: by 2002:a05:6638:2508:: with SMTP id v8mr5363107jat.133.1618600841007; Fri, 16 Apr 2021 12:20:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600841; cv=none; d=google.com; s=arc-20160816; b=WD0uvaY7dEWusaxRpFuK2RrIwSwJ8z/CbXhWiNSalXuHipav8cM/yAQLD+LMFu6nrf ML7O7CkQpHevKiP7E/LHA4RbhyHLUJsMPzd10Davd5+So+2w5EDi0aSNpV02f6fGQhv8 DygtgI4Dp4lIloBSHf97QCdMHL0x1A/nsmVdpIhehDXCQnWvuPDA2FLzYQ7dPnHE5pVX cnNGgSr4YHfgwM4L2AY4iRZx57WIFEJGh/n/jetnjOkYpEjyNMTl/NqTTGuCIthT4WUh tYkgw0d2Ua0O5xBclezl5NygPE+WXcEU64xaEkqF3bbSEt6XE+GDS+uGc1LWzroUE+Kx DLXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JvIEukWRJcec2HtgegM57M5MObIvx3MKZPreWQgWndE=; b=d8X2wGAsnJyFNxSzr08/9c91hxjtQItuy4IqfEvfpgPDwBv/2889e+/RFhgplMceV/ /H7uJUEGf0uvWRy9fHZzZByD97Xd3jyaSh6WZmBanIo3JeaC9lDLiV9aeCq4TTm6PK9Q taVAKXFHGCcR59qK8EV15ntlh1oAm6djyZZ/536fgoIdGfrOtSKIvqYGyt4tx54fbx2/ YZYq8I5mbsg7ySKUu5O1o2s87SskZfWsj52J8CI6XXiMsg3KrAzCAUKVoLv3WESMBcAF mKchMg1q4cr/nkyjayusEWmfGqzG95SNAojnGoQnGl7/qJNlO5/SJJ3f8cB9M4YmOL7W YDIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yFUMFO9x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h10si6430716ilo.148.2021.04.16.12.20.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:20:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yFUMFO9x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40336 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXU1A-0005Zc-9R for patch@linaro.org; Fri, 16 Apr 2021 15:20:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50658) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXTi6-000441-UR for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:59 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:40602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThb-0004TK-VW for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:57 -0400 Received: by mail-pl1-x62a.google.com with SMTP id 20so10524590pll.7 for ; Fri, 16 Apr 2021 12:00:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JvIEukWRJcec2HtgegM57M5MObIvx3MKZPreWQgWndE=; b=yFUMFO9xoRJ83pGRrwjhUbC3pZHO4Lc4Z6IZI7XqTZhoqpWMUVcUpLy9Q9UbXTihuz HDNQJeuJFTNwU6vNPbe8WI1/ZXYgJ68jspnz8r+wOae4qNMiJ9MKPCtMGHJpNyW0CjyB ZSLESLcQAuD6ykfybyS1Ll6OapdAclWQ8oRA2+6zKFx5oXyfzdCDPjR3k4odubUPc1aF bJkE/ZmLIv41Hryj0MeBec2D7UKQKWiVnnXU/CABxMTQPv7kC7YHGpXkyr7cYQJMCFbI bq4H2VrahfFeajoFS7mU1ni9ctIoVVrdqocEjfyj/2e6VFDN4CRNnz1w320WeauC1uU9 XSWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JvIEukWRJcec2HtgegM57M5MObIvx3MKZPreWQgWndE=; b=dOm7lfKxT4aAPPw8N1DDanDd90Xl0LGvfyfdt8+xzE9njnWPBt/Np35uwwsPpSA9cM otG/ePIAi257sfzuMDVg69lVGV45E1/OPAUfwV69vZsOcLthPQVD8+XFglhfL7GoQeVc IqvtyJJAan0fEmZZijPQKGEwDY9U9kim3pEfVeSG8QemFn1bJV+fGgaYi5bzlKgIWxES EebtAKBzQyHw1awXQCInAtEgFEMQsB1OL9hn+uriCCsfhkPSmGYMoSV8ceVPN63rsdW/ xPtQzM/phGSPxMgVw3ZAz3FLC3YmGTnBaO+dpqusVEMeLdhGLqh8DW3oe83JRadUpJ+z h80w== X-Gm-Message-State: AOAM532cCvf5Ad07ptxbnuZa52Z8dFCLdLr6lzhW4nvtBwKKQ9DqzzSD GKTwBQT4+/uemZgoJzSl2EqfkA5S82ayHQ== X-Received: by 2002:a17:90b:2291:: with SMTP id kx17mr10970936pjb.79.1618599625568; Fri, 16 Apr 2021 12:00:25 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 25/30] target/arm: Use finalize_memop for aa64 fpr load/store Date: Fri, 16 Apr 2021 11:59:54 -0700 Message-Id: <20210416185959.1520974-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For 128-bit load/store, use 16-byte alignment. This requires that we perform the two operations in the correct order so that we generate the alignment fault before modifying memory. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 42 +++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f2995d2b74..b90d6880e7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -963,25 +963,33 @@ static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) { /* This writes the bottom N bits of a 128 bit wide vector to memory */ - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64)); + TCGv_i64 tmplo = tcg_temp_new_i64(); + MemOp mop; + + tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64)); + if (size < 4) { - tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), - s->be_data + size); + mop = finalize_memop(s, size); + tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { bool be = s->be_data == MO_BE; TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); + TCGv_i64 tmphi = tcg_temp_new_i64(); + tcg_gen_ld_i64(tmphi, cpu_env, fp_reg_hi_offset(s, srcidx)); + + mop = s->be_data | MO_Q; + tcg_gen_qemu_st_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s), + mop | (s->align_mem ? MO_ALIGN_16 : 0)); tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); - tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), - s->be_data | MO_Q); - tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx)); - tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), - s->be_data | MO_Q); + tcg_gen_qemu_st_i64(be ? tmplo : tmphi, tcg_hiaddr, + get_mem_index(s), mop); + tcg_temp_free_i64(tcg_hiaddr); + tcg_temp_free_i64(tmphi); } - tcg_temp_free_i64(tmp); + tcg_temp_free_i64(tmplo); } /* @@ -992,10 +1000,11 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) /* This always zero-extends and writes to a full 128 bit wide vector */ TCGv_i64 tmplo = tcg_temp_new_i64(); TCGv_i64 tmphi = NULL; + MemOp mop; if (size < 4) { - MemOp memop = s->be_data + size; - tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); + mop = finalize_memop(s, size); + tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { bool be = s->be_data == MO_BE; TCGv_i64 tcg_hiaddr; @@ -1003,11 +1012,12 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) tmphi = tcg_temp_new_i64(); tcg_hiaddr = tcg_temp_new_i64(); + mop = s->be_data | MO_Q; + tcg_gen_qemu_ld_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s), + mop | (s->align_mem ? MO_ALIGN_16 : 0)); tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); - tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), - s->be_data | MO_Q); - tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), - s->be_data | MO_Q); + tcg_gen_qemu_ld_i64(be ? tmplo : tmphi, tcg_hiaddr, + get_mem_index(s), mop); tcg_temp_free_i64(tcg_hiaddr); } From patchwork Fri Apr 16 18:59:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422574 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp655188jaf; Fri, 16 Apr 2021 12:13:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJylr5yclXxkTnR83x/0rLiUlnMwlHmFqMYFkwqPbuFqHJpn+GYPiDIXfJ8q6gBczCuTOU9+ X-Received: by 2002:a05:6e02:12c4:: with SMTP id i4mr8373733ilm.79.1618600432803; Fri, 16 Apr 2021 12:13:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600432; cv=none; d=google.com; s=arc-20160816; b=jzEZ3yY3Lyf3pcU7PBWYucnuECbA4cVrZ9Dj+sA+s2DneNpbXFQciUCBpBoOxAou0b DX9Uny6jSlcTYiPgOQJMBs2/dLWO2oPZVjL7kcGCiOjCnNhSKm3wPC1FIFqIZwmXd45C 3O1/WEjTP1qdIIj/3d5xu2Q7H+kSFLR4YEYmq9fJdDkZvCm+8jzwJVfKz8hoBWFI2n8f uQq9SUyS/Cl9ly6WRRm9Hfq2uPSsyHrEow/zANuVtfVR/3CkQB1kvYoMDnwjCXSwzT7P cjJNPCLlO6XQoiKJKE00PgKEB7cdJiMeaVSm57brxQFfOXWGAIQMQ2llj6R7GqEwtzMM NdIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4YmyrCHsuRewu4q7IzToC9sV4YEHbKzZOaqHia3EHmw=; b=m8h/jYzcjj8xQwakZgqlrMmgHFVHSbZSpbOF3c/pkDgeGWitBJvHxGBaXqBpApGiQL uhBcJrDsjJ3odupMlsHbMO2DrZCAo+xcJmNYTO5+8Thhwv7reoPNNEkq2mAk0ckcEnYU Sg6kNzVtlP2q6VpJJJuCdEdGUk7RdVd8Cox50Bvbe4Lp8H9aeIeABFr14v97ghoyNTxg eTGnGYK/aogoFfoah6ds5z2GaEz61Nr2+luGACipaSQ8RoClbXt9CJ9f9oNZapHgP6y3 sCcgpxHrFbCs/x8yailiWAWR0PP/XByN03CuaLjAzzMuqsmCDJfk3iTR5D3wIaBLpkGB Y4Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IwAjoN70; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g19si1135868jat.91.2021.04.16.12.13.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:13:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IwAjoN70; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42366 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTua-00032k-8S for patch@linaro.org; Fri, 16 Apr 2021 15:13:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXTi6-000440-UD for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:59 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:53815) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThb-0004TZ-VB for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:57 -0400 Received: by mail-pj1-x1033.google.com with SMTP id nk8so1353253pjb.3 for ; Fri, 16 Apr 2021 12:00:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4YmyrCHsuRewu4q7IzToC9sV4YEHbKzZOaqHia3EHmw=; b=IwAjoN70hRWeh3MYx/1PnYv+cGIuW9RRGf5UqDkUYjqI6Uwyh+naFo570QuneTnhvD KObAhv6AyqucCb7hiJ+MMf/dNAtf8azE1hUPKZvkzcXAUnoRJWOTbctpQIT38UHjhlgj T+1FwJJsrjv5kUW5BKOBOkRFHfXioLYgIya6RmKJ9jYTGBzHAa/JjdgHfm1X00qzoAsf 865dAbSifzHBq0G9r+onnMDtP4zH2cerRJ6G3exNYedOq9e5AlzOOexp0MRl7KXrsQ0P R/KFMOsMA8nSO/YPDoscw9KujsA26lhTyKnStch7dm2j8PkK675swKJduuGfUH77jPdO 8Ltw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4YmyrCHsuRewu4q7IzToC9sV4YEHbKzZOaqHia3EHmw=; b=hQxN4agdRr5sTG05mvb+irjn/4+hfqqqO6Y4GiHq4Cj1Yv5C6aRcey8WWO21O34oHm wgXk6RIxG7/XD//D8TNCkrKHDfEXsl8MQzrciFT2+aAModGUFoOzVoTUJjjzvKZmr6bD 3sMpemduL9NB4HpIm/vHBNcxnchr8+T1xEkCYD6qocw6CNceNz8NiC54PAo9gkHjJ0Vd MqNs4FlV1OwfJhhGSNmuZ4toLl6EuQXVD/E1NOrV+70E0yypOwUmQIBEGUkgQlU+mW9h 4k0C5+Z/g9NUKTsWRwsEdEI3+2u7QbeMwEiIiwmIh7bKe/bQbcHSQG4Uysxo4nWSTLmM 482g== X-Gm-Message-State: AOAM5316My+NeqG2jlrW3iX5DiYNN/X4+BSqmCWxLdlR7iuPScXlTq4f UKJoeo7emPoRa9j56dZ+ikDxqOVrZrFFrw== X-Received: by 2002:a17:90a:6396:: with SMTP id f22mr11221502pjj.91.1618599626461; Fri, 16 Apr 2021 12:00:26 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 26/30] target/arm: Enforce alignment for aa64 load-acq/store-rel Date: Fri, 16 Apr 2021 11:59:55 -0700 Message-Id: <20210416185959.1520974-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b90d6880e7..ac60dcf760 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2699,7 +2699,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, size); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + do_gpr_st(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2716,8 +2717,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) } clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, size); - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt, - disas_ldst_compute_iss_sf(size, false, 0), is_lasr); + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, false, true, + rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -3505,15 +3507,18 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) int size = extract32(insn, 30, 2); TCGv_i64 clean_addr, dirty_addr; bool is_store = false; - bool is_signed = false; bool extend = false; bool iss_sf; + MemOp mop; if (!dc_isar_feature(aa64_rcpc_8_4, s)) { unallocated_encoding(s); return; } + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + mop = size | MO_ALIGN; + switch (opc) { case 0: /* STLURB */ is_store = true; @@ -3525,21 +3530,21 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } - is_signed = true; + mop |= MO_SIGN; break; case 3: /* LDAPURS* 32-bit variant */ if (size > 1) { unallocated_encoding(s); return; } - is_signed = true; + mop |= MO_SIGN; extend = true; /* zero-extend 32->64 after signed load */ break; default: g_assert_not_reached(); } - iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); + iss_sf = disas_ldst_compute_iss_sf(size, (mop & MO_SIGN) != 0, opc); if (rn == 31) { gen_check_sp_alignment(s); @@ -3552,13 +3557,13 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) if (is_store) { /* Store-Release semantics */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true); + do_gpr_st(s, cpu_reg(s, rt), clean_addr, mop, true, rt, iss_sf, true); } else { /* * Load-AcquirePC semantics; we implement as the slightly more * restrictive Load-Acquire. */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size + is_signed * MO_SIGN, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, extend, true, rt, iss_sf, true); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } From patchwork Fri Apr 16 18:59:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422588 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp661893jaf; Fri, 16 Apr 2021 12:25:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzurWqqqF0dycJBd4uQEfcctEmcj6hJc2klFNd0cQhwsCtMynNWpRJADUO9QkUP3mjPGZzR X-Received: by 2002:a6b:8bd3:: with SMTP id n202mr4580947iod.57.1618601102101; Fri, 16 Apr 2021 12:25:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618601102; cv=none; d=google.com; s=arc-20160816; b=N+lAPp7qZ0kC3vpWdF4VD/J1WvkjnKMzTFXcIXAanrAEhywe6ob47+70wph13KmyL+ kpYgUnu96wJpmZ0igERq4jMo1z5kAp0pQSIQ0SJt4O1bHqwWS32uaQ4rwPCTuIBguC4V c45GRgdMhrYCKuln3/qEgZ+nHF+eNZ1JY7xIlfs7KchzRP+qFoH4e3ijwWfxEa6Vb/uh 1BAdgxl2oycFR7o7OGHfembAzhwbZ8iBPrrrX26VJWmmTaLoJ2SMjsmSKw3qZjpLoqMz W8gOgF8dkEBASGlrgxELocuBeWGfPP/YHgDbtQOgayb3p1RfXiKeSdkGwtTvU4FUGuaU snuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aHJm4yhflwYT0zFdnhDkesD7hVJG4+2l6Mj+AHEyIq8=; b=P5O3v+d2VJWM2dGa8AqKR2m2DUdv6U63jmiFwsUckQhtpZNiUcPW93WpnkzkHEfvbh cESUE/vrpy1i1JLUTTMtdpBmkQu7+HYcoCByimfu3C5NwAQeuumAJ0fkGXmdGOvAbN0/ As509fkTIN4q5V+RcbERlrcHhaP0TVnFTuUXcg7sJzaQdUXFPDbE+iUDZP0WbRoQhz5P UbRIlqei8iKeOCL7g1IUypX2/VnILdGQXkGzETDSzrjpIaXCP2AqxdA/46EtGhczv2Gs +X3OV/4cvNaOOqok1HPVq2bxzR3ENoTJw1dbub9I6qRIuz1JWDmJIipP8B6XYOyKYjCG JhYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nHrXZFf1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r1si3308530ilj.50.2021.04.16.12.25.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:25:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nHrXZFf1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56778 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXU5N-0003zH-Jy for patch@linaro.org; Fri, 16 Apr 2021 15:25:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50758) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXTiF-00047v-OG for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:01:07 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:39750) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThc-0004Tk-Th for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:01:07 -0400 Received: by mail-pj1-x102d.google.com with SMTP id ot17-20020a17090b3b51b0290109c9ac3c34so16896732pjb.4 for ; Fri, 16 Apr 2021 12:00:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aHJm4yhflwYT0zFdnhDkesD7hVJG4+2l6Mj+AHEyIq8=; b=nHrXZFf1gghtBb9qtMWpo63WL8owrcPR5+vouErtFy9wQMzWy77IrXrwuWlT3YnErg 95VOFeQBa0wVZT+b4SiUxp9+x3seqP1jOcLggxHSCDpYUGjuc0oc94qDvZmVKsYvXBXi qyDKfQ2+mpTi2vyb/b9dvJExQaH3LOjHDtunlnn4dbdaR6L90GQ9eEkoJ2H55NbTWmpb CvguinCNcSlFwdZweuU76WLU0UfF60D+KZ0csHtBIA5Lc+x3zJUKXDGQhfSAWDMQgY/6 vMcCujie7cK9OjynbhVIssT+1N8uB7v8r7PBORANy+8EwVR/PzfMMoG/AHq5J0us/Kvr ahiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aHJm4yhflwYT0zFdnhDkesD7hVJG4+2l6Mj+AHEyIq8=; b=IOv78nLYzmLqkDkaUzS31Ry9zm6wSgEfO+ZDyOsIZRdw9KuRhhMvH8dZtfKC1Riaqs 9t+r1pvtXBG0Ly/lngT5f6n9dcyC0bC0mIMwSun6OJc4/lVl4oE9qhp7d0yowBLlviE/ tQgHv2dmGvWYHekpH4TXeFpxBNS3u7BMcn4Olb/pvCc2EawfrrbH6VWpvQyc82uDDWnm pQsDuqQhS7paaisogMUfKmI7djHLhrt6Qsczr/4MnOqOkI9C2vWPykTw/xo9XrsnaEQI WaywHPLohVXmAhLW8Tav9pY5WX0Wb8Tc7SMRbgxWSzrbSmC4vqZDDJ1HNylW/OkXaLwH y58w== X-Gm-Message-State: AOAM530iholGkewew5WdEmwUqGAZfEhx6fkV6/0kO52gXMUa6lA3IEmq DtqQHj5md9m8mO4njBz4ZP/5axorFOJtPQ== X-Received: by 2002:a17:90a:4381:: with SMTP id r1mr11700641pjg.214.1618599627423; Fri, 16 Apr 2021 12:00:27 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 27/30] target/arm: Use MemOp for size + endian in aa64 vector ld/st Date: Fri, 16 Apr 2021 11:59:56 -0700 Message-Id: <20210416185959.1520974-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ac60dcf760..d3bda16ecd 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1146,24 +1146,24 @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, /* Store from vector register to memory */ static void do_vec_st(DisasContext *s, int srcidx, int element, - TCGv_i64 tcg_addr, int size, MemOp endian) + TCGv_i64 tcg_addr, MemOp mop) { TCGv_i64 tcg_tmp = tcg_temp_new_i64(); - read_vec_element(s, tcg_tmp, srcidx, element, size); - tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); + read_vec_element(s, tcg_tmp, srcidx, element, mop & MO_SIZE); + tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), mop); tcg_temp_free_i64(tcg_tmp); } /* Load from memory to vector register */ static void do_vec_ld(DisasContext *s, int destidx, int element, - TCGv_i64 tcg_addr, int size, MemOp endian) + TCGv_i64 tcg_addr, MemOp mop) { TCGv_i64 tcg_tmp = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); - write_vec_element(s, tcg_tmp, destidx, element, size); + tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), mop); + write_vec_element(s, tcg_tmp, destidx, element, mop & MO_SIZE); tcg_temp_free_i64(tcg_tmp); } @@ -3734,9 +3734,9 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) for (xs = 0; xs < selem; xs++) { int tt = (rt + r + xs) % 32; if (is_store) { - do_vec_st(s, tt, e, clean_addr, size, endian); + do_vec_st(s, tt, e, clean_addr, size | endian); } else { - do_vec_ld(s, tt, e, clean_addr, size, endian); + do_vec_ld(s, tt, e, clean_addr, size | endian); } tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); } @@ -3885,9 +3885,9 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } else { /* Load/store one element per register */ if (is_load) { - do_vec_ld(s, rt, index, clean_addr, scale, s->be_data); + do_vec_ld(s, rt, index, clean_addr, scale | s->be_data); } else { - do_vec_st(s, rt, index, clean_addr, scale, s->be_data); + do_vec_st(s, rt, index, clean_addr, scale | s->be_data); } } tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); From patchwork Fri Apr 16 18:59:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422576 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp656404jaf; Fri, 16 Apr 2021 12:15:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJygo/XVgdeQfTixnXpoO65T7xtlKq+ujj5WWUgwHH7UcoqlY788tQXeKQL0LSBJsDN860u6 X-Received: by 2002:a05:6e02:118b:: with SMTP id y11mr8249218ili.163.1618600548438; Fri, 16 Apr 2021 12:15:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600548; cv=none; d=google.com; s=arc-20160816; b=QsOfoWnHUXtJBbfkfKCcDTxYw/uAni7KmVXZIdVyi1RGWp0NkZjNKBp5ToW49FLtWg E/BpE4u/neANMBmPraL81YB9Oj5btBZYctXpmTq/Uyyw9o1jwh8dF7bkfQ8lclzV3w/v Fk9A//gFcgbKHzCKCT9weG/6YtoLlapbhdw2CloCfkBkpdr3sBY1MzRGyU6skTlrPDc6 v+8k1wRO34Oprnrfttx3M8fpgPqWKPgiAbGvC+5GoSSagjdv4gc9s/WGYHpANJKEn3xG TmD0hsBuxQr7SkBAKe6KBPYh/HZ4mxbQTD23s8J+g9Ftw6OBedNzgGcY5WfeJnVgl2Pd Xgiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oROkq8j4qfMtXcJP6tdXRKN1rqEpL50c3TD7tut7lv8=; b=w0yFizNclFuKLjOXfxNa1rkDjmO+jW9kEBLZGE4HE5sWAOXdTpTGpDTXlb50LkwjlJ JIGtsRgt1pzR/0ppq44iIC+XgOIAsJq2spwsFuEZBrbOD26PJh8mx6y4Ux7wzzIp0tSJ 1ql8wU6BTjRcuOh9ospuS1yCrrsdlvZKyfIjJX/BerU2fL1Cd2WvNftDy1RVHykpFI2F eAO4qDjwFJJn+xDCl2z08FguWveHVZxvLp72JvP1b+C6IAxfpOoMwSgSaZr5Qievk7iI lHs8YPUIr5hYlHj5hCxsJnqwHe36ofWu9OV5SBvUAksp5zJaIUaLcAqkeSGO8p9AGJiN E/Gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Pp5wJJdb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u4si6610923jad.126.2021.04.16.12.15.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:15:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Pp5wJJdb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTwR-0006hY-Tx for patch@linaro.org; Fri, 16 Apr 2021 15:15:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXTi8-00044O-J2 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:01:01 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:37886) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThd-0004U2-Qb for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:01:00 -0400 Received: by mail-pl1-x62c.google.com with SMTP id h20so14482894plr.4 for ; Fri, 16 Apr 2021 12:00:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oROkq8j4qfMtXcJP6tdXRKN1rqEpL50c3TD7tut7lv8=; b=Pp5wJJdbpbNTuPzihsrXk7K5ywC9Lg5xHWPIeXFcBGdpjJITw6xMFnc9JwDIpISafI eMxHdZCxKMKD2nTj4XDHtjF5bL8H+AnDIryf73T7oqvcCykFP9F++2fyIy3kMURaz3TK LRo8XOLtuMunRNuq9/I/Xl31HQnm0ql7gCaj4O+JiI1HPd04JK9PEQpskI8den5xLLI5 dghhQgyGTjn3IpnW3cJU0Z7vHhr5uuAI9L+uSzT/qsZfeLSTacZyrAOHgOLCxiupYSC5 UFw/xYxxlb3h32Hw8eokLL5XWtN/qSSd3+U+yQ8thnUHjdjJVtfZebD/I9VxzzeiXXiV ao4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oROkq8j4qfMtXcJP6tdXRKN1rqEpL50c3TD7tut7lv8=; b=R4VQa5J8m36ytOlcUTFsWh8ZLEkdnXlZ0EN+vvmhaO5lps6SqHBK760mXIYSx1IUJz /CM0nUKgwIaOwBIRhqSjQVyJTk7jQiSeS3rsG2fupPA1GEdk771BX0mvlwCTQDjJs/uM OTh3mWW+RQMtTco/mVAlYVew4vhImUIokeT2BuqC0nRMIDSyQwEvXv4s/7vFh331kb8z LYFP3txgWVeSv9juzbThL2V6w6/58N1z7N2HBDNA/I8pmYz5CFt6zteFSlDPXqqAYanW yJT2aTBYNWs2FQFwDEs/u7YJCJOMZCSvmX/n/krE+3AKtRvvPzZvvWfMq8QNZaunqxgQ f3gg== X-Gm-Message-State: AOAM532hdWnFYAQ4wvreIUQdUdrrPBhjdMzqOvb6SosrENuHmOOmncRp qWoWh65tLxSTOETpxA46oSLrUryxUfzVUQ== X-Received: by 2002:a17:90b:14c4:: with SMTP id jz4mr10456007pjb.144.1618599628524; Fri, 16 Apr 2021 12:00:28 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Date: Fri, 16 Apr 2021 11:59:57 -0700 Message-Id: <20210416185959.1520974-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d3bda16ecd..2a82dbbd6d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3635,7 +3635,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) bool is_postidx = extract32(insn, 23, 1); bool is_q = extract32(insn, 30, 1); TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; - MemOp endian = s->be_data; + MemOp endian, align, mop; int total; /* total bytes */ int elements; /* elements per vector */ @@ -3703,6 +3703,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) } /* For our purposes, bytes are always little-endian. */ + endian = s->be_data; if (size == 0) { endian = MO_LE; } @@ -3721,11 +3722,17 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) * Consecutive little-endian elements from a single register * can be promoted to a larger little-endian operation. */ + align = MO_ALIGN; if (selem == 1 && endian == MO_LE) { + align = pow2_align(size); size = 3; } - elements = (is_q ? 16 : 8) >> size; + if (!s->align_mem) { + align = 0; + } + mop = endian | size | align; + elements = (is_q ? 16 : 8) >> size; tcg_ebytes = tcg_const_i64(1 << size); for (r = 0; r < rpt; r++) { int e; @@ -3734,9 +3741,9 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) for (xs = 0; xs < selem; xs++) { int tt = (rt + r + xs) % 32; if (is_store) { - do_vec_st(s, tt, e, clean_addr, size | endian); + do_vec_st(s, tt, e, clean_addr, mop); } else { - do_vec_ld(s, tt, e, clean_addr, size | endian); + do_vec_ld(s, tt, e, clean_addr, mop); } tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); } From patchwork Fri Apr 16 18:59:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422586 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp659943jaf; Fri, 16 Apr 2021 12:21:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwDb4NirkM9bqMLlibJwKRuqKsQUNe+B5varY3bcyqujnfFfND9ZGRJGpuUmMivrDW0W6ur X-Received: by 2002:a6b:e814:: with SMTP id f20mr4771590ioh.206.1618600898502; Fri, 16 Apr 2021 12:21:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600898; cv=none; d=google.com; s=arc-20160816; b=TBcApObSoOp+mzDdBW3eDsenyIM0vvuEw6BTRigBtdCsciYtluHSBB9tEwGeB0kMyo MURu/ngbrxX5E1wlAPio44VB59lULztm/USmjAy7CJ85YOQnmBH1LcJw67W3Qe4fsblu OLKmOPaeT/4YhZ/oAVa/fahICBXPzD/K+86383xT3BDSIqxY/FPJFIlTaMumK2yTI7pE H1lAvSPx2wEker7PiYUVMp0+oWQ+owc5scERMXOldQ2xgzZH+svK4ghhMwyQI5QgOBkD P7VnKHBsvqCYbKFXuEb397P9JRBLQJ1ugpGdqWUKwpTyZwJIan32kqZh5ptKALRHxjIP BKTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zsvdYXq6ehB6Yi/U879OLLmvPBBL5YJ5lhH9C+FI0w0=; b=dLOvFL1ETGtfoP4uqmiAAyz9Z0NyW2PSh9wNM0qmMZN49MCrEFRpzFew/vO0E0RnHi +sxFv+4G+mZ/38b3AF4KqDkDRsNICc6aXASLZDvvWIugPwYs0zYxsg68ol/XDn0UAy3m yWVigkDEAHySb6FtjHeBTQPGrUbZicQMi/G/7kj/jctAsqZzLcLCSx+u0jObPCm6Nke9 VgeHRiltnNPkVpyhXPeKj/vw9N/pZftxQ7TjOklSutj+WJhkj4FEAKIWuIO618WXWcT3 5FM9870bPlv02ixb0p3b1D8U+wCoWM4ycdDOiqGa+OihorokeWf0mEo/u7S0LArhzROx VN8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="HCKE/RTu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v9si7890583ilu.68.2021.04.16.12.21.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:21:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="HCKE/RTu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXU25-00078W-Hg for patch@linaro.org; Fri, 16 Apr 2021 15:21:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXTiD-00046x-K6 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:01:05 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:37501) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThf-0004VK-21 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:01:05 -0400 Received: by mail-pg1-x532.google.com with SMTP id p2so4355076pgh.4 for ; Fri, 16 Apr 2021 12:00:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zsvdYXq6ehB6Yi/U879OLLmvPBBL5YJ5lhH9C+FI0w0=; b=HCKE/RTuzwdMoopodiWGlcV8Lg6/4kqC1kjNOZUBCv8qF8BO9rrGeSx4+F12t2epvN UiogMdj92B8uWMzXd9fOhPtnGLHZ4LWjrU2FL2D/C2LZGGmwhSlVn6gFNsdV85CydOfc 5LQMmRCrT3g5+REKRVrn5xi2B1bKRMTcoT047+6uGrZAHlP/fcyVT30Qjlj0Cvj6Bssa Zrk76TWWNUXZRZdySZkaGs8KnMJXqlbD4TKq1I/ICdiwQCrAo+ZbZj+QESsHuMBbqOZh sCHQRt3gSaAs5SsJ6sSaUOx096/abAfOA60ON2fVqbb59QSe3x4T9iX6H7zRhpHsR21p yzIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zsvdYXq6ehB6Yi/U879OLLmvPBBL5YJ5lhH9C+FI0w0=; b=SkWuF3GrBXx4HUWv4CmdWGyrpBpy1x+hUVJDK4dpijkdWdoL1R/NsCrhKB9NGWITCK 7NKejx74Q8CKzkszObwrB4atb8f7dClylMOO0Cc6goNprw5sAjkjIrbBMPS2J8JyCU// VhEdI/Eb6Kp/d5iyvoMU+A8yLP1Kh2d3pztQKWTMswYfIJG6RXBaH8gMB830EZ+Oi0wF fiT1SVYb5lPvXU4skW0SCVJEl7X2X5A+FACZvWQw2pFfa/HwEhidkaCYP47tP+VpRgTP 9iuQC44D6GIgkHNiT2tHi9cohzZ2qRhH+bS/+X+sGbMNfWWz/bWr06ECpyzyhjv7zAqQ 9hGA== X-Gm-Message-State: AOAM532BBTjcMVhYXTmlIuotpJj1TQyn9E51VbgRsW7ZysB/d9UcjYWv M+O3n4mT/OCDFtjCZAedXhRf1fvD/w1R+A== X-Received: by 2002:a63:5004:: with SMTP id e4mr466189pgb.61.1618599629297; Fri, 16 Apr 2021 12:00:29 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Date: Fri, 16 Apr 2021 11:59:58 -0700 Message-Id: <20210416185959.1520974-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2a82dbbd6d..95897e63af 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3815,6 +3815,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) int index = is_q << 3 | S << 2 | size; int xs, total; TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; + MemOp mop; if (extract32(insn, 31, 1)) { unallocated_encoding(s); @@ -3876,6 +3877,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31, total); + mop = finalize_memop(s, scale); tcg_ebytes = tcg_const_i64(1 << scale); for (xs = 0; xs < selem; xs++) { @@ -3883,8 +3885,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) /* Load and replicate to all elements */ TCGv_i64 tcg_tmp = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, - get_mem_index(s), s->be_data + scale); + tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop); tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), (is_q + 1) * 8, vec_full_reg_size(s), tcg_tmp); @@ -3892,9 +3893,9 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } else { /* Load/store one element per register */ if (is_load) { - do_vec_ld(s, rt, index, clean_addr, scale | s->be_data); + do_vec_ld(s, rt, index, clean_addr, mop); } else { - do_vec_st(s, rt, index, clean_addr, scale | s->be_data); + do_vec_st(s, rt, index, clean_addr, mop); } } tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); From patchwork Fri Apr 16 18:59:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422582 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp658152jaf; Fri, 16 Apr 2021 12:18:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxY7fmKQ/KNAFFX7LDzD252572FRhneNMT5YuPJM3kjONOVAjIeONFrLdwJj3vgC+5YwA6Z X-Received: by 2002:a92:c649:: with SMTP id 9mr8015769ill.303.1618600723480; Fri, 16 Apr 2021 12:18:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600723; cv=none; d=google.com; s=arc-20160816; b=HXoqNM+W6jJR94J4UTeF6HfwPCh+EaukhaJpJLaVTrPNnWmPVZiPjw36l27wGqSl+w HvhQcdbay8t9subNyMU28gwIadTcYmun0dFVLfo5n/duJIulaNwgFYfzo961LNqgW8KD +cZLRwDtN6gx3OgfxMnJ5Daa1+85K/ArxHeDi1vhshu9uMYH00RlsNlB0vW2n4Ir0YcI 4ERMKBLUTDz2b4w443j477gQDHX4CNei6wICIOR05ax4/bZUq24Jb3JERb+5wYwexvvA aqBJFmd/cmLqdBy2/+c8F6sGFO9OVYQXd7qgxbsVJFOxM2qBrmMvIr02ZPnQkmjRd+s1 /J1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Sur9/JZybq5xVkGAS9I0yc1/ThRv4l764lANHeDVf88=; b=WVeX/7qL75OYJL/QVdtpHtZLwwZEXN6wjXDRJXMnGuKY4JNOIpfYA3jcQ8kqYR0tQh sxo1tN8v8ofODxwMXYDdstoBce78jJ65wda80dTXqfkv6a/RUjFtxTbMPF7F85sktj5E Ae5oo0p9mKjru3jzGVHJVGyXpjJbHqPAFR3OP7sl84dO4WXCG88rEu0Arni8nko17NXf uoFtc8FzZKzy2xCFDHsNen28NdJ+syRbVGUm/MN42BFQ7G5wFym71KDZXAfSaboFawxM uSXkR3FrjEZKAExK/xakgbC1tRbV/zd11exdw+B+gHQAf/wj+3i3BKfqrPMqbN2WFlS1 Dclg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=on1k2vf5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e9si6709151ilu.109.2021.04.16.12.18.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:18:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=on1k2vf5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59648 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTzG-00021M-Vg for patch@linaro.org; Fri, 16 Apr 2021 15:18:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXTiD-00046c-Ec for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:01:05 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:34330) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThf-0004W5-Mc for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:01:04 -0400 Received: by mail-pl1-x629.google.com with SMTP id t22so14153224ply.1 for ; Fri, 16 Apr 2021 12:00:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Sur9/JZybq5xVkGAS9I0yc1/ThRv4l764lANHeDVf88=; b=on1k2vf5G4Nx0xIg2DtfIG3D/oabpkqS+D0rI2KXDgx4ppDZNlgW8cDBjiQfP0InmB Th4tPlGBmBPZ/5Q/9P8Zv146QycNLlmlFzPGbK3tJ9Y/dUW6VVMTLHLbEyxVpwQbZLkP YwbCBTX1OcvVUhIjqdNjn0C1xXKVnWQ3rlYQkDhGm3WCELDVnBh3KrL+KxejzuyLV0go Fo2vf/8oTbWDWZA2a9jtGS0As9IVtn8HcdI9PRJ3QoIAeTr8vKQrbvY6P1efdVA+3tKQ OQAXiJWqIFt7G7xq/5clfJ2ocZ+3OwBK1EdFijfe6YSbEJIs+siwoiuiZr+WiXmEb/4F rEYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Sur9/JZybq5xVkGAS9I0yc1/ThRv4l764lANHeDVf88=; b=RwnChH5NTA6REt3D0lLwdaO36v07DC6PtGKhDgE5RsTh9FywgqGp2lc8EOT6V+Fd2U HXcdR7cSZ6DtouySr7sS7Yr59WbZLcvLnbpqUvLfEWKk1JOFQxgT3ErWGhRDxGR5KWYi mHBaVsWMdcdI5OxOwA/Zhw2W4HzXMhZJULZiDUZOq0w7vx/wbz7AQqhPqkkT92Yzl1a3 V6hT3GHs75Ccw0Of6o+NfFW3NH0RZ2jbEX4qnBuEpgtJV/O1ddBjm4FsKA0f9twbFF/3 cR5a9eWw0RSB4Z4Dsp3joTNgLuXX4pIHcCU4FUxo8pD99hyPWdI9gvwsDJa1vpgj/NOQ UagQ== X-Gm-Message-State: AOAM532gvSWqbLgsb3lWEIUV/OEA44K8GLm9cu2s0YFIelxHQqllcExt 1D5tpw5fbMoE61aSU+ff/6ABun4FayrWiA== X-Received: by 2002:a17:90a:a389:: with SMTP id x9mr10964450pjp.232.1618599630294; Fri, 16 Apr 2021 12:00:30 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 30/30] target/arm: Enforce alignment for sve LD1R Date: Fri, 16 Apr 2021 11:59:59 -0700 Message-Id: <20210416185959.1520974-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 584c4d047c..864ed669c4 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5001,7 +5001,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) clean_addr = gen_mte_check1(s, temp, false, true, msz); tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), - s->be_data | dtype_mop[a->dtype]); + finalize_memop(s, dtype_mop[a->dtype])); /* Broadcast to *all* elements. */ tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd),