From patchwork Wed Apr 14 15:53:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 421935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93234C433B4 for ; Wed, 14 Apr 2021 15:54:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 70E97611C9 for ; Wed, 14 Apr 2021 15:54:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234046AbhDNPyW (ORCPT ); Wed, 14 Apr 2021 11:54:22 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:63831 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352551AbhDNPyN (ORCPT ); Wed, 14 Apr 2021 11:54:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1618415633; x=1649951633; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=U0hIUeY4b5TuO5xsSS+g8pI9TVKt+grIjGH3oSWbGcQ=; b=oDymzJ9NwhJ6SH9Dg0Or182G8h0JGJ2Qb7P7riozBjwYEl5v3ffzGWhD aIaOQCHRcpdbduImd3ndofB8k4NYbZNBJP7n9QLshFJrm/BZhHqMdcpme nYOoDYdiJxOCG36hKyklJmQxkWagEyY7awH6axXImQX9J8856Y9JhpHYC S4FmIBZ0fy1+v3/41DGzaxo/Z+pHBZm8rFEcUQ9hml7YQtnGJClVvyXOd T4KsG+v3spQ+o10g2TgTjcMIKFiq0dysbrgSW4RhSeVI0z54AaGriJKLV WdJ0xTAAhw6I8Temdk/Y1rEZPrwvLqi+qLImyolZNviwUEIBvWWZJnqia A==; IronPort-SDR: QB54bq9iVlIBqTnCW4bHD6DiaiygwYM3GHWEQpjf/E8l/7V8AMoTb69iW4sjm+PT+LvRNrHReX L28ayEtI54zZF1SGMN2p73TQ1/FFAYCOTtWzEL5KTExUxjCB0b7vu8pZDHc+LoPNisrEZK1fc3 ju497GHP55ut1UDzVyahf53yKc8UdMWDnhNRzVlaBYV7X0etrgJNXIcvUxYsP4AcLqznuFESdE p3LPLxFxHG+EsvIPftgW86Ms8MpOxYsTLPQxCr9LGnb6juN9NM1KAFPVNFRc5cmFYEoNsMugtu fzs= X-IronPort-AV: E=Sophos;i="5.82,222,1613458800"; d="scan'208";a="113573280" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Apr 2021 08:53:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Wed, 14 Apr 2021 08:53:51 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Wed, 14 Apr 2021 08:53:48 -0700 From: To: , , , , , , , , CC: , , , , , , Conor Dooley Subject: [PATCH v6 4/5] soc: add polarfire soc system controller Date: Wed, 14 Apr 2021 16:53:48 +0100 Message-ID: <20210414155348.29695-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley This driver provides an interface for other drivers to access the functions of the system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/microchip/Kconfig | 10 ++ drivers/soc/microchip/Makefile | 1 + drivers/soc/microchip/mpfs-sys-controller.c | 119 ++++++++++++++++++++ 5 files changed, 132 insertions(+) create mode 100644 drivers/soc/microchip/Kconfig create mode 100644 drivers/soc/microchip/Makefile create mode 100644 drivers/soc/microchip/mpfs-sys-controller.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index e8a30c4c5aec..b33142e020e0 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -12,6 +12,7 @@ source "drivers/soc/imx/Kconfig" source "drivers/soc/ixp4xx/Kconfig" source "drivers/soc/litex/Kconfig" source "drivers/soc/mediatek/Kconfig" +source "drivers/soc/microchip/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index f678e4d9e585..10cfdcd972c7 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/ obj-y += mediatek/ +obj-y += microchip/ obj-y += amlogic/ obj-y += qcom/ obj-y += renesas/ diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig new file mode 100644 index 000000000000..eb656b33156b --- /dev/null +++ b/drivers/soc/microchip/Kconfig @@ -0,0 +1,10 @@ +config POLARFIRE_SOC_SYS_CTRL + tristate "POLARFIRE_SOC_SYS_CTRL" + depends on POLARFIRE_SOC_MAILBOX + help + This driver adds support for the PolarFire SoC (MPFS) system controller. + + To compile this driver as a module, choose M here. the + module will be called mpfs_system_controller. + + If unsure, say N. diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile new file mode 100644 index 000000000000..14489919fe4b --- /dev/null +++ b/drivers/soc/microchip/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) += mpfs-sys-controller.o diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c new file mode 100644 index 000000000000..3cfee997fa59 --- /dev/null +++ b/drivers/soc/microchip/mpfs-sys-controller.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip PolarFire SoC (MPFS) system controller driver + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_MUTEX(transaction_lock); + +struct mpfs_sys_controller { + struct mbox_client client; + struct mbox_chan *chan; + struct completion c; + u32 enabled; +}; + +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg) +{ + int ret; + + mutex_lock_interruptible(&transaction_lock); + + reinit_completion(&mpfs_client->c); + + ret = mbox_send_message(mpfs_client->chan, msg); + if (ret >= 0) { + if (wait_for_completion_timeout(&mpfs_client->c, HZ)) { + ret = 0; + } else { + ret = -ETIMEDOUT; + dev_warn(mpfs_client->client.dev, "MPFS sys controller transaction timeout\n"); + } + } else { + dev_err(mpfs_client->client.dev, + "mpfs sys controller transaction returned %d\n", ret); + } + + mutex_unlock(&transaction_lock); + + return ret; +} +EXPORT_SYMBOL(mpfs_blocking_transaction); + +static void rx_callback(struct mbox_client *client, void *msg) +{ + struct mpfs_sys_controller *mpfs_client = + container_of(client, struct mpfs_sys_controller, client); + + complete(&mpfs_client->c); +} + +static int mpfs_sys_controller_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mpfs_sys_controller *mpfs_client; + + mpfs_client = devm_kzalloc(dev, sizeof(*mpfs_client), GFP_KERNEL); + if (!mpfs_client) + return -ENOMEM; + + mpfs_client->client.dev = dev; + mpfs_client->client.rx_callback = rx_callback; + mpfs_client->client.tx_block = 1U; + + mpfs_client->chan = mbox_request_channel(&mpfs_client->client, 0); + if (IS_ERR(mpfs_client->chan)) + return dev_err_probe(dev, PTR_ERR(mpfs_client->chan), + "Failed to get mbox channel\n"); + + init_completion(&mpfs_client->c); + + platform_set_drvdata(pdev, mpfs_client); + + dev_info(&pdev->dev, "Registered MPFS system controller driver\n"); + + return 0; +} + +struct mpfs_sys_controller * +mpfs_sys_controller_get(struct device_node *mss_node) +{ + struct platform_device *pdev = of_find_device_by_node(mss_node); + + if (!pdev) + return NULL; + + return platform_get_drvdata(pdev); +} +EXPORT_SYMBOL(mpfs_sys_controller_get); + +static const struct of_device_id mpfs_sys_controller_of_match[] = { + {.compatible = "microchip,polarfire-soc-sys-controller", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_sys_controller_of_match); + +static struct platform_driver mpfs_sys_controller_driver = { + .driver = { + .name = "mpfs-sys-controller", + .of_match_table = mpfs_sys_controller_of_match, + }, + .probe = mpfs_sys_controller_probe, +}; +module_platform_driver(mpfs_sys_controller_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("MPFS system controller driver");