From patchwork Tue Apr 13 07:16:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Petrosyan X-Patchwork-Id: 420613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18177C433B4 for ; Tue, 13 Apr 2021 07:16:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E9649613B6 for ; Tue, 13 Apr 2021 07:16:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237911AbhDMHQ5 (ORCPT ); Tue, 13 Apr 2021 03:16:57 -0400 Received: from smtprelay-out1.synopsys.com ([149.117.87.133]:59700 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237810AbhDMHQy (ORCPT ); Tue, 13 Apr 2021 03:16:54 -0400 Received: from mailhost.synopsys.com (mdc-mailhost2.synopsys.com [10.225.0.210]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 8DE52C00F4; Tue, 13 Apr 2021 07:16:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1618298195; bh=nj1BeKTbsJpmOWsKzyw4Q4Ak3JprmbRdIDgrwfON3Og=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=AQc4n6WTE0XgPFcAK3CyJW0lI1tkkEFiWAoJj4tdW5xTIvMp4EPZ3FlKAE4iOrw4U fo1ISl6pCHWj6GuC24dMriXWgLl87QR3NaStL3V4EgbFeiukB7Zxanxp4UX8iJYrAR MziL9opYZWXdPNaYokkE891RsmIT10JPoQAAYuoJua0wHZ5Ms4z+SmDJn1mSVvVf0L DXRDvamukJplXZURGFjMFKOYmZFDeig1AC0Q+KZJBganYwsRE7VsBf4Jn1JLw30nMw XTKleAf9GY49JQeRGW95Kwax04l07YCiaXkzCGNp0e7aiMaRg/caMg2BJyj2IxrDAl OryDdj9NY/nQQ== Received: from razpc-HP (razpc-hp.internal.synopsys.com [10.116.126.207]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailhost.synopsys.com (Postfix) with ESMTPSA id 9F77EA0094; Tue, 13 Apr 2021 07:16:32 +0000 (UTC) Received: by razpc-HP (sSMTP sendmail emulation); Tue, 13 Apr 2021 11:16:31 +0400 Date: Tue, 13 Apr 2021 11:16:31 +0400 Message-Id: <58dc1c1805b583fa87f9615e9d17e9ff88644718.1618297800.git.Arthur.Petrosyan@synopsys.com> In-Reply-To: References: X-SNPS-Relay: synopsys.com From: Artur Petrosyan Subject: [PATCH 03/12] usb: dwc2: Allow entering clock gating from USB_SUSPEND interrupt To: Felipe Balbi , Greg Kroah-Hartman , Minas Harutyunyan , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Cc: John Youn , Artur Petrosyan , Minas Harutyunyan Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org If core doesn't support hibernation or partial power down power saving options, power can still be saved using clock gating on all the clocks. - Added entering clock gating state from USB_SUSPEND interrupt. Signed-off-by: Artur Petrosyan Acked-by: Minas Harutyunyan --- drivers/usb/dwc2/core_intr.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c index 8c0152b514be..ab7fe303c0f9 100644 --- a/drivers/usb/dwc2/core_intr.c +++ b/drivers/usb/dwc2/core_intr.c @@ -529,14 +529,18 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) /* Ask phy to be suspended */ if (!IS_ERR_OR_NULL(hsotg->uphy)) usb_phy_set_suspend(hsotg->uphy, true); - } - - if (hsotg->hw_params.hibernation) { + } else if (hsotg->hw_params.hibernation) { ret = dwc2_enter_hibernation(hsotg, 0); if (ret && ret != -ENOTSUPP) dev_err(hsotg->dev, "%s: enter hibernation failed\n", __func__); + } else { + /* + * If not hibernation nor partial power down are supported, + * clock gating is used to save power. + */ + dwc2_gadget_enter_clock_gating(hsotg); } skip_power_saving: /*