From patchwork Tue Jun 5 06:01:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 137668 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp545341lji; Mon, 4 Jun 2018 23:02:31 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKieE+/qB45nnrjhhMfigAQ6WgtpsUYW4tlzm+dq2JHTqvUb/z3ptRQFiHoAAFokYol/HxJ X-Received: by 2002:a17:902:2805:: with SMTP id e5-v6mr25211825plb.55.1528178551135; Mon, 04 Jun 2018 23:02:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528178551; cv=none; d=google.com; s=arc-20160816; b=dEULpCH0F+crs+g+ZoOxST97gb3U8rVEulmk2zeyBa+BYRCKyRHg6aUMfNFCR9x9QJ AxdLTaY07CCoU9FEye56YS5oenka1Y/bFW4mDHfkW1m9Gg9CZqdRDUyYjCa3XV3dk0Aq 1sb8vRAww7/B5SkocCq2M6/KVUR6wppr6+IYguIGWDuV4UVKfpUMXqeWjz9ztIyiiKI1 C0iGnmD8mXs1BNmC8Is9PJLHnUmy3rhGemgdxIULXuxP0yM7yaS87bMCyv3qv+zq61xy zlAp4cX3UmJt4zUwmuJ3zcb3Iq/jWLfOip/mBX/JkGTJSSF+HsZIzITouPyVCbW1KxWB OuqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=1v9ZeZmD/hSn3eg8pEPrFndhCq8wE7Qcjpl9b4I81c8=; b=HSF/F/wAqqeSLBm5q6UN+KwAwfPVao4M8fu43ziobCONrWfibBZpDyoVq5WMtZVBLn c3UarpEO7Io0p5JVz0LVgGBk+IljiiC8Z5UGz5beQ4uCMaehFHMMmDWPGceZrtQWroZz BKw0CknkmFDni4803ii49v4fwf0iEMinD+LTVvZAcRR5zL2//nLvu3Ubc+Ei2g4mUD9x xse2YGxvTaB9ho5S4nAeFFqmgVO6H6xUt3eZt+vuZ9eUGsDEdQw61Docq81mNonqKT1L Rv7Dse4zkusXAll8lNlNipqYd/b5bBf2uVKI72ppoNTc1yEILtBTzKICdVW9gpHgZxUH 0ysA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OLGZSoe8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h91-v6si47083646pld.132.2018.06.04.23.02.30; Mon, 04 Jun 2018 23:02:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OLGZSoe8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751805AbeFEGC3 (ORCPT + 30 others); Tue, 5 Jun 2018 02:02:29 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:15465 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751729AbeFEGCZ (ORCPT ); Tue, 5 Jun 2018 02:02:25 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w5561k8F004804; Tue, 5 Jun 2018 01:01:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1528178506; bh=1v9ZeZmD/hSn3eg8pEPrFndhCq8wE7Qcjpl9b4I81c8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OLGZSoe8Uw2rXNxqPdUOcA9RjQRJv19Zoc71+oATQQ4SUhkkdOlnEWPo+zY/EL7BZ r3ayxY98HG9uEx9T3ZTtt/+HrWWeHROtfxc3raRDvLoIyZCi/UJoFIY0OqyzY2k8J+ /jUKM1BWz21xfmoqPixITyLpzcZJGcpoXjTRf3SU= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5561kJK022896; Tue, 5 Jun 2018 01:01:46 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 5 Jun 2018 01:01:46 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 5 Jun 2018 01:01:46 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5561kN0007704; Tue, 5 Jun 2018 01:01:46 -0500 From: Nishanth Menon To: Santosh Shilimkar , Will Deacon , Catalin Marinas , Greg Kroah-Hartman , Mark Rutland , Rob Herring CC: , , , , Tony Lindgren , Vignesh R , Tero Kristo , Russell King , Sudeep Holla , Nishanth Menon , Sekhar Nori Subject: [RFC PATCH 3/6] serial: 8250_omap: Add support for AM654 UART controller Date: Tue, 5 Jun 2018 01:01:22 -0500 Message-ID: <20180605060125.9518-4-nm@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180605060125.9518-1-nm@ti.com> References: <20180605060125.9518-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AM654 uses a UART controller that is compatible (partially) with existing 8250 UART, however, has a few differences with respect to DMA support and control paths. Introduce a base definition that allows us to build up the differences in follow on patches. Cc: Sekhar Nori Cc: Vignesh R Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/serial/omap_serial.txt | 1 + drivers/tty/serial/8250/8250_omap.c | 1 + 2 files changed, 2 insertions(+) -- 2.15.1 diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt index 4b0f05adb228..c35d5ece1156 100644 --- a/Documentation/devicetree/bindings/serial/omap_serial.txt +++ b/Documentation/devicetree/bindings/serial/omap_serial.txt @@ -1,6 +1,7 @@ OMAP UART controller Required properties: +- compatible : should be "ti,am654-uart" for AM654 controllers - compatible : should be "ti,omap2-uart" for OMAP2 controllers - compatible : should be "ti,omap3-uart" for OMAP3 controllers - compatible : should be "ti,omap4-uart" for OMAP4 controllers diff --git a/drivers/tty/serial/8250/8250_omap.c b/drivers/tty/serial/8250/8250_omap.c index 1b337fee07ed..a019286f8bb6 100644 --- a/drivers/tty/serial/8250/8250_omap.c +++ b/drivers/tty/serial/8250/8250_omap.c @@ -1115,6 +1115,7 @@ static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE; static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE; static const struct of_device_id omap8250_dt_ids[] = { + { .compatible = "ti,am654-uart" }, { .compatible = "ti,omap2-uart" }, { .compatible = "ti,omap3-uart" }, { .compatible = "ti,omap4-uart", .data = &omap4_habit, }, From patchwork Tue Jun 5 06:01:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 137671 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp546516lji; Mon, 4 Jun 2018 23:03:17 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLSICfpjZTLDrpiTHcNn9V416a4d3I58Np+OJ19Piht8OXmuOoyTTTxd0hDhXJmFlPMmV9D X-Received: by 2002:a65:4487:: with SMTP id l7-v6mr7532145pgq.357.1528178597840; Mon, 04 Jun 2018 23:03:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528178597; cv=none; d=google.com; s=arc-20160816; b=fnS5C1emLhf92S1iDgEO4s2NVmpdzSOd5Wc62po/0R3qBYGZGSGV4vwRgP4QKFXJz3 WHMTL2jAdJUSRZ9AJIUDJHuZ34kuqgdOGQ55sJ2j1p6Q/Vax8c6yH6ewgxqBj6HMoPLq dnmNOh8C88M9bg8mnQSo90F3BzmQpHAPEf6gNpoKfyJcG7csFlmJG/7InnX1CeJ+gSd/ jLqRrmDO3IEDGvVwN/hQT83WVx/ErFm+Z9BnD4acu+rVEbtbEGnvuTV8JbVynP7WImZf yaqLH4TC8KFpRUBqrSgerNh5R1CW1SII9rjB3sctv8c0Qs5osbUb6KiReLgo1rec/O9n ua2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=4LYpy5x8gyFauu6OzvbPae/68Sig2mw1+qtl4E5l4y4=; b=G2IghsRdOaZDkk1QA3D8I9TfAWpoELLAHV3d44yPxPno9VMYzO4YY6rz9qU1CqyFfF jOkg3cQsljBMyoShenueuJnAGSHnHloDC9LytZsZ3x/6IbWVw3u0H2UzPCgMA8BnztIY LgqRwk+9TKYEDQYDXnx851/b6ZMT25CczG7ujJH/AliMxz4lRi0+b7ahT2f2G58x7oDw 7wCcpx2uOFVk30DZz9cxslI+bwScyAufiJzzpkxHfyb3VxktIVzIR72b0mnzNqsSw+Cz p22+xIZemNu4mh6iWLhzZ+ZEZm7uhEWnvChtAiA2YMQ8eckGyWdqeuazKAyMyC1ty2Wb Oh9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=aIsdJySm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Lokesh Vutla Signed-off-by: Nishanth Menon --- drivers/tty/serial/8250/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.15.1 diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index f005eaf8bc57..15c2c5463835 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -375,7 +375,7 @@ config SERIAL_8250_RT288X config SERIAL_8250_OMAP tristate "Support for OMAP internal UART (8250 based driver)" - depends on SERIAL_8250 && ARCH_OMAP2PLUS + depends on SERIAL_8250 && (ARCH_OMAP2PLUS || ARCH_K3) help If you have a machine based on an Texas Instruments OMAP CPU you can enable its onboard serial ports by enabling this option. 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[209.132.180.67]) by mx.google.com with ESMTP id l189-v6si26833713pfc.365.2018.06.04.23.05.53; Mon, 04 Jun 2018 23:05:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rb7vL6lz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751840AbeFEGFv (ORCPT + 30 others); Tue, 5 Jun 2018 02:05:51 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:15643 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751632AbeFEGFi (ORCPT ); Tue, 5 Jun 2018 02:05:38 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w5565BJn005951; Tue, 5 Jun 2018 01:05:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1528178711; bh=4z+5m602+sJbIw79ZOp/J/EqIYeprVHPL8e7vDMkjDo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rb7vL6lznhqWEZJHqWfpfn/YE/RuQgYPY+U4vNRTLtEYZRfq9sP6+PeUQw8bF2Mk0 N29WpTn1crfmJ2rtiGESUj3+cg2UJcNCmtsw2O2AU6Z9FbhS1SXvUIcJKy2SRLCLG+ XPllV5thJ0ExvcmoKkqnu98ZN/+YDyyY4Rgr7BXs= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5565B9R028474; Tue, 5 Jun 2018 01:05:11 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 5 Jun 2018 01:05:10 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 5 Jun 2018 01:05:10 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5565Au6004123; Tue, 5 Jun 2018 01:05:10 -0500 From: Nishanth Menon To: Santosh Shilimkar , Will Deacon , Catalin Marinas , Greg Kroah-Hartman , Mark Rutland , Rob Herring CC: , , , , Tony Lindgren , Vignesh R , Tero Kristo , Russell King , Sudeep Holla , Subject: [RFC PATCH 5/6] arm64: dts: ti: Add Support for AM654 SoC Date: Tue, 5 Jun 2018 01:05:09 -0500 Message-ID: <20180605060510.32473-1-nm@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <=<20180605060125.9518-1-nm@ti.com> References: <=<20180605060125.9518-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The AM654 SoC is a lead device of the K3 Multicore SoC architecture platform, targeted for broad market and industrial control with aim to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Quad ARMv8 A53 cores split over two clusters * GICv3 compliant GIC500 * Configurable L3 Cache and IO-coherent architecture * Dual lock-step capable R5F uC for safety-critical applications * High data throughput capable distributed DMA architecture under NAVSS * Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual PRUs and dual RTUs * Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL * Centralized System Controller for Security, Power, and Resource management. * Dual ADCSS, eQEP/eCAP, eHRPWM, dual CAN-FD * Flash subystem with OSPI and Hyperbus interfaces * Multimedia capability with CAL, DSS7-UL, SGX544, McASP * Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI, GPIO See AM65x Technical Reference Manual (SPRUID7, April 2018) for further details: http://www.ti.com/lit/pdf/spruid7 We introduce the Kconfig symbol for the SoC along with this patch since it is logically relevant point, however the usage is in subsequent patches. NOTE: AM654 is the first of the device variants, hence we introduce a generic am6.dtsi. Signed-off-by: Benjamin Fair Signed-off-by: Nishanth Menon --- MAINTAINERS | 1 + arch/arm64/boot/dts/ti/k3-am6.dtsi | 144 +++++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am654.dtsi | 117 ++++++++++++++++++++++++++++ drivers/soc/ti/Kconfig | 14 ++++ 4 files changed, 276 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am6.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am654.dtsi -- 2.15.1 diff --git a/MAINTAINERS b/MAINTAINERS index cfb35b252ac7..5f5c4eddec7a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2092,6 +2092,7 @@ M: Nishanth Menon L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported F: Documentation/devicetree/bindings/arm/ti/k3.txt +F: arch/arm64/boot/dts/ti/k3-* ARM/TEXAS INSTRUMENT KEYSTONE ARCHITECTURE M: Santosh Shilimkar diff --git a/arch/arm64/boot/dts/ti/k3-am6.dtsi b/arch/arm64/boot/dts/ti/k3-am6.dtsi new file mode 100644 index 000000000000..cdfa12173aac --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC Family + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include +#include +#include + +/ { + model = "Texas Instruments K3 AM654 SoC"; + compatible = "ti,am654"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + }; + + chosen { }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + soc0: soc0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + /* Recommendation from GIC500 TRM Table A.3 */ + interrupts = ; + }; + + gic: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + /* + * NOTE: we are NOT gicv2 backward compat, so no GICC, + * GICH or GICV + */ + reg = <0x0 0x01800000 0x0 0x10000>, /* GICD */ + <0x0 0x01880000 0x0 0x90000>; /* GICR */ + + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = ; + + gic_its: gic-its@1000000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x1820000 0x0 0x10000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + wkup_uart0: serial@42300000 { + compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a"; + reg = <0x0 0x42300000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + status = "disabled"; + }; + + mcu_uart0: serial@40a00000 { + compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a"; + reg = <0x0 0x40a00000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <96000000>; + current-speed = <115200>; + status = "disabled"; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a"; + reg = <0x0 0x02800000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + status = "disabled"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a"; + reg = <0x0 0x02810000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + status = "disabled"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a"; + reg = <0x0 0x02820000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi new file mode 100644 index 000000000000..d9b70081daba --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am654.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC family in Quad core configuration + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include "k3-am6.dtsi" + +/ { + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu = <&cpu2>; + }; + + core1 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@100 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_1>; + }; + + cpu3: cpu@101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_1>; + }; + }; +}; + +&soc0 { + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&msmc_l3>; + }; + + L2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + }; +}; diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 92770d84a288..be4570baad96 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -1,3 +1,17 @@ +# 64-bit ARM SoCs from TI +if ARM64 + +if ARCH_K3 + +config ARCH_K3_AM6_SOC + bool "K3 AM6 SoC" + help + Enable support for TI's AM6 SoC Family support + +endif + +endif + # # TI SOC drivers #