From patchwork Fri Jun 1 16:06:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 137541 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1126487lji; Fri, 1 Jun 2018 09:06:08 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJ2PpH07NaKEqKD2iouwdQ3PfH9Aj3QyLIBYaSKf8tShgM19Z23EeC6dDh6knNFpkZfGjAu X-Received: by 2002:a62:3e9a:: with SMTP id y26-v6mr11409605pfj.98.1527869168535; Fri, 01 Jun 2018 09:06:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527869168; cv=none; d=google.com; s=arc-20160816; b=Z0BkAcaLfATZodgVOu1BNqiaS1PsZSROyIGsXOIUyBTH2NdD1PVYxVgHbBZxcmKyc0 88+7RO5x0wBXVIULlRhl3Jp/KNNqGd2e5wOp/d0NagZQzN+CWCPNkj/UHl5x9+9do274 ACmsSmjPmE5LtUOPBNmRxTfKMpel2GabhPuFVELDx+NNCGfqb51bqFeBwnM1IOQuIc8/ /zx81+zNyAGhHrkop/FiYOTcuj446v1GweSaXKMsu86s1ra27cxX1ZdIjcQdoPRwdEAE C0xMNLh0lke17C032vT2jfLm+u5WvwlYBjzrv1z0IpzGBlClrESr2unRglNqa9sKKkYm 1Z+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=uYayreNaCexijW8oKgvS7R7gvZQf9Kw/3zESbbf2Yx0=; b=B5IH+x/fQzXl4G9AXcGuRmSA9InsDENZFBizLeNSkTBSntaOQeDEFGWk5+Q8WMMhvF bs92cw/NOtnlEj6EGtLkHf5nVCl/u1sLcztNoAmO2PniePgaM9mx8+THamLgApEbtOn+ J5gdImwRUybL+Xgys25QUnnTTadrSYW7b8OqiZ2BNZr/Ib6ZHkcfAzKdJFVL4e67C/29 pthi8x/YZHRzAG8oWzfJF74wRiez7BqEzM08IAFmYTd3OZhgg9XNG53TPagO9me+4TSz WSGtqpNW1YhOFOidb8mSovT99OWmyC+NCSIW4DBv6wrVShhYR/udBGFjpVRaDvfqFAA9 p4Tg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u75-v6si39767607pfd.328.2018.06.01.09.06.08; Fri, 01 Jun 2018 09:06:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753069AbeFAQGG (ORCPT + 30 others); Fri, 1 Jun 2018 12:06:06 -0400 Received: from foss.arm.com ([217.140.101.70]:54960 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751655AbeFAQGA (ORCPT ); Fri, 1 Jun 2018 12:06:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C23B715AB; Fri, 1 Jun 2018 09:05:59 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 945183F59F; Fri, 1 Jun 2018 09:05:59 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 193E41AE0C4E; Fri, 1 Jun 2018 17:06:30 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon , Yoshinori Sato Subject: [PATCH v2 1/9] h8300: Don't include linux/kernel.h in asm/atomic.h Date: Fri, 1 Jun 2018 17:06:21 +0100 Message-Id: <1527869189-31512-2-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527869189-31512-1-git-send-email-will.deacon@arm.com> References: <1527869189-31512-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org linux/kernel.h isn't needed by asm/atomic.h and will result in circular dependencies when the asm-generic atomic bitops are built around the tomic_long_t interface. Remove the broad include and replace it with linux/compiler.h for READ_ONCE etc and asm/irqflags.h for arch_local_irq_save etc. Cc: Yoshinori Sato Signed-off-by: Will Deacon --- arch/h8300/include/asm/atomic.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.1.4 diff --git a/arch/h8300/include/asm/atomic.h b/arch/h8300/include/asm/atomic.h index 941e7554e886..b174dec099bf 100644 --- a/arch/h8300/include/asm/atomic.h +++ b/arch/h8300/include/asm/atomic.h @@ -2,8 +2,10 @@ #ifndef __ARCH_H8300_ATOMIC__ #define __ARCH_H8300_ATOMIC__ +#include #include #include +#include /* * Atomic operations that C can't guarantee us. Useful for @@ -15,8 +17,6 @@ #define atomic_read(v) READ_ONCE((v)->counter) #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i)) -#include - #define ATOMIC_OP_RETURN(op, c_op) \ static inline int atomic_##op##_return(int i, atomic_t *v) \ { \ From patchwork Fri Jun 1 16:06:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 137540 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1126429lji; Fri, 1 Jun 2018 09:06:06 -0700 (PDT) X-Google-Smtp-Source: ADUXVKI6YCIgcCtbP1Bn7PiqC89Hj8Vzy6w0OswkpFKHgkK3CDTdiEArENBnPfdozw3IO8oA5AXc X-Received: by 2002:a17:902:7688:: with SMTP id m8-v6mr8646775pll.54.1527869166075; Fri, 01 Jun 2018 09:06:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527869166; cv=none; d=google.com; s=arc-20160816; b=YvMV695UN9VCykMaJXekBWOX9fBqPQkzusNV5ae3Qqe/smgqLbublG+wK/EXXPlGgQ god86AL40W9R2JQWbnzg51jA8qqF82mpWreaVAzxISEhkzQDIU80omsCNFzb2/RtkS5/ DPGiSaByjACp0SVKc+j4AcUtiJ4MI5V/htCiH02W/+Sax7x41gnjUxM2HHBpu5ui5GKj Eksfl7smLzKZxyfSV5ekpDOgLyyWa29bu3HwtsQCrFvM48rpRNKzrR+L4fNAECMTevfl KKKMYGAhIl7WATb+kIOA9uyBT+yomKyp9on0c0mIXEijgK8otdiJCadh5xXkH4Bg99U4 O/8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=KPoO3xkmTJNlaTbhFQlzQWdV0d+0c5MF04CUiFuVFTI=; b=vrXdsF5Yv3YrDeKrTpV0mHzJQmzBzowr1tJwa7W5dXy2g42IS1mv+ucKVJGOCyLmiG i64ZwfC1z1ZsFeE2RzFZ7FTp+PujyP90FCTKxCD3K7BR1lZvDLnPPt2gnAzbC2V+jT8n 9fd1Sx80Sr5fFLWf6OCkeQ7DuKIYm24hE/mfjo3zFcazWo/z8rDH1y66ZQMAZDxnp7mj BZBPw1o20vYOtq/IFxiuRahk19IBLTezd1oSEpyhjCRqWImLxgs1wXlXUerFAj0+AyPq FGkrfYQZ4mSG/NqWkaCkZivmfqACA/J23WmZeX2+GPdCVbD0OTJP/hsgI0SJI7TH9Ovz wCww== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o10-v6si4551939pgr.175.2018.06.01.09.06.05; Fri, 01 Jun 2018 09:06:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752960AbeFAQGD (ORCPT + 30 others); Fri, 1 Jun 2018 12:06:03 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:54966 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751584AbeFAQGA (ORCPT ); Fri, 1 Jun 2018 12:06:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D7E8A15BE; Fri, 1 Jun 2018 09:05:59 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AA0D83F5C9; Fri, 1 Jun 2018 09:05:59 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 2B7FC1AE5055; Fri, 1 Jun 2018 17:06:30 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH v2 2/9] m68k: Don't use asm-generic/bitops/lock.h Date: Fri, 1 Jun 2018 17:06:22 +0100 Message-Id: <1527869189-31512-3-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527869189-31512-1-git-send-email-will.deacon@arm.com> References: <1527869189-31512-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org asm-generic/bitops/lock.h is shortly going to be built on top of the atomic_long_* API, which introduces a nasty circular dependency for m68k where linux/atomic.h pulls in linux/bitops.h via: linux/atomic.h asm/atomic.h linux/irqflags.h asm/irqflags.h linux/preempt.h asm/preempt.h asm-generic/preempt.h linux/thread_info.h asm/thread_info.h asm/page.h asm-generic/getorder.h linux/log2.h linux/bitops.h Since m68k isn't SMP and doesn't support ACQUIRE/RELEASE barriers, we can just define the lock bitops in terms of the atomic bitops in the asm/bitops.h header. Acked-by: Geert Uytterhoeven Signed-off-by: Will Deacon --- arch/m68k/include/asm/bitops.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index 93b47b1f6fb4..18193419f97d 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -515,12 +515,16 @@ static inline int __fls(int x) #endif +/* Simple test-and-set bit locks */ +#define test_and_set_bit_lock test_and_set_bit +#define clear_bit_unlock clear_bit +#define __clear_bit_unlock clear_bit_unlock + #include #include #include #include #include -#include #endif /* __KERNEL__ */ #endif /* _M68K_BITOPS_H */ From patchwork Fri Jun 1 16:06:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 137548 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1128018lji; Fri, 1 Jun 2018 09:07:30 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKWoaXHH+OxjFxQGTUWkIkSBLzT0TTDfFhkxz2o+8Brqwf+4CykQqIFciLSgR7ts414julg X-Received: by 2002:a17:902:7484:: with SMTP id h4-v6mr11455023pll.154.1527869250081; Fri, 01 Jun 2018 09:07:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527869250; cv=none; d=google.com; s=arc-20160816; b=yzZf7Ue1YpuJOKB2TbHGfosuf0aATC/07sJT5WtYdHtT3VGqjcUUDdt+8X1SqMAOla XKi7ZzyvJtT+W7F02NVhYNxdNOZDZJtTx2TyX5B1Q+Zzf60G/xN+k03/pA5IO8+GnUHM Wopi1qfvBWzZTec/fkqhjLf3OxzO3D6JWvqDqKgrWwsTnbH2r6PmOYdGszheE5YVWj3O MtL93jQHvyj37YycNeTTLDayXlWSmr/mA/EkU0S4WUTztQ4912rD5t7tamR9BiSCvBHi nlscEap195nATicFSNbYsXE+wHSEIprI2CsvProYZVc07+BalA0TiPzCy+XxtcBGjEzM bdNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=dxsWqaY+cyvP9/Wn+QoATPyiIJKTrgv/4wVaFT6fg7E=; b=wLrwD2DZGs4znqpYrDS94+LVaSwpFklj0y/0MPmkRdHf4t1wuFa5vnZbKRkcO3F0cj htrW7nJEs/4sPEuB7EMhK7vMxI2I48L9v4UiQL9AgsTUGd0HD+Z/80exCLMPKN7OftTc 5KSnQm0gyJgYoGynm+3sAG5oAATBEK2LIjCeQVDWdm+m9lIBJr4ZkgTUAXG/50B4uM2W wbg28qrMv34Y4l0kcSf02/v+JEvVM2L+SwxOI3LBHDmErD3OUNhkdFMk1kLIw7/KQ9Ph q3IpRQtftkR7AJDAJ8Kc+s0v9WIvu3KxcY8Ae0BurbDSrYNAnIKdmT87zC4pF82tRmhy Ky1A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b7-v6si9712327pgq.564.2018.06.01.09.07.29; Fri, 01 Jun 2018 09:07:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752370AbeFAQH2 (ORCPT + 30 others); Fri, 1 Jun 2018 12:07:28 -0400 Received: from foss.arm.com ([217.140.101.70]:54972 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751693AbeFAQGA (ORCPT ); Fri, 1 Jun 2018 12:06:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E8AE4164F; Fri, 1 Jun 2018 09:05:59 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BAD983F557; Fri, 1 Jun 2018 09:05:59 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 41DF31AE5058; Fri, 1 Jun 2018 17:06:30 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH v2 3/9] asm-generic: Move some macros from linux/bitops.h to a new bits.h file Date: Fri, 1 Jun 2018 17:06:23 +0100 Message-Id: <1527869189-31512-4-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527869189-31512-1-git-send-email-will.deacon@arm.com> References: <1527869189-31512-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation for implementing the asm-generic atomic bitops in terms of atomic_long_*, we need to prevent asm/atomic.h implementations from pulling in linux/bitops.h. A common reason for this include is for the BITS_PER_BYTE definition, so move this and some other BIT and masking macros into a new header file, linux/bits.h Signed-off-by: Will Deacon --- include/linux/bitops.h | 22 +--------------------- include/linux/bits.h | 26 ++++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 21 deletions(-) create mode 100644 include/linux/bits.h -- 2.1.4 diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 4cac4e1a72ff..af419012d77d 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -2,29 +2,9 @@ #ifndef _LINUX_BITOPS_H #define _LINUX_BITOPS_H #include +#include -#ifdef __KERNEL__ -#define BIT(nr) (1UL << (nr)) -#define BIT_ULL(nr) (1ULL << (nr)) -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) -#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) -#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) -#define BITS_PER_BYTE 8 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) -#endif - -/* - * Create a contiguous bitmask starting at bit position @l and ending at - * position @h. For example - * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. - */ -#define GENMASK(h, l) \ - (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) - -#define GENMASK_ULL(h, l) \ - (((~0ULL) - (1ULL << (l)) + 1) & \ - (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) extern unsigned int __sw_hweight8(unsigned int w); extern unsigned int __sw_hweight16(unsigned int w); diff --git a/include/linux/bits.h b/include/linux/bits.h new file mode 100644 index 000000000000..2b7b532c1d51 --- /dev/null +++ b/include/linux/bits.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_BITS_H +#define __LINUX_BITS_H +#include + +#define BIT(nr) (1UL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) +#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) +#define BITS_PER_BYTE 8 + +/* + * Create a contiguous bitmask starting at bit position @l and ending at + * position @h. For example + * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. + */ +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define GENMASK_ULL(h, l) \ + (((~0ULL) - (1ULL << (l)) + 1) & \ + (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + +#endif /* __LINUX_BITS_H */ From patchwork Fri Jun 1 16:06:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 137547 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1127924lji; Fri, 1 Jun 2018 09:07:25 -0700 (PDT) X-Google-Smtp-Source: ADUXVKK1oxtdtae4kqVnFgCpJX4piRdV7TIrJx/KsIqrpBz+nkKAGCX0ZeJbWSPD/wUEpkaSArEV X-Received: by 2002:a65:4081:: with SMTP id t1-v6mr9625176pgp.32.1527869245708; Fri, 01 Jun 2018 09:07:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527869245; cv=none; d=google.com; s=arc-20160816; b=oVHJvlDXK6A+xJoWN/muKfE8oCtSjCq37J4lS7cjzJ7ufunuF+IhJzH9Gsf6g9g8Yn PNTvDLzYTvkqAN2ZUDNMvG61NC30GrZV8QgUih/iEE0EPynFeCUpfYT0F7K6qRGgPP1N 7PJRzdB/klKL5ta6Tx8Ju/UR7Yuj9C+cDpQO47EQ3uN8vXTi96EXql13r4rTXI4sm0kS yfmeyobQmL7LbvYSKOqvpcmN78LUQ22CRsHWGvkK4dQ7/1FHnklB9yi15nooYgV6qEKn 78f1Ze0+Hm4g745//wDYS5Sno3koASa4o6w9ErK8xPd4kLcMPUUijFuGW3b7OQyjmBzJ 74Ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=xXZM+SI2dlCVbKrYLzQGoyA6pW2OyLL1pq3eXR+nMv8=; b=F//Wwvpv897Pp3Ee531w+IzEbaF7nw9Sa5VrG8bfp5TclLkMXUZsoL5v7o6oyaudHb GiOPIccw+reIKuYwwtvtjilNuICWzMiiHXeNjWOprffTjNfsgRu9xxZd8WKG4fkjDJkE S4+BwunwgcvpQlWZH2NTRu08z+OcciVNxmMyrwJ9kLF0CE6dg4t+jb6jM15+N5iqM5RT 9KncALjOgiZz+dbx/f25D007ZLExGeAubmQdzV1L1b4RF2H+7V4jGZGhgsU1/JNR9EuJ mmiSHOkjiM1bvumBUQQ96vSUroYHBnbolfyVZSdR+PUWzLFyqlGLuSojefxvDEUeXBCK rdSA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b7-v6si9712327pgq.564.2018.06.01.09.07.25; Fri, 01 Jun 2018 09:07:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753389AbeFAQHW (ORCPT + 30 others); Fri, 1 Jun 2018 12:07:22 -0400 Received: from foss.arm.com ([217.140.101.70]:54988 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751854AbeFAQGA (ORCPT ); Fri, 1 Jun 2018 12:06:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 029A21650; Fri, 1 Jun 2018 09:06:00 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C8F063F59F; Fri, 1 Jun 2018 09:05:59 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 5223B1AE50C7; Fri, 1 Jun 2018 17:06:30 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH v2 4/9] openrisc: Don't pull in all of linux/bitops.h in asm/cmpxchg.h Date: Fri, 1 Jun 2018 17:06:24 +0100 Message-Id: <1527869189-31512-5-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527869189-31512-1-git-send-email-will.deacon@arm.com> References: <1527869189-31512-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The openrisc implementation of asm/cmpxchg.h pulls in linux/bitops.h so that it can refer to BITS_PER_BYTE. It also transitively relies on this pulling in linux/compiler.h for READ_ONCE. Replace the #include with linux/bits.h and linux/compiler.h Signed-off-by: Will Deacon --- arch/openrisc/include/asm/cmpxchg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/openrisc/include/asm/cmpxchg.h b/arch/openrisc/include/asm/cmpxchg.h index d29f7db53906..f9cd43a39d72 100644 --- a/arch/openrisc/include/asm/cmpxchg.h +++ b/arch/openrisc/include/asm/cmpxchg.h @@ -16,8 +16,9 @@ #ifndef __ASM_OPENRISC_CMPXCHG_H #define __ASM_OPENRISC_CMPXCHG_H +#include +#include #include -#include #define __HAVE_ARCH_CMPXCHG 1 From patchwork Fri Jun 1 16:06:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 137546 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1127831lji; Fri, 1 Jun 2018 09:07:21 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLjrMDx3hBvWWYKEDQINQBqu/cLQaU+kawtHSZ6rcF9JMLZG0eq8zFafDlUQNl6e+LOsGVM X-Received: by 2002:a62:1656:: with SMTP id 83-v6mr11430616pfw.61.1527869241497; Fri, 01 Jun 2018 09:07:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527869241; cv=none; d=google.com; s=arc-20160816; b=kqbX9PLlgLaRe0CVAyZzWKhCRlDReXm+q7+uSYz8KpBAQ5KxW8uuiJ+VBJSzUDc2uO isr/p/z+helHbcgCYFnoEyizYwcQupCGpGo/RE7EwdWLkHEG/PS5SFbDQIlIzDOBc+eG klPsottRJ42E1KXriFKX2A1M1ncGMIejwgc77xfWEThNUDqbePUkji8B8pYZhohEgno/ VetsncaDbGAlGYl4yVyBUSZuTFYo6nfTLY1Mb8MwXNmbREnw7+0tQzZdhWPTcnY4sb0l /pYnBSS209pHs7awCi7IHRB7fsadlR2dIuZvrrPEYMLNZ6/MXXXLyeWrIPynoHZiM9UK XE6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Cc8BEwAhVFO5E0uxxh5DaP653Zwr8wKoE8TAsag6eVg=; b=QCJnZj8RTEZ7nH8H9doVhL/RBb2KUb+J5pydpK7Ceffdvm6S2R/xu+gsFmWL/5Xzo/ hI66NJut95wy/XE83AVMz6h2xF5u+56idR2gEreXFMlfiaWlYuCxTgVfyd+DfpyqY5IM wx8YnSCLurb3hjmU6YzNg/j0US1MCFHsyIetBrM0ONk/NBD9QzO1K5cZw43yif2bSgCw dIo3f8iD88tpSNb5ladQhNv1c8RPlBIQ7N+vIsSHdMUzpb+fYpVxtyBzGki+9/QJ3wH8 /fpeYM5v5Fi0SzjDMQNq+TFnuplF7mQDB+5q8M6VF+z75gsQ24j0oogiIyt8DUns0pIk 6jCQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b7-v6si9712327pgq.564.2018.06.01.09.07.21; Fri, 01 Jun 2018 09:07:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753367AbeFAQHS (ORCPT + 30 others); Fri, 1 Jun 2018 12:07:18 -0400 Received: from foss.arm.com ([217.140.101.70]:55022 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752308AbeFAQGA (ORCPT ); Fri, 1 Jun 2018 12:06:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9EB4E165D; Fri, 1 Jun 2018 09:06:00 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 70E2D3F557; Fri, 1 Jun 2018 09:06:00 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 606431AE514F; Fri, 1 Jun 2018 17:06:30 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH v2 5/9] sh: Don't pull in all of linux/bitops.h in asm/cmpxchg-xchg.h Date: Fri, 1 Jun 2018 17:06:25 +0100 Message-Id: <1527869189-31512-6-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527869189-31512-1-git-send-email-will.deacon@arm.com> References: <1527869189-31512-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The sh implementation of asm/cmpxchg-xchg.h pulls in linux/bitops.h so that it can refer to BITS_PER_BYTE. It also transitively relies on this pulling in linux/compiler.h for READ_ONCE. Replace the #include with linux/bits.h and linux/compiler.h Signed-off-by: Will Deacon --- arch/sh/include/asm/cmpxchg-xchg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/sh/include/asm/cmpxchg-xchg.h b/arch/sh/include/asm/cmpxchg-xchg.h index 1e881f5db659..593a9704782b 100644 --- a/arch/sh/include/asm/cmpxchg-xchg.h +++ b/arch/sh/include/asm/cmpxchg-xchg.h @@ -8,7 +8,8 @@ * This work is licensed under the terms of the GNU GPL, version 2. See the * file "COPYING" in the main directory of this archive for more details. */ -#include +#include +#include #include /* From patchwork Fri Jun 1 16:06:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 137545 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1127738lji; Fri, 1 Jun 2018 09:07:17 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKTefxfaX3SzWSlCng3424PSjAR6lBGiI8koaac38cTjWvEVBV657VsWXrATDjOG5NKGr/P X-Received: by 2002:a62:ec6:: with SMTP id 67-v6mr11514424pfo.36.1527869237251; Fri, 01 Jun 2018 09:07:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527869237; cv=none; d=google.com; s=arc-20160816; b=L1B8qlQ9JxnFB3Ysd5tuxo6QIz14GTt8CAX1IF/8NuuepKyNQDDHuenHreZG6/xeMw aiqDOeLeVMrjT4DKy57fYoSI3bRw8GjH3cYLbo6BY+U/BjB/HVkG2tReeH49TQ6UmEI0 3reRCsATxSnlDRhgxmcRcYurWn9H50lG64HpLUNodsqfWIYXEiLwjoFhRNIBLY3ldBDT 1JGXdEbkgIbBLZeT/ysvFHVmGl3fydFLlhqSd8Ea3DfgMRo4nEEMpXeEFwKnfs8TxeKP ikA6FmyBKXeqa8wyhNEpz5D8oNuneFa1zXwb5dLcf0SYGwIjpxGsToYPSa7dRV2xlDMA B4DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=/XMaWtquSYmnSNXULJ0CtIdpGiR5urrLK9UKQMc88HI=; b=Avc/l6O8QMhA4GToCGt6jiO7TcSnwE0u4yAn0y9bH2Ha5UaZYkLwyXp9cezoiChJWy QP06S99fzbCkr55QhfhxcvyOC0cEYWhf4PLko5dlcrdSdff1kFYylYUt4FkJNucb7a+5 uSZw9t0KE/2e9IbgDJ84wMVKSHRiHPbkntUNUwhSwq3KeRkf/pqnwi0ce8I4FtE97GQH BGxiFwDaDoRnA9x0xeYC+1x+0V1/FkaxK9vCy37+clfBYt/YTKRRMztQiTcz+gWTl2tF CkwHDc7JFSp+2b0LF9Zmk+adgN9ByZcg81bEJqTw+4/ag4ZWijfwF0rwV3PPfKjSiC6H WOhQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h12-v6si40156393pfd.253.2018.06.01.09.07.16; Fri, 01 Jun 2018 09:07:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753324AbeFAQHP (ORCPT + 30 others); Fri, 1 Jun 2018 12:07:15 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:55026 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752333AbeFAQGA (ORCPT ); Fri, 1 Jun 2018 12:06:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A85641684; Fri, 1 Jun 2018 09:06:00 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 79E943F59F; Fri, 1 Jun 2018 09:06:00 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 70B341AE5176; Fri, 1 Jun 2018 17:06:30 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH v2 6/9] asm-generic/bitops/atomic.h: Rewrite using atomic_* Date: Fri, 1 Jun 2018 17:06:26 +0100 Message-Id: <1527869189-31512-7-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527869189-31512-1-git-send-email-will.deacon@arm.com> References: <1527869189-31512-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The atomic bitops can actually be implemented pretty efficiently using the atomic_* ops, rather than explicit use of spinlocks. Cc: Peter Zijlstra Cc: Ingo Molnar Signed-off-by: Will Deacon --- include/asm-generic/bitops/atomic.h | 188 +++++++----------------------------- 1 file changed, 33 insertions(+), 155 deletions(-) -- 2.1.4 diff --git a/include/asm-generic/bitops/atomic.h b/include/asm-generic/bitops/atomic.h index 04deffaf5f7d..dd90c9792909 100644 --- a/include/asm-generic/bitops/atomic.h +++ b/include/asm-generic/bitops/atomic.h @@ -2,189 +2,67 @@ #ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_ #define _ASM_GENERIC_BITOPS_ATOMIC_H_ -#include -#include - -#ifdef CONFIG_SMP -#include -#include /* we use L1_CACHE_BYTES */ - -/* Use an array of spinlocks for our atomic_ts. - * Hash function to index into a different SPINLOCK. - * Since "a" is usually an address, use one spinlock per cacheline. - */ -# define ATOMIC_HASH_SIZE 4 -# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) - -extern arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; - -/* Can't use raw_spin_lock_irq because of #include problems, so - * this is the substitute */ -#define _atomic_spin_lock_irqsave(l,f) do { \ - arch_spinlock_t *s = ATOMIC_HASH(l); \ - local_irq_save(f); \ - arch_spin_lock(s); \ -} while(0) - -#define _atomic_spin_unlock_irqrestore(l,f) do { \ - arch_spinlock_t *s = ATOMIC_HASH(l); \ - arch_spin_unlock(s); \ - local_irq_restore(f); \ -} while(0) - - -#else -# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) -# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) -#endif +#include +#include +#include /* - * NMI events can occur at any time, including when interrupts have been - * disabled by *_irqsave(). So you can get NMI events occurring while a - * *_bit function is holding a spin lock. If the NMI handler also wants - * to do bit manipulation (and they do) then you can get a deadlock - * between the original caller of *_bit() and the NMI handler. - * - * by Keith Owens + * Implementation of atomic bitops using atomic-fetch ops. + * See Documentation/atomic_bitops.txt for details. */ -/** - * set_bit - Atomically set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * This function is atomic and may not be reordered. See __set_bit() - * if you do not require the atomic guarantees. - * - * Note: there are no guarantees that this function will not be reordered - * on non x86 architectures, so if you are writing portable code, - * make sure not to rely on its reordering guarantees. - * - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void set_bit(int nr, volatile unsigned long *addr) +static inline void set_bit(unsigned int nr, volatile unsigned long *p) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p |= mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + atomic_long_or(BIT_MASK(nr), (atomic_long_t *)p); } -/** - * clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and may not be reordered. However, it does - * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() - * in order to ensure changes are visible on other processors. - */ -static inline void clear_bit(int nr, volatile unsigned long *addr) +static inline void clear_bit(unsigned int nr, volatile unsigned long *p) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p &= ~mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + atomic_long_andnot(BIT_MASK(nr), (atomic_long_t *)p); } -/** - * change_bit - Toggle a bit in memory - * @nr: Bit to change - * @addr: Address to start counting from - * - * change_bit() is atomic and may not be reordered. It may be - * reordered on other architectures than x86. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void change_bit(int nr, volatile unsigned long *addr) +static inline void change_bit(unsigned int nr, volatile unsigned long *p) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p ^= mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + atomic_long_xor(BIT_MASK(nr), (atomic_long_t *)p); } -/** - * test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It may be reordered on other architectures than x86. - * It also implies a memory barrier. - */ -static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +static inline int test_and_set_bit(unsigned int nr, volatile unsigned long *p) { + long old; unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old | mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + if (READ_ONCE(*p) & mask) + return 1; - return (old & mask) != 0; + old = atomic_long_fetch_or(mask, (atomic_long_t *)p); + return !!(old & mask); } -/** - * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It can be reorderdered on other architectures other than x86. - * It also implies a memory barrier. - */ -static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +static inline int test_and_clear_bit(unsigned int nr, volatile unsigned long *p) { + long old; unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old & ~mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + if (!(READ_ONCE(*p) & mask)) + return 0; - return (old & mask) != 0; + old = atomic_long_fetch_andnot(mask, (atomic_long_t *)p); + return !!(old & mask); } -/** - * test_and_change_bit - Change a bit and return its old value - * @nr: Bit to change - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +static inline int test_and_change_bit(unsigned int nr, volatile unsigned long *p) { + long old; unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old ^ mask; - _atomic_spin_unlock_irqrestore(p, flags); - return (old & mask) != 0; + p += BIT_WORD(nr); + old = atomic_long_fetch_xor(mask, (atomic_long_t *)p); + return !!(old & mask); } #endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */ From patchwork Fri Jun 1 16:06:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 137544 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1127686lji; Fri, 1 Jun 2018 09:07:15 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKiEq6iM88LW6aw/a/2cR5Ntlvt52bU5QC1p4H3lP92AVrR43A8ksVmKSZLPwEZIgV+XsvX X-Received: by 2002:a63:a119:: with SMTP id b25-v6mr4540167pgf.279.1527869235480; Fri, 01 Jun 2018 09:07:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527869235; cv=none; d=google.com; s=arc-20160816; b=wIud3l7fL5jXY29mD65LIrXtMuvnIbYXqUYyO4mIyRnKdcToIXuw5415arFRPRuJgM 1H8Gzwy3VlHCOi81Bc44mMJLVvpXPtqNuk7qODCPx7EVpta6pM7sKJ8BhjpTvc7IQOPa bPf9bMP42WhuXmvUNwYfdqpmOzMR5+qFSE5ga08dTdnRvqIpM2zEVg8ytyBYGeycCWMd Aj1+GbwDXcOnrvmaZF60I9QMU+impnod66eUciW8u549KRzncCDA+FzUBXwKuG0XcbBr YPGok3DZmY7D1KVzf54apXQWVAVWycG+Ht6pN0xcqVdNSk/0rcf0vNeQ4r+Y22bkyhEU fUNg== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id h12-v6si40156393pfd.253.2018.06.01.09.07.15; Fri, 01 Jun 2018 09:07:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753297AbeFAQHM (ORCPT + 30 others); Fri, 1 Jun 2018 12:07:12 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:55030 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752360AbeFAQGA (ORCPT ); Fri, 1 Jun 2018 12:06:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B12581688; Fri, 1 Jun 2018 09:06:00 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 82EBC3F5C9; Fri, 1 Jun 2018 09:06:00 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 8302F1AE519B; Fri, 1 Jun 2018 17:06:30 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH v2 7/9] asm-generic/bitops/lock.h: Rewrite using atomic_fetch_* Date: Fri, 1 Jun 2018 17:06:27 +0100 Message-Id: <1527869189-31512-8-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527869189-31512-1-git-send-email-will.deacon@arm.com> References: <1527869189-31512-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The lock bitops can be implemented more efficiently using the atomic_fetch_* ops, which provide finer-grained control over the memory ordering semantics than the bitops. Cc: Peter Zijlstra Cc: Ingo Molnar Signed-off-by: Will Deacon --- include/asm-generic/bitops/lock.h | 68 ++++++++++++++++++++++++++++++++------- 1 file changed, 56 insertions(+), 12 deletions(-) -- 2.1.4 diff --git a/include/asm-generic/bitops/lock.h b/include/asm-generic/bitops/lock.h index 67ab280ad134..3ae021368f48 100644 --- a/include/asm-generic/bitops/lock.h +++ b/include/asm-generic/bitops/lock.h @@ -2,6 +2,10 @@ #ifndef _ASM_GENERIC_BITOPS_LOCK_H_ #define _ASM_GENERIC_BITOPS_LOCK_H_ +#include +#include +#include + /** * test_and_set_bit_lock - Set a bit and return its old value, for lock * @nr: Bit to set @@ -11,7 +15,20 @@ * the returned value is 0. * It can be used to implement bit locks. */ -#define test_and_set_bit_lock(nr, addr) test_and_set_bit(nr, addr) +static inline int test_and_set_bit_lock(unsigned int nr, + volatile unsigned long *p) +{ + long old; + unsigned long mask = BIT_MASK(nr); + + p += BIT_WORD(nr); + if (READ_ONCE(*p) & mask) + return 1; + + old = atomic_long_fetch_or_acquire(mask, (atomic_long_t *)p); + return !!(old & mask); +} + /** * clear_bit_unlock - Clear a bit in memory, for unlock @@ -20,11 +37,11 @@ * * This operation is atomic and provides release barrier semantics. */ -#define clear_bit_unlock(nr, addr) \ -do { \ - smp_mb__before_atomic(); \ - clear_bit(nr, addr); \ -} while (0) +static inline void clear_bit_unlock(unsigned int nr, volatile unsigned long *p) +{ + p += BIT_WORD(nr); + atomic_long_fetch_andnot_release(BIT_MASK(nr), (atomic_long_t *)p); +} /** * __clear_bit_unlock - Clear a bit in memory, for unlock @@ -37,11 +54,38 @@ do { \ * * See for example x86's implementation. */ -#define __clear_bit_unlock(nr, addr) \ -do { \ - smp_mb__before_atomic(); \ - clear_bit(nr, addr); \ -} while (0) +static inline void __clear_bit_unlock(unsigned int nr, + volatile unsigned long *p) +{ + unsigned long old; -#endif /* _ASM_GENERIC_BITOPS_LOCK_H_ */ + p += BIT_WORD(nr); + old = READ_ONCE(*p); + old &= ~BIT_MASK(nr); + atomic_long_set_release((atomic_long_t *)p, old); +} + +/** + * clear_bit_unlock_is_negative_byte - Clear a bit in memory and test if bottom + * byte is negative, for unlock. + * @nr: the bit to clear + * @addr: the address to start counting from + * + * This is a bit of a one-trick-pony for the filemap code, which clears + * PG_locked and tests PG_waiters, + */ +#ifndef clear_bit_unlock_is_negative_byte +static inline bool clear_bit_unlock_is_negative_byte(unsigned int nr, + volatile unsigned long *p) +{ + long old; + unsigned long mask = BIT_MASK(nr); + + p += BIT_WORD(nr); + old = atomic_long_fetch_andnot_release(mask, (atomic_long_t *)p); + return !!(old & BIT(7)); +} +#define clear_bit_unlock_is_negative_byte clear_bit_unlock_is_negative_byte +#endif +#endif /* _ASM_GENERIC_BITOPS_LOCK_H_ */ From patchwork Fri Jun 1 16:06:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 137543 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1127200lji; Fri, 1 Jun 2018 09:06:49 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJMHFgtB88p45xGO3Aqq5Rol54SqdUuumRFJP2RUh2xovsqCqab3kRD3tgVGi2WGmQzDuxA X-Received: by 2002:aa7:8254:: with SMTP id e20-v6mr11555772pfn.140.1527869209040; Fri, 01 Jun 2018 09:06:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527869209; cv=none; d=google.com; s=arc-20160816; b=Q6VGQj5ewQcaSNE5cluOgDHnrfXtSwE7jd7mY/HshzYe2HpGKLulXRlJlWhqDqvJtt Z4HYy267MiCzRs4YkP7//QAVZpx0mwUbHSemVZeNHeK/lirioIvDSkRljNIxlrqe9Yp6 FafvLbe5CCF6NkWtHtPQeKURGjKsbzCaAQC6IF7iN/XFoDxwoici1d0EpfYj2cleA5Qb ePR3Z6V1scKgqEwuQjKYlFuDQpzO11OavsuESuh+i1DHCA9frE73o10DSuHnEMFcYRyK UVK8TKaZcPONT3NdNZijfld4kwdb21v4CL6C2oAS0+bvIAbMs1YJb37U77tND8o4Dvo5 nr9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=88Np3PUNTEYxNN1Z+7fZ0C9DrRKS+lculQW06jbIgMw=; b=RNVdiZeVeq8U9w/6BC4yvgTqV4PsqW/8x89VO0flRUPxzGzrTWWicdWTbTPewrhXQT 78rO14TRU6IVb1txKuTBT5LbRcAidXbk0Hy9aeRbEMButihbDmV2dx7tvopr3I45RNIr 9zTKr9OzZ7d9etiT6CExIejRC3YqXG+uG85pdc2/FzkfprZyjOxiIifqIfasuzp/pd04 MpNzHNeEzNn+83xPqCCIP30UqTRvo+6zdye5H1rX+VHuMDQy3Het8pEE7jXsMRHgu/Yy zFISRwxEgzTFI5sMcz8e2EEQ6VNIGugQ/hAaKwDKERLvcEqBVw7rlUP852qkutPH0mNc Jc0Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l30-v6si39778664plg.420.2018.06.01.09.06.48; Fri, 01 Jun 2018 09:06:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753237AbeFAQGr (ORCPT + 30 others); Fri, 1 Jun 2018 12:06:47 -0400 Received: from foss.arm.com ([217.140.101.70]:55034 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752416AbeFAQGB (ORCPT ); Fri, 1 Jun 2018 12:06:01 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BA06F169F; Fri, 1 Jun 2018 09:06:00 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8C9343F7A6; Fri, 1 Jun 2018 09:06:00 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 934911AE51AF; Fri, 1 Jun 2018 17:06:30 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH v2 8/9] arm64: Replace our atomic/lock bitop implementations with asm-generic Date: Fri, 1 Jun 2018 17:06:28 +0100 Message-Id: <1527869189-31512-9-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527869189-31512-1-git-send-email-will.deacon@arm.com> References: <1527869189-31512-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The asm-generic/bitops/{atomic,lock}.h implementations are built around the atomic-fetch ops, which we implement efficiently for both LSE and LL/SC systems. Use that instead of our hand-rolled, out-of-line bitops.S. Signed-off-by: Will Deacon --- arch/arm64/include/asm/bitops.h | 14 ++------ arch/arm64/lib/Makefile | 2 +- arch/arm64/lib/bitops.S | 76 ----------------------------------------- 3 files changed, 3 insertions(+), 89 deletions(-) delete mode 100644 arch/arm64/lib/bitops.S -- 2.1.4 diff --git a/arch/arm64/include/asm/bitops.h b/arch/arm64/include/asm/bitops.h index 9c19594ce7cb..13501460be6b 100644 --- a/arch/arm64/include/asm/bitops.h +++ b/arch/arm64/include/asm/bitops.h @@ -17,22 +17,11 @@ #define __ASM_BITOPS_H #include -#include #ifndef _LINUX_BITOPS_H #error only can be included directly #endif -/* - * Little endian assembly atomic bitops. - */ -extern void set_bit(int nr, volatile unsigned long *p); -extern void clear_bit(int nr, volatile unsigned long *p); -extern void change_bit(int nr, volatile unsigned long *p); -extern int test_and_set_bit(int nr, volatile unsigned long *p); -extern int test_and_clear_bit(int nr, volatile unsigned long *p); -extern int test_and_change_bit(int nr, volatile unsigned long *p); - #include #include #include @@ -44,8 +33,9 @@ extern int test_and_change_bit(int nr, volatile unsigned long *p); #include #include -#include +#include +#include #include #include diff --git a/arch/arm64/lib/Makefile b/arch/arm64/lib/Makefile index 137710f4dac3..68755fd70dcf 100644 --- a/arch/arm64/lib/Makefile +++ b/arch/arm64/lib/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -lib-y := bitops.o clear_user.o delay.o copy_from_user.o \ +lib-y := clear_user.o delay.o copy_from_user.o \ copy_to_user.o copy_in_user.o copy_page.o \ clear_page.o memchr.o memcpy.o memmove.o memset.o \ memcmp.o strcmp.o strncmp.o strlen.o strnlen.o \ diff --git a/arch/arm64/lib/bitops.S b/arch/arm64/lib/bitops.S deleted file mode 100644 index 43ac736baa5b..000000000000 --- a/arch/arm64/lib/bitops.S +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Based on arch/arm/lib/bitops.h - * - * Copyright (C) 2013 ARM Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -/* - * x0: bits 5:0 bit offset - * bits 31:6 word offset - * x1: address - */ - .macro bitop, name, llsc, lse -ENTRY( \name ) - and w3, w0, #63 // Get bit offset - eor w0, w0, w3 // Clear low bits - mov x2, #1 - add x1, x1, x0, lsr #3 // Get word offset -alt_lse " prfm pstl1strm, [x1]", "nop" - lsl x3, x2, x3 // Create mask - -alt_lse "1: ldxr x2, [x1]", "\lse x3, [x1]" -alt_lse " \llsc x2, x2, x3", "nop" -alt_lse " stxr w0, x2, [x1]", "nop" -alt_lse " cbnz w0, 1b", "nop" - - ret -ENDPROC(\name ) - .endm - - .macro testop, name, llsc, lse -ENTRY( \name ) - and w3, w0, #63 // Get bit offset - eor w0, w0, w3 // Clear low bits - mov x2, #1 - add x1, x1, x0, lsr #3 // Get word offset -alt_lse " prfm pstl1strm, [x1]", "nop" - lsl x4, x2, x3 // Create mask - -alt_lse "1: ldxr x2, [x1]", "\lse x4, x2, [x1]" - lsr x0, x2, x3 -alt_lse " \llsc x2, x2, x4", "nop" -alt_lse " stlxr w5, x2, [x1]", "nop" -alt_lse " cbnz w5, 1b", "nop" -alt_lse " dmb ish", "nop" - - and x0, x0, #1 - ret -ENDPROC(\name ) - .endm - -/* - * Atomic bit operations. - */ - bitop change_bit, eor, steor - bitop clear_bit, bic, stclr - bitop set_bit, orr, stset - - testop test_and_change_bit, eor, ldeoral - testop test_and_clear_bit, bic, ldclral - testop test_and_set_bit, orr, ldsetal From patchwork Fri Jun 1 16:06:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 137542 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1127160lji; Fri, 1 Jun 2018 09:06:47 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLEyKSTWZjwTKwq3jkJa95QVywdmLPKDGGqPsCN6cevrmjZxGOoLRaet+YUtLkLxDKNFQbs X-Received: by 2002:a17:902:a9c1:: with SMTP id b1-v6mr11931501plr.181.1527869207069; Fri, 01 Jun 2018 09:06:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527869207; cv=none; d=google.com; s=arc-20160816; b=x05f/dmzb5GVjd7fGrkVKRacqTzfHI3ft34V4dyxtivC1zHb5wuCbiIIwlVIMzDxIB tfWDbq02EDbMKfDJ4nt6JvN99kGYYoUCEpL9+LsfPSCpWl3202UHtPFqAblhYGEpsek4 qNcO5qRTndD2Urmf4tX3rltTDy+8KCvN7a1nZuXRPRsbZAo6ZJhrMi9w8dDc3WR6b+Zb cPlwWsgQUL12Lsq+L81kcbS5ebQharhYcfyB0qb6YY8qKHyXGfoZkrxxkgLCLaIQZZC4 GODoBWASuEV8V2C/aR46zZFaWQV1SPOjbzQpEI5IRYErWpuWxbD6GDgcpZSLZXPAbyxV Uvtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=n5MGW/pfF/fJTATDJDJJ2DG14cgfSYeD3F8Z9NccPfo=; b=jTvannyDiUHFWHaENR2y1U0668eGm2YR4xO7C/ZP4e4Ib+rR3YnIIH3IfOK11WDXun TC5hh7x2Czh37M+VwFlcjFIc8dmu3wwW+ffivlKKlZgrtwRQhMAw83kEtGoiIURjdFUp 2lKxgopDOZwPwyP11fpfqUUIXnvuCBh6Q+dMMp8JiF7zPqZEeDUZrG/WEDgC3bohc2sB T49C+/de4y5WdKStAehJxNGvry3E8gh5xwU7vU09Axay5sW9mE6Zz9RcPQSDx95yiSvu //X6MI59ZHGeZs3cxV43uUXIzgA23i7JpToTAXq9YPhHFDxi1dg9n0lx91oeTTKD0wXi X2iw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l30-v6si39778664plg.420.2018.06.01.09.06.46; Fri, 01 Jun 2018 09:06:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753197AbeFAQGp (ORCPT + 30 others); Fri, 1 Jun 2018 12:06:45 -0400 Received: from foss.arm.com ([217.140.101.70]:55038 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752486AbeFAQGB (ORCPT ); Fri, 1 Jun 2018 12:06:01 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C294816A0; Fri, 1 Jun 2018 09:06:00 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 952DF3F855; Fri, 1 Jun 2018 09:06:00 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id A39391AE51B2; Fri, 1 Jun 2018 17:06:30 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH v2 9/9] arm64: bitops: Include Date: Fri, 1 Jun 2018 17:06:29 +0100 Message-Id: <1527869189-31512-10-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527869189-31512-1-git-send-email-will.deacon@arm.com> References: <1527869189-31512-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org asm-generic/bitops/ext2-atomic-setbit.h provides the ext2 atomic bitop definitions, so we don't need to define our own. Signed-off-by: Will Deacon --- arch/arm64/include/asm/bitops.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/bitops.h b/arch/arm64/include/asm/bitops.h index 13501460be6b..10d536b1af74 100644 --- a/arch/arm64/include/asm/bitops.h +++ b/arch/arm64/include/asm/bitops.h @@ -38,11 +38,6 @@ #include #include #include - -/* - * Ext2 is defined to use little-endian byte ordering. - */ -#define ext2_set_bit_atomic(lock, nr, p) test_and_set_bit_le(nr, p) -#define ext2_clear_bit_atomic(lock, nr, p) test_and_clear_bit_le(nr, p) +#include #endif /* __ASM_BITOPS_H */