From patchwork Wed Apr 7 04:50:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qingfang Deng X-Patchwork-Id: 418086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F613C433B4 for ; Wed, 7 Apr 2021 04:51:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2EBC6613A7 for ; Wed, 7 Apr 2021 04:51:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238399AbhDGEvH (ORCPT ); Wed, 7 Apr 2021 00:51:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229825AbhDGEvG (ORCPT ); Wed, 7 Apr 2021 00:51:06 -0400 Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F31F0C06174A; Tue, 6 Apr 2021 21:50:55 -0700 (PDT) Received: by mail-pg1-x530.google.com with SMTP id d10so7240993pgf.12; Tue, 06 Apr 2021 21:50:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lyTJens9zZlmUSEkr38es8/+vCcoQq7SShpXH3x4bPw=; b=oFD11JK7q6mh0Ju5B3WMz6aTtVCgncnckaMWd5AlYppZ/OYPHWZ1SfMs3eXJm68Kz7 tdDVx/phEosetSVbaMHCyv/t8H6IOk7dzao+76kstunjk2gUsurKmJ3P67gqNSl+ZKW0 hKpJcuGfxhOW9/58F6hJbQDUF0zq7INbpRKeDznzhk9SIwskiz2oHzF+AKRXg/Lu25uc uZyl0JDi0G7J00MIi2b4TwS56xxv1nbn2U9dNhWOmw99c5Eu3yAyQIHLONDeZAE7RW9J XbB+uW/Oo5HPwwZaGr5j72HJrInXjKqmsODie6JKaI3v2IDuaqWTPES6fEh825h3GQ9W 6zLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lyTJens9zZlmUSEkr38es8/+vCcoQq7SShpXH3x4bPw=; b=j2j3Hiym0Lhrf8S7Z3mBFZifQzsRtE9CjnUw2o4OAr0zA0pLgCuZWaDZ8tplczl3eI rmxD03yubAsLLH6znuoOt7DxqpNOCJM8il0LluWqtDFRbKtAn3OLd9GI9ekwp7+CCDYh PrS8SNx9NU/ou3/z81d21ZltNWjGS4MgM1V7naJv330f2Htm92Y0Lqxj4HupUZwNrhDU qaihMzJuAShzdmxgK0hiViNhkFg90ZZSzRGs9wBoOBvn8DV/1lFqZ6o8SDKEWqcwWyyU pnmpq0c8kJchl6OAG0ofRgV8suOCwZBa57ymryaz7+3vsuRovS2r+Lq4cjosNGQtFp5G oSmw== X-Gm-Message-State: AOAM530Q7029aJj+m1DXCkAt/SnAWu0NUfwaLj+oZpv5KCndmy4nRM3E K/ctXq5UsXysiSGFCS5/aOo= X-Google-Smtp-Source: ABdhPJwOH3HebZXnuFSPXy6P7qzRP0QFUiwfqUNvx1tsUVuRgd770tOM/PJscsDSbQr/rOtkbrFNGw== X-Received: by 2002:a63:d70f:: with SMTP id d15mr1580642pgg.397.1617771055602; Tue, 06 Apr 2021 21:50:55 -0700 (PDT) Received: from localhost.localdomain ([138.197.212.246]) by smtp.gmail.com with ESMTPSA id n52sm882679pfv.13.2021.04.06.21.50.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 21:50:55 -0700 (PDT) From: DENG Qingfang To: "David S. Miller" , Andrew Lunn , Florian Fainelli , Heiner Kallweit , Jakub Kicinski , Landen Chao , Matthias Brugger , Russell King , Sean Wang , Vivien Didelot , Vladimir Oltean , Rob Herring , Linus Walleij , Greg Kroah-Hartman , Sergio Paracuellos , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-staging@lists.linux.dev, devicetree@vger.kernel.org, netdev@vger.kernel.org Cc: Weijie Gao , Chuanhong Guo , =?utf-8?q?Ren=C3=A9_van_Dorst?= Subject: [RFC v2 net-next 1/4] net: phy: add MediaTek PHY driver Date: Wed, 7 Apr 2021 12:50:35 +0800 Message-Id: <20210407045038.1436843-2-dqfext@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210407045038.1436843-1-dqfext@gmail.com> References: <20210407045038.1436843-1-dqfext@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for MediaTek PHYs found in MT7530 and MT7531 switches. The initialization procedure is from the vendor driver, but due to lack of documentation, the function of some register values remains unknown. Signed-off-by: DENG Qingfang --- RFC v1 -> RFC v2: - Add PHY interface mode check, suggested by Andrew. drivers/net/phy/Kconfig | 5 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/mediatek.c | 112 +++++++++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 drivers/net/phy/mediatek.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index a615b3660b05..edd858cec9ec 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -207,6 +207,11 @@ config MARVELL_88X2222_PHY Support for the Marvell 88X2222 Dual-port Multi-speed Ethernet Transceiver. +config MEDIATEK_PHY + tristate "MediaTek PHYs" + help + Supports the MediaTek switch integrated PHYs. + config MICREL_PHY tristate "Micrel PHYs" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index de683e3abe63..9ed7dbab7770 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_LXT_PHY) += lxt.o obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o obj-$(CONFIG_MARVELL_PHY) += marvell.o obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o +obj-$(CONFIG_MEDIATEK_PHY) += mediatek.o obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o obj-$(CONFIG_MICREL_PHY) += micrel.o diff --git a/drivers/net/phy/mediatek.c b/drivers/net/phy/mediatek.c new file mode 100644 index 000000000000..1faed57e2ed9 --- /dev/null +++ b/drivers/net/phy/mediatek.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include +#include +#include + +#define MTK_EXT_PAGE_ACCESS 0x1f +#define MTK_PHY_PAGE_STANDARD 0x0000 +#define MTK_PHY_PAGE_EXTENDED 0x0001 +#define MTK_PHY_PAGE_EXTENDED_2 0x0002 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003 +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 + +static int mtk_phy_read_page(struct phy_device *phydev) +{ + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +} + +static int mtk_phy_write_page(struct phy_device *phydev, int page) +{ + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); +} + +static void mtk_phy_config_init(struct phy_device *phydev) +{ + /* Disable EEE */ + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); + + /* Enable HW auto downshift */ + phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); + + /* Increase SlvDPSready time */ + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); + __phy_write(phydev, 0x10, 0xafae); + __phy_write(phydev, 0x12, 0x2f); + __phy_write(phydev, 0x10, 0x8fae); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + /* Adjust 100_mse_threshold */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); + + /* Disable mcc */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); +} + +static int mt7530_phy_config_init(struct phy_device *phydev) +{ + mtk_phy_config_init(phydev); + + /* Increase post_update_timer */ + phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b); + + return 0; +} + +static int mt7531_phy_config_init(struct phy_device *phydev) +{ + if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL) + return -EINVAL; + + mtk_phy_config_init(phydev); + + /* PHY link down power saving enable */ + phy_set_bits(phydev, 0x17, BIT(4)); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); + + /* Set TX Pair delay selection */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); + + return 0; +} + +static struct phy_driver mtk_phy_driver[] = { + { + PHY_ID_MATCH_EXACT(0x03a29412), + .name = "MediaTek MT7530 PHY", + .config_init = mt7530_phy_config_init, + /* Interrupts are handled by the switch, not the PHY + * itself. + */ + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, + .read_page = mtk_phy_read_page, + .write_page = mtk_phy_write_page, + }, + { + PHY_ID_MATCH_EXACT(0x03a29441), + .name = "MediaTek MT7531 PHY", + .config_init = mt7531_phy_config_init, + /* Interrupts are handled by the switch, not the PHY + * itself. + */ + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, + .read_page = mtk_phy_read_page, + .write_page = mtk_phy_write_page, + }, +}; + +module_phy_driver(mtk_phy_driver); + +static struct mdio_device_id __maybe_unused mtk_phy_tbl[] = { + { PHY_ID_MATCH_VENDOR(0x03a29400) }, + { } +}; + +MODULE_DESCRIPTION("MediaTek switch integrated PHY driver"); +MODULE_AUTHOR("DENG, Qingfang "); +MODULE_LICENSE("GPL"); + +MODULE_DEVICE_TABLE(mdio, mtk_phy_tbl); From patchwork Wed Apr 7 04:50:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qingfang Deng X-Patchwork-Id: 417252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45BBAC43460 for ; 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Tue, 06 Apr 2021 21:51:02 -0700 (PDT) Received: from localhost.localdomain ([138.197.212.246]) by smtp.gmail.com with ESMTPSA id n52sm882679pfv.13.2021.04.06.21.50.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 21:51:01 -0700 (PDT) From: DENG Qingfang To: "David S. Miller" , Andrew Lunn , Florian Fainelli , Heiner Kallweit , Jakub Kicinski , Landen Chao , Matthias Brugger , Russell King , Sean Wang , Vivien Didelot , Vladimir Oltean , Rob Herring , Linus Walleij , Greg Kroah-Hartman , Sergio Paracuellos , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-staging@lists.linux.dev, devicetree@vger.kernel.org, netdev@vger.kernel.org Cc: Weijie Gao , Chuanhong Guo , =?utf-8?q?Ren=C3=A9_van_Dorst?= Subject: [RFC v2 net-next 2/4] net: dsa: mt7530: add interrupt support Date: Wed, 7 Apr 2021 12:50:36 +0800 Message-Id: <20210407045038.1436843-3-dqfext@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210407045038.1436843-1-dqfext@gmail.com> References: <20210407045038.1436843-1-dqfext@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for MT7530 interrupt controller to handle internal PHYs. In order to assign an IRQ number to each PHY, the registration of MDIO bus is also done in this driver. Signed-off-by: DENG Qingfang --- RFC v1 -> RFC v2: - Split MDIO and IRQ setup function drivers/net/dsa/Kconfig | 1 + drivers/net/dsa/mt7530.c | 238 +++++++++++++++++++++++++++++++++++---- drivers/net/dsa/mt7530.h | 18 ++- 3 files changed, 236 insertions(+), 21 deletions(-) diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig index a5f1aa911fe2..264384449f09 100644 --- a/drivers/net/dsa/Kconfig +++ b/drivers/net/dsa/Kconfig @@ -36,6 +36,7 @@ config NET_DSA_LANTIQ_GSWIP config NET_DSA_MT7530 tristate "MediaTek MT753x and MT7621 Ethernet switch support" select NET_DSA_TAG_MTK + select MEDIATEK_PHY help This enables support for the MediaTek MT7530, MT7531, and MT7621 Ethernet switch chips. diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 2bd1bab71497..813703339db0 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -596,18 +597,14 @@ mt7530_mib_reset(struct dsa_switch *ds) mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); } -static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) +static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum) { - struct mt7530_priv *priv = ds->priv; - return mdiobus_read_nested(priv->bus, port, regnum); } -static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, +static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum, u16 val) { - struct mt7530_priv *priv = ds->priv; - return mdiobus_write_nested(priv->bus, port, regnum, val); } @@ -785,9 +782,8 @@ mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, } static int -mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum) +mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum) { - struct mt7530_priv *priv = ds->priv; int devad; int ret; @@ -803,10 +799,9 @@ mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum) } static int -mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum, +mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum, u16 data) { - struct mt7530_priv *priv = ds->priv; int devad; int ret; @@ -1828,6 +1823,202 @@ mt7530_setup_gpio(struct mt7530_priv *priv) } #endif /* CONFIG_GPIOLIB */ +static irqreturn_t +mt7530_irq(int irq, void *data) +{ + struct mt7530_priv *priv = data; + bool handled = false; + u32 val; + int p; + + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); + mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); + mutex_unlock(&priv->bus->mdio_lock); + + for (p = 0; p < MT7530_NUM_PHYS; p++) { + if (BIT(p) & val) { + handle_nested_irq(irq_find_mapping(priv->irq_domain, + p)); + handled = true; + } + } + + return IRQ_RETVAL(handled); +} + +static void +mt7530_irq_mask(struct irq_data *d) +{ + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); + + priv->irq_enable &= ~BIT(d->hwirq); +} + +static void +mt7530_irq_unmask(struct irq_data *d) +{ + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); + + priv->irq_enable |= BIT(d->hwirq); +} + +static void +mt7530_irq_bus_lock(struct irq_data *d) +{ + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); + + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); +} + +static void +mt7530_irq_bus_sync_unlock(struct irq_data *d) +{ + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); + + mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); + mutex_unlock(&priv->bus->mdio_lock); +} + +static struct irq_chip mt7530_irq_chip = { + .name = KBUILD_MODNAME, + .irq_mask = mt7530_irq_mask, + .irq_unmask = mt7530_irq_unmask, + .irq_bus_lock = mt7530_irq_bus_lock, + .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, +}; + +static int +mt7530_irq_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_data(irq, domain->host_data); + irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); + irq_set_noprobe(irq); + + return 0; +} + +static const struct irq_domain_ops mt7530_irq_domain_ops = { + .map = mt7530_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static void +mt7530_setup_mdio_irq(struct mt7530_priv *priv) +{ + struct dsa_switch *ds = priv->ds; + int p; + + for (p = 0; p < MT7530_NUM_PHYS; p++) { + if (BIT(p) & ds->phys_mii_mask) { + unsigned int irq; + + irq = irq_create_mapping(priv->irq_domain, p); + ds->slave_mii_bus->irq[p] = irq; + } + } +} + +static int +mt7530_setup_irq(struct mt7530_priv *priv) +{ + struct device *dev = priv->dev; + struct device_node *np = dev->of_node; + int parent_irq, ret; + + if (!of_property_read_bool(np, "interrupt-controller")) { + dev_info(dev, "no interrupt support\n"); + return 0; + } + + parent_irq = of_irq_get(np, 0); + if (parent_irq <= 0) { + dev_err(dev, "failed to get parent IRQ: %d\n", parent_irq); + return parent_irq ? : -EINVAL; + } + + priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, + &mt7530_irq_domain_ops, priv); + if (!priv->irq_domain) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } + + /* This register must be set for MT7530 to properly fire interrupts */ + if (priv->id != ID_MT7531) + mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); + + ret = devm_request_threaded_irq(dev, parent_irq, NULL, mt7530_irq, + IRQF_ONESHOT, KBUILD_MODNAME, priv); + if (ret) { + dev_err(dev, "failed to request IRQ: %d\n", ret); + return ret; + } + + return 0; +} + +static void +mt7530_free_mdio_irq(struct mt7530_priv *priv) +{ + int p; + + for (p = 0; p < MT7530_NUM_PHYS; p++) { + if (BIT(p) & priv->ds->phys_mii_mask) { + unsigned int irq; + + irq = irq_find_mapping(priv->irq_domain, p); + irq_dispose_mapping(irq); + } + } +} + +static void +mt7530_free_irq(struct mt7530_priv *priv) +{ + mt7530_free_mdio_irq(priv); + + irq_domain_remove(priv->irq_domain); +} + +static int +mt7530_setup_mdio(struct mt7530_priv *priv) +{ + struct dsa_switch *ds = priv->ds; + struct device *dev = priv->dev; + struct mii_bus *bus; + static int idx; + int ret; + + bus = devm_mdiobus_alloc(dev); + if (!bus) + return -ENOMEM; + + ds->slave_mii_bus = bus; + bus->priv = priv; + bus->name = KBUILD_MODNAME "-mii"; + snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); + bus->read = mt753x_phy_read; + bus->write = mt753x_phy_write; + bus->parent = dev; + bus->phy_mask = ~ds->phys_mii_mask; + + if (priv->irq_domain) + mt7530_setup_mdio_irq(priv); + + ret = mdiobus_register(bus); + if (ret) { + if (priv->irq_domain) + mt7530_free_irq(priv); + + dev_err(dev, "failed to register MDIO bus: %d\n", ret); + return ret; + } + + return 0; +} + static int mt7530_setup(struct dsa_switch *ds) { @@ -2780,32 +2971,38 @@ static int mt753x_setup(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; + int ret = priv->info->sw_setup(ds); + + if (ret) + return ret; - return priv->info->sw_setup(ds); + ret = mt7530_setup_irq(priv); + if (ret) + return ret; + + return mt7530_setup_mdio(priv); } static int -mt753x_phy_read(struct dsa_switch *ds, int port, int regnum) +mt753x_phy_read(struct mii_bus *bus, int port, int regnum) { - struct mt7530_priv *priv = ds->priv; + struct mt7530_priv *priv = bus->priv; - return priv->info->phy_read(ds, port, regnum); + return priv->info->phy_read(priv, port, regnum); } static int -mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) +mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val) { - struct mt7530_priv *priv = ds->priv; + struct mt7530_priv *priv = bus->priv; - return priv->info->phy_write(ds, port, regnum, val); + return priv->info->phy_write(priv, port, regnum, val); } static const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, .get_strings = mt7530_get_strings, - .phy_read = mt753x_phy_read, - .phy_write = mt753x_phy_write, .get_ethtool_stats = mt7530_get_ethtool_stats, .get_sset_count = mt7530_get_sset_count, .set_ageing_time = mt7530_set_ageing_time, @@ -2986,6 +3183,9 @@ mt7530_remove(struct mdio_device *mdiodev) dev_err(priv->dev, "Failed to disable io pwr: %d\n", ret); + if (priv->irq_domain) + mt7530_free_irq(priv); + dsa_unregister_switch(priv->ds); mutex_destroy(&priv->reg_mutex); } diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index ec36ea5dfd57..e4429e152cde 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -7,6 +7,7 @@ #define __MT7530_H #define MT7530_NUM_PORTS 7 +#define MT7530_NUM_PHYS 5 #define MT7530_CPU_PORT 6 #define MT7530_NUM_FDB_RECORDS 2048 #define MT7530_ALL_MEMBERS 0xff @@ -381,6 +382,12 @@ enum mt7531_sgmii_force_duplex { #define SYS_CTRL_SW_RST BIT(1) #define SYS_CTRL_REG_RST BIT(0) +/* Register for system interrupt */ +#define MT7530_SYS_INT_EN 0x7008 + +/* Register for system interrupt status */ +#define MT7530_SYS_INT_STS 0x700c + /* Register for PHY Indirect Access Control */ #define MT7531_PHY_IAC 0x701C #define MT7531_PHY_ACS_ST BIT(31) @@ -702,6 +709,11 @@ static const char *p5_intf_modes(unsigned int p5_interface) } } +/* Forward declaration */ +struct mt7530_priv; +static int mt753x_phy_read(struct mii_bus *, int, int); +static int mt753x_phy_write(struct mii_bus *, int, int, u16); + /* struct mt753x_info - This is the main data structure for holding the specific * part for each supported device * @sw_setup: Holding the handler to a device initialization @@ -726,8 +738,8 @@ struct mt753x_info { enum mt753x_id id; int (*sw_setup)(struct dsa_switch *ds); - int (*phy_read)(struct dsa_switch *ds, int port, int regnum); - int (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val); + int (*phy_read)(struct mt7530_priv *priv, int port, int regnum); + int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); int (*cpu_port_config)(struct dsa_switch *ds, int port); bool (*phy_mode_supported)(struct dsa_switch *ds, int port, @@ -782,6 +794,8 @@ struct mt7530_priv { struct mt7530_port ports[MT7530_NUM_PORTS]; /* protect among processes for registers access*/ struct mutex reg_mutex; + struct irq_domain *irq_domain; + u32 irq_enable; }; struct mt7530_hw_vlan_entry { From patchwork Wed Apr 7 04:50:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qingfang Deng X-Patchwork-Id: 418085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79F3FC43461 for ; Wed, 7 Apr 2021 04:51:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4EC61613A7 for ; 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Tue, 06 Apr 2021 21:51:08 -0700 (PDT) From: DENG Qingfang To: "David S. Miller" , Andrew Lunn , Florian Fainelli , Heiner Kallweit , Jakub Kicinski , Landen Chao , Matthias Brugger , Russell King , Sean Wang , Vivien Didelot , Vladimir Oltean , Rob Herring , Linus Walleij , Greg Kroah-Hartman , Sergio Paracuellos , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-staging@lists.linux.dev, devicetree@vger.kernel.org, netdev@vger.kernel.org Cc: Weijie Gao , Chuanhong Guo , =?utf-8?q?Ren=C3=A9_van_Dorst?= Subject: [RFC v2 net-next 3/4] dt-bindings: net: dsa: add MT7530 interrupt controller binding Date: Wed, 7 Apr 2021 12:50:37 +0800 Message-Id: <20210407045038.1436843-4-dqfext@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210407045038.1436843-1-dqfext@gmail.com> References: <20210407045038.1436843-1-dqfext@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add device tree binding to support MT7530 interrupt controller. Signed-off-by: DENG Qingfang --- RFC v1 -> RFC v2: - No changes. Documentation/devicetree/bindings/net/dsa/mt7530.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt b/Documentation/devicetree/bindings/net/dsa/mt7530.txt index de04626a8e9d..26b34888eb62 100644 --- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt +++ b/Documentation/devicetree/bindings/net/dsa/mt7530.txt @@ -81,6 +81,11 @@ Optional properties: - gpio-controller: Boolean; if defined, MT7530's LED controller will run on GPIO mode. - #gpio-cells: Must be 2 if gpio-controller is defined. +- interrupt-controller: Boolean; Enables the internal interrupt controller. + +If interrupt-controller is defined, the following property is required. + +- interrupts: Parent interrupt for the interrupt controller. See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional required, optional properties and how the integrated switch subnodes must From patchwork Wed Apr 7 04:50:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qingfang Deng X-Patchwork-Id: 417251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB17EC433B4 for ; Wed, 7 Apr 2021 04:51:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 819216139C for ; Wed, 7 Apr 2021 04:51:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343572AbhDGEva (ORCPT ); Wed, 7 Apr 2021 00:51:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344432AbhDGEvY (ORCPT ); Wed, 7 Apr 2021 00:51:24 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB719C06174A; Tue, 6 Apr 2021 21:51:14 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id q6-20020a17090a4306b02900c42a012202so640965pjg.5; Tue, 06 Apr 2021 21:51:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V+6L2oYqEs/QSzIuajaQppBr7eHY4K1Hd4WvlAlIz/c=; b=UeAdH92teKX9nqcjZrk6pjPXGRY/rZBLvzZum7GHe0oWmKCSm4tAQ4eAOvRQAT5pgy PF7nSdVhu89VA+F1sjXLLRN9YSm8CeaAXQm/HThDqjJ/5qxZTBR0FRr4iPTXGv44eaAh mn32RaEya6zyckqOH+zEUfmh1v7kWe2tPpGev7txR5rly1tFsWI0fsbXkxy2kYwdtN6n rJEZFeVZV7hA743py53NBrlmr/2FAbsMfrg0Y+ugHTzfLkphin/HBXO1pEkySxvaYL3O Ma86/uJ93tkIAFC9A8krTtyTUfP5xZ9R/ZuHxTfrbv7ljpg4SB2C+Y4kOLzRpAWdVssR rg8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V+6L2oYqEs/QSzIuajaQppBr7eHY4K1Hd4WvlAlIz/c=; b=cOArZdJ8Mv/IutBLmRZOYTS+RNNFXbwTeqw2wVjzHB0OdYNhHy8R9QsST+SXySpRGj kuLIk04N2hmOn73UyyzvnCk0FNZMV11QltvDS8zohdH699H0jKhmlokqHkv6dtB11Vn3 jpIfJaUUTOxM3Xk2CPoxWrGZPOD9aDbLUaM9pLIcOPxwHB9AgoqBYQ76t7FKBmVWw8Ke prReyYT3oFVVsoJy09Ep9irsA6rZiCKONlJaYdROwLVCpUr2Ag9oAc0giJU82IYGy/UZ wu/zWIn1OrRBnGbEOVWPiurX3RqT3TzJLp56BoY8EibxXBb5CyQUFfplTve27Fv/60VF HKMQ== X-Gm-Message-State: AOAM532LbanVhFbUfHC/u0tBcqCrAVuCGQUkQ3OW+PMfOdZXtbgHZ182 3WI1KSbz5zKIbNzC52TnSRw= X-Google-Smtp-Source: ABdhPJwwV7+KRnS4AYoBBARd+AzL4vj5vm1mLsxuvTDRCFHHfrgCqfllBL734AbDkmtPtKYUoSdcVA== X-Received: by 2002:a17:902:ea10:b029:e8:e2e9:d9a5 with SMTP id s16-20020a170902ea10b02900e8e2e9d9a5mr1414313plg.22.1617771074590; Tue, 06 Apr 2021 21:51:14 -0700 (PDT) Received: from localhost.localdomain ([138.197.212.246]) by smtp.gmail.com with ESMTPSA id n52sm882679pfv.13.2021.04.06.21.51.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 21:51:14 -0700 (PDT) From: DENG Qingfang To: "David S. Miller" , Andrew Lunn , Florian Fainelli , Heiner Kallweit , Jakub Kicinski , Landen Chao , Matthias Brugger , Russell King , Sean Wang , Vivien Didelot , Vladimir Oltean , Rob Herring , Linus Walleij , Greg Kroah-Hartman , Sergio Paracuellos , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-staging@lists.linux.dev, devicetree@vger.kernel.org, netdev@vger.kernel.org Cc: Weijie Gao , Chuanhong Guo , =?utf-8?q?Ren=C3=A9_van_Dorst?= Subject: [RFC v2 net-next 4/4] staging: mt7621-dts: enable MT7530 interrupt controller Date: Wed, 7 Apr 2021 12:50:38 +0800 Message-Id: <20210407045038.1436843-5-dqfext@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210407045038.1436843-1-dqfext@gmail.com> References: <20210407045038.1436843-1-dqfext@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Enable MT7530 interrupt controller in the MT7621 SoC. Signed-off-by: DENG Qingfang --- RFC v1 -> RFC v2: - No changes. drivers/staging/mt7621-dts/mt7621.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 16fc94f65486..ebf8b0633e88 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -447,6 +447,9 @@ switch0: switch0@0 { mediatek,mcm; resets = <&rstctrl 2>; reset-names = "mcm"; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = ; ports { #address-cells = <1>;