From patchwork Wed May 30 18:19:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 137283 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp5646046lji; Wed, 30 May 2018 11:19:39 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKyld2/8GKcZpQjWnJgnUl3Ke3EfTMET6FEGaPWUyQ9YB+yp4UFgm/E9KgiRl+wc2Hq3CAW X-Received: by 2002:a62:df12:: with SMTP id u18-v6mr3753954pfg.230.1527704379305; Wed, 30 May 2018 11:19:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527704379; cv=none; d=google.com; s=arc-20160816; b=kKfQQf91aFgUObRK+ATpDct6UaEe98r2Z3LnUW07EjvKFycNH0UdgDbo0psf8nwJX7 Z+wFBLfb3CrnmIpDCmPzZjxCS5D03m+B4WUnJ6nP5tqBqGD6J8M4es4ZYap6vmLlVYE8 zS6SNOWOHfc7e0ADMIlm41A/+elnlZNqlry5j4vHw97NxKKLsuUUBUPrxvfUSneX0Eo4 kPrO2wwCFCMwlKOfGttpm7xj5VhlD+NQwPb/C+JSx833bzqz6lrtQJ/betJzbvLwnBF7 dyyyexZsjICEePlEdRR8Nw1FOdNci1FL9dFMOGz/tdCXXTijVpbdTKSe/CBVHaf4DrU5 QDoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=V6u1cPCNBKoecDyMrA8piiqIDKyAv5ak+EBEZYUjckQ=; b=0pUCdiZAiHsMvhQo7oKgvPNF+S1RaDX7jVL/l7L236axx8LTBHnBuumrPR7hVAeOvI JolBWJQSbWYmSbbHNFLdaYB2weG/zcsQBZm0VfUsECKCFTOU6N+1nKRFwhwo5kbsHUno 7SmzdAKkb9h+FMnsr9kjgyjcRpuvTdYcOEw3MUDXQ/KIyqvXPZzgJvuUlSzBEXYzaOoH YYBDZxEWYUeI6JPAmwg+idYNLT+jJnI+fiaZB9bJeCJQS163OixodotU9cvXZIBX5Z5f 8GGbxpjP6iRRdwo0gsHkx6MMTBS7Wtyb2pmZwBOFbK2s9ElFi/qFfBb437t6DW5mVfCV CWDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dvsDysyT; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id 95-v6si36328983plc.383.2018.05.30.11.19.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dvsDysyT; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A2981210C998E; Wed, 30 May 2018 11:19:38 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1AEBE210C997A for ; Wed, 30 May 2018 11:19:37 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id i12-v6so30496480wrc.4 for ; Wed, 30 May 2018 11:19:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RNOHp2TbxVLH+DSFojfAFSFGNlt0bp2vpVXkOF7Ryzc=; b=dvsDysyT6UTseVQ853f0Oo+JTyKhNRbxXAqdBa/NmbszfeH7uaJdazTvmL0pOWVoOL nHuoXdv0BYLiIDkqliPQ7V/ecbuvNzGTSDF9mTXFmxjeMTjXAlCwDLbJQzzZCjed5jN5 2dEixtjNZGp/nUMGfGDBJVlJ/MYo13IajO0Bc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RNOHp2TbxVLH+DSFojfAFSFGNlt0bp2vpVXkOF7Ryzc=; b=ns1jsUWL4ZVHzE0GQ7uJseCJvlVIXkJVXY6Irf82TnUE9nMqSzKWbTC3JG3mpFMsYq Es+StDfiI1UXV5YU/r/x/pZeorAD2k2xEt8LyKCXKTFGO5gYWbwd7/r22LB4QIVC66FK kS3WsgNOPG6UkG3awup1VzDZkTUMmn1tNGxk/EkUoI6nTWJ3QxLpYTFbZVniL66Lucyo oPjt7K6/MC4r6PPCMU2QU+jRU0QOlZPwd61I+4h7cX2d2Ar60LfNviAHySUSHKOxXP8k BUZdseAPAeivR3LVvAt+U4Qh41cN6Jgy7IXWDg9ESPeNKqDhQ7oy7IWYwztke8q0BYBE Vygg== X-Gm-Message-State: ALKqPwdYpwHxR+E32WxGSdmYSw+pS9Y2NTGYzsdf1zzyWr4NcEGTkcqb wQ8xtWD2ccvkB+opt9XeYjW9ptl225s= X-Received: by 2002:adf:9f4a:: with SMTP id f10-v6mr2895278wrg.216.1527704375304; Wed, 30 May 2018 11:19:35 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id b105-v6sm48315705wrd.64.2018.05.30.11.19.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:34 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 30 May 2018 20:19:27 +0200 Message-Id: <20180530181929.5066-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530181929.5066-1-ard.biesheuvel@linaro.org> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/3] Silicon/SynQuacerPciHostBridgeLib: add workaround for PCIe MMIO64 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Masahisa KOJIMA The current revision of SC2A11 contains PCIe bus issue. In MRd transaction, 1st/Last DW BE fields are not correctly set by hardware. As a workaround, set TH bit and specify MSG_CODE in iATU. With this setup, the value specified as MSG_CODE is set to the 1st/Last DW BE fields and PCIe controller can emit the correct MRd TLP header. Same workaround was already included for MMIO32 region, MMIO64 region also requires this workaround. Some deivices, such as Samsong SSD 970 EVO, do not work without this modification. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Masahisa KOJIMA --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index e4679543cc66..227f9a725ce8 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -359,8 +359,9 @@ PciInitControllerPost ( RootBridge->MemAbove4G.Base, RootBridge->MemAbove4G.Base, RootBridge->MemAbove4G.Limit - RootBridge->MemAbove4G.Base + 1, - IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, - 0); + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); } // enable link From patchwork Wed May 30 18:19:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 137284 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp5646094lji; Wed, 30 May 2018 11:19:43 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIx1XYidObMpXLuaRJJuSgX1TuQjhj7Zr5cQSp03eflHYXyBg7tZWdPggKjEeDSRR/R+hww X-Received: by 2002:a62:8785:: with SMTP id i127-v6mr3768297pfe.201.1527704383170; Wed, 30 May 2018 11:19:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527704383; cv=none; d=google.com; s=arc-20160816; b=MCodj9+Ct0Srq3uny6Kd/2O4jzWl+42EgskZlxthgwzyjxaD/AhI+XLSbTpFbq9iZK yC2Pbg/2763ssYWFjHwmdtlN8C+Grvpug1guwalbvJ6QeRoGSRTGWz4lrgxY6v4woM0Y Weqh++g0LSolxzBKybzaHEOaXYKhYuhNI+LfjGD0/JCWXzK6eNj2pv9IwuNNg5ix0kuR MuKe+WiXm7OdxO0TUgHKOxF5ckm/WtoIlSoXvKYyllFY9vGgdAo5TK5KOypYuH35k0vl BdgFfLqcDjgKhXn2l97qtA4+glxHI8gzY8t/ZE2EoKLd+DhWBnYhyolqqJi7pjN0Wy+F 0rFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=QvDXzwZEq7gQ4iLOlMDIXOPqy0b5B6ezkBMlt1nguPQ=; b=U/lQKtBHOT8uu+TichSiEoN6qcohFF+CBYKjzUVExd3yibfgMHtyRS2mK3Ywxtr5Z+ LsWOY1TsTaCpKSyNzPNhMmZV80phjMtNn6kMvVVmddQZhjFMbwMK96NiEiHy9C2xDEm9 WxSYVYEpw3Ckz0I30hks1U9n5Z31o2EWVsHJn3JAXl0jYnfZ9LB3APN3N8yFTmMHIs+F 5ZqnpTV2NCZzFS1CynP4FoxsQf6MSGNRLMUa0Pdj78Iv+ebxOAhzsJP6izOdx5ZiTTTZ CnJEXMtBYBgu3QnaXoKQRymchzqwNsQFAt/4ITXCm5vSSEnFrPPWbFqpXu4MkzFzpXKY qEZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fkvS55e3; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id k6-v6si27640468pgq.85.2018.05.30.11.19.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fkvS55e3; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CE5D5210C9994; Wed, 30 May 2018 11:19:39 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::233; helo=mail-wm0-x233.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x233.google.com (mail-wm0-x233.google.com [IPv6:2a00:1450:400c:c09::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8ED9F210C9985 for ; Wed, 30 May 2018 11:19:38 -0700 (PDT) Received: by mail-wm0-x233.google.com with SMTP id 18-v6so43933965wml.2 for ; Wed, 30 May 2018 11:19:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cw2vi7HLHO3WaOEBU2ul3+x4/qgdXHTLiFXzAKjeLKo=; b=fkvS55e3iwNDvHwcGzIGzXxCaPn7UWUJWNS0lM/jpwwz10cg1UgeJ7VhCVg6U9Aw7C tzj0+/Qoj0fBMcDOmpVtr/RrSJEiI2cRM7Qe9tyAknMgAgXZJmw3aLpC0+OkfqWM6+p2 BSrkzDVzBaxPNKeFuvY6lU9Vvg4jyTWT4Ip+c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cw2vi7HLHO3WaOEBU2ul3+x4/qgdXHTLiFXzAKjeLKo=; b=WnUVoryuYRZ7ExVPmxsuR2daJW/PR8kPDuBCeLOsP9VPMKR0x1FfDB9J4kdR3AvRh3 JgyVECqML781qpTTRd1LHeRnm7ADOrCl6ebDZC+012Ykz0dDK+6kQnUXt4C1m8KTab7B tVrafpWspyP9bJu7cTaNoAcb06Dqt9JHtp7n1WWb6eB1/E+YF/zvgkmJHR2owPddw1jB dGLX+mYYoQ9MNPmS5czqKGen9GyaYFt4IRD7dLo/NjBgPR1vQr6rAWvX9jcnVH+c3G6C L1bKvt3xqI3KdPy3mgtxsl/IkGcntXW8YwO/JFvIZmsnR4dErZKGY/rP3LOy+N2TFIzP LfBg== X-Gm-Message-State: ALKqPwemuDZEJ4xNvGAvSKNAFQg/c+/bxa/PjpXoQLCnp1AkQMkPqrZl pLBbaFjn36FLWTAot1uYrA4rOwdSZAk= X-Received: by 2002:a1c:6952:: with SMTP id e79-v6mr2380730wmc.76.1527704376794; Wed, 30 May 2018 11:19:36 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id b105-v6sm48315705wrd.64.2018.05.30.11.19.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:36 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 30 May 2018 20:19:28 +0200 Message-Id: <20180530181929.5066-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530181929.5066-1-ard.biesheuvel@linaro.org> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/3] Silicon/Socionext/SynQuacer/Stage2Tables: add north SMMU level 3 table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Extend the static stage 2 page tables with a set of level 3 tables that describe the ECAM space in a manner that allows the north SMMU to be used to make the ECAM space appear sane to the CPUs. It is up to the secure firmware to manipulate the north SMMU page tables so that the level 2 block entries corresponding with busses #0 .. #1 in the respective config spaces of PCI0 and PCI1 are replaced with table entries pointing to the level 3 tables added by this patch. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 35 +++++++++++++++----- 1 file changed, 26 insertions(+), 9 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S index 313ef3c56abc..af55f27bca47 100644 --- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S @@ -20,15 +20,17 @@ * the SoC. */ -#define TT_S2_CONT_SHIFT 52 -#define TT_S2_AF (0x1 << 10) -#define TT_S2_SH_NON_SHAREABLE (0x0 << 8) -#define TT_S2_AP_RW (0x3 << 6) -#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2) -#define TT_S2_MEMATTR_MEMORY_WB (0xf << 2) -#define TT_S2_TABLE (0x3 << 0) -#define TT_S2_L3_PAGE (0x1 << 1) -#define TT_S2_VALID (0x1 << 0) +#define TT_S2_CONT_SHIFT 52 +#define TT_S2_AF (0x1 << 10) +#define TT_S2_SH_NON_SHAREABLE (0x0 << 8) +#define TT_S2_AP_RO (0x1 << 6) +#define TT_S2_AP_RW (0x3 << 6) +#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2) +#define TT_S2_MEMATTR_DEVICE_nGnRE (0x1 << 2) +#define TT_S2_MEMATTR_MEMORY_WB (0xf << 2) +#define TT_S2_TABLE (0x3 << 0) +#define TT_S2_L3_PAGE (0x1 << 1) +#define TT_S2_VALID (0x1 << 0) .altmacro .macro for, start, count, do, arg2, arg3, arg4 @@ -58,6 +60,12 @@ TT_S2_L3_PAGE | TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT) .endm + .macro smmu_l3_entry, base, offset=0, ignore=0 + .quad ((\base << 12) + \offset) | TT_S2_AF | TT_S2_AP_RO | \ + TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_DEVICE_nGnRE | \ + TT_S2_L3_PAGE | TT_S2_VALID + .endm + .section ".rodata", "a", %progbits /* level 1 */ s2_mem_entry 0 /* 0x0000_0000 - 0x3fff_ffff */ @@ -86,3 +94,12 @@ 3:for 0, 8, s2_l3_entry, 0x70000000 for 0, 8, s2_l3_entry, 0x70010000 /* hide device #1 */ for 0, 496, s2_l3_entry, 0x70010000, 1 + + /* level 3 for north SMMU */ + .org 0x6000 + for 0, 8, smmu_l3_entry, 0xc00060000000 + for 0, 8, smmu_l3_entry, 0xc00060010000 /* hide device #1 */ + for 0, 496, smmu_l3_entry, 0xc00060010000 + for 0, 8, smmu_l3_entry, 0x800070000000 + for 0, 8, smmu_l3_entry, 0x800070010000 /* hide device #1 */ + for 0, 496, smmu_l3_entry, 0x800070010000 From patchwork Wed May 30 18:19:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 137285 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp5646153lji; Wed, 30 May 2018 11:19:46 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJ6H4Jukeq/QaqVShBY/aUhAChnA6ikQMeElshRsbIUGlCGDlRA/iicM5R9THmp5CTKMR3a X-Received: by 2002:a17:902:7841:: with SMTP id e1-v6mr3903419pln.197.1527704386621; Wed, 30 May 2018 11:19:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527704386; cv=none; d=google.com; s=arc-20160816; b=w/qjPVSMYjKT7nh6deVEWViF5yQ0Dx3XknWEZlwD9ZMe28y2Aga+Rx3HYSPVhgxexz XrfNYDvpUpi/GKE2D/P6U+QvTkiRiellbxfuKsG85hWbOY2gRIHg3vZoKHE3rIvEXHSv CJvwwYXsdWcNCDrWMy8ImQ8KVuX6d8I6SLvk6UshH6plFIhlXZZUjXii2ajqxiCzznf6 KE7eh6Ys8/r3YEYlhyqvsfEkpovaqRrFG9hn7eUvL2l9K9pvWtHREduVedInBQ7RxeHC j44X2jfsVlH9Oc0AQ7ozxHsO/du9oNt5CluXbddf6gB3dv+gwUa54mwKTw8yY1YkxfE9 r2xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=0nfs6Xla9I32Bww2BO/CdD9jZ7BnARF6k061anRRm08=; b=gXIIBr/b4yr1D319vuIHa1tE7X4ZncrF/K3KMTfTzd6Du/4h+aDMetx+f2pxCC0QHh 8s2xX4dgoARLG/01550+vkO8KKuT2GT5GhN01zdggyqBTvGPgorFMZ8HO7Nspz0mtGkZ RYhsONYmImd4kpomWg0rsDkgWma6703KDw8sGYVBVlTpIrQFg6Ehk74GY4zZsPMm9tcZ l23Lk9ZwCAOZ7H0u9diD9WE16htuaxKzgNm/P6GsIKQWZhY9RMUl7saTj5dq097dl2ds 9AEclFWe4c/UnAmlBQqxYoGkljAtwVlCD2x7ZA+RJgNPvnxvBj3W9PMMYmddHnuG0Je+ DCLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gCABZ4tF; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id t12-v6si28251547pgr.690.2018.05.30.11.19.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gCABZ4tF; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0316A210C9987; Wed, 30 May 2018 11:19:42 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 12796210C9978 for ; Wed, 30 May 2018 11:19:40 -0700 (PDT) Received: by mail-wm0-x244.google.com with SMTP id 18-v6so43934053wml.2 for ; Wed, 30 May 2018 11:19:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fgYoYKWoshTorOCl2oPSlXJYjjZylJuB8SbfjrHR4GQ=; b=gCABZ4tFg/2lbL7dlQKIO6TiHkVwh4SzB2+s6Co8H6jNdTpbHQ6y3lLkaYk246OtaJ R4uX0JM2dQfHzjNBhgl/Y6DFZdZeuxDKNDGy3ETe5KYrwhkje3WoxqyWDCcDPlBpgeEr gTQHpXLYTTXAW+5B09jDqSAVEXGMBuXIEVt+Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fgYoYKWoshTorOCl2oPSlXJYjjZylJuB8SbfjrHR4GQ=; b=DgFltTx6ICWNoHgF8AoCHWc+RgpIvFmXY29OxKkbzfQT0zJnD3Meh4OjVbuLRm3Shu xCVZiluaifTUA6D1GyUvWAb5LiVnXIjmBbDQE/1bPFRGy+2f+3fddgIDaBMwodXRUz1Q cw62fXUyEqaqWXvQNcTX8aLGlCNZWnb0gxokNTvhV83tlcwh5X3+UwKmTASWMYWw/Vpr piG05yG1d5SLPse7T3ucq4N9+IJrsl83SUWJ7P/HUL3PNu9bKZG21cwCs5KeqyTH+3a6 tLxakq8rN3K5zLrehAA3A6eh+OqOcZKHfokmf+ESAkf4kzeIVgIui3Gy/wccl9/CXwac 8QHQ== X-Gm-Message-State: ALKqPwe3taOoj2WUkH0DRR7/nis4HCMXrrBmRGsqyldYOIbR8YXVKtBH lce2ffo754s35RbCDVxaHpwWDbo8zSs= X-Received: by 2002:a1c:17c9:: with SMTP id 192-v6mr2103620wmx.95.1527704378347; Wed, 30 May 2018 11:19:38 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id b105-v6sm48315705wrd.64.2018.05.30.11.19.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:37 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 30 May 2018 20:19:29 +0200 Message-Id: <20180530181929.5066-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530181929.5066-1-ard.biesheuvel@linaro.org> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 3/3] Silicon/SynQuacer/AcpiTables: add NETSEC/eMMC SMMU to the IORT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add a description of the SMMU that sits in front of the NETSEC and eMMC controllers to the IORT table so that ACPI based OSes can utilize it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 109 +++++++++++++++++++- 1 file changed, 107 insertions(+), 2 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc index 92c485f8006f..3f2aaa3d8858 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc @@ -13,6 +13,7 @@ **/ #include +#include #include "AcpiTables.h" @@ -29,10 +30,23 @@ typedef struct { EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; } SYNQUACER_RC_NODE; +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[8]; +} SYNQUACER_SMMU_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node; + CONST CHAR8 Name[11]; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; +} SYNQUACER_NC_NODE; + typedef struct { EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; SYNQUACER_ITS_NODE ItsNode; SYNQUACER_RC_NODE RcNode[2]; + SYNQUACER_SMMU_NODE SmmuNode; + SYNQUACER_NC_NODE NamedCompNode[2]; } SYNQUACER_IO_REMAPPING_STRUCTURE; #define __SYNQUACER_ID_MAPPING(In, Num, Out, Ref, Flags) \ @@ -49,7 +63,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, SYNQUACER_IO_REMAPPING_STRUCTURE, EFI_ACPI_IO_REMAPPING_TABLE_REVISION), - 3, // NumNodes + 6, // NumNodes sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset 0 // Reserved }, { @@ -94,7 +108,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { // __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE), - }, { + }, { // PciRcNode { { @@ -121,6 +135,97 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE), } + }, { + // NETSEC/eMMC SMMU node + { + { + EFI_ACPI_IORT_TYPE_SMMUv1v2, + sizeof(SYNQUACER_SMMU_NODE), + 0x0, + 0x0, + 0x0, + 0x0, + }, + SYNQUACER_SCB_SMMU_BASE, + SYNQUACER_SCB_SMMU_SIZE, + EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500, + EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, + FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, + SMMU_NSgIrpt), + 0x8, + sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), + 0x0, + 0x0, + 228, + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, + 0x0, + 0x0, + }, { + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + }, + }, { + { + // NETSEC named component node + { + { + EFI_ACPI_IORT_TYPE_NAMED_COMP, + sizeof(SYNQUACER_NC_NODE), + 0x0, + 0x0, + 0x1, + FIELD_OFFSET(SYNQUACER_NC_NODE, RcIdMapping), + }, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, + 0x0, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, + 40, + }, { + "\\_SB_.NET0" + }, { + 0x0, + 0x0, + 0x0, + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, SmmuNode), + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE + } + }, { + // eMMC named component node + { + { + EFI_ACPI_IORT_TYPE_NAMED_COMP, + sizeof(SYNQUACER_NC_NODE), + 0x0, + 0x0, + 0x1, + FIELD_OFFSET(SYNQUACER_NC_NODE, RcIdMapping), + }, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, + 0x0, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, + 40, + }, { + "\\_SB_.MMC0" + }, { + 0x0, + 0x0, + 0x0, + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, SmmuNode), + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE + } + } } };