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[82.65.169.74]) by smtp.googlemail.com with ESMTPSA id yh6sm3732875ejb.37.2021.04.07.07.57.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 07:57:40 -0700 (PDT) From: Jerome Brunet To: Mark Brown , Liam Girdwood Subject: [PATCH] ASoC: meson: axg-frddr: set fifo depth according to the period Date: Wed, 7 Apr 2021 16:57:14 +0200 Message-Id: <20210407145714.311138-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Patchwork-Bot: notify Cc: linux-amlogic@lists.infradead.org, alsa-devel@alsa-project.org, Kevin Hilman , linux-kernel@vger.kernel.org, Jerome Brunet X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" When the period is small, using all the FRDDR fifo depth increases the latency of the playback because the following device won't start pulling data until the fifo reaches the depth set. We can adjust this depth so trim it down for small periods. Signed-off-by: Jerome Brunet --- sound/soc/meson/axg-frddr.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/sound/soc/meson/axg-frddr.c b/sound/soc/meson/axg-frddr.c index c3ae8ac30745..8ed114de0bdf 100644 --- a/sound/soc/meson/axg-frddr.c +++ b/sound/soc/meson/axg-frddr.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -46,11 +47,28 @@ static int g12a_frddr_dai_prepare(struct snd_pcm_substream *substream, return 0; } +static int axg_frddr_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); + unsigned int period, depth, val; + + period = params_period_bytes(params); + + /* Trim the FIFO depth if the period is small to improve latency */ + depth = min(period, fifo->depth); + val = (depth / AXG_FIFO_BURST) - 1; + regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK, + CTRL1_FRDDR_DEPTH(val)); + + return 0; +} + static int axg_frddr_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); - unsigned int val; int ret; /* Enable pclk to access registers and clock the fifo ip */ @@ -61,11 +79,6 @@ static int axg_frddr_dai_startup(struct snd_pcm_substream *substream, /* Apply single buffer mode to the interface */ regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0); - /* Use all fifo depth */ - val = (fifo->depth / AXG_FIFO_BURST) - 1; - regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK, - CTRL1_FRDDR_DEPTH(val)); - return 0; } @@ -84,6 +97,7 @@ static int axg_frddr_pcm_new(struct snd_soc_pcm_runtime *rtd, } static const struct snd_soc_dai_ops axg_frddr_ops = { + .hw_params = axg_frddr_dai_hw_params, .startup = axg_frddr_dai_startup, .shutdown = axg_frddr_dai_shutdown, };