From patchwork Tue Apr 6 17:40:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 415932 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4783740jai; Tue, 6 Apr 2021 10:45:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwAk/UypDVecVasDo1OHzwolCByI2CbAy9gTmO7R6FXE00fVJSwfIHJIeHUb0yY6ZBt76kH X-Received: by 2002:a05:6e02:1068:: with SMTP id q8mr14107294ilj.175.1617731107819; Tue, 06 Apr 2021 10:45:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617731107; cv=none; d=google.com; s=arc-20160816; b=Em3iP6HmcY4RXeiOQYV/cSNOyQrbIeY3yzbAewZtSOY6wkPTDWlCIpe5E9l6W7NNSQ tPGjt6sI1oXMtCogz3m2LKuCQRR4z1QhF9Y+h2rDBQknpiExyyQ79+CxvWKHRukEcuze 17zBCeYWI+/0Rf8u83kUpVjVw5nxaKr5+hYVimPRyYa+ATKuF830fM6yG3MgpYArmrCN 9628sfUu/yokztpI9BGhi0vCgpo7X0CvUDo6/ZsrGKwKJsp35hZgwRyryT7NHldRcAxV 9k9Qzt/lfE00l+tD7/BuleViw9Ei3dIUriZ9lnOFLkW9LXOda8+WyvUdCm8pKPc4tnPW Inbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=N2mWsQLvcKb8vumKiyJlzF6R6pJ22LkeGfPO+NZbgZA=; b=GEQHq4FqbM1gMaCalYs7Y17wWeF8JedrhXzXsKfPWoF2E3fnEGI0bJ6Mc2pwUhAp3L y81c3wpKnZllOgrXKPZr+aijdlcvKXWKcRZXJS6ElnbqZHetnSKTdEUd3EKKrzxokngK 5r6I/4u/JaFScPs3CeqgzpKxVWLAp2/PVo+vd4dbWm/zKCKxYkpK3YSYYixoPa4RlQKx 2t0PYKyBpgZvzePtNbPd9maqa/l1z54hmJBalVt2uk83jm3Ne5FsPyXhbHvOZ/ZG1sIT lGnKpLUeUxn+/U3CMwoZaEUqsM4B3v0iS+OFIwEKqfPxe/cA5+SmRd7YvDBLd+JdoVAO FLbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IkKFB1mn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e8si18615232ilc.89.2021.04.06.10.45.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Apr 2021 10:45:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IkKFB1mn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56070 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lTplD-0006cg-5x for patch@linaro.org; Tue, 06 Apr 2021 13:45:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45678) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lTpgt-0001ax-0B for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:39 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:39523) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lTpgp-0006Hq-M7 for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:38 -0400 Received: by mail-pj1-x1030.google.com with SMTP id ot17-20020a17090b3b51b0290109c9ac3c34so10054094pjb.4 for ; Tue, 06 Apr 2021 10:40:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N2mWsQLvcKb8vumKiyJlzF6R6pJ22LkeGfPO+NZbgZA=; b=IkKFB1mnYH976x7d57AqzXamfVgFP1B4L2ZY6qM8E+omyZNz4sYzq4hjt5kXWVZJzd 9dXNw2Z1NbYfOkoIjiFpIdr+jAfbMk3nCz9z8XIEJOKF+gmIp4bEswSjBSmAajHo8aik pWd3f2N+AUYqUJrTkV3Z5fBhRkNJ5SEAmTIeS6cp6/WGdxkADzqtFCZIAZ9iDQXEQhFj nZAL2gt+2DHHv+WpKMDmmmVJLdggLfF4S7trJTq6IFEZ/LgGwLfsw4tEhQe0IEr3C6LU /yHG08DPIC3JTxL2vIHswpQDX3kD2fuqTv1lt0qTQLkopaNceHhgVfEG4Wub0wbGc9xL wnlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N2mWsQLvcKb8vumKiyJlzF6R6pJ22LkeGfPO+NZbgZA=; b=pdOk4gq782h/Fi9zNA8XsiXK6XAmpkxn6HJVkbufXcYMKleMguJ0dIBp2XKHhSZlI5 VKD+mxdsGXcYcYdd0DdGQ+R4toBREm5vrgSBZ+bw6AOiZW2sI4UdOhqhtVW6WY/+39o/ /jOshyMSadJFEjUAz4EtaTHo4nXrlFrA5aZVh1+7LYvWy5T29R6f5CnnJfVmrdr3scHX B3sawv0eFfHqhrjW0ezrDxpZEEQbZfu3hDU3ul6amWevgTGAOY2STvQsfEWyMlLD3tEk 5AsnduOh+99sCN0PpYECibvtLs2+Ygr+t9DqdIck9ohrE/VfXwnD6nmAkpwp/KhDBFM1 tT4A== X-Gm-Message-State: AOAM531rC1I+r0l9qvfOyhYp830ejkO/POe/wGUirXY42axEZ27qB6df TvUXYzeUsKyylwUFMa0pHbDrlcUuVQAiUQ== X-Received: by 2002:a17:90a:c28a:: with SMTP id f10mr5667383pjt.15.1617730834303; Tue, 06 Apr 2021 10:40:34 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id h15sm19148056pfo.20.2021.04.06.10.40.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 10:40:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/12] accel/tcg: Preserve PAGE_ANON when changing page permissions Date: Tue, 6 Apr 2021 10:40:20 -0700 Message-Id: <20210406174031.64299-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210406174031.64299-1-richard.henderson@linaro.org> References: <20210406174031.64299-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, Stephen Long Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Using mprotect() to change PROT_* does not change the MAP_ANON previously set with mmap(). Our linux-user version of MTE only works with MAP_ANON pages, so losing PAGE_ANON caused MTE to stop working. Reported-by: Stephen Long Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte.h | 3 ++- accel/tcg/translate-all.c | 9 +++++-- tests/tcg/aarch64/mte-6.c | 43 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 2 +- 4 files changed, 53 insertions(+), 4 deletions(-) create mode 100644 tests/tcg/aarch64/mte-6.c -- 2.25.1 Tested-by: Alex Bennée Reviewed-by: Alex Bennée diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h index 141cef522c..0805676b11 100644 --- a/tests/tcg/aarch64/mte.h +++ b/tests/tcg/aarch64/mte.h @@ -48,7 +48,8 @@ static void enable_mte(int tcf) } } -static void *alloc_mte_mem(size_t size) +static void * alloc_mte_mem(size_t size) __attribute__((unused)); +static void * alloc_mte_mem(size_t size) { void *p = mmap(NULL, size, PROT_READ | PROT_WRITE | PROT_MTE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f32df8b240..ba6ab09790 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2714,6 +2714,8 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) a missing call to h2g_valid. */ assert(end - 1 <= GUEST_ADDR_MAX); assert(start < end); + /* Only set PAGE_ANON with new mappings. */ + assert(!(flags & PAGE_ANON) || (flags & PAGE_RESET)); assert_memory_lock(); start = start & TARGET_PAGE_MASK; @@ -2737,11 +2739,14 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) p->first_tb) { tb_invalidate_phys_page(addr, 0); } - if (reset_target_data && p->target_data) { + if (reset_target_data) { g_free(p->target_data); p->target_data = NULL; + p->flags = flags; + } else { + /* Using mprotect on a page does not change MAP_ANON. */ + p->flags = (p->flags & PAGE_ANON) | flags; } - p->flags = flags; } } diff --git a/tests/tcg/aarch64/mte-6.c b/tests/tcg/aarch64/mte-6.c new file mode 100644 index 0000000000..60d51d18be --- /dev/null +++ b/tests/tcg/aarch64/mte-6.c @@ -0,0 +1,43 @@ +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code == SEGV_MTESERR); + exit(0); +} + +int main(void) +{ + enable_mte(PR_MTE_TCF_SYNC); + + void *brk = sbrk(16); + if (brk == (void *)-1) { + perror("sbrk"); + return 2; + } + + if (mprotect(brk, 16, PROT_READ | PROT_WRITE | PROT_MTE)) { + perror("mprotect"); + return 2; + } + + int *p1, *p2; + long excl = 1; + + asm("irg %0,%1,%2" : "=r"(p1) : "r"(brk), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r"(p1)); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(brk), "r"(excl)); + asm("stg %0,[%0]" : : "r"(p1)); + + *p1 = 0; + + struct sigaction sa; + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction = pass; + sa.sa_flags = SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + *p2 = 0; + + abort(); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 56e48f4b34..05b2622bfc 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -37,7 +37,7 @@ AARCH64_TESTS += bti-2 # MTE Tests ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),) -AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 +AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-6 mte-%: CFLAGS += -march=armv8.5-a+memtag endif From patchwork Tue Apr 6 17:40:21 2021 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id p12si6793098ios.6.2021.04.06.10.43.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Apr 2021 10:43:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="X/xm6Ep5"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lTpjS-0004F5-Sr for patch@linaro.org; Tue, 06 Apr 2021 13:43:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lTpgv-0001fe-H7 for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:41 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:40958) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lTpgr-0006J2-0B for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:41 -0400 Received: by mail-pg1-x534.google.com with SMTP id b17so7244791pgh.7 for ; Tue, 06 Apr 2021 10:40:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fmCgzHtzk5qDGe2eGqNAc4vF9R/bc/UzkhnNYf8s1aw=; b=X/xm6Ep5i+3WG9oCNPKExXqJNHZTZUZo9HQfDwtMnsP5WgJECs90FR9/S1r5qNNJBa lkmwpACXwZHh9u+8vihMS+7CrVNHX/AaEwNjowi0Ka3K0N/8zEgF9JodWqRqp12KziSe rNF9gmmvvvSWjTRAedBDLLZWSDK3icm836KQLBYAYikdK55udG92S1zlmdF65mu1B2yB wdbIUNN+XzcErvMdKLLq0cKb5Q6z1Hx0SiK49Vd7p1Ne9hdAKkUMo/1rVotRYO04Emnt NdIfpdAFmR3JKsveCZJKfN1ZrbAqD0wDgNzRwWtZK28mxQ4AgH7i92yWpDXDXwMYc1BV P4UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fmCgzHtzk5qDGe2eGqNAc4vF9R/bc/UzkhnNYf8s1aw=; b=EbmQLfehi78EnKp0QGf69eLEvthrs5ioGg3Qfa7bbMbHGEJEsW6dIi8VjZFdjneA+u jcWCekL1E1bTME9krQguIBiiuvg3zlVp3/4sdlmn+uHwEi6SbskPhKaP09K5RTmKVjkI nNZ3zoEGF2STuKF4LEYVxv7glHkZIUI2qAePRsVPwmTAWI2m8uhitA5NuzRkRBl0wKh+ 60tHdLyznatuBVuHl/bRqfh9ySElWyL810EdmK9fa37r8QDqvocmsNEobstHAhm7cZJG TSyM7qjrvd8Bn6pY6CL5KlB2LV3jQI+ePNa8sRuGL6fDf6VVeEazvFU9iEqAvY51v3V2 eaKQ== X-Gm-Message-State: AOAM531dUsAJxE2rcJLFJ1CMF9eqp9tOji+kOppEi2hxKu6W6sB5qsAs kpUX8RoCFY9KTlsCYfIGDmqUBZAupxTU6A== X-Received: by 2002:a63:dc43:: with SMTP id f3mr20047475pgj.290.1617730835344; Tue, 06 Apr 2021 10:40:35 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id h15sm19148056pfo.20.2021.04.06.10.40.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 10:40:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/12] target/arm: Check PAGE_WRITE_ORG for MTE writeability Date: Tue, 6 Apr 2021 10:40:21 -0700 Message-Id: <20210406174031.64299-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210406174031.64299-1-richard.henderson@linaro.org> References: <20210406174031.64299-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can remove PAGE_WRITE when (internally) marking a page read-only because it contains translated code. This can be triggered by tests/tcg/aarch64/bti-2, after having serviced SIGILL trampolines on the stack. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 0bbb9ec346..8be17e1b70 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -83,7 +83,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, uint8_t *tags; uintptr_t index; - if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ))) { + if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) { /* SIGSEGV */ arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, ptr_mmu_idx, false, ra); From patchwork Tue Apr 6 17:40:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 415935 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4786069jai; Tue, 6 Apr 2021 10:48:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwsdDhQSeWDfnZqRHWOSEJG5z429l0LCnvCrq/hseBnV8qBy/RTNOsPyRh8ReA6JFwgHrcN X-Received: by 2002:a92:dc05:: with SMTP id t5mr25736766iln.172.1617731324668; Tue, 06 Apr 2021 10:48:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617731324; cv=none; d=google.com; s=arc-20160816; b=oLgGuKStsTH/gFLx0lwJQzMhOyE/Bsemk0sdsuV+yZsbLbN0UW2fEvFrq/sZCxw6tN 6B2EL5GIHa0Vcv01RTDhL+3IIYtg98sU4kfodSJBrMzunacsYtI+M2SfKvTonh5XHjX6 AXLlzhZFlVr2A3NaUBgBkJfVSbOKU5gCuDzQrMqNItGay0g4uQZr/D4xhKpHvvjGbXwa fVcAKNaY9E5HQFlLXwW81rdzSUuD5IZA8UcYzB9BNf8N5QleEc3o1TwXg63a85wKyJPS ptuTYZ5ZyJlfSJng7kXyjJ9xrBLpeYQr2G6UtbOzo/6hdu3525fCTlKL1btKoRixq7Aj p4nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3mgQ/AwHCdEqMYqaEDNteTClCiB0ojdl1YSqbUogses=; b=Q/tHTLtRaKI1bl3ZCMxlrNqxvuJll3MGzNRdH5p0GQdz5TwCrSHZcksLklH7fOlIfQ tOIh3HARJzEGvCR9EdYc7UIdzRKqcIZO1o8n72FHzR3Qpv4SwkzcaWeFzVLojRA4WN6O t1JGZAhDvLwaKx+abJOFEbMdpSd2b0JgWgWQTC7wZkuM5MCYmFRWDmbl/Q79+QodV6TJ KaCP1eOpw9vDvZyuEYrNbpLnh7cdx7INOP3xV0Jlmw4DheF/Ab1kuknTi0viZr18n52F W0vmvqZ+HWcwOrlS+mBDJ25c5b/V87NVHWyDsgZCuVMUd5vMCS3GOfaqsOXQkiVkrpyC fdqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EFdail5Q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a15si20456264iok.43.2021.04.06.10.48.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Apr 2021 10:48:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EFdail5Q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lTpoi-0001YO-3o for patch@linaro.org; Tue, 06 Apr 2021 13:48:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45736) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lTpgu-0001dk-Je for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:40 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:52792) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lTpgs-0006Jc-0a for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:40 -0400 Received: by mail-pj1-x102c.google.com with SMTP id ha17so8331443pjb.2 for ; Tue, 06 Apr 2021 10:40:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3mgQ/AwHCdEqMYqaEDNteTClCiB0ojdl1YSqbUogses=; b=EFdail5Q39YUUjQu5flb2sWdqSnNPtN7VWpuZ3Ao31OyVEdtjKW5InWYnb/KHdW48h PfigFSl7c/1Q6TNHm7s6dDZh8hFaVMydS0LdIWOvNkkt7y5+G2J0lYvSbM70WlUpzvkD cV0uS31wZwF1s8IfUiULKhuIC86oYa8R4JtcLo0U+TNuTiE8m4/13gkH92x6Guv5JZQ6 WjHDtjTzF9fHSKccVlzik0TmqlcgwwFZP9nqcX4nn9A7Kh7P709zR1bqIvtFduv/BmiM v6jRYVBFmPmce4uVGKUFJWdi1qZ3a/FFiade46iINImsxyBBPO1Li4dkTil3HuV0q1a2 +5Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3mgQ/AwHCdEqMYqaEDNteTClCiB0ojdl1YSqbUogses=; b=Zh2vzHT6Nh7IoVksVNpGy+HlwMPnDjkSMdwsli8btCji4vZd7H7cxqa+gK2gwnwxg6 jvUV225Tgd7gytfjtP/92a2y0Bz1aYLmTr6jPWXciYl/FfDXbb8BLOVlDep4whIR5ckk 9opSmPMu9Zt32na6MXJZEXqIh5EHRsDFfkx2Zlsl40TFluPnzRBOeKhGkypJjV9zpAmH ty+Zkga75gJLWQb8vccEWXhtmMv4EwnsiDlfNW8Reb5IbdqtGDiO6EOZ61rqf09lgKQ6 s/p8+EEyO5E7GWL/L16KA4CLpofVqPDHDykItmycVcwnEGB63amKRppKzZT+gbZhJr64 Bqqw== X-Gm-Message-State: AOAM531E2HR5eFlvTp++KxsiUL06hVhKDijNC1/5IvXfDfyRTmVHaXwm gAvSonyJEF+UgOHLLdAQZBXvnuceHz8QCg== X-Received: by 2002:a17:902:b908:b029:e9:4010:7fd3 with SMTP id bf8-20020a170902b908b02900e940107fd3mr3679881plb.55.1617730836381; Tue, 06 Apr 2021 10:40:36 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id h15sm19148056pfo.20.2021.04.06.10.40.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 10:40:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/12] target/arm: Fix mte_checkN Date: Tue, 6 Apr 2021 10:40:22 -0700 Message-Id: <20210406174031.64299-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210406174031.64299-1-richard.henderson@linaro.org> References: <20210406174031.64299-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We were incorrectly assuming that only the first byte of an MTE access is checked against the tags. But per the ARM, unaligned accesses are pre-decomposed into single-byte accesses. So by the time we reach the actual MTE check in the ARM pseudocode, all accesses are aligned. Therefore, the first failure is always either the first byte of the access, or the first byte of the granule. In addition, some of the arithmetic is off for last-first -> count. This does not become directly visible until a later patch that passes single bytes into this function, so ptr == ptr_last. Buglink: https://bugs.launchpad.net/bugs/1921948 Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 38 +++++++++++++++++--------------------- 1 file changed, 17 insertions(+), 21 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 8be17e1b70..c87717127c 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -757,10 +757,10 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra) { int mmu_idx, ptr_tag, bit55; - uint64_t ptr_last, ptr_end, prev_page, next_page; - uint64_t tag_first, tag_end; - uint64_t tag_byte_first, tag_byte_end; - uint32_t esize, total, tag_count, tag_size, n, c; + uint64_t ptr_last, prev_page, next_page; + uint64_t tag_first, tag_last; + uint64_t tag_byte_first, tag_byte_last; + uint32_t total, tag_count, tag_size, n, c; uint8_t *mem1, *mem2; MMUAccessType type; @@ -779,29 +779,27 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD; - esize = FIELD_EX32(desc, MTEDESC, ESIZE); total = FIELD_EX32(desc, MTEDESC, TSIZE); /* Find the addr of the end of the access, and of the last element. */ - ptr_end = ptr + total; - ptr_last = ptr_end - esize; + ptr_last = ptr + total - 1; /* Round the bounds to the tag granule, and compute the number of tags. */ tag_first = QEMU_ALIGN_DOWN(ptr, TAG_GRANULE); - tag_end = QEMU_ALIGN_UP(ptr_last, TAG_GRANULE); - tag_count = (tag_end - tag_first) / TAG_GRANULE; + tag_last = QEMU_ALIGN_DOWN(ptr_last, TAG_GRANULE); + tag_count = ((tag_last - tag_first) / TAG_GRANULE) + 1; /* Round the bounds to twice the tag granule, and compute the bytes. */ tag_byte_first = QEMU_ALIGN_DOWN(ptr, 2 * TAG_GRANULE); - tag_byte_end = QEMU_ALIGN_UP(ptr_last, 2 * TAG_GRANULE); + tag_byte_last = QEMU_ALIGN_DOWN(ptr_last, 2 * TAG_GRANULE); /* Locate the page boundaries. */ prev_page = ptr & TARGET_PAGE_MASK; next_page = prev_page + TARGET_PAGE_SIZE; - if (likely(tag_end - prev_page <= TARGET_PAGE_SIZE)) { + if (likely(tag_last - prev_page <= TARGET_PAGE_SIZE)) { /* Memory access stays on one page. */ - tag_size = (tag_byte_end - tag_byte_first) / (2 * TAG_GRANULE); + tag_size = ((tag_byte_last - tag_byte_first) / (2 * TAG_GRANULE)) + 1; mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, total, MMU_DATA_LOAD, tag_size, ra); if (!mem1) { @@ -815,9 +813,9 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, next_page - ptr, MMU_DATA_LOAD, tag_size, ra); - tag_size = (tag_byte_end - next_page) / (2 * TAG_GRANULE); + tag_size = ((tag_byte_last - next_page) / (2 * TAG_GRANULE)) + 1; mem2 = allocation_tag_mem(env, mmu_idx, next_page, type, - ptr_end - next_page, + ptr_last - next_page + 1, MMU_DATA_LOAD, tag_size, ra); /* @@ -838,15 +836,13 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, } /* - * If we failed, we know which granule. Compute the element that - * is first in that granule, and signal failure on that element. + * If we failed, we know which granule. For the first granule, the + * failure address is @ptr, the first byte accessed. Otherwise the + * failure address is the first byte of the nth granule. */ if (unlikely(n < tag_count)) { - uint64_t fail_ofs; - - fail_ofs = tag_first + n * TAG_GRANULE - ptr; - fail_ofs = ROUND_UP(fail_ofs, esize); - mte_check_fail(env, desc, ptr + fail_ofs, ra); + uint64_t fault = (n == 0 ? ptr : tag_first + n * TAG_GRANULE); + mte_check_fail(env, desc, fault, ra); } done: From patchwork Tue Apr 6 17:40:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 415931 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4782793jai; Tue, 6 Apr 2021 10:43:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz+RwPpSwUP7HAGcFNsWZ/V8ijtIyuWCbD6UVEVx/zfSKQts7bB3C14U76L2VBV2c77R5yv X-Received: by 2002:a02:9718:: with SMTP id x24mr30649580jai.75.1617731021026; Tue, 06 Apr 2021 10:43:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617731021; cv=none; d=google.com; s=arc-20160816; b=pl5KdY2eG/2itW/fnFqqFiF7g2GUmUtGr2eN0yK57DwJHzaGHF3Y88wd2aU99TF4Om ixfkty3NgkoC9ag/XbvY1cUr72SkR/lryfiFR/xuRBBRIToIc7eQ+15sUbi7rsnO3R9J 0c5GKQuYuOyHIpCehOWXifAJ8f6LyFq9+yEFEsQbtGCzU2DIADS90Yuw2x3mXhG4lRuL nGCGqWQOqNW7bozdpGKVL6yRnqCK2Kj1Hl+VgJLyvWRaJEYHBv2UCCz/S0lhe7WjAzYo SJl/SZQL+/YtLwI0jubnbMASAEwmLNJ/q0OVMWe2G4PulbM7Upk3+ybC6OamUTZZGqZg 2HAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YQ1L8vImC9BAqb2R2P9ZLLT4N7NCVNuCBmSGEW3fZ+M=; b=HyI7H9qSWalf7v+hFbQv9YHXo4oLC5npuACFNx2AqS6tX7qLwpXcBGL6SrYvMPGEmD zaEUerlhZlKo9wcZBQfuXSwdoLGnhHUGb9od2sXncSXfdSE72QVgJkINxVJscaKZ6nZp Blk2MSm8wzRnhbQYAMY/+KrqU9Cnd+/+vKD024obSOxGa4gIJGx0b4wnn9wS6ePhzy/F p1cQZ2NDifdqf99FgZYxEndmtLwzY7OETDVXHR7PMfjmGsHXy1yA7bYisn+bXh7wRxNM VCLW144ImyW5b8QGa9iLZU6zR+IB6VGJ3YQI1w/DK5MLPvGVviwTM8W4Zi4+FaXHZvPx W+9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=prMx0V7M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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So far, just use this in mte_checkN itself. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 52 +++++++++++++++++++++++++++++++---------- 1 file changed, 40 insertions(+), 12 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index c87717127c..144bfa4a51 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -753,33 +753,45 @@ static int checkN(uint8_t *mem, int odd, int cmp, int count) return n; } -uint64_t mte_checkN(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra) +/* + * mte_probe_int: + * @env: CPU environment + * @desc: MTEDESC descriptor + * @ptr: virtual address of the base of the access + * @fault: return virtual address of the first check failure + * + * Internal routine for both mte_probe and mte_check. + * Return zero on failure, filling in *fault. + * Return negative on trivial success for tbi disabled. + * Return positive on success with tbi enabled. + */ +static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr, + uintptr_t ra, uint32_t total, uint64_t *fault) { int mmu_idx, ptr_tag, bit55; uint64_t ptr_last, prev_page, next_page; uint64_t tag_first, tag_last; uint64_t tag_byte_first, tag_byte_last; - uint32_t total, tag_count, tag_size, n, c; + uint32_t tag_count, tag_size, n, c; uint8_t *mem1, *mem2; MMUAccessType type; bit55 = extract64(ptr, 55, 1); + *fault = ptr; /* If TBI is disabled, the access is unchecked, and ptr is not dirty. */ if (unlikely(!tbi_check(desc, bit55))) { - return ptr; + return -1; } ptr_tag = allocation_tag_from_addr(ptr); if (tcma_check(desc, bit55, ptr_tag)) { - goto done; + return 1; } mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD; - total = FIELD_EX32(desc, MTEDESC, TSIZE); /* Find the addr of the end of the access, and of the last element. */ ptr_last = ptr + total - 1; @@ -803,7 +815,7 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, total, MMU_DATA_LOAD, tag_size, ra); if (!mem1) { - goto done; + return 1; } /* Perform all of the comparisons. */ n = checkN(mem1, ptr & TAG_GRANULE, ptr_tag, tag_count); @@ -829,23 +841,39 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, } if (n == c) { if (!mem2) { - goto done; + return 1; } n += checkN(mem2, 0, ptr_tag, tag_count - c); } } + if (likely(n == tag_count)) { + return 1; + } + /* * If we failed, we know which granule. For the first granule, the * failure address is @ptr, the first byte accessed. Otherwise the * failure address is the first byte of the nth granule. */ - if (unlikely(n < tag_count)) { - uint64_t fault = (n == 0 ? ptr : tag_first + n * TAG_GRANULE); - mte_check_fail(env, desc, fault, ra); + if (n > 0) { + *fault = tag_first + n * TAG_GRANULE; } + return 0; +} - done: +uint64_t mte_checkN(CPUARMState *env, uint32_t desc, + uint64_t ptr, uintptr_t ra) +{ + uint64_t fault; + uint32_t total = FIELD_EX32(desc, MTEDESC, TSIZE); + int ret = mte_probe_int(env, desc, ptr, ra, total, &fault); + + if (unlikely(ret == 0)) { + mte_check_fail(env, desc, fault, ra); + } else if (ret < 0) { + return ptr; + } return useronly_clean_ptr(ptr); } From patchwork Tue Apr 6 17:40:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 415934 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4785191jai; Tue, 6 Apr 2021 10:47:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw/85c6w2n1gwXz90LuCu3lyxKS/FvCOBVVSo9Y34VeUO2YpxJWCBfePQzK9stviC65F4tF X-Received: by 2002:a6b:650f:: with SMTP id z15mr24477166iob.128.1617731238920; Tue, 06 Apr 2021 10:47:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617731238; cv=none; d=google.com; s=arc-20160816; b=xS1EmBltLJR419dOFYT5Yw8TLmNHYjTvxb3f3GEdAyEkHdOSLYFLURv1RKz0lZbij1 xesDbI646q9tbP+6/Q9brgnaPXANL9y72HGMqJziODICOJj02oHgekcTav8Lt2UeOdLF 5TmFQv9HIGCC/mkkuSLsetZN5+Ycidzg3EIkGC+ddWcszdJ0nzhRQ1DgdkJRHYzEEZ38 eTpyHHbBe6vdNEwrLz7AfKp6VAnMh30efpK+DlkdrlS3IV86SoIenpFK68akd282ay7e Dcm7GkRsC+CE2xz0vHFu58jmQ4Ln0NjkNGDtfxruANapSgRmh5Hbewj3gDS6wXsjF1Vv Nw8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bmRgp+hz0GAy8sBEmRvnPYPMAtwbiJML48v1bJslbg4=; b=WUZ/00Dlz5pRBQgNSDHR0Prp9P8q0S9TbYYwjwgOqpFO7CUO7/HKus/2kkfTaNv9or ZKLq5UlUfkryXern84byEZzfmwaCof3IRmc77MLBWt1rzfMv4/M6Usa5xM06votIpztA rUhmqJg+wjH8Zlhq5p4MdAXmu5W2qj8Q6ik7FV3IvTddG+1+Y5e7M+tsC7YNB2KSirkp 2YH4Ori9NvbQ3LYDlcmakQjeSbAPhg8sZfFYCqw0fdgMepC3BG4k/IMy/ZAxmz9gpTI3 9f1PArq/FoVsAVVKlHSF/zHnmlPbDB6YSdazh17NyErfwrVYWqgKnApms46RfiF7GzmU Va5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O9BipY2W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v6si19603097jas.90.2021.04.06.10.47.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Apr 2021 10:47:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O9BipY2W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lTpnK-00007v-5R for patch@linaro.org; Tue, 06 Apr 2021 13:47:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45824) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lTpgw-0001iB-UJ for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:42 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:39518) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lTpgt-0006L4-W2 for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:42 -0400 Received: by mail-pj1-x102a.google.com with SMTP id ot17-20020a17090b3b51b0290109c9ac3c34so10054206pjb.4 for ; Tue, 06 Apr 2021 10:40:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bmRgp+hz0GAy8sBEmRvnPYPMAtwbiJML48v1bJslbg4=; b=O9BipY2WU4pSGlOlhX/14k5F3S8mHtQQ7IXOFREecGcmHEoViXZCQNOueXwQH9FGWs MQF4gBLIYXgoWsM+BKYf1KGcpmewgOIQB74fn9dwh5sEo9ipr+mejKzzNqE2W2KJ3Yze sOA9swCnbSZIX/sk1VgGIAeQkdFLtMXi9h+7Nwr7RJDMGUO8KsK3jrLmU/qV70qlk/Nj RZCqvg55wrbXAKT2+5WXEYMuIyY6diFG07jpTklBpT+P3/M3iYyQehoWHLWhxhm1kR/L kek7dVAnbuLjkzdRa2xaSMWcDv0HdQdbKPOTn64cEAViuu8gtS3MKcb06ZoLpZG1mUPy vp5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bmRgp+hz0GAy8sBEmRvnPYPMAtwbiJML48v1bJslbg4=; b=EsoWjqw4o8NOoIGLwAf8AgVbYB7YVnumf5Z5iI3LZ4WKeiohHtT2gYLruMweWZBk4m tpph76MSvnMOPvzX9rtfrimlRalKerXxd1A4qfALe0EDXrmKNa8K595Wd2+sjnAicX2W uKtcwsDCjyddxaITNVeTnUoiWUQACvUIPM6ffYz4RGwd3WXRhO5/fu+WWqn5k8zETkZX llgOtuxY9f5CRiQhsIpluy4bJSNHFzSy93D49yK7lz48sLLpcAXTW9sWgWJXSE01R2zn 8P88kE2Y1xbaUkSPqUtFctDYfGDcM3W/1FfyKZjZuvHRaIE8KfrSt1f0eX0WIylYRA+s su9Q== X-Gm-Message-State: AOAM531b1VYbxkV7fn4986+kmLbIUf7BrjopviPyzrLUhmeJ9o8F2Mqa Efk8y2eg+jk/Tm3ir5/CXwUiK9p6kfdU4Q== X-Received: by 2002:a17:90b:e18:: with SMTP id ge24mr5479320pjb.199.1617730838218; Tue, 06 Apr 2021 10:40:38 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id h15sm19148056pfo.20.2021.04.06.10.40.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 10:40:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/12] target/arm: Fix unaligned checks for mte_check1, mte_probe1 Date: Tue, 6 Apr 2021 10:40:24 -0700 Message-Id: <20210406174031.64299-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210406174031.64299-1-richard.henderson@linaro.org> References: <20210406174031.64299-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We were incorrectly assuming that only the first byte of an MTE access is checked against the tags. But per the ARM, unaligned accesses are pre-decomposed into single-byte accesses. So by the time we reach the actual MTE check in the ARM pseudocode, all accesses are aligned. We cannot tell a priori whether or not a given scalar access is aligned, therefore we must at least check. Use mte_probe_int, which is already set up for checking multiple granules. Buglink: https://bugs.launchpad.net/bugs/1921948 Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 109 +++++++++++++--------------------------- 1 file changed, 35 insertions(+), 74 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée Tested-by: Alex Bennée diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 144bfa4a51..619c4b9351 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -617,80 +617,6 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, } } -/* - * Perform an MTE checked access for a single logical or atomic access. - */ -static bool mte_probe1_int(CPUARMState *env, uint32_t desc, uint64_t ptr, - uintptr_t ra, int bit55) -{ - int mem_tag, mmu_idx, ptr_tag, size; - MMUAccessType type; - uint8_t *mem; - - ptr_tag = allocation_tag_from_addr(ptr); - - if (tcma_check(desc, bit55, ptr_tag)) { - return true; - } - - mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); - type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD; - size = FIELD_EX32(desc, MTEDESC, ESIZE); - - mem = allocation_tag_mem(env, mmu_idx, ptr, type, size, - MMU_DATA_LOAD, 1, ra); - if (!mem) { - return true; - } - - mem_tag = load_tag1(ptr, mem); - return ptr_tag == mem_tag; -} - -/* - * No-fault version of mte_check1, to be used by SVE for MemSingleNF. - * Returns false if the access is Checked and the check failed. This - * is only intended to probe the tag -- the validity of the page must - * be checked beforehand. - */ -bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr) -{ - int bit55 = extract64(ptr, 55, 1); - - /* If TBI is disabled, the access is unchecked. */ - if (unlikely(!tbi_check(desc, bit55))) { - return true; - } - - return mte_probe1_int(env, desc, ptr, 0, bit55); -} - -uint64_t mte_check1(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra) -{ - int bit55 = extract64(ptr, 55, 1); - - /* If TBI is disabled, the access is unchecked, and ptr is not dirty. */ - if (unlikely(!tbi_check(desc, bit55))) { - return ptr; - } - - if (unlikely(!mte_probe1_int(env, desc, ptr, ra, bit55))) { - mte_check_fail(env, desc, ptr, ra); - } - - return useronly_clean_ptr(ptr); -} - -uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) -{ - return mte_check1(env, desc, ptr, GETPC()); -} - -/* - * Perform an MTE checked access for multiple logical accesses. - */ - /** * checkN: * @tag: tag memory to test @@ -882,6 +808,41 @@ uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t desc, uint64_t ptr) return mte_checkN(env, desc, ptr, GETPC()); } +uint64_t mte_check1(CPUARMState *env, uint32_t desc, + uint64_t ptr, uintptr_t ra) +{ + uint64_t fault; + uint32_t total = FIELD_EX32(desc, MTEDESC, ESIZE); + int ret = mte_probe_int(env, desc, ptr, ra, total, &fault); + + if (unlikely(ret == 0)) { + mte_check_fail(env, desc, fault, ra); + } else if (ret < 0) { + return ptr; + } + return useronly_clean_ptr(ptr); +} + +uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) +{ + return mte_check1(env, desc, ptr, GETPC()); +} + +/* + * No-fault version of mte_check1, to be used by SVE for MemSingleNF. + * Returns false if the access is Checked and the check failed. This + * is only intended to probe the tag -- the validity of the page must + * be checked beforehand. + */ +bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr) +{ + uint64_t fault; + uint32_t total = FIELD_EX32(desc, MTEDESC, ESIZE); + int ret = mte_probe_int(env, desc, ptr, 0, total, &fault); + + return ret != 0; +} + /* * Perform an MTE checked access for DC_ZVA. */ From patchwork Tue Apr 6 17:40:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 415936 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4786367jai; Tue, 6 Apr 2021 10:49:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxxMdp5qnePZMI8qH9lPmKcGbLdK+J+yommjRanj7pb8p06bz+he6VB9YMr0iG28u0yK7Va X-Received: by 2002:a5d:8788:: with SMTP id f8mr14814028ion.7.1617731348814; Tue, 06 Apr 2021 10:49:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617731348; cv=none; d=google.com; s=arc-20160816; b=UcFP0fgX4LFt7fVzElvewW1mn1Aueb7u13kCA6ujHfxR3fTkNFcEZC4TRhd/YTliUu PO4Mb6qasSsqWfPR7xsM8UXcjeRprTet7H3jtNIfuXf2jWxXGt6XudH64NJtvhl4ufbS aa2e7WsblOpRF85wqft8CANlxP0C3lsC47zeQAwUkg3OQVn2TRnRuvebemXCMkQAJtO6 amwh7sXZ0yhvm3Qe9l/JakarojJioxOHgJJK7QoPvJtIf0cpJ5N9XxkgidVyWUIdlwSU 3vGWeF0nTEG3Tf7dBM+pYVn09TVhQWJvwrJ9e2ITTRURI5H8mKl28zb8Tfv7y2f/i5Su xCXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=w7i6Gze7kec69WvQyswSUuzpscM5477tzDtA09nT/yo=; b=OtBvxVd8XmCZ3oElUDclaVDnfF/kA8/ZVKa4MRlOO4OOH8aRfrMt2Ort0TowlkIcLT 8/11M149bchWBDc5qkuFkHb83rq1UQ+Oy5XmXnJEJCQb7m5A7ZBdocBnsF8MFzIwAlEn 7HPwa8qU0MySxfuP3gtjruox/0xNlFh2JlHun7zRxLxvcg0Y3qSa4tJ2Zx0gHVZTYrYC 4dENlOjVJtq46I772wrYoo3Dq412D2b4+ksEmyqSGF40mKpOLmm/Qywdme0GKnbwLQMc 5OYynkbOigEcqup2oeB6yRGwH/rxXSH05SlEH99A55nQ47/T00ZMWJ/iDufTPZG4OQOF Vy5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K1mDPPAf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 06 Apr 2021 10:40:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/12] test/tcg/aarch64: Add mte-5 Date: Tue, 6 Apr 2021 10:40:25 -0700 Message-Id: <20210406174031.64299-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210406174031.64299-1-richard.henderson@linaro.org> References: <20210406174031.64299-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Buglink: https://bugs.launchpad.net/bugs/1921948 Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte-5.c | 44 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 2 +- 2 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/mte-5.c -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tests/tcg/aarch64/mte-5.c b/tests/tcg/aarch64/mte-5.c new file mode 100644 index 0000000000..6dbd6ab3ea --- /dev/null +++ b/tests/tcg/aarch64/mte-5.c @@ -0,0 +1,44 @@ +/* + * Memory tagging, faulting unaligned access. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code == SEGV_MTESERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + void *p0, *p1, *p2; + long excl = 1; + + enable_mte(PR_MTE_TCF_SYNC); + p0 = alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction = pass; + sa.sa_flags = SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + /* Store store two different tags in sequential granules. */ + asm("stg %0, [%0]" : : "r"(p1)); + asm("stg %0, [%0]" : : "r"(p2 + 16)); + + /* Perform an unaligned load crossing the granules. */ + asm volatile("ldr %0, [%1]" : "=r"(p0) : "r"(p1 + 12)); + abort(); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 05b2622bfc..928357b10a 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -37,7 +37,7 @@ AARCH64_TESTS += bti-2 # MTE Tests ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),) -AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-6 +AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-%: CFLAGS += -march=armv8.5-a+memtag endif From patchwork Tue Apr 6 17:40:26 2021 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id q13si17228763ilv.154.2021.04.06.10.46.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Apr 2021 10:46:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qvjFN2vp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lTpm5-0008DL-Ui for patch@linaro.org; Tue, 06 Apr 2021 13:46:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45896) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lTpgz-0001nN-44 for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:45 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:40936) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lTpgv-0006My-Oa for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:44 -0400 Received: by mail-pl1-x630.google.com with SMTP id h8so7904425plt.7 for ; Tue, 06 Apr 2021 10:40:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZaA3NtLF5Ui7foJuQjgVLcu0S8y+Fhr8vfitmrcwFuI=; b=qvjFN2vpjrKFab1daG84wTGcDW0Xwkl7KxTDer267wj3SZebbxlRyYKGI7xvqDB5Cx xuBj8PTwoOksc2s/NnilR52lNijPe+CIX+Bw8/Pmh2LpxzEQrdQyPTqxZ3LPHvCvvEBE IHjOU08fD8ZFFY5GxqoWXcTRCnkddMwSzT8LMQry6S57qF5hVFDZ0Ny6lNUv+jmALMpN M0dUK60+dqKlccPj8lRYblKwoKxfWQgqXRGNjC9QpLdmEZhK66s2P8HVj0mSiu2H7+YA 0OPtpqe7FeSzT3iHgaBXfebJCbpXO9cYkoh9mBG7Jt09aZjnlm4xxYaeVBOXgGFK8cPD ZGVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZaA3NtLF5Ui7foJuQjgVLcu0S8y+Fhr8vfitmrcwFuI=; b=cNBs/5ADvoY+xXsKhf7015rlZTp2MaWIWnsqpY4GFPMqvvWe0QOAREgBtf0Zil7Whd Xs0NWFGL/BOAwqVvwiqUEidGOp76dh2Gk8uguT8uyT178sOAoCt5F6p5WrODLc8T3hEs yCw2IYkJ8XZKZ6XBIib/4Gmq5758FlVJ7WhcUMlufMHsZBpQCg1XCR0jkADtGgfh3SRA noKzYupUaClNPH4txROIyy/wSjYmcoxwc6s3gzyqIckpjewT6EFqIpzzxH7tpxEMFRiu vGxXNvsnefRvCZqWF9rrJLx+Zz+YL8pSfzB4m86kJk0GsWGgxrJzMDXNbdcyKyuWYHLY taGw== X-Gm-Message-State: AOAM5333xv36Jb27hopE5Z/C0mkVS3uHl0uQjLKc5v5qICDXIcR2YcCu 00biVNZXrJL0iRXvX6XiuOXQioaHNUPK1w== X-Received: by 2002:a17:902:a587:b029:e7:347d:4872 with SMTP id az7-20020a170902a587b02900e7347d4872mr30396100plb.2.1617730840241; Tue, 06 Apr 2021 10:40:40 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id h15sm19148056pfo.20.2021.04.06.10.40.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 10:40:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/12] target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1 Date: Tue, 6 Apr 2021 10:40:26 -0700 Message-Id: <20210406174031.64299-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210406174031.64299-1-richard.henderson@linaro.org> References: <20210406174031.64299-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" After recent changes, mte_checkN does not use ESIZE, and mte_check1 never used TSIZE. We can combine the two into a single field: SIZEM1. Choose to pass size - 1 because size == 0 is never used, our immediate need in mte_probe_int is for the address of the last byte (ptr + size - 1), and since almost all operations are powers of 2, this makes the immediate constant one bit smaller. Signed-off-by: Richard Henderson --- target/arm/internals.h | 4 ++-- target/arm/mte_helper.c | 18 ++++++++---------- target/arm/translate-a64.c | 5 ++--- target/arm/translate-sve.c | 5 ++--- 4 files changed, 14 insertions(+), 18 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/target/arm/internals.h b/target/arm/internals.h index f11bd32696..2c77f2d50f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -26,6 +26,7 @@ #define TARGET_ARM_INTERNALS_H #include "hw/registerfields.h" +#include "tcg/tcg-gvec-desc.h" #include "syndrome.h" /* register banks for CPU modes */ @@ -1142,8 +1143,7 @@ FIELD(MTEDESC, MIDX, 0, 4) FIELD(MTEDESC, TBI, 4, 2) FIELD(MTEDESC, TCMA, 6, 2) FIELD(MTEDESC, WRITE, 8, 1) -FIELD(MTEDESC, ESIZE, 9, 5) -FIELD(MTEDESC, TSIZE, 14, 10) /* mte_checkN only */ +FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr); uint64_t mte_check1(CPUARMState *env, uint32_t desc, diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 619c4b9351..9dfbb14358 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -692,13 +692,13 @@ static int checkN(uint8_t *mem, int odd, int cmp, int count) * Return positive on success with tbi enabled. */ static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr, - uintptr_t ra, uint32_t total, uint64_t *fault) + uintptr_t ra, uint64_t *fault) { int mmu_idx, ptr_tag, bit55; uint64_t ptr_last, prev_page, next_page; uint64_t tag_first, tag_last; uint64_t tag_byte_first, tag_byte_last; - uint32_t tag_count, tag_size, n, c; + uint32_t sizem1, tag_count, tag_size, n, c; uint8_t *mem1, *mem2; MMUAccessType type; @@ -718,9 +718,10 @@ static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr, mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD; + sizem1 = FIELD_EX32(desc, MTEDESC, SIZEM1); /* Find the addr of the end of the access, and of the last element. */ - ptr_last = ptr + total - 1; + ptr_last = ptr + sizem1; /* Round the bounds to the tag granule, and compute the number of tags. */ tag_first = QEMU_ALIGN_DOWN(ptr, TAG_GRANULE); @@ -738,7 +739,7 @@ static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr, if (likely(tag_last - prev_page <= TARGET_PAGE_SIZE)) { /* Memory access stays on one page. */ tag_size = ((tag_byte_last - tag_byte_first) / (2 * TAG_GRANULE)) + 1; - mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, total, + mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, sizem1 + 1, MMU_DATA_LOAD, tag_size, ra); if (!mem1) { return 1; @@ -792,8 +793,7 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra) { uint64_t fault; - uint32_t total = FIELD_EX32(desc, MTEDESC, TSIZE); - int ret = mte_probe_int(env, desc, ptr, ra, total, &fault); + int ret = mte_probe_int(env, desc, ptr, ra, &fault); if (unlikely(ret == 0)) { mte_check_fail(env, desc, fault, ra); @@ -812,8 +812,7 @@ uint64_t mte_check1(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra) { uint64_t fault; - uint32_t total = FIELD_EX32(desc, MTEDESC, ESIZE); - int ret = mte_probe_int(env, desc, ptr, ra, total, &fault); + int ret = mte_probe_int(env, desc, ptr, ra, &fault); if (unlikely(ret == 0)) { mte_check_fail(env, desc, fault, ra); @@ -837,8 +836,7 @@ uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr) { uint64_t fault; - uint32_t total = FIELD_EX32(desc, MTEDESC, ESIZE); - int ret = mte_probe_int(env, desc, ptr, 0, total, &fault); + int ret = mte_probe_int(env, desc, ptr, 0, &fault); return ret != 0; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0b42e53500..3af00ae90e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -272,7 +272,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_size); + desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1); tcg_desc = tcg_const_i32(desc); ret = new_tmp_a64(s); @@ -306,8 +306,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_esize); - desc = FIELD_DP32(desc, MTEDESC, TSIZE, total_size); + desc = FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); tcg_desc = tcg_const_i32(desc); ret = new_tmp_a64(s); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 0eefb61214..5179c1f836 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4509,8 +4509,7 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz); - desc = FIELD_DP32(desc, MTEDESC, TSIZE, mte_n << msz); + desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1); desc <<= SVE_MTEDESC_SHIFT; } else { addr = clean_data_tbi(s, addr); @@ -5189,7 +5188,7 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz); + desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1); desc <<= SVE_MTEDESC_SHIFT; } desc = simd_desc(vsz, vsz, desc | scale); From patchwork Tue Apr 6 17:40:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 415938 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4787587jai; 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Drop mte_check1 and rename mte_checkN to mte_check. Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 3 +-- target/arm/internals.h | 5 +---- target/arm/mte_helper.c | 26 +++----------------------- target/arm/sve_helper.c | 14 +++++++------- target/arm/translate-a64.c | 4 ++-- 5 files changed, 14 insertions(+), 38 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index c139fa81f9..7b706571bb 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -104,8 +104,7 @@ DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) -DEF_HELPER_FLAGS_3(mte_check1, TCG_CALL_NO_WG, i64, env, i32, i64) -DEF_HELPER_FLAGS_3(mte_checkN, TCG_CALL_NO_WG, i64, env, i32, i64) +DEF_HELPER_FLAGS_3(mte_check, TCG_CALL_NO_WG, i64, env, i32, i64) DEF_HELPER_FLAGS_3(mte_check_zva, TCG_CALL_NO_WG, i64, env, i32, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2c77f2d50f..af1db2cd9c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1146,10 +1146,7 @@ FIELD(MTEDESC, WRITE, 8, 1) FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr); -uint64_t mte_check1(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra); -uint64_t mte_checkN(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra); +uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra); static inline int allocation_tag_from_addr(uint64_t ptr) { diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 9dfbb14358..04479f33a1 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -789,8 +789,7 @@ static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr, return 0; } -uint64_t mte_checkN(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra) +uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra) { uint64_t fault; int ret = mte_probe_int(env, desc, ptr, ra, &fault); @@ -803,28 +802,9 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc, return useronly_clean_ptr(ptr); } -uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t desc, uint64_t ptr) +uint64_t HELPER(mte_check)(CPUARMState *env, uint32_t desc, uint64_t ptr) { - return mte_checkN(env, desc, ptr, GETPC()); -} - -uint64_t mte_check1(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra) -{ - uint64_t fault; - int ret = mte_probe_int(env, desc, ptr, ra, &fault); - - if (unlikely(ret == 0)) { - mte_check_fail(env, desc, fault, ra); - } else if (ret < 0) { - return ptr; - } - return useronly_clean_ptr(ptr); -} - -uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) -{ - return mte_check1(env, desc, ptr, GETPC()); + return mte_check(env, desc, ptr, GETPC()); } /* diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index fd6c58f96a..b63ddfc7f9 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4442,7 +4442,7 @@ static void sve_cont_ldst_mte_check1(SVEContLdSt *info, CPUARMState *env, uintptr_t ra) { sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize, - mtedesc, ra, mte_check1); + mtedesc, ra, mte_check); } static void sve_cont_ldst_mte_checkN(SVEContLdSt *info, CPUARMState *env, @@ -4451,7 +4451,7 @@ static void sve_cont_ldst_mte_checkN(SVEContLdSt *info, CPUARMState *env, uintptr_t ra) { sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize, - mtedesc, ra, mte_checkN); + mtedesc, ra, mte_check); } @@ -4826,7 +4826,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, if (fault == FAULT_FIRST) { /* Trapping mte check for the first-fault element. */ if (mtedesc) { - mte_check1(env, mtedesc, addr + mem_off, retaddr); + mte_check(env, mtedesc, addr + mem_off, retaddr); } /* @@ -5373,7 +5373,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, info.attrs, BP_MEM_READ, retaddr); } if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { - mte_check1(env, mtedesc, addr, retaddr); + mte_check(env, mtedesc, addr, retaddr); } host_fn(&scratch, reg_off, info.host); } else { @@ -5386,7 +5386,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, BP_MEM_READ, retaddr); } if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { - mte_check1(env, mtedesc, addr, retaddr); + mte_check(env, mtedesc, addr, retaddr); } tlb_fn(env, &scratch, reg_off, addr, retaddr); } @@ -5552,7 +5552,7 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, */ addr = base + (off_fn(vm, reg_off) << scale); if (mtedesc) { - mte_check1(env, mtedesc, addr, retaddr); + mte_check(env, mtedesc, addr, retaddr); } tlb_fn(env, vd, reg_off, addr, retaddr); @@ -5773,7 +5773,7 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, } if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { - mte_check1(env, mtedesc, addr, retaddr); + mte_check(env, mtedesc, addr, retaddr); } } i += 1; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3af00ae90e..a68d5dd5d1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -276,7 +276,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, tcg_desc = tcg_const_i32(desc); ret = new_tmp_a64(s); - gen_helper_mte_check1(ret, cpu_env, tcg_desc, addr); + gen_helper_mte_check(ret, cpu_env, tcg_desc, addr); tcg_temp_free_i32(tcg_desc); return ret; @@ -310,7 +310,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, tcg_desc = tcg_const_i32(desc); ret = new_tmp_a64(s); - gen_helper_mte_checkN(ret, cpu_env, tcg_desc, addr); + gen_helper_mte_check(ret, cpu_env, tcg_desc, addr); tcg_temp_free_i32(tcg_desc); return ret; From patchwork Tue Apr 6 17:40:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 415937 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4786560jai; Tue, 6 Apr 2021 10:49:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxEeEyGem/98GFMIIg+C5RwstV96/yzxl5GAgCTw1aqdnCuf43dNGNqhba/adjai1qmYAYg X-Received: by 2002:a92:de0c:: with SMTP id x12mr2421385ilm.169.1617731364402; Tue, 06 Apr 2021 10:49:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617731364; cv=none; d=google.com; s=arc-20160816; b=Ue0XDI6iBAisK4E56pFqPonpTIWcqhodxXdPjLWPOOpw0xN0GHqEcT2XCwtrzglwDc cOWZt6StbxMdBU3K67idJjl5P6aYsY7FC+RER5oGMQFr57HA5LHM8zEBba1JlqdAOcPZ bQ58eH9uhWqpqLUbchbfAUOVSP0T9TypqjiQQqeoq5DyN4zoOfSGhFnCsgYZKE1eLcNj v/wTtKCGB4c7uXx6ma1WSS15KiQ9WTtH6gUqPdRMTxqF0FKyX1yJZgwaS2pO14YrMS+G CFRRJciL9BflBi1/SD222KcnljESR2wWtdgnMd73YQPpCzWSSoyjeCglWAEVsv1s8ydG SJiA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id s7si19268913jan.4.2021.04.06.10.49.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Apr 2021 10:49:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XJxzJFhv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lTppL-0002Vz-Rb for patch@linaro.org; Tue, 06 Apr 2021 13:49:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45964) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lTph1-0001sU-D4 for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:47 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:47047) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lTpgx-0006OE-PU for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:47 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d124so2116144pfa.13 for ; Tue, 06 Apr 2021 10:40:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P65R6awgu2+jcma22h8y387cCYyU3w5GvnO8K3vdbOs=; b=XJxzJFhvQ+qKpRYv3+KlnCvl6Zoxf+3xYr/5Q8REfVGnjRYr2f+3LrY/3jYzk1odna bGljYDg5EMIOGXDb8S7bhmDJpNcXdvfsImjH1PdsHDkJYfzQB+CelDx5zvTYvT/Fmf3f B+swJwkbcu5OKUDIy1x7RTTK3YQz2jlqQobG+6yGelybSy0c96Fof7UKmrj6hruxPrRD VYWhqefi/uWBVZo6cg7QEbNFe8qa49N696VitbWU2X4Z2mCjDUFnIBmgKBAYEKpzI+Xl jT0ux+lHLjtGEaowpfP8CwpugHMGyIx0WO+N/AGOJ/BF/1F+WuHy4vNQ2cFKAZcpArMA czQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P65R6awgu2+jcma22h8y387cCYyU3w5GvnO8K3vdbOs=; b=grPlKO3FLoA5XNTswn1zI3Ha7lkupI5BoGhlGc8ntHp/S8FLdIvnObqqPGGiAAs97l 1EBvdH7Y1HfMTZrzv8BVTp8ZF0SPc9OZ1B/CEKq7VEfmrjG9OcCxvZDoKl1kJYKrFwV9 9HwwbA8befSyCuMh+cENsWanJOnvA2kIdycM5s6PB8Gfh6y0bCerGMJMOXeAOW1IlV50 ssIwVY450nM+DJVmeyH3WfANcMkjRj4hVB8w+eTXW0Ks41lbyiSfAc283WlaSiqXi7Le HsdCuefCp9lMOnA4L48vyuj/xbNtYr19qy3rEcvXarm7RQH3C4d460UJx+6KUJdqm3so 2SNg== X-Gm-Message-State: AOAM5310Pqlom0MC32ppBTdRQRiWbK45Y8lyjUb+vcePBHGi3m7zO8rN blB7comWl2hkfhXRcCHkdPhdi3xIFyJSoQ== X-Received: by 2002:a63:703:: with SMTP id 3mr28597454pgh.253.1617730842113; Tue, 06 Apr 2021 10:40:42 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id h15sm19148056pfo.20.2021.04.06.10.40.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 10:40:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/12] target/arm: Rename mte_probe1 to mte_probe Date: Tue, 6 Apr 2021 10:40:28 -0700 Message-Id: <20210406174031.64299-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210406174031.64299-1-richard.henderson@linaro.org> References: <20210406174031.64299-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For consistency with the mte_check1 + mte_checkN merge to mte_check, rename the probe function as well. Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/mte_helper.c | 6 +++--- target/arm/sve_helper.c | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/target/arm/internals.h b/target/arm/internals.h index af1db2cd9c..886db56b58 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1145,7 +1145,7 @@ FIELD(MTEDESC, TCMA, 6, 2) FIELD(MTEDESC, WRITE, 8, 1) FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ -bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr); +bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra); static inline int allocation_tag_from_addr(uint64_t ptr) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 04479f33a1..6ac1d21318 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -121,7 +121,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, * exception for inaccessible pages, and resolves the virtual address * into the softmmu tlb. * - * When RA == 0, this is for mte_probe1. The page is expected to be + * When RA == 0, this is for mte_probe. The page is expected to be * valid. Indicate to probe_access_flags no-fault, then assert that * we received a valid page. */ @@ -808,12 +808,12 @@ uint64_t HELPER(mte_check)(CPUARMState *env, uint32_t desc, uint64_t ptr) } /* - * No-fault version of mte_check1, to be used by SVE for MemSingleNF. + * No-fault version of mte_check, to be used by SVE for MemSingleNF. * Returns false if the access is Checked and the check failed. This * is only intended to probe the tag -- the validity of the page must * be checked beforehand. */ -bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr) +bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr) { uint64_t fault; int ret = mte_probe_int(env, desc, ptr, 0, &fault); diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index b63ddfc7f9..982240d104 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4869,7 +4869,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, /* Watchpoint hit, see below. */ goto do_fault; } - if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) { + if (mtedesc && !mte_probe(env, mtedesc, addr + mem_off)) { goto do_fault; } /* @@ -4919,7 +4919,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, & BP_MEM_READ)) { goto do_fault; } - if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) { + if (mtedesc && !mte_probe(env, mtedesc, addr + mem_off)) { goto do_fault; } host_fn(vd, reg_off, host + mem_off); @@ -5588,7 +5588,7 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, } if (mtedesc && arm_tlb_mte_tagged(&info.attrs) && - !mte_probe1(env, mtedesc, addr)) { + !mte_probe(env, mtedesc, addr)) { goto fault; } From patchwork Tue Apr 6 17:40:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 415929 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4781910jai; Tue, 6 Apr 2021 10:42:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxmbL0XZV9y9yJZlHhLes5ALtJNVATYgXvFuzljHiBycYc8ZAJBALmC1eOTyK4HNE7ErYDA X-Received: by 2002:a05:6e02:4b2:: with SMTP id e18mr9882015ils.251.1617730933381; Tue, 06 Apr 2021 10:42:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617730933; cv=none; d=google.com; s=arc-20160816; b=u9Ey+56gRSjHJkAs0D5baU4zOYSjTIURyAOr2O9hEvj0ErunCsNiawb/JuMrmOwx2T tFWEBLZtE+hj5/muyaro23FVMBE/JmGj7kACiGngGhL09y4IdpvFLSI2YGtEqOnddLFB 9NZCVWEjH+BJpX3hgv8iGCQXVtzNEMAv9wQKbNjHLRmyZXxvQ50UleqZB3qL1azaeqrV ov1cY5s0eHPFt3V+IGOUKWvSHcPPIDjMrSgT23HO/gO3IfINTiSNzdgSOADfSY4JGzyS 0n5F/p2Qb69Iu8YtQ3UkO+CJnnvArwAl6Bf8ysOOSfM28p+4TZGSUMdstwYtaV4Cmbxo o1cQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Xg0dHSSHbNndr4UE+t8eLAkBBwNMOnWRtx1WrZnfz3o=; b=evHl4jQHdAslTf3XS0cufOpR1suV7ES7m8/KLtHKEctj4ZMUM3+iHdZk18E3ZXPAh/ cHpZVpyoihk7XduReOH8sOZKFcKPbJ3zhAp8b52cTSnnV5pQmDXxrPFCZn6owUrLZV3T cOksAijMJZX8jEwmp4xsPTTI6Moy6Va+h2KN9oaqGe8Nyr1vE7A4zYtuhu3XpplKs14L t10FS875oUyhTbyAikzp0hxNoqs6CuL9MyxFZN/I+u9t6GvGpFKYpcP8R15H8nqJxCoD sf8s73+pjzATcHY5kV+huAiHMp1P5p/hABavlh+SOtt9N0JUs8BGnHd/iMzmwOKs0daE eRLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Chjr2TH7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Which means that we can eliminate the function pointer into sve_ldN_r and sve_stN_r, calling sve_cont_ldst_mte_check directly. Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 84 +++++++++++++---------------------------- 1 file changed, 26 insertions(+), 58 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 982240d104..c068dfa0d5 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4382,13 +4382,9 @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, #endif } -typedef uint64_t mte_check_fn(CPUARMState *, uint32_t, uint64_t, uintptr_t); - -static inline QEMU_ALWAYS_INLINE -void sve_cont_ldst_mte_check_int(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, int esize, - int msize, uint32_t mtedesc, uintptr_t ra, - mte_check_fn *check) +static void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, int esize, + int msize, uint32_t mtedesc, uintptr_t ra) { intptr_t mem_off, reg_off, reg_last; @@ -4405,7 +4401,7 @@ void sve_cont_ldst_mte_check_int(SVEContLdSt *info, CPUARMState *env, uint64_t pg = vg[reg_off >> 6]; do { if ((pg >> (reg_off & 63)) & 1) { - check(env, mtedesc, addr, ra); + mte_check(env, mtedesc, addr, ra); } reg_off += esize; mem_off += msize; @@ -4422,7 +4418,7 @@ void sve_cont_ldst_mte_check_int(SVEContLdSt *info, CPUARMState *env, uint64_t pg = vg[reg_off >> 6]; do { if ((pg >> (reg_off & 63)) & 1) { - check(env, mtedesc, addr, ra); + mte_check(env, mtedesc, addr, ra); } reg_off += esize; mem_off += msize; @@ -4431,30 +4427,6 @@ void sve_cont_ldst_mte_check_int(SVEContLdSt *info, CPUARMState *env, } } -typedef void sve_cont_ldst_mte_check_fn(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, - int esize, int msize, uint32_t mtedesc, - uintptr_t ra); - -static void sve_cont_ldst_mte_check1(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, - int esize, int msize, uint32_t mtedesc, - uintptr_t ra) -{ - sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize, - mtedesc, ra, mte_check); -} - -static void sve_cont_ldst_mte_checkN(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, - int esize, int msize, uint32_t mtedesc, - uintptr_t ra) -{ - sve_cont_ldst_mte_check_int(info, env, vg, addr, esize, msize, - mtedesc, ra, mte_check); -} - - /* * Common helper for all contiguous 1,2,3,4-register predicated stores. */ @@ -4463,8 +4435,7 @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr, uint32_t desc, const uintptr_t retaddr, const int esz, const int msz, const int N, uint32_t mtedesc, sve_ldst1_host_fn *host_fn, - sve_ldst1_tlb_fn *tlb_fn, - sve_cont_ldst_mte_check_fn *mte_check_fn) + sve_ldst1_tlb_fn *tlb_fn) { const unsigned rd = simd_data(desc); const intptr_t reg_max = simd_oprsz(desc); @@ -4493,9 +4464,9 @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const target_ulong addr, * Handle mte checks for all active elements. * Since TBI must be set for MTE, !mtedesc => !mte_active. */ - if (mte_check_fn && mtedesc) { - mte_check_fn(&info, env, vg, addr, 1 << esz, N << msz, - mtedesc, retaddr); + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, 1 << esz, N << msz, + mtedesc, retaddr); } flags = info.page[0].flags | info.page[1].flags; @@ -4621,8 +4592,7 @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr, mtedesc = 0; } - sve_ldN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_fn, - N == 1 ? sve_cont_ldst_mte_check1 : sve_cont_ldst_mte_checkN); + sve_ldN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_fn); } #define DO_LD1_1(NAME, ESZ) \ @@ -4630,7 +4600,7 @@ void HELPER(sve_##NAME##_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, 1, 0, \ - sve_##NAME##_host, sve_##NAME##_tlb, NULL); \ + sve_##NAME##_host, sve_##NAME##_tlb); \ } \ void HELPER(sve_##NAME##_r_mte)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ @@ -4644,22 +4614,22 @@ void HELPER(sve_##NAME##_le_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, 0, \ - sve_##NAME##_le_host, sve_##NAME##_le_tlb, NULL); \ + sve_##NAME##_le_host, sve_##NAME##_le_tlb); \ } \ void HELPER(sve_##NAME##_be_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, 0, \ - sve_##NAME##_be_host, sve_##NAME##_be_tlb, NULL); \ + sve_##NAME##_be_host, sve_##NAME##_be_tlb); \ } \ void HELPER(sve_##NAME##_le_r_mte)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ + target_ulong addr, uint32_t desc) \ { \ sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \ sve_##NAME##_le_host, sve_##NAME##_le_tlb); \ } \ void HELPER(sve_##NAME##_be_r_mte)(CPUARMState *env, void *vg, \ - target_ulong addr, uint32_t desc) \ + target_ulong addr, uint32_t desc) \ { \ sve_ldN_r_mte(env, vg, addr, desc, GETPC(), ESZ, MSZ, 1, \ sve_##NAME##_be_host, sve_##NAME##_be_tlb); \ @@ -4693,7 +4663,7 @@ void HELPER(sve_ld##N##bb_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_ldN_r(env, vg, addr, desc, GETPC(), MO_8, MO_8, N, 0, \ - sve_ld1bb_host, sve_ld1bb_tlb, NULL); \ + sve_ld1bb_host, sve_ld1bb_tlb); \ } \ void HELPER(sve_ld##N##bb_r_mte)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ @@ -4707,13 +4677,13 @@ void HELPER(sve_ld##N##SUFF##_le_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, 0, \ - sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb, NULL); \ + sve_ld1##SUFF##_le_host, sve_ld1##SUFF##_le_tlb); \ } \ void HELPER(sve_ld##N##SUFF##_be_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_ldN_r(env, vg, addr, desc, GETPC(), ESZ, ESZ, N, 0, \ - sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb, NULL); \ + sve_ld1##SUFF##_be_host, sve_ld1##SUFF##_be_tlb); \ } \ void HELPER(sve_ld##N##SUFF##_le_r_mte)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ @@ -5090,8 +5060,7 @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, uint32_t desc, const uintptr_t retaddr, const int esz, const int msz, const int N, uint32_t mtedesc, sve_ldst1_host_fn *host_fn, - sve_ldst1_tlb_fn *tlb_fn, - sve_cont_ldst_mte_check_fn *mte_check_fn) + sve_ldst1_tlb_fn *tlb_fn) { const unsigned rd = simd_data(desc); const intptr_t reg_max = simd_oprsz(desc); @@ -5117,9 +5086,9 @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target_ulong addr, * Handle mte checks for all active elements. * Since TBI must be set for MTE, !mtedesc => !mte_active. */ - if (mte_check_fn && mtedesc) { - mte_check_fn(&info, env, vg, addr, 1 << esz, N << msz, - mtedesc, retaddr); + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, 1 << esz, N << msz, + mtedesc, retaddr); } flags = info.page[0].flags | info.page[1].flags; @@ -5233,8 +5202,7 @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr, mtedesc = 0; } - sve_stN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_fn, - N == 1 ? sve_cont_ldst_mte_check1 : sve_cont_ldst_mte_checkN); + sve_stN_r(env, vg, addr, desc, ra, esz, msz, N, mtedesc, host_fn, tlb_fn); } #define DO_STN_1(N, NAME, ESZ) \ @@ -5242,7 +5210,7 @@ void HELPER(sve_st##N##NAME##_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MO_8, N, 0, \ - sve_st1##NAME##_host, sve_st1##NAME##_tlb, NULL); \ + sve_st1##NAME##_host, sve_st1##NAME##_tlb); \ } \ void HELPER(sve_st##N##NAME##_r_mte)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ @@ -5256,13 +5224,13 @@ void HELPER(sve_st##N##NAME##_le_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, 0, \ - sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb, NULL); \ + sve_st1##NAME##_le_host, sve_st1##NAME##_le_tlb); \ } \ void HELPER(sve_st##N##NAME##_be_r)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ { \ sve_stN_r(env, vg, addr, desc, GETPC(), ESZ, MSZ, N, 0, \ - sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb, NULL); \ + sve_st1##NAME##_be_host, sve_st1##NAME##_be_tlb); \ } \ void HELPER(sve_st##N##NAME##_le_r_mte)(CPUARMState *env, void *vg, \ target_ulong addr, uint32_t desc) \ From patchwork Tue Apr 6 17:40:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 415939 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4787723jai; Tue, 6 Apr 2021 10:51:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxDvtKt9v6rRg3JNQFWK1jpqjD6evYgTbkq7S/PsOAnNuW5CepJ4dAr49UGjfX70ifDjLIH X-Received: by 2002:a5d:8f90:: with SMTP id l16mr24935242iol.76.1617731478067; Tue, 06 Apr 2021 10:51:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617731478; cv=none; d=google.com; s=arc-20160816; b=Q4xMlkSfxRgGwdGFhjlvM9Jb+O/GVgGB0IP4l2mz9V4E4WuhYYvDhLpuPLIqDSzctm +cDy1wxeGIbgphvhSfJy2/3LNywZmep6jBjaXpEt3tkdBRRyY708Chgpvyj9sd0m1vrS 0zr5oaKecDGh2FqzeIVtTeGdB7zal2YUAB2X4YY9FnahLhH89/s3nKsxZ2TVMN1Yn+FV pC6fEsfapUDUf4W0WbWBcdlXTRh8Cah9Wr1HEiI3TvI68L3gEfSgnR2NR9LKI3HM2h9D RNYzD9xIk3hmjn8Y99+byE0hXCW1OmZwbFA3o19py/W5fgBtXNvLdhwXVyJOu1nOQd1e 83qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=h30NLvQUFSmWb89iN67sfFCqk9/Ie+AiL5gYJeDwQgI=; b=iH23o0bJHRicROdCFs6dUTXkqj5LMFTTT/KrFdfVD77ptsvEjx6hc6SYKaNybB3PlR s/Se5ltiKTUqnKMSlxpSXjf/Xul9ODy5ktkrtM87GzVr52fe2XMN8s2ixe5jRbTWKzlO TtJVgIdlOotD9WsrA8myWwPDKBbuIoQUX+tIPfW+eMn1AhqghI+y28ng1BjSjRpkpmvf OP3TLniF4xgJ0z/mXB5dzgDxHQTVlAL1FEcUnLjR3GH2+1PXhrvevNqbnEUB4275bwf+ HRvBRLI5SonV685RZEAZ7yi8XxIMb3WIkThSy2dlQoeLv/lTHiehgUy/0uZnrVPhXY3V FVnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y7siJFPq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r14si3487188ilm.23.2021.04.06.10.51.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Apr 2021 10:51:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y7siJFPq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46106 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lTprB-0005mg-FV for patch@linaro.org; Tue, 06 Apr 2021 13:51:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46016) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lTph3-0001wM-0Y for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:49 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:41951) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lTpgz-0006QC-O5 for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:48 -0400 Received: by mail-pg1-x536.google.com with SMTP id f29so8434480pgm.8 for ; Tue, 06 Apr 2021 10:40:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h30NLvQUFSmWb89iN67sfFCqk9/Ie+AiL5gYJeDwQgI=; b=Y7siJFPq8qtozCvxgCYoT+kEVPjekeJ1JjIuCSAxQX22U6IQ8O5IHqMQ0jx7+vPBbA xoBDUdHOV6VTAs08BWneIztMxGy+wm1daTJZw8iNdPSatE12w8B2ntdmKTMAXwnMB4Gf qyXH7VOz6qLRlEQrwV2UhtT3/NXSpQHzsyGpwzA1XYS02X9xdpgANP9qGgRJxzZniLNv q4lK2hCOZJKZRPRWGoWxlKor/bDDGsZuMgMVRw0pyWLoDDEl/JEtsuyG/t7dHNopwFRI knxNb+snK3xek4SURYZ4zgVO8ocsk4MM4UgTbM6lS7quAYyPT+6nO3lkcfkIE0TVXh/E Duug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h30NLvQUFSmWb89iN67sfFCqk9/Ie+AiL5gYJeDwQgI=; b=Ta5X86DWHsG32lIFbBXnStJ/ASdAnloZIJ3fYTQreA0JEQysNmsuKp2LgqN9DAYkfl 1E+xWDTT6HhW4Jx1AqCapZiMZ0L5XNRjyTOz8V+ZR/LpxwGjGG8V3/hwbXd3d5ZgoAup HaLQrzEQsf2U1YdGyxX78Q43XP8wYhnHAg7iJfSvRhbdJg00Z2+qFPpGb8vbVrGCiSGF N/HA3aiinprBo+jfOy/CegltIbrSG8ksdzPV/zxH1mF/qeQLWvJD6xrDiYBJE8joeERr RbBN7YjsEMb0kBeyHEGx9MWdj74SiRKdRLelq/JqRYhkXVTDEdVcLq8Zc6fbISktvvvk uViA== X-Gm-Message-State: AOAM530MSJAGGAL3w5OPnxqifrrQhigdElWUiyqisdX1aK+2+6x4iUAf nNRdXIkFhavmMkKLW+HTqYRFnIbfqy9/Tw== X-Received: by 2002:a63:d309:: with SMTP id b9mr27613922pgg.96.1617730843916; Tue, 06 Apr 2021 10:40:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id h15sm19148056pfo.20.2021.04.06.10.40.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 10:40:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/12] target/arm: Remove log2_esize parameter to gen_mte_checkN Date: Tue, 6 Apr 2021 10:40:30 -0700 Message-Id: <20210406174031.64299-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210406174031.64299-1-richard.henderson@linaro.org> References: <20210406174031.64299-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The log2_esize parameter is not used except trivially. Drop the parameter and the deferral to gen_mte_check1. This fixes a bug in that the parameters as documented in the header file were the reverse from those in the implementation. Which meant that translate-sve.c was passing the parameters in the wrong order. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 2 +- target/arm/translate-a64.c | 15 +++++++-------- target/arm/translate-sve.c | 4 ++-- 3 files changed, 10 insertions(+), 11 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 3668b671dd..868d355048 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -44,7 +44,7 @@ TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, - bool tag_checked, int count, int log2_esize); + bool tag_checked, int size); /* We should have at some point before trying to access an FP register * done the necessary access check, so assert that diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a68d5dd5d1..f35a5e8174 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -295,9 +295,9 @@ TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, * For MTE, check multiple logical sequential accesses. */ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, - bool tag_checked, int log2_esize, int total_size) + bool tag_checked, int size) { - if (tag_checked && s->mte_active[0] && total_size != (1 << log2_esize)) { + if (tag_checked && s->mte_active[0]) { TCGv_i32 tcg_desc; TCGv_i64 ret; int desc = 0; @@ -306,7 +306,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc = FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); + desc = FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1); tcg_desc = tcg_const_i32(desc); ret = new_tmp_a64(s); @@ -315,7 +315,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, return ret; } - return gen_mte_check1(s, addr, is_write, tag_checked, log2_esize); + return clean_data_tbi(s, addr); } typedef struct DisasCompare64 { @@ -2965,8 +2965,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) } clean_addr = gen_mte_checkN(s, dirty_addr, !is_load, - (wback || rn != 31) && !set_tag, - size, 2 << size); + (wback || rn != 31) && !set_tag, 2 << size); if (is_vector) { if (is_load) { @@ -3713,7 +3712,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) * promote consecutive little-endian elements below. */ clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31, - size, total); + total); /* * Consecutive little-endian elements from a single register @@ -3866,7 +3865,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) tcg_rn = cpu_reg_sp(s, rn); clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31, - scale, total); + total); tcg_ebytes = tcg_const_i64(1 << scale); for (xs = 0; xs < selem; xs++) { diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 5179c1f836..584c4d047c 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4264,7 +4264,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) dirty_addr = tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); - clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len, MO_8); + clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len); tcg_temp_free_i64(dirty_addr); /* @@ -4352,7 +4352,7 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) dirty_addr = tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); - clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len, MO_8); + clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len); tcg_temp_free_i64(dirty_addr); /* Note that unpredicated load/store of vector/predicate registers From patchwork Tue Apr 6 17:40:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 415940 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4789957jai; Tue, 6 Apr 2021 10:54:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzADSD5dzfmmKVR0UUYqtjDa5WdOHDd9YaJHx036/shwZpSTiF27PHK4bG11wuwv9GUPh/p X-Received: by 2002:a05:6602:2e82:: with SMTP id m2mr24559895iow.70.1617731670512; Tue, 06 Apr 2021 10:54:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617731670; cv=none; d=google.com; s=arc-20160816; b=U7n5SjstNgQ/cHqpLj79h7wYniDJ7N/SQv/1GdlExaMlskDZTxyW+tf0s4sQBK+/u3 vYGcDuV9OhYKTrhE9WC0M1ehMIdULABx82WEXjpjydjJ90vQ3dZVccfOmzhfHnka8fvu +lC52SnZwOIqb8lZcev+2gjfRPTZxLhQV7Nbd6ar5B14qnioU4ZQdgmIKsr/PgUGWAFR QloGvv5kPoN1hSonFEMNPBcEFQbtt27hIAxD7zonOpmj8ljEturIFwjt94EX6wXngrS7 voKJzHr3M1bFXZITdOHvoujzzgqjP9h/IeiJBJPtE1HhCIiT2qstqUqk06E+PJniIbZ3 k4mA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id m11si19101181ilu.158.2021.04.06.10.54.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Apr 2021 10:54:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ca6yD3Kd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53486 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lTpuH-0000NI-Dw for patch@linaro.org; Tue, 06 Apr 2021 13:54:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46040) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lTph4-0001z1-15 for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:50 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:47096) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lTph0-0006Rf-NN for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:49 -0400 Received: by mail-pj1-x1032.google.com with SMTP id q6-20020a17090a4306b02900c42a012202so8031292pjg.5 for ; Tue, 06 Apr 2021 10:40:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KoBTGUZmyMctY5haXIfN8TiPwOcc2SyNXLP6NLjWLR4=; b=ca6yD3KdlP5KFU0u/1D3iFM2QN7G3MjvEwrFRF8iha8PtBfAge2O/p93CLrpXj0eZk egGV14FHEq/Mkd4A8xss3iig3FBbSS+PURlN5U2fPFgUq6XzlVjhNZlwHlnARPhZURyG w3lDdmjnzIxS1Y39bPn0ILIqE7PXpmIyh6RISEgMJ1CHijW91Su/UxLAoY/Ij6pp7qRe HQ7eyEqa018XdG8x1fLe/nN2qlZ00zAJQMQguEfwit65bbW3bN5CyY4h8PKXGAwTK5ul yUqQ5LKIuNkYFQPjXF7uzBC2AwtYTUcMbcgoYhlMs2g9oJ8GRRv9Df027x95BpTzGPkR YLKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KoBTGUZmyMctY5haXIfN8TiPwOcc2SyNXLP6NLjWLR4=; b=ojRuPosPon49XucMgK0fKpDZk5ZgKP4FCkIru68LsgBsNvCtu/FOR8BWOGya+C9r5e NUuCMim/cavTMdaRTiVNK967tcE9e5TSMrHwO6+8WuORIzG5C7nIq2Pae8pxBw1m7diS uvOCk/lF1z7GaneZgyxcHEUCINxz44DGOOXtBOWANPTAYA27aNFc36hFtVQfMyzg0Ewx bDb2GF/YHXARAytHjMaKGAG7dHgE8BpVnOnJ84nRVIEwdTkXFC68wtl0uvKOy79hBzOk v+EbG3GVr13EqM3dG0Q8qlKqUDixhlfUW+OmT/hcfqwd8jZtS3mhLZvxlkKg1OXlmhn2 ZbVw== X-Gm-Message-State: AOAM531ppcX5oMlg67P1b2DlPYmJ03/a8snA3WEQtkoZBDISNv9en2mR uURpFfKKJT1EykgZdJ7ulCB9nos1m6D1kA== X-Received: by 2002:a17:903:2306:b029:e7:1c8d:63fc with SMTP id d6-20020a1709032306b02900e71c8d63fcmr30115307plh.35.1617730845171; Tue, 06 Apr 2021 10:40:45 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id h15sm19148056pfo.20.2021.04.06.10.40.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 10:40:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/12] exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 Date: Tue, 6 Apr 2021 10:40:31 -0700 Message-Id: <20210406174031.64299-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210406174031.64299-1-richard.henderson@linaro.org> References: <20210406174031.64299-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Unfortuately, the elements of PAGE_* were not in numerical order and so PAGE_ANON was added to an "unused" bit. As an arbitrary choice, move PAGE_TARGET_{1,2} together. Cc: Laurent Vivier Fixes: 26bab757d41b ("linux-user: Introduce PAGE_ANON") Buglink: https://bugs.launchpad.net/bugs/1922617 Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Laurent Vivier Tested-by: Laurent Vivier Reviewed-by: Alex Bennée Tested-by: Nathan Chancellor diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index d76b0b9e02..32cfb634c6 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -268,8 +268,8 @@ extern intptr_t qemu_host_page_mask; #define PAGE_RESERVED 0x0100 #endif /* Target-specific bits that will be used via page_get_flags(). */ -#define PAGE_TARGET_1 0x0080 -#define PAGE_TARGET_2 0x0200 +#define PAGE_TARGET_1 0x0200 +#define PAGE_TARGET_2 0x0400 #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f);