From patchwork Mon Apr 5 16:43:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 415299 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3823345jai; Mon, 5 Apr 2021 09:43:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzJlDx9z2T1EgE6crIZtIcdLHGwfinNqlAFYUsbA4udWePT/tLn/TbqoECU+tZQoaTwEbSK X-Received: by 2002:a05:6402:4244:: with SMTP id g4mr32351152edb.204.1617641037830; Mon, 05 Apr 2021 09:43:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617641037; cv=none; d=google.com; s=arc-20160816; b=aV2A3zUHYvAfbg10zRrMol1aTO15LRGN7UBz0DRV2hPx12sikpY9mQ3mCx9c4/ewKg AJxilbjzDumdUaBZQWIMwnqw0Jt9Ft6Z36hoAH3qmMtXju3Bksm44jmAD1KevRSdUjTh DtWlHoI9R9r1hNdvn5tmLIYi8BqTZiuAH3U1lqUHoSskYX/OvCKlU9wM4hSY0K8GZh6g De1ZVHiy7Lo0OH1ZxIfmBthOmfWxplnHqGYtmYzD7rMFVM03cxc3CdAEopgoDpc03vcH TINhMKiy4qFB0EtR9TyCfv18lY9RfvVn0x8/5mWxdaGzp+3u5CdI+JS+Z16q4iSipQFV BMzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=qfn6jGon0qgqmtb6d35dtBsvCJnPVPOaTPqplESd+iY=; b=el3ac1Vl22QMNKZcxgyp7ZHFrE58HybhzP/ZqS6NVHscmOJ530JdfEbHcIjOY+Xxg3 TPTlVoxGB/ACxQRjbMiYcuRjJJVYJg1UpSfPZBWH+5s8ywDfKrnYn9obCAc2BLFwfoXs RI3lv/Hh5tCxweplWNynq2jcuvpYIGPOxqHjgOg3FRmYWPETa+YvQDth0dBfJ2uUqYbJ gwWeLwvakZG5hpxBU1l+n0EteqAkLUHwuq1noMcxMYUm/pPbdXqxdqDN1Tbz/Ac4lRDh QQ23ZXAb01a6bHm48JnGkDsvRsxAsDUMpkUiqdkM36lD1GEnhIF65HuXAebteYsiUHfD qB2Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y23si13460141ejp.249.2021.04.05.09.43.57; Mon, 05 Apr 2021 09:43:57 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242614AbhDEQoA (ORCPT + 6 others); Mon, 5 Apr 2021 12:44:00 -0400 Received: from foss.arm.com ([217.140.110.172]:56070 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242605AbhDEQn7 (ORCPT ); Mon, 5 Apr 2021 12:43:59 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3EC8731B; Mon, 5 Apr 2021 09:43:53 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7786F3F694; Mon, 5 Apr 2021 09:43:51 -0700 (PDT) From: Suzuki K Poulose To: maz@kernel.org, mathieu.poirier@linaro.org Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, anshuman.khandual@arm.com, mike.leach@linaro.org, catalin.marinas@arm.com, will@kernel.org, peterz@infradead.org, leo.yan@linaro.org, robh@kernel.org, Suzuki K Poulose , devicetree@vger.kernel.org Subject: [PATCH v6 14/20] dts: bindings: Document device tree bindings for ETE Date: Mon, 5 Apr 2021 17:43:01 +0100 Message-Id: <20210405164307.1720226-15-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20210405164307.1720226-1-suzuki.poulose@arm.com> References: <20210405164307.1720226-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the device tree bindings for Embedded Trace Extensions. ETE can be connected to legacy coresight components and thus could optionally contain a connection graph as described by the CoreSight bindings. Cc: devicetree@vger.kernel.org Cc: Mathieu Poirier Cc: Mike Leach Reviewed-by: Rob Herring Signed-off-by: Suzuki K Poulose --- .../devicetree/bindings/arm/ete.yaml | 75 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/ete.yaml -- 2.24.1 diff --git a/Documentation/devicetree/bindings/arm/ete.yaml b/Documentation/devicetree/bindings/arm/ete.yaml new file mode 100644 index 000000000000..7f9b2d1e1147 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ete.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright 2021, Arm Ltd +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/ete.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ARM Embedded Trace Extensions + +maintainers: + - Suzuki K Poulose + - Mathieu Poirier + +description: | + Arm Embedded Trace Extension(ETE) is a per CPU trace component that + allows tracing the CPU execution. It overlaps with the CoreSight ETMv4 + architecture and has extended support for future architecture changes. + The trace generated by the ETE could be stored via legacy CoreSight + components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer + Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to + legacy CoreSight components, a node must be listed per instance, along + with any optional connection graph as per the coresight bindings. + See bindings/arm/coresight.txt. + +properties: + $nodename: + pattern: "^ete([0-9a-f]+)$" + compatible: + items: + - const: arm,embedded-trace-extension + + cpu: + description: | + Handle to the cpu this ETE is bound to. + $ref: /schemas/types.yaml#/definitions/phandle + + out-ports: + description: | + Output connections from the ETE to legacy CoreSight trace bus. + $ref: /schemas/graph.yaml#/properties/ports + properties: + port: + description: Output connection from the ETE to legacy CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - cpu + +additionalProperties: false + +examples: + +# An ETE node without legacy CoreSight connections + - | + ete0 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu_0>; + }; +# An ETE node with legacy CoreSight connections + - | + ete1 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu_1>; + + out-ports { /* legacy coresight connection */ + port { + ete1_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index aa84121c5611..2a20a36c724a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1761,6 +1761,7 @@ F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt F: Documentation/devicetree/bindings/arm/coresight-cti.yaml F: Documentation/devicetree/bindings/arm/coresight.txt +F: Documentation/devicetree/bindings/arm/ete.yaml F: Documentation/trace/coresight/* F: drivers/hwtracing/coresight/* F: include/dt-bindings/arm/coresight-cti-dt.h From patchwork Mon Apr 5 16:43:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 415300 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3823489jai; Mon, 5 Apr 2021 09:44:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzqv7yK8XVn8f8sjuflW6M1RlaxIyxSpyqr/fV3IN6ysDy4uMgitcoa+aRQXaEsjISBbw2O X-Received: by 2002:a17:906:f8d7:: with SMTP id lh23mr3089293ejb.457.1617641051030; Mon, 05 Apr 2021 09:44:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617641051; cv=none; d=google.com; s=arc-20160816; b=hasJq4OAshHKAvHz7oN+Hj9usgm2fItaYcukOSGkRalAjU8c5va1VsfY6k5S6m5+i1 Nl/bGkpQ6PTUg1KWx/nwD1LKAJjV9l40RUi6atlelJ5ExiI46UOQIHz/KdJGHCSehCLA ke55+cyzZTPQOsTLXJ96t2gLzcRT3e074ZMcTO/up5FPkF/BzBFrkCQv+UJ4SVR5f0Ew BSfGdCv/3123aXdODad+KWu+5/wSItZw0+MbsSD/PDuattEMyDxRQgINPUpgAwrHpHjb 2h32R3NwG4yQXuLgdaPyMqLigMHuzVNaXxn5LBd7B29OuaOkAVEJlEJ0qJLgCsJweIla DMgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=kqhALUxnpP/n7ulpaXSXuKkFrGWB006/qf/mTyaVpCE=; b=QX7+bFit5aw7lWvyAy2d7rR1iIqG9MmvJmhrJDMSN2tcgPJrMWr3bmUX0l4zj9HPaX QUUvMoT7iwVaE1g0lxAqrO1RDh6bqeoND6ifiZRBTFANykfnfsy1Q7LRus/w0nmRx2p7 N4P2hKYIM7SLRmhY9PMFqY9kLScZWvCWeAjzc34l9+asn8kLKLuu6hN+vsZ2Ie5m0Pty WYJnRz3mdYe2nheD/twiQZHGHbrYm1B9U4Y8hKRxCS1CNDS7pqBpczaJ9f/ucX+tgjqf kVwszCAxKV//fKoTYaFHj+zKfe8oaW/+ukECPWpSwTakuPWykTluGim1j6d79H4rK3o6 o6bw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y23si13460141ejp.249.2021.04.05.09.44.10; Mon, 05 Apr 2021 09:44:11 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242616AbhDEQoO (ORCPT + 6 others); Mon, 5 Apr 2021 12:44:14 -0400 Received: from foss.arm.com ([217.140.110.172]:56150 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242697AbhDEQoL (ORCPT ); Mon, 5 Apr 2021 12:44:11 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 164AA31B; Mon, 5 Apr 2021 09:44:05 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4CE523F694; Mon, 5 Apr 2021 09:44:03 -0700 (PDT) From: Suzuki K Poulose To: maz@kernel.org, mathieu.poirier@linaro.org Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, anshuman.khandual@arm.com, mike.leach@linaro.org, catalin.marinas@arm.com, will@kernel.org, peterz@infradead.org, leo.yan@linaro.org, robh@kernel.org, Suzuki K Poulose , devicetree@vger.kernel.org Subject: [PATCH v6 20/20] dts: bindings: Document device tree bindings for Arm TRBE Date: Mon, 5 Apr 2021 17:43:07 +0100 Message-Id: <20210405164307.1720226-21-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20210405164307.1720226-1-suzuki.poulose@arm.com> References: <20210405164307.1720226-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the device tree bindings for Trace Buffer Extension (TRBE). Cc: Anshuman Khandual Cc: Mathieu Poirier Cc: Rob Herring Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Suzuki K Poulose --- .../devicetree/bindings/arm/trbe.yaml | 49 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/trbe.yaml -- 2.24.1 diff --git a/Documentation/devicetree/bindings/arm/trbe.yaml b/Documentation/devicetree/bindings/arm/trbe.yaml new file mode 100644 index 000000000000..4402d7bfd1fc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/trbe.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright 2021, Arm Ltd +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/trbe.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ARM Trace Buffer Extensions + +maintainers: + - Anshuman Khandual + +description: | + Arm Trace Buffer Extension (TRBE) is a per CPU component + for storing trace generated on the CPU to memory. It is + accessed via CPU system registers. The software can verify + if it is permitted to use the component by checking the + TRBIDR register. + +properties: + $nodename: + const: "trbe" + compatible: + items: + - const: arm,trace-buffer-extension + + interrupts: + description: | + Exactly 1 PPI must be listed. For heterogeneous systems where + TRBE is only supported on a subset of the CPUs, please consult + the arm,gic-v3 binding for details on describing a PPI partition. + maxItems: 1 + +required: + - compatible + - interrupts + +additionalProperties: false + +examples: + + - | + #include + + trbe { + compatible = "arm,trace-buffer-extension"; + interrupts = ; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 2a20a36c724a..471d04bb2d5e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1762,6 +1762,7 @@ F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt F: Documentation/devicetree/bindings/arm/coresight-cti.yaml F: Documentation/devicetree/bindings/arm/coresight.txt F: Documentation/devicetree/bindings/arm/ete.yaml +F: Documentation/devicetree/bindings/arm/trbe.yaml F: Documentation/trace/coresight/* F: drivers/hwtracing/coresight/* F: include/dt-bindings/arm/coresight-cti-dt.h