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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:05 -0500 Message-Id: <20180527141324.11937-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 01/20] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These values are unused. Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stafford Horne diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index e7c96ca990..f4f2f37e28 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -41,9 +41,7 @@ ## __VA_ARGS__) /* is_jmp field values */ -#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ -#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ typedef struct DisasContext { DisasContextBase base; @@ -1467,8 +1465,6 @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) gen_goto_tb(dc, 0, dc->base.pc_next); break; case DISAS_NORETURN: - case DISAS_JUMP: - case DISAS_TB_JUMP: break; case DISAS_UPDATE: /* indicate that the hash table must be used From patchwork Sun May 27 14:13:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137009 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1783428lji; Sun, 27 May 2018 07:14:05 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIgAjvz0vqFjIof4+AMV2zCUr05wnw3prSl1kjhlOAv0kIDx9VbYuSJxxZ0q8jWjbkNfcbZ X-Received: by 2002:ac8:534b:: with SMTP id d11-v6mr9234111qto.141.1527430445748; Sun, 27 May 2018 07:14:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527430445; cv=none; d=google.com; s=arc-20160816; b=FKQru9T3NvxWdt3Ca23KeLGX+RlxTokUSP6PeLsr4Nku+HhpC6aS/AdG4dJmiIOhJg 0OC6Qx/lYL/bungSCZmiC/3LCrJGZXKBGWnw1+aaAOPqUXdu5Rw76EH97NcSzYJdOCSx cHRh1Mhab6Xl6ftsHWGvTB4+Z2/76fAOAJJFqfjCGLGL6xHV45yv9xv0X8a6Fy4ZIoxu HERFmIANSsMUxv+eIF9LoUEUtT11jRsh5tL+tOQFCxwBOkdoM6rqdC70KkeEq8AhMC5x trZ7jurZrrUHGYHJNnUW5SNDBCnCpaBBtoJzi4Wbn1s5awI5GR7OvDAKCXdEZga6JUrx 1sCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=v5a5CtWLlrTHKhlg23p0wCWnGJn/uksZC6j3BEgsUGQ=; b=QaH3iU+QB7Pv3IKikW0HNvcUnRtg9MvyfI+XW0JtB9oMYvzqSd6tz5lmmKWcJqy12c j9aPDNvf+xfzYaw3TKLNvy85rMtOPkR/jdxblHt6xZ3Y09KmVr9xygehV18GDshaAHZj WEN5lpbJ3pFRhL19puqqv6+SvIpvWfc4q2Wr6VyxjGUG1hhdUSQpoVZmo/8R/3FyXIF2 vC9dS5e40S9s291CVAkRcxCHH5Et2M7UvrWK5666n0T+aTFlBMHrXIlwcmSbr7zecjuw 5CBV4BEvUfiBdSAJW7Z/+YTrZM1KC34JfBLqdsNdtOOAbxD/5VqkHuyQBjRGVeqqYbUp Lhlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AFTgsBhx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:06 -0500 Message-Id: <20180527141324.11937-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH 02/20] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" No need to use the interrupt mechanisms when we can simply exit the tb directly. Signed-off-by: Richard Henderson --- target/openrisc/interrupt_helper.c | 3 +-- target/openrisc/translate.c | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) -- 2.17.0 Reviewed-by: Stafford Horne diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c index 56620e0571..b865738f8b 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -26,7 +26,6 @@ void HELPER(rfe)(CPUOpenRISCState *env) { OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - CPUState *cs = CPU(cpu); #ifndef CONFIG_USER_ONLY int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); @@ -53,8 +52,8 @@ void HELPER(rfe)(CPUOpenRISCState *env) } if (need_flush_tlb) { + CPUState *cs = CPU(cpu); tlb_flush(cs); } #endif - cs->interrupt_request |= CPU_INTERRUPT_EXITTB; } diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index f4f2f37e28..dae673afa4 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -41,6 +41,7 @@ ## __VA_ARGS__) /* is_jmp field values */ +#define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ typedef struct DisasContext { @@ -1233,7 +1234,7 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn) gen_illegal_exception(dc); } else { gen_helper_rfe(cpu_env); - dc->base.is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_EXIT; } #endif return true; @@ -1467,8 +1468,7 @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_NORETURN: break; case DISAS_UPDATE: - /* indicate that the hash table must be used - to find the next TB */ + case DISAS_EXIT: tcg_gen_exit_tb(0); break; default: From patchwork Sun May 27 14:13:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137016 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1788465lji; Sun, 27 May 2018 07:20:19 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIxiiqhSbKjyFtY+HdkM2YG1olYj+NNF6X9IPkemrd48FKx12bmEKzEV2kzyYLP9PRa13MT X-Received: by 2002:a0c:81e1:: with SMTP id 30-v6mr9030217qve.187.1527430819502; Sun, 27 May 2018 07:20:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527430819; cv=none; d=google.com; s=arc-20160816; b=qcdfhZz9nd7rCzBr0RqT39F/OB7DiZIyjn9NYrEY7LNdc71wWaHgxP/RjRXyoEKA5O p1dhxseZY51aacAsGc+V6JbL7h0H44cRVTdN0z0/hV9uWIebkKYVHUpG/D/t/rmgpffM kG+k8MXvSyLigUfVIdtlu01/shnCOSdVCnOc7SYEhiZjDIxWgatEHRndnzM2OuwcKEcz PDOEhPzlo2YC731T+BZARt//ZcaLt4dIhHe/aGInM34V4OUGraQQXgPFi7GKY8SP2OUD aPDo2aB2dspRLqsjI4rd76DxPcll6Sf9JPihOnJpC0NsbMzpcrBnZxEuWgKGV9xtNKcr BFXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=r57v6jrRbtE42Q+OBojj/J0UuniCJHknBOwTp86sJ0c=; b=jeWAMs/ChXbDcUc/JSr0z7Bj2nRenZfgNG3oA5sXMfayj9p61V4tHJCSpxen8i3Gw/ M/LaQA0L3NmH2OL5oaZ4zhBIts3Z8E7cZHPEf0FoU+4Kjiiolsbm9zQgTp6uMAznz5AA xBJVgPIA8+CuERaxsAqRr0EauH+1YYDfgFOBoxeljxEcgCdZcJj3iOV+5Ki8+ReOgTmq O7+lt11NN276WaOEhatQn1kRq2CB43FZDSkdhG2S+dzP1vEwhljehK3N4L5UXZESwAGp OJ348H1A66wZOaEXpx1CDq4JdKP2Ffmhm+8Ae9/V7TKT0dunnIXWMFXzD0zHzTAes6L9 jT8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=D5LGFh8X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:07 -0500 Message-Id: <20180527141324.11937-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22c Subject: [Qemu-devel] [PATCH 03/20] target/openrisc: Fix singlestep_enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We failed to store to cpu_pc before raising the exception, which caused us to re-execute the same insn that we stepped. Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) -- 2.17.0 Reviewed-by: Stafford Horne diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index dae673afa4..e566be6d3c 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1449,31 +1449,30 @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); + /* If we have already exited the TB, nothing following has effect. */ + if (dc->base.is_jmp == DISAS_NORETURN) { + return; + } + if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) { tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0); } tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4); - if (dc->base.is_jmp == DISAS_NEXT) { - dc->base.is_jmp = DISAS_UPDATE; - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - } - if (unlikely(dc->base.singlestep_enabled)) { - gen_exception(dc, EXCP_DEBUG); - } else { - switch (dc->base.is_jmp) { - case DISAS_TOO_MANY: - gen_goto_tb(dc, 0, dc->base.pc_next); - break; - case DISAS_NORETURN: - break; - case DISAS_UPDATE: - case DISAS_EXIT: + switch (dc->base.is_jmp) { + case DISAS_TOO_MANY: + gen_goto_tb(dc, 0, dc->base.pc_next); + break; + case DISAS_UPDATE: + case DISAS_EXIT: + if (unlikely(dc->base.singlestep_enabled)) { + gen_exception(dc, EXCP_DEBUG); + } else { tcg_gen_exit_tb(0); - break; - default: - g_assert_not_reached(); } + break; + default: + g_assert_not_reached(); } } From patchwork Sun May 27 14:13:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137015 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1788437lji; Sun, 27 May 2018 07:20:17 -0700 (PDT) X-Google-Smtp-Source: ADUXVKICi4iL2TJE8gOa0Rc1eKle9vI8EJqxgEsdn6nNSCjuuSBLV5VZW/RIPMEkj/DRu/8nhGuU X-Received: by 2002:ac8:2acc:: with SMTP id c12-v6mr8897719qta.389.1527430817656; Sun, 27 May 2018 07:20:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527430817; cv=none; d=google.com; s=arc-20160816; b=yUC228C7I5InlcwwywYOyf4IPGJijbwNrsu3LJK/+lRPYyo5TmtEC4EdgWjU8z96F8 pFhCzxDzOHxDqqMGd74C06psMNGtc6jEzQ8bwl6kQvfTsmm4ec+gwGEw7xmm5hj3ghrI fP8e8U/VpUmf3PxGtMjwQ5/m61PaYvlUcM3XCCqmXlbxr1XdSC8FGBBv2KzeaYMlaoqz H1xniB4g8Sh/xAnDxpmJElM1XreJ8vnHTDjk5LswrTlFZAW6DMrjDMtQMQ6+ZDE2ecm4 vvC3Bwxw84ABIAaK5jzljOMb26pc5kMIR1cK1/8Jqg4BNbHMnW9TF+JZJR5HOor9stxn MsZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=QDXgm3i/pXo06XR66oqaDP01zaQl6YB/cBs/fNoDwM0=; b=et9vazsE+64SMwNNRsqvHl9UfAwNU2e9gYvLnnF8NyDcBX6EE3E5tXkmYm461J7f1Z pp7KhKmhwjh2OvkWBLy+h5p0DEdHwwyzykXICB9b1McBq1onH/AsuFz269AaoQ79HECD WDgC+vMhXgHCl5Q/vivjaRc0oEcLt6139y/CiRg9YJv88YqO727s5Fs4FM5qW6cWtFKh bpysIzxLGxO+NTg3oRHUTbiJuOuwV01EwV7QS8PNza9Ca/tAyChyqp8OCtQR3XEZwY4N SmoZN/oEy99XJOF5PIeqPQ/omsOsn+fvyvi6tW7Pq/HJ5ppTygBlz/rNz0Z0Jqn9A+/I WJHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eLVrZn8Q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:08 -0500 Message-Id: <20180527141324.11937-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22e Subject: [Qemu-devel] [PATCH 04/20] target/openrisc: Link more translation blocks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Track direct jumps via dc->jmp_pc_imm. Use that in preference to jmp_pc when possible. Emit goto_tb in that case, and lookup_and_goto_tb otherwise. Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 82 +++++++++++++++++++++---------------- 1 file changed, 46 insertions(+), 36 deletions(-) -- 2.17.0 Reviewed-by: Stafford Horne diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index e566be6d3c..a8afb9a562 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -42,13 +42,16 @@ /* is_jmp field values */ #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ -#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */ typedef struct DisasContext { DisasContextBase base; uint32_t mem_idx; uint32_t tb_flags; uint32_t delayed_branch; + + /* If not -1, jmp_pc contains this value and so is a direct jump. */ + target_ulong jmp_pc_imm; } DisasContext; /* Include the auto-generated decoder. */ @@ -164,34 +167,6 @@ static void check_ov64s(DisasContext *dc) } \ } while (0) -static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) -{ - if (unlikely(dc->base.singlestep_enabled)) { - return false; - } - -#ifndef CONFIG_USER_ONLY - return (dc->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); -#else - return true; -#endif -} - -static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) -{ - if (use_goto_tb(dc, dest)) { - tcg_gen_movi_tl(cpu_pc, dest); - tcg_gen_goto_tb(n); - tcg_gen_exit_tb((uintptr_t)dc->base.tb + n); - } else { - tcg_gen_movi_tl(cpu_pc, dest); - if (dc->base.singlestep_enabled) { - gen_exception(dc, EXCP_DEBUG); - } - tcg_gen_exit_tb(0); - } -} - static void gen_ove_cy(DisasContext *dc) { if (dc->tb_flags & SR_OVE) { @@ -655,6 +630,7 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a, uint32_t insn) LOG_DIS("l.j %d\n", a->n); tcg_gen_movi_tl(jmp_pc, tmp_pc); + dc->jmp_pc_imm = tmp_pc; dc->delayed_branch = 2; return true; } @@ -669,6 +645,7 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a, uint32_t insn) /* Optimize jal being used to load the PC for PIC. */ if (tmp_pc != ret_pc) { tcg_gen_movi_tl(jmp_pc, tmp_pc); + dc->jmp_pc_imm = tmp_pc; dc->delayed_branch = 2; } return true; @@ -1381,6 +1358,8 @@ static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->mem_idx = cpu_mmu_index(env, false); dc->tb_flags = dc->base.tb->flags; dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0; + dc->jmp_pc_imm = -1; + bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); } @@ -1437,10 +1416,7 @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) if (dc->delayed_branch) { dc->delayed_branch--; if (!dc->delayed_branch) { - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); - dc->base.is_jmp = DISAS_UPDATE; - return; + dc->base.is_jmp = DISAS_JUMP; } } } @@ -1448,22 +1424,56 @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong jmp_dest; /* If we have already exited the TB, nothing following has effect. */ if (dc->base.is_jmp == DISAS_NORETURN) { return; } + /* Adjust the delayed branch state for the next TB. */ if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) { tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0); } - tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4); + /* For DISAS_TOO_MANY, jump to the next insn. */ + jmp_dest = dc->base.pc_next; + tcg_gen_movi_tl(cpu_ppc, jmp_dest - 4); + switch (dc->base.is_jmp) { + case DISAS_JUMP: + jmp_dest = dc->jmp_pc_imm; + if (jmp_dest == -1) { + /* The jump destination is indirect/computed; use jmp_pc. */ + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + if (unlikely(dc->base.singlestep_enabled)) { + gen_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_lookup_and_goto_ptr (); + } + break; + } + /* The jump destination is direct; use jmp_pc_imm. + However, we will have stored into jmp_pc as well; + we know now that it wasn't needed. */ + tcg_gen_discard_tl(jmp_pc); + /* fallthru */ + case DISAS_TOO_MANY: - gen_goto_tb(dc, 0, dc->base.pc_next); + if (unlikely(dc->base.singlestep_enabled)) { + tcg_gen_movi_tl(cpu_pc, jmp_dest); + gen_exception(dc, EXCP_DEBUG); + } else if ((dc->base.pc_first ^ jmp_dest) & TARGET_PAGE_MASK) { + tcg_gen_movi_tl(cpu_pc, jmp_dest); + tcg_gen_lookup_and_goto_ptr (); + } else { + tcg_gen_goto_tb(0); + tcg_gen_movi_tl(cpu_pc, jmp_dest); + tcg_gen_exit_tb((uintptr_t)dc->base.tb + 0); + } break; - case DISAS_UPDATE: + case DISAS_EXIT: if (unlikely(dc->base.singlestep_enabled)) { gen_exception(dc, EXCP_DEBUG); From patchwork Sun May 27 14:13:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137017 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1788752lji; Sun, 27 May 2018 07:20:46 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJVaEsgP3veDRUZgSwCtBK+dhFMO0rEsoF44bsRx4ms46kdQaZwYdYI0Xc+acSc2Uq16jwz X-Received: by 2002:a37:9dd4:: with SMTP id g203-v6mr4263857qke.197.1527430846740; Sun, 27 May 2018 07:20:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527430846; cv=none; d=google.com; s=arc-20160816; b=hOqpTiKpvHxTprR9QYhfVz36OwV2dKmz5ifC2+3gxZ/vCqCekwnLG42q/0FBvScyIl urN+Kf+DEDkpXb4MM+FZ4qt1TVusvXGf67R6JMEHTfNywuM4lOsnc6EFBsL6vitzuRoc XEEQ9t59FV/X26W8NznljqvzRgckNrYkSOZs1nmkTJvb2UbpVlm8MrO977aO7Yr6Vqmm CfH1X9OAbOO3M+gRjuaWQVKTyn2UTOH9hk1Qhcr67uI0hwhMyClTtA2mqgvIWj4lcNUm y7hbQIMzy/rAiYOa9RDv43RLUavnanACnd+Nww92a3J3LTEtD7VJePmtzaYXyZEKsnrD ATfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Qhm86MLlNHiOqum7WU9JuSQ80vU+puuKZ6sHQm5Pl70=; b=QeODQurwg7Y0iy4/OdKJbpJ/e7D9rjj9yO1fWKAV3AHos1O5xVYoIKDEOw87H1KKYx XspCt0PdX1rTn9+mHeVsjfsmM7DPs4FphI9RJG2eNwy1vZwdzSGSUqDZ0UA5vo7VIImi NWQdYayVMi4/qtJBkK+Dgh4EDwQajML6B/ZBgP8VkCXzaKbNZPYcoXyz21zW6T9u+LMe 9FuDghaR5pqLmrP9kSCDWsoJoyYUKxAF0rqZkRMuBAw4Gi2RtSBVtCbf24l+Yf2ouO3o znuo2m3idrAURoLATdsUZUtEp0ajAuPyJAy7itDD6D/44N9S7zBjNmjJM73xXFZS+8O0 phfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LyH6Qtr1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:09 -0500 Message-Id: <20180527141324.11937-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH 05/20] target/openrisc: Split out is_user X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows us to limit the amount of ifdefs and isolate the test for usermode. Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stafford Horne diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a8afb9a562..61e6deef69 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -54,6 +54,15 @@ typedef struct DisasContext { target_ulong jmp_pc_imm; } DisasContext; +static inline bool is_user(DisasContext *dc) +{ +#ifdef CONFIG_USER_ONLY + return true; +#else + return dc->mem_idx == MMU_USER_IDX; +#endif +} + /* Include the auto-generated decoder. */ #include "decode.inc.c" @@ -914,17 +923,13 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn) LOG_DIS("l.mfspr r%d, r%d, %d\n", a->d, a->a, a->k); check_r0_write(a->d); -#ifdef CONFIG_USER_ONLY - gen_illegal_exception(dc); -#else - if (dc->mem_idx == MMU_USER_IDX) { + if (is_user(dc)) { gen_illegal_exception(dc); } else { TCGv_i32 ti = tcg_const_i32(a->k); gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], ti); tcg_temp_free_i32(ti); } -#endif return true; } @@ -932,17 +937,13 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) { LOG_DIS("l.mtspr r%d, r%d, %d\n", a->a, a->b, a->k); -#ifdef CONFIG_USER_ONLY - gen_illegal_exception(dc); -#else - if (dc->mem_idx == MMU_USER_IDX) { + if (is_user(dc)) { gen_illegal_exception(dc); } else { TCGv_i32 ti = tcg_const_i32(a->k); gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); tcg_temp_free_i32(ti); } -#endif return true; } @@ -1204,16 +1205,12 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn) { LOG_DIS("l.rfe\n"); -#ifdef CONFIG_USER_ONLY - gen_illegal_exception(dc); -#else - if (dc->mem_idx == MMU_USER_IDX) { + if (is_user(dc)) { gen_illegal_exception(dc); } else { gen_helper_rfe(cpu_env); dc->base.is_jmp = DISAS_EXIT; } -#endif return true; } From patchwork Sun May 27 14:13:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137013 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1786321lji; Sun, 27 May 2018 07:17:31 -0700 (PDT) X-Google-Smtp-Source: ADUXVKI04+4HWl58KHq27G3WgLrQH/CFwLvzqrM53hLg8FBr91QKT8+LEidAWt1yaLJ5rDs+IsXu X-Received: by 2002:a0c:b503:: with SMTP id d3-v6mr9103057qve.107.1527430651127; Sun, 27 May 2018 07:17:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527430651; cv=none; d=google.com; s=arc-20160816; b=VQQnxKY3B+fBJubUNRg5oQaqPPw575JbGs2bifKp+WBgfHA/RpkI4ntt+WKE3fGSSH UloCxhWg4gXEsZMUC4QV35r4WbSIrpAOuYLSyheWgknlLNVLtknyNczCcVo12K9o1P0Z 01mYJer90zgfVTRxoG3flZfML/97idBVZm1FW0aFu3xnsUiBsK0yqoq/JIG+fucvoBqW y3UChNKyIBVSfthMgFY0BtGVq/wGwIUKNgTLTaTzaUjniwLy7o5v/ul87WNM1UtWeby0 O0M7rTq7dn0VXNsWX8pbYvJeOZk/zYni/7Fw7TGgM38RCl33RfFhVI5HDEhNZWvzK+ei Dd5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=7xiVnQhbVRorvuZfqDUYYp2ZTVo4pufmMXCHOnvHU4w=; b=ofe3dH32nF/+YeBthbbHbeFRv/JPGOCGn/kMjPAzZNEH6Y2w6dfNqjXqVRipc+/VAd oE9ZCEu8kIVeUMimnYV29vGZWEYcXyGGF9446ilKagE5oGCPq5OSze/fExwAPZse3aWs XE9MJoqBckhp6sAQhYJ7kXf0+tz8vMJwb5iuUO8Ktx2KdqBbLbQHcOCnUCxvLYeFSc0u Piw54Zhh2KM1ypOMR/Fd8KtkNzKW9upkX8IdVDP63D5UDExXCrgBEhhIfDWlunXUHbMH luKR6CTE5nncQda8K1lM5QuowNTJSoaz9rGZmRU81Qmc2ObJorbWo2+znPR8Z01274c0 D18Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cdIBGUJX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:10 -0500 Message-Id: <20180527141324.11937-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 06/20] target/openrisc: Exit the TB after l.mtspr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A store to SR changes interrupt state, which should return to the main loop to recognize that state. Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) -- 2.17.0 Reviewed-by: Stafford Horne diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 61e6deef69..c7bfb395b0 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -940,9 +940,31 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) if (is_user(dc)) { gen_illegal_exception(dc); } else { - TCGv_i32 ti = tcg_const_i32(a->k); + TCGv_i32 ti; + + /* For SR, we will need to exit the TB to recognize the new + * exception state. For NPC, in theory this counts as a branch + * (although the SPR only exists for use by an ICE). Save all + * of the cpu state first, allowing it to be overwritten. + */ + if (dc->tb_flags & TB_FLAGS_DFLAG) { + tcg_gen_movi_i32(cpu_dflag, 0); + } + tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next); + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); + + ti = tcg_const_i32(a->k); gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); tcg_temp_free_i32(ti); + + /* For PPC, we want the value that was just written and not + the generic update that we'd get from DISAS_EXIT. */ + if (unlikely(dc->base.singlestep_enabled)) { + gen_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_exit_tb(0); + } + dc->base.is_jmp = DISAS_NORETURN; } return true; } From patchwork Sun May 27 14:13:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137012 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1785853lji; Sun, 27 May 2018 07:16:58 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKgDoSwk3DTmXyJXUT+I3hvJlrpt87hLEWYtGXEH9ixeQYuZIJJLlXFawWOjJJr/j/cfKPg X-Received: by 2002:a37:aaca:: with SMTP id t193-v6mr8547466qke.104.1527430618498; Sun, 27 May 2018 07:16:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527430618; cv=none; d=google.com; s=arc-20160816; b=EEl19MubODKzFq/RbpwYwwspcwPcu6Ha1ob+gKekJmrcV5JnBAVrlZ8c4yBTUqWi7n E5hTBMxxQN1LV1RY3JPZ5w6rsCAe4bZJZTnbkv+ft1wiKn38VUEjLE4pyfXaoQZba58E Q5oO7ohHGdZ4c8JhwRRLwN10IKfdQp+m3icg4RkBguLqGsmbCUVDCF3D1IG6/FohWp0H NQEGTH3wMgjlxS1w5DpO45Gu5Uwk5uLNfeHGRmdCYjgptIujKdhU8HOVfC3qzGibHfHe iV36hF1zk9RgcwSNlBOsbYZg7jENPSlVoyU9QUO3mjbyZWQgGoftP7JKrBQ85cxtY0qF ESAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=/0ZGkCb7Sjx7eXtRm4QaOBlfYw+yU8MW3fU4EH6sJQI=; b=JpI4/g9rlFrH1pLoFHBtHb9qXCtMhZD5JYU34PPKe91OiXBL643G1c53IwYrXNo+cj I7ju4KCF7tBRDr1enkf1e0Ca7X2PjYvS3cIa7ZM8UsBQ/8EWHd51/3qRsuph42YXRm4K Cb0fopsxxYvRz6n5kW6rnMB/UY9lPq8RWa6K1shx1bDGjAfyh50pcS0sFk9gSNBitd+w 8bM6Xc82DYVJ8eQNEwfzKt0GrwpzN6JjvowJ2927pXnyZ6ifXh0YYn6FZdzV1MWMsZLB 7PZkM4gKiE+KhU6etp8gqmkJJyMlrMwXGnwBQ2zo+vqq1vnfI2GG6UVIb4tziK1cX86n QRPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RFnoxHr0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:11 -0500 Message-Id: <20180527141324.11937-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH 07/20] target/openrisc: Form the spr index from tcg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than pass base+offset to the helper, pass the full index. In most cases the base is r0 and optimization yields a constant. Signed-off-by: Richard Henderson --- target/openrisc/helper.h | 4 ++-- target/openrisc/sys_helper.c | 9 +++------ target/openrisc/translate.c | 16 +++++++++------- 3 files changed, 14 insertions(+), 15 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index e37dabc77a..9db9bf3963 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -56,5 +56,5 @@ FOP_CMP(le) DEF_HELPER_FLAGS_1(rfe, 0, void, env) /* sys */ -DEF_HELPER_FLAGS_4(mtspr, 0, void, env, tl, tl, tl) -DEF_HELPER_FLAGS_4(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl, tl) +DEF_HELPER_FLAGS_3(mtspr, 0, void, env, tl, tl) +DEF_HELPER_FLAGS_3(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index b284064381..a8d287d6ef 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -27,13 +27,11 @@ #define TO_SPR(group, number) (((group) << 11) + (number)) -void HELPER(mtspr)(CPUOpenRISCState *env, - target_ulong ra, target_ulong rb, target_ulong offset) +void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) { #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = openrisc_env_get_cpu(env); CPUState *cs = CPU(cpu); - int spr = (ra | offset); int idx; switch (spr) { @@ -201,13 +199,12 @@ void HELPER(mtspr)(CPUOpenRISCState *env, #endif } -target_ulong HELPER(mfspr)(CPUOpenRISCState *env, - target_ulong rd, target_ulong ra, uint32_t offset) +target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, + target_ulong spr) { #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = openrisc_env_get_cpu(env); CPUState *cs = CPU(cpu); - int spr = (ra | offset); int idx; switch (spr) { diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index c7bfb395b0..b26c473870 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -926,9 +926,10 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn) if (is_user(dc)) { gen_illegal_exception(dc); } else { - TCGv_i32 ti = tcg_const_i32(a->k); - gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], ti); - tcg_temp_free_i32(ti); + TCGv spr = tcg_temp_new(); + tcg_gen_ori_tl(spr, cpu_R[a->a], a->k); + gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], spr); + tcg_temp_free(spr); } return true; } @@ -940,7 +941,7 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) if (is_user(dc)) { gen_illegal_exception(dc); } else { - TCGv_i32 ti; + TCGv spr; /* For SR, we will need to exit the TB to recognize the new * exception state. For NPC, in theory this counts as a branch @@ -953,9 +954,10 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next); tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); - ti = tcg_const_i32(a->k); - gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); - tcg_temp_free_i32(ti); + spr = tcg_temp_new(); + tcg_gen_ori_tl(spr, cpu_R[a->a], a->k); + gen_helper_mtspr(cpu_env, spr, cpu_R[a->b]); + tcg_temp_free(spr); /* For PPC, we want the value that was just written and not the generic update that we'd get from DISAS_EXIT. */ From patchwork Sun May 27 14:13:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137019 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1790817lji; Sun, 27 May 2018 07:23:24 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJXSJJxD+hHunwgMPuLA24vc2y7wymhAa1s8AbgFJ5xId9hGEUKhiipjwQ6wGrJk3x9zIYe X-Received: by 2002:ae9:dfc1:: with SMTP id t184-v6mr8602863qkf.274.1527431004120; Sun, 27 May 2018 07:23:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527431004; cv=none; d=google.com; s=arc-20160816; b=nUj278xtSU5XQcPLpq8W5rpUs8TVkct3Boja5NxhJs5uwyl/Yx/JcOklkG+ZmLccq6 TU8KldXhgldZNOLYxyO4QgK1hxD92LfYkRIUJSeZNB8KMTf6cZwUeccF0qBGxtKsS7rW Iv1g6/HsLIBW7EUK9qyXPtu7c6AjcxCchkG49lRK4ptFuf/4bLpwFCMiz5E7iIZXvCOG 8O/00+yNHObzXQN6SSX5RiVWHjBHUSmk+422L/sUxybsfVIGqStDf325QZFxeCIeXcy7 c2ftDZ8OJTMSaJNMUVS81kBnhSYdtKly5O9z13rpzN0Wy1198/bnUI0/wD4kAwXwFntv pCng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Sv9zObxVynIk9vFcf+d4KHvYBtLjN9PZrOzpuL0EaM8=; b=If636vhO7o0qHXnxRF8X/0T9LY7Lrz8M8tAizOcBhYj1Ep8qj8iuPPir3FQ9PXbsrs ZWDXuvVRGJ0of99OIVu0ssFgxRosVKG1cDVuphrStovCPCbIKpRT+90xKOMX6o2rDmUR rPMbNouBxxj5LA0h3TM4QHoe9+iWg59/HlivGtyC2ACsfCnYCRB5PmPFyNa+aV4irRnU kSsL1zsLxm8XcuSlKvb5zZ3tQgJslyGLUvH+p0PRIC3uVee3edUTfNZy9MjaZxWuJR+S Hz56TwKioond+7tJiDVKLtZg6Nbxu8d+48WTi4gTIJxgLyuEh5FjjZuOKJPRGuKlry9e QoKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Zzq0i1El; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:12 -0500 Message-Id: <20180527141324.11937-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::236 Subject: [Qemu-devel] [PATCH 08/20] target/openrisc: Merge tlb allocation into CPUOpenRISCState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is no reason to allocate this separately. This was probably copied from target/mips which makes the same mistake. While doing so, move tlb into the clear-on-reset range. While not all of the TLB bits are guaranteed zero on reset, all of the valid bits are cleared, and the rest of the bits are unspecified. Therefore clearing the whole of the TLB is correct. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 6 ++++-- target/openrisc/interrupt.c | 4 ++-- target/openrisc/interrupt_helper.c | 8 +++---- target/openrisc/machine.c | 15 ++++++------- target/openrisc/mmu.c | 34 ++++++++++++++---------------- target/openrisc/sys_helper.c | 28 ++++++++++++------------ 6 files changed, 46 insertions(+), 49 deletions(-) -- 2.17.0 Reviewed-by: Stafford Horne diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 35cab65f11..edc06be40e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -301,6 +301,10 @@ typedef struct CPUOpenRISCState { uint32_t dflag; /* In delay slot (boolean) */ +#ifndef CONFIG_USER_ONLY + CPUOpenRISCTLBContext tlb; +#endif + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; @@ -310,8 +314,6 @@ typedef struct CPUOpenRISCState { uint32_t cpucfgr; /* CPU configure register */ #ifndef CONFIG_USER_ONLY - CPUOpenRISCTLBContext * tlb; - QEMUTimer *timer; uint32_t ttmr; /* Timer tick mode register */ int is_counting; diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 3959671c59..8b8b14ace0 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -62,8 +62,8 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr &= ~SR_TEE; env->pmr &= ~PMR_DME; env->pmr &= ~PMR_SME; - env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; - env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; + env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; + env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; env->lock_addr = -1; if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c index b865738f8b..dc97b38704 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -36,18 +36,18 @@ void HELPER(rfe)(CPUOpenRISCState *env) #ifndef CONFIG_USER_ONLY if (cpu->env.sr & SR_DME) { - cpu->env.tlb->cpu_openrisc_map_address_data = + cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_data; } else { - cpu->env.tlb->cpu_openrisc_map_address_data = + cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; } if (cpu->env.sr & SR_IME) { - cpu->env.tlb->cpu_openrisc_map_address_code = + cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_code; } else { - cpu->env.tlb->cpu_openrisc_map_address_code = + cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; } diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 0a793eb14d..c10d28b055 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -30,18 +30,18 @@ static int env_post_load(void *opaque, int version_id) /* Restore MMU handlers */ if (env->sr & SR_DME) { - env->tlb->cpu_openrisc_map_address_data = + env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_data; } else { - env->tlb->cpu_openrisc_map_address_data = + env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; } if (env->sr & SR_IME) { - env->tlb->cpu_openrisc_map_address_code = + env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_code; } else { - env->tlb->cpu_openrisc_map_address_code = + env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; } @@ -77,10 +77,6 @@ static const VMStateDescription vmstate_cpu_tlb = { } }; -#define VMSTATE_CPU_TLB(_f, _s) \ - VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext) - - static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { CPUOpenRISCState *env = opaque; @@ -143,7 +139,8 @@ static const VMStateDescription vmstate_env = { VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), - VMSTATE_CPU_TLB(tlb, CPUOpenRISCState), + VMSTATE_STRUCT(tlb, CPUOpenRISCState, 1, + vmstate_cpu_tlb, CPUOpenRISCTLBContext), VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), VMSTATE_UINT32(ttmr, CPUOpenRISCState), diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 2bd782f89b..5665bb7cc9 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -46,19 +46,19 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, int idx = vpn & ITLB_MASK; int right = 0; - if ((cpu->env.tlb->itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { + if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb->itlb[0][idx].mr & 1)) { + if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { return TLBRET_INVALID; } if (cpu->env.sr & SR_SM) { /* supervisor mode */ - if (cpu->env.tlb->itlb[0][idx].tr & SXE) { + if (cpu->env.tlb.itlb[0][idx].tr & SXE) { right |= PAGE_EXEC; } } else { - if (cpu->env.tlb->itlb[0][idx].tr & UXE) { + if (cpu->env.tlb.itlb[0][idx].tr & UXE) { right |= PAGE_EXEC; } } @@ -67,7 +67,7 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, return TLBRET_BADADDR; } - *physical = (cpu->env.tlb->itlb[0][idx].tr & TARGET_PAGE_MASK) | + *physical = (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) | (address & (TARGET_PAGE_SIZE-1)); *prot = right; return TLBRET_MATCH; @@ -81,25 +81,25 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, int idx = vpn & DTLB_MASK; int right = 0; - if ((cpu->env.tlb->dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { + if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb->dtlb[0][idx].mr & 1)) { + if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { return TLBRET_INVALID; } if (cpu->env.sr & SR_SM) { /* supervisor mode */ - if (cpu->env.tlb->dtlb[0][idx].tr & SRE) { + if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { right |= PAGE_READ; } - if (cpu->env.tlb->dtlb[0][idx].tr & SWE) { + if (cpu->env.tlb.dtlb[0][idx].tr & SWE) { right |= PAGE_WRITE; } } else { - if (cpu->env.tlb->dtlb[0][idx].tr & URE) { + if (cpu->env.tlb.dtlb[0][idx].tr & URE) { right |= PAGE_READ; } - if (cpu->env.tlb->dtlb[0][idx].tr & UWE) { + if (cpu->env.tlb.dtlb[0][idx].tr & UWE) { right |= PAGE_WRITE; } } @@ -111,7 +111,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, return TLBRET_BADADDR; } - *physical = (cpu->env.tlb->dtlb[0][idx].tr & TARGET_PAGE_MASK) | + *physical = (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) | (address & (TARGET_PAGE_SIZE-1)); *prot = right; return TLBRET_MATCH; @@ -126,10 +126,10 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, if (rw == MMU_INST_FETCH) { /* ITLB */ *physical = 0; - ret = cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical, + ret = cpu->env.tlb.cpu_openrisc_map_address_code(cpu, physical, prot, address, rw); } else { /* DTLB */ - ret = cpu->env.tlb->cpu_openrisc_map_address_data(cpu, physical, + ret = cpu->env.tlb.cpu_openrisc_map_address_data(cpu, physical, prot, address, rw); } @@ -247,9 +247,7 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) { - cpu->env.tlb = g_malloc0(sizeof(CPUOpenRISCTLBContext)); - - cpu->env.tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; - cpu->env.tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; + cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; + cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; } #endif diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index a8d287d6ef..f26c688df6 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -61,18 +61,18 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) } cpu_set_sr(env, rb); if (env->sr & SR_DME) { - env->tlb->cpu_openrisc_map_address_data = + env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_data; } else { - env->tlb->cpu_openrisc_map_address_data = + env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; } if (env->sr & SR_IME) { - env->tlb->cpu_openrisc_map_address_code = + env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_code; } else { - env->tlb->cpu_openrisc_map_address_code = + env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; } break; @@ -100,14 +100,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK); } - env->tlb->dtlb[0][idx].mr = rb; + env->tlb.dtlb[0][idx].mr = rb; break; case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); - env->tlb->dtlb[0][idx].tr = rb; + env->tlb.dtlb[0][idx].tr = rb; break; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -119,14 +119,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK); } - env->tlb->itlb[0][idx].mr = rb; + env->tlb.itlb[0][idx].mr = rb; break; case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); - env->tlb->itlb[0][idx].tr = rb; + env->tlb.itlb[0][idx].tr = rb; break; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ @@ -258,11 +258,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); - return env->tlb->dtlb[0][idx].mr; + return env->tlb.dtlb[0][idx].mr; case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); - return env->tlb->dtlb[0][idx].tr; + return env->tlb.dtlb[0][idx].tr; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -274,11 +274,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); - return env->tlb->itlb[0][idx].mr; + return env->tlb.itlb[0][idx].mr; case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); - return env->tlb->itlb[0][idx].tr; + return env->tlb.itlb[0][idx].tr; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ From patchwork Sun May 27 14:13:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137025 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1793878lji; Sun, 27 May 2018 07:27:18 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJTS+F8FDudrFTAiurs8QpNzmpJooOyxPSVK4Ob1gwcOIE0oHON+/BlMcrF7NVD94eNa7iA X-Received: by 2002:a0c:bed1:: with SMTP id f17-v6mr9040743qvj.18.1527431238424; Sun, 27 May 2018 07:27:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527431238; cv=none; d=google.com; s=arc-20160816; b=NmZHzRHmbhUR4nBDbA7pMLYIWEI1qerZQ2F+l4BMKAuCLtroLsWcKBHtYAH9r99ewT yIyqhqN3JPTJExvoxa1kTucZxKWf/wnczo28D3hdW6mfsNBALZzGb2PGZqHFxwcpXaHg 7DZhDYa9W94b4ib8W91vhvBT0YqJNl0Z7K29Tu3vcKVm0aSAuf2hkeQbDdCuKSyZ9ymu CRRmWfAifKAAcLib0i6efIBHGPZ+Y3MEEXnc3Tii2At6ApU1yPG0360WhN2QAJaThX/R HNGrQ/6M93LRxXSGiDuXphFGVxHXfhhjxCCuVdk0Gb2ISuj/ApS85v6YhMoM4SII1HbX pAzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=OrKE/LaWGVC7jD4c6j/qmNaBdA8y+YAphWEAoiEVCZQ=; b=cCOmDoZ8mFMX6r4gqfS4A25HMHtoSir2bCMsdohiIRfanZxoR57G5NZwW+j8LIOZgP FQS1otI02AOYkM/aZKKydx5Y+rgVAqcRkg2u3XR9MvPcnCR3k8Gw4RYjq3wII2Flreo+ BfrEdfH81KbgQYwKynIbTK3c1XkGYG3hSwVhG4eviAmCPqGfXj32ctJ9Iy049gk971cY SYee21jFD+edTqazxDZZS8HvLl+5tNihy7Z6OayaFQckP8ejIa3aB7zOsqxx65v1LEml 1H+r2hfYRNE/eNFYUqj2MojZA3tMmEqeg9NlXdfx1iM/KXElzYHebPKYlbYMMUPRzU4i cDjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DsYORja6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:13 -0500 Message-Id: <20180527141324.11937-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 09/20] target/openrisc: Remove indirect function calls for mmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is no reason to use an indirect branch instead of simply testing the SR bits that control mmu state. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 11 ----- target/openrisc/cpu.c | 4 -- target/openrisc/interrupt.c | 2 - target/openrisc/interrupt_helper.c | 25 ++--------- target/openrisc/machine.c | 26 ------------ target/openrisc/mmu.c | 66 +++++++++++++----------------- target/openrisc/sys_helper.c | 15 ------- 7 files changed, 31 insertions(+), 118 deletions(-) -- 2.17.0 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index edc06be40e..13107058cb 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -378,17 +378,6 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu); void cpu_openrisc_timer_update(OpenRISCCPU *cpu); void cpu_openrisc_count_start(OpenRISCCPU *cpu); void cpu_openrisc_count_stop(OpenRISCCPU *cpu); - -void cpu_openrisc_mmu_init(OpenRISCCPU *cpu); -int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); -int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); -int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); #endif #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 20b115afae..b2711a961e 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -88,10 +88,6 @@ static void openrisc_cpu_initfn(Object *obj) OpenRISCCPU *cpu = OPENRISC_CPU(obj); cs->env_ptr = &cpu->env; - -#ifndef CONFIG_USER_ONLY - cpu_openrisc_mmu_init(cpu); -#endif } /* CPU models */ diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 8b8b14ace0..d9cb363fea 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -62,8 +62,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr &= ~SR_TEE; env->pmr &= ~PMR_DME; env->pmr &= ~PMR_SME; - env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; - env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; env->lock_addr = -1; if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c index dc97b38704..a2e9003969 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -29,31 +29,12 @@ void HELPER(rfe)(CPUOpenRISCState *env) #ifndef CONFIG_USER_ONLY int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); -#endif - cpu->env.pc = cpu->env.epcr; - cpu_set_sr(&cpu->env, cpu->env.esr); - cpu->env.lock_addr = -1; - -#ifndef CONFIG_USER_ONLY - if (cpu->env.sr & SR_DME) { - cpu->env.tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_data; - } else { - cpu->env.tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_nommu; - } - - if (cpu->env.sr & SR_IME) { - cpu->env.tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_code; - } else { - cpu->env.tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_nommu; - } - if (need_flush_tlb) { CPUState *cs = CPU(cpu); tlb_flush(cs); } #endif + cpu->env.pc = cpu->env.epcr; + cpu->env.lock_addr = -1; + cpu_set_sr(&cpu->env, cpu->env.esr); } diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index c10d28b055..73e0abcfd7 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -24,31 +24,6 @@ #include "hw/boards.h" #include "migration/cpu.h" -static int env_post_load(void *opaque, int version_id) -{ - CPUOpenRISCState *env = opaque; - - /* Restore MMU handlers */ - if (env->sr & SR_DME) { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_data; - } else { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_nommu; - } - - if (env->sr & SR_IME) { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_code; - } else { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_nommu; - } - - - return 0; -} - static const VMStateDescription vmstate_tlb_entry = { .name = "tlb_entry", .version_id = 1, @@ -102,7 +77,6 @@ static const VMStateDescription vmstate_env = { .name = "env", .version_id = 6, .minimum_version_id = 6, - .post_load = env_post_load, .fields = (VMStateField[]) { VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 5665bb7cc9..b2effaa6d7 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -29,18 +29,16 @@ #endif #ifndef CONFIG_USER_ONLY -int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static inline int get_phys_nommu(hwaddr *physical, int *prot, + target_ulong address) { *physical = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } -int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, + target_ulong address, int rw, bool supervisor) { int vpn = address >> TARGET_PAGE_BITS; int idx = vpn & ITLB_MASK; @@ -52,8 +50,7 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { return TLBRET_INVALID; } - - if (cpu->env.sr & SR_SM) { /* supervisor mode */ + if (supervisor) { if (cpu->env.tlb.itlb[0][idx].tr & SXE) { right |= PAGE_EXEC; } @@ -62,7 +59,6 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, right |= PAGE_EXEC; } } - if ((rw & 2) && ((right & PAGE_EXEC) == 0)) { return TLBRET_BADADDR; } @@ -73,9 +69,8 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, return TLBRET_MATCH; } -int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, + target_ulong address, int rw, bool supervisor) { int vpn = address >> TARGET_PAGE_BITS; int idx = vpn & DTLB_MASK; @@ -87,8 +82,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { return TLBRET_INVALID; } - - if (cpu->env.sr & SR_SM) { /* supervisor mode */ + if (supervisor) { if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { right |= PAGE_READ; } @@ -117,20 +111,24 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, return TLBRET_MATCH; } -static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, - int rw) +static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical, + int *prot, target_ulong address, int rw) { - int ret = TLBRET_MATCH; + bool supervisor = (cpu->env.sr & SR_SM) != 0; + int ret; - if (rw == MMU_INST_FETCH) { /* ITLB */ - *physical = 0; - ret = cpu->env.tlb.cpu_openrisc_map_address_code(cpu, physical, - prot, address, rw); - } else { /* DTLB */ - ret = cpu->env.tlb.cpu_openrisc_map_address_data(cpu, physical, - prot, address, rw); + /* Assume nommu results for a moment. */ + ret = get_phys_nommu(physical, prot, address); + + /* Overwrite with TLB lookup if enabled. */ + if (rw == MMU_INST_FETCH) { + if (cpu->env.sr & SR_IME) { + ret = get_phys_code(cpu, physical, prot, address, rw, supervisor); + } + } else { + if (cpu->env.sr & SR_DME) { + ret = get_phys_data(cpu, physical, prot, address, rw, supervisor); + } } return ret; @@ -186,8 +184,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, hwaddr physical = 0; int prot = 0; - ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot, - address, rw); + ret = get_phys_addr(cpu, &physical, &prot, address, rw); if (ret == TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, @@ -225,17 +222,16 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) /* Check memory for any kind of address, since during debug the gdb can ask for anything, check data tlb for address */ - miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + miss = get_phys_addr(cpu, &phys_addr, &prot, addr, 0); /* Check instruction tlb */ if (miss) { - miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, - MMU_INST_FETCH); + miss = get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETCH); } /* Last, fall back to a plain address */ if (miss) { - miss = cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr, 0); + miss = get_phys_nommu(&phys_addr, &prot, addr); } if (miss) { @@ -244,10 +240,4 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } } - -void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) -{ - cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; - cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; -} #endif diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index f26c688df6..a1285894ad 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -60,21 +60,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) tlb_flush(cs); } cpu_set_sr(env, rb); - if (env->sr & SR_DME) { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_data; - } else { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_nommu; - } - - if (env->sr & SR_IME) { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_code; - } else { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_nommu; - } break; case TO_SPR(0, 18): /* PPC */ From patchwork Sun May 27 14:13:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137026 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1794243lji; Sun, 27 May 2018 07:27:48 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJoTbvX5ghYHKTUK31OX5t9dQON1FJOuVckVjwMCiUxAt5AuPOKYOgJjQjVbtAhV4hknqy+ X-Received: by 2002:aed:24d1:: with SMTP id u17-v6mr9687800qtc.116.1527431268282; Sun, 27 May 2018 07:27:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527431268; cv=none; d=google.com; s=arc-20160816; b=Q3yFMXp6vF1kMw32KP+ybIqmBxX2mkE6CwZJYSbEpJXXQ8uj5lR61ZEqerhS9gYsSY S9Fk656RN42SWz2RvDKkDx7SPSAHfNyS3N9ZFxCXkESLhi7P33/MTtYvj4pbqMW2yvYA 3vTp8VMf8ImpWCwNTpbA1y2NCgKzjdKdl2woJjrr/uyHKlfNEXQzrmvA+XXr9cLVrJL6 yeOEFCaezPTZ5EEIjS0SGrA/Ykj/wYj4rTMDcnggI3ssjJGPthNW1mdV9GIYJNEyTdcj GjTXc9+UdXOUqmCx3KhKXT1UGr9LFvB3Z0mwmJX1NZT4atvqshePdpbhgmGVSYjtWbHJ RVGw== ARC-Message-Signature: i=1; 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:14 -0500 Message-Id: <20180527141324.11937-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH 10/20] target/openrisc: Merge mmu_helper.c into mmu.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With tlb_fill in mmu.c, we can simplify things further. Signed-off-by: Richard Henderson --- target/openrisc/mmu.c | 11 ++++++++++ target/openrisc/mmu_helper.c | 40 ----------------------------------- target/openrisc/Makefile.objs | 2 +- 3 files changed, 12 insertions(+), 41 deletions(-) delete mode 100644 target/openrisc/mmu_helper.c -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index b2effaa6d7..9b4b5cf04f 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -240,4 +240,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } } + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + int ret = openrisc_cpu_handle_mmu_fault(cs, addr, size, + access_type, mmu_idx); + if (ret) { + /* Raise Exception. */ + cpu_loop_exit_restore(cs, retaddr); + } +} #endif diff --git a/target/openrisc/mmu_helper.c b/target/openrisc/mmu_helper.c deleted file mode 100644 index 97e1d17b5a..0000000000 --- a/target/openrisc/mmu_helper.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * OpenRISC MMU helper routines - * - * Copyright (c) 2011-2012 Jia Liu - * Zhizhou Zhang - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/exec-all.h" -#include "exec/cpu_ldst.h" - -#ifndef CONFIG_USER_ONLY - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = openrisc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - - if (ret) { - /* Raise Exception. */ - cpu_loop_exit_restore(cs, retaddr); - } -} -#endif diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs index 1b98a911ea..957ce02199 100644 --- a/target/openrisc/Makefile.objs +++ b/target/openrisc/Makefile.objs @@ -1,7 +1,7 @@ obj-$(CONFIG_SOFTMMU) += machine.o obj-y += cpu.o exception.o interrupt.o mmu.o translate.o obj-y += exception_helper.o fpu_helper.o \ - interrupt_helper.o mmu_helper.o sys_helper.o + interrupt_helper.o sys_helper.o obj-y += gdbstub.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py From patchwork Sun May 27 14:13:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137018 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1790791lji; Sun, 27 May 2018 07:23:22 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJAWMg9mpoibbQJYq9UFBm+Ulc/GZbaUWy3ssqlmxpQlw4A5smgPfwCdh9c1p8f48fJl1Ah X-Received: by 2002:ac8:3854:: with SMTP id r20-v6mr2522198qtb.190.1527431002573; Sun, 27 May 2018 07:23:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527431002; cv=none; d=google.com; s=arc-20160816; b=ZgxvAk1Jh9X6tcNjDJR/EI3YWmjlws43jubTqvc3JHRW0g9BbmAGHI2gUN8xU9v+N0 i+RSU2fuUrgnXcIRY/O3j9pqqeMzJ88mT0eWnjOHxXnkH33O9okwKj8ULPHGYvGyADH4 6NEMiNteQYyM6uXPMLDtRjBPaYXeTA2mo8E+sDAQiCukrxhecOOapbEiigJHhJsgYRCB Hi1BElexRToGjtxxFSfQA8Yubanu2w4fysNuaS/cExum018fsj6wa3rNOFGmGcm5Luwi tASNIxkMj8q3SUNcuZ+wQfI8YOptIOnBgl7p8aIX9GkFj/sr4cduqXeWTbiraU5jYLP1 ZNLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=NRIJ9Lwc5CFHxEmzWGEY918Q+UpbMyHa2iijO6bsHM4=; b=Eau2M0luZ0bHvOipcgvPbBemZhTDI+d25OzZVFWOVlZo+ZrfdexBtmnSQpiCppDkNb XCKH4sMoEzrrFm40uQcvCifvpvdXP9a/8xGUmZfRfUWTQ1lCBIIxXjiedhYwLPhQrkrR RURMsQxud/sPKYOgpJ7a0lCyezCaAQHFLVaLjRX7RKYhrPfb24tSN4Zn5OxZRmjZQcJd hxvXK0jflr3qpDootXNLGfTrWThuSYvEM/SI9TuoXYi4+bFqcImyHEdEhNK/umuVIZsI fKh8v1hxltqXk5uZFZrBWDOIi59M1kzvxqhQxhjOxfSrq/iyA++N2InHtOL6C9xQnahl dY9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g7H63wcu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:15 -0500 Message-Id: <20180527141324.11937-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 11/20] target/openrisc: Reduce tlb to a single dimension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While we had defines for *_WAY, we didn't define more than 1. Reduce the complexity by eliminating this unused dimension. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 6 ++---- target/openrisc/machine.c | 6 ++---- target/openrisc/mmu.c | 30 ++++++++++++++++-------------- target/openrisc/sys_helper.c | 20 ++++++++++---------- 4 files changed, 30 insertions(+), 32 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 13107058cb..947ca00d8d 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,10 +222,8 @@ enum { /* TLB size */ enum { - DTLB_WAYS = 1, DTLB_SIZE = 64, DTLB_MASK = (DTLB_SIZE-1), - ITLB_WAYS = 1, ITLB_SIZE = 64, ITLB_MASK = (ITLB_SIZE-1), }; @@ -256,8 +254,8 @@ typedef struct OpenRISCTLBEntry { #ifndef CONFIG_USER_ONLY typedef struct CPUOpenRISCTLBContext { - OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE]; - OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE]; + OpenRISCTLBEntry itlb[ITLB_SIZE]; + OpenRISCTLBEntry dtlb[DTLB_SIZE]; int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, hwaddr *physical, diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 73e0abcfd7..b795b56dc6 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -42,11 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { - VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext, - ITLB_WAYS, ITLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), - VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext, - DTLB_WAYS, DTLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), VMSTATE_END_OF_LIST() } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 9b4b5cf04f..23edd8c78c 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -43,19 +43,21 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, int vpn = address >> TARGET_PAGE_BITS; int idx = vpn & ITLB_MASK; int right = 0; + uint32_t mr = cpu->env.tlb.itlb[idx].mr; + uint32_t tr = cpu->env.tlb.itlb[idx].tr; - if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { + if ((mr >> TARGET_PAGE_BITS) != vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { + if (!(mr & 1)) { return TLBRET_INVALID; } if (supervisor) { - if (cpu->env.tlb.itlb[0][idx].tr & SXE) { + if (tr & SXE) { right |= PAGE_EXEC; } } else { - if (cpu->env.tlb.itlb[0][idx].tr & UXE) { + if (tr & UXE) { right |= PAGE_EXEC; } } @@ -63,8 +65,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, return TLBRET_BADADDR; } - *physical = (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) | - (address & (TARGET_PAGE_SIZE-1)); + *physical = (tr & TARGET_PAGE_MASK) | (address & (TARGET_PAGE_SIZE-1)); *prot = right; return TLBRET_MATCH; } @@ -75,25 +76,27 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, int vpn = address >> TARGET_PAGE_BITS; int idx = vpn & DTLB_MASK; int right = 0; + uint32_t mr = cpu->env.tlb.dtlb[idx].mr; + uint32_t tr = cpu->env.tlb.dtlb[idx].tr; - if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { + if ((mr >> TARGET_PAGE_BITS) != vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { + if (!(mr & 1)) { return TLBRET_INVALID; } if (supervisor) { - if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { + if (tr & SRE) { right |= PAGE_READ; } - if (cpu->env.tlb.dtlb[0][idx].tr & SWE) { + if (tr & SWE) { right |= PAGE_WRITE; } } else { - if (cpu->env.tlb.dtlb[0][idx].tr & URE) { + if (tr & URE) { right |= PAGE_READ; } - if (cpu->env.tlb.dtlb[0][idx].tr & UWE) { + if (tr & UWE) { right |= PAGE_WRITE; } } @@ -105,8 +108,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, return TLBRET_BADADDR; } - *physical = (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) | - (address & (TARGET_PAGE_SIZE-1)); + *physical = (tr & TARGET_PAGE_MASK) | (address & (TARGET_PAGE_SIZE-1)); *prot = right; return TLBRET_MATCH; } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index a1285894ad..8ad7a7d898 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -85,14 +85,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK); } - env->tlb.dtlb[0][idx].mr = rb; + env->tlb.dtlb[idx].mr = rb; break; case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); - env->tlb.dtlb[0][idx].tr = rb; + env->tlb.dtlb[idx].tr = rb; break; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -104,14 +104,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK); } - env->tlb.itlb[0][idx].mr = rb; + env->tlb.itlb[idx].mr = rb; break; case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); - env->tlb.itlb[0][idx].tr = rb; + env->tlb.itlb[idx].tr = rb; break; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ @@ -243,11 +243,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); - return env->tlb.dtlb[0][idx].mr; + return env->tlb.dtlb[idx].mr; case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); - return env->tlb.dtlb[0][idx].tr; + return env->tlb.dtlb[idx].tr; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -259,11 +259,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); - return env->tlb.itlb[0][idx].mr; + return env->tlb.itlb[idx].mr; case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); - return env->tlb.itlb[0][idx].tr; + return env->tlb.itlb[idx].tr; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ From patchwork Sun May 27 14:13:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137028 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1796473lji; Sun, 27 May 2018 07:30:41 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIKAMqNHdy2Vuc5NA4Pzdzdj0BFmBMF52FSPAFQsRtGm6pXBUKPhJy7jQFLvWET4ZTLuxAu X-Received: by 2002:a0c:f604:: with SMTP id r4-v6mr9059125qvm.138.1527431441262; Sun, 27 May 2018 07:30:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527431441; cv=none; d=google.com; s=arc-20160816; b=m5bWKUZUvC79TKs3zdf6aBfmoYY59PAZA7wl4Ynn03hmksOsl9T/TJ8Vy2j+aM/bgO ixcswZ++oyCrX3XeDB520h1pAsbzU2XuIk38/cInZDlsSRcCNGuL9GKjVxtjPEyV0fxR dhEpMrOoRHLlfs2yyHyECm5vrEk5oXeZcs2bdo5QwxTja16nctHH+AhRCmT8jTNYFxv3 RTBrcXPJSm0Cpb1uxOPkWoLeBIoB2Giyl1CRGgM8Q+unR+XjxXQk8YgKrh07TbGIuj5X G5xFLYwHLgmul51scWzOK0J2DvWd/+DRHyO24GVJBn1v7oUGTglTSYGLB7ENcK8YPu5p 3K1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=v4CJ/+3Lq/AhnRzfAd+D5Kf34+Ue0qdakQgog/y5diw=; b=lQZfloi3M9CkdeYbpTBLFMwiFLXpJnmQaQPpIRnSpCM3R/N8kNemGE5kMYuAGmDzg0 e6kHltC0wFocAGBUZDzMemEo18xYYdigfETm0E1YgujlxKUZT+QKlVDKtZUwEhpkUgLY y90itYRmCtDy7+79XlrPJXMsdgY7JKMJDY2RPvX4/44LM3HIbFm+xVoHmjTDYxViZLKd SM4+enlrj7ychVtj0sTx6JeQ5dOo7GVXmocSBfrjfsAZtzlFVnUQ42siq+hE9Y/PKPne 3RcBRU6HEkNq2eQ37uXrUFW8/fhmiiHn4LkEHISzPPOk5egKUuUrSv4Ecq4neE/+450e eFiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cN+Xh8Fd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:16 -0500 Message-Id: <20180527141324.11937-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22d Subject: [Qemu-devel] [PATCH 12/20] target/openrisc: Fix tlb flushing in mtspr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The previous code was confused, avoiding the flush of the old entry if the new entry is invalid. We need to flush the old page if the old entry is valid and the new page if the new entry is valid. This bug was masked by over-flushing elsewhere. Signed-off-by: Richard Henderson --- target/openrisc/sys_helper.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) -- 2.17.0 diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 8ad7a7d898..e00aaa332e 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -32,6 +32,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = openrisc_env_get_cpu(env); CPUState *cs = CPU(cpu); + target_ulong mr; int idx; switch (spr) { @@ -84,12 +85,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); - if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK); + mr = env->tlb.dtlb[idx].mr; + if (mr & 1) { + tlb_flush_page(cs, mr & TARGET_PAGE_MASK); + } + if (rb & 1) { + tlb_flush_page(cs, rb & TARGET_PAGE_MASK); } env->tlb.dtlb[idx].mr = rb; break; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); env->tlb.dtlb[idx].tr = rb; @@ -101,14 +105,18 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; + case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); - if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK); + mr = env->tlb.itlb[idx].mr; + if (mr & 1) { + tlb_flush_page(cs, mr & TARGET_PAGE_MASK); + } + if (rb & 1) { + tlb_flush_page(cs, rb & TARGET_PAGE_MASK); } env->tlb.itlb[idx].mr = rb; break; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); env->tlb.itlb[idx].tr = rb; @@ -120,6 +128,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ break; + case TO_SPR(5, 1): /* MACLO */ env->mac = deposit64(env->mac, 0, 32, rb); break; From patchwork Sun May 27 14:13:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137022 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1793085lji; Sun, 27 May 2018 07:26:17 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLSxTFy33OZEPsm77rh5/5DLsw3PkgsdT8IqxpdieIghWAZqTHI4bbPbxHWtM2B/48NnGZT X-Received: by 2002:a0c:bc90:: with SMTP id l16-v6mr8867425qvg.178.1527431177882; Sun, 27 May 2018 07:26:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527431177; cv=none; d=google.com; s=arc-20160816; b=rOSfsdEqjRnz2NVLlTVvGMccJhmvOTwWlVDAUWUgddxFxTiB9HSz6yTuPGzfPwapm8 D67rXOP8w8BXXcXC0HAmIGxelq01h1HollnMPOeVNtCtlY7Ly8ytCurT7f8W1eYo0PI0 h5ct4LLktSDAexcjzW2HJ8kebD+85mxPwVQdFos/qOcn2iy/L6upO7JZ88ctyftS5y4l ipzvsRjImRS30v2jiBSpb7z5MYDRG26aV7dtiQY7amW1FYEsFUky5tw8Cl7uXt/xJP5E UypB4pEpvkZMRH+gHGAw9Ny1aJuHtzpP1jw6U+GB11NYLiLD0X03qS+IwIJ2ixkvljDJ TfMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=+UJZeN1m/QtO2jUaIK6hf846Z5qo9hFYlZMDX00ufaI=; b=Qc7AZuTMcCtM0U5elvQ9ApZtXCu3pKsHyUbXdBRC0nzQQVHCAgHj6ZrcCtX7PZaz2W aT/hNOwXONw4t44GOiz9zFw3Z3YT3OGnmZH8VwsBG2NOnfQkmDuCLq/JG8FWZ7g/tx1b /o69rD/vSuIKBi45wHdkbE8I9d8K7D8WqA6J0jAxMTWd/8GMjnTRlDI9aK+MEbkXUuA7 f5E36gJIWERfrbFvccpdwaLmBdJSiuv9qIFbOyrNSQ3HaM39+7t/XV7jtXYEysx6J9no tpJW2TQZCx65+PKabPS3BrfX87ZFmTbEuqq7fM3bvVoJHgdYSUmX0QCGjaG4siTjwCiw CsAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MiVO6F7Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:17 -0500 Message-Id: <20180527141324.11937-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH 13/20] target/openrisc: Fix cpu_mmu_index X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The code in cpu_mmu_index does not properly honor SR_DME. This bug has workarounds elsewhere in that we flush the tlb more often than necessary, on the state changes that should be reflected in a change of mmu_index. Fixing this means that we can respect the mmu_index that is given to tlb_flush. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 23 +++++++++++++-------- target/openrisc/interrupt.c | 4 ---- target/openrisc/interrupt_helper.c | 15 +++----------- target/openrisc/mmu.c | 33 +++++++++++++++++++++++++++--- target/openrisc/sys_helper.c | 4 ---- target/openrisc/translate.c | 2 +- 6 files changed, 49 insertions(+), 32 deletions(-) -- 2.17.0 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 947ca00d8d..c48802ad8f 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -384,9 +384,12 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #include "exec/cpu-all.h" -#define TB_FLAGS_DFLAG 1 -#define TB_FLAGS_R0_0 2 +#define TB_FLAGS_SM SR_SM +#define TB_FLAGS_DME SR_DME +#define TB_FLAGS_IME SR_IME #define TB_FLAGS_OVE SR_OVE +#define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */ +#define TB_FLAGS_R0_0 4 /* reuse SR_IEE */ static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) { @@ -404,17 +407,21 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, { *pc = env->pc; *cs_base = 0; - *flags = (env->dflag - | (cpu_get_gpr(env, 0) == 0 ? TB_FLAGS_R0_0 : 0) - | (env->sr & SR_OVE)); + *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) { - if (!(env->sr & SR_IME)) { - return MMU_NOMMU_IDX; + int ret = MMU_NOMMU_IDX; /* mmu is disabled */ + + if (env->sr & (ifetch ? SR_IME : SR_DME)) { + /* The mmu is enabled; test supervisor state. */ + ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; } - return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; + + return ret; } static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index d9cb363fea..e28042856a 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -50,10 +50,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->eear = env->pc; } - /* For machine-state changed between user-mode and supervisor mode, - we need flush TLB when we enter&exit EXCP. */ - tlb_flush(cs); - env->esr = cpu_get_sr(env); env->sr &= ~SR_DME; env->sr &= ~SR_IME; diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c index a2e9003969..9c5489f5f7 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -25,16 +25,7 @@ void HELPER(rfe)(CPUOpenRISCState *env) { - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); -#ifndef CONFIG_USER_ONLY - int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ - (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); - if (need_flush_tlb) { - CPUState *cs = CPU(cpu); - tlb_flush(cs); - } -#endif - cpu->env.pc = cpu->env.epcr; - cpu->env.lock_addr = -1; - cpu_set_sr(&cpu->env, cpu->env.esr); + env->pc = env->epcr; + env->lock_addr = -1; + cpu_set_sr(env, env->esr); } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 23edd8c78c..11b8187cda 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -246,9 +246,36 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret = openrisc_cpu_handle_mmu_fault(cs, addr, size, - access_type, mmu_idx); - if (ret) { + OpenRISCCPU *cpu = OPENRISC_CPU(cs); + int ret, prot = 0; + hwaddr physical = 0; + + if (mmu_idx == MMU_NOMMU_IDX) { + ret = get_phys_nommu(&physical, &prot, addr); + } else { + bool super = mmu_idx == MMU_SUPERVISOR_IDX; + if (access_type == MMU_INST_FETCH) { + ret = get_phys_code(cpu, &physical, &prot, addr, 2, super); + } else { + ret = get_phys_data(cpu, &physical, &prot, addr, + access_type == MMU_DATA_STORE, super); + } + } + + if (ret == TLBRET_MATCH) { + tlb_set_page(cs, addr & TARGET_PAGE_MASK, + physical & TARGET_PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); + } else if (ret < 0) { + int rw; + if (access_type == MMU_INST_FETCH) { + rw = 2; + } else if (access_type == MMU_DATA_STORE) { + rw = 1; + } else { + rw = 0; + } + cpu_openrisc_raise_mmu_exception(cpu, addr, rw, ret); /* Raise Exception. */ cpu_loop_exit_restore(cs, retaddr); } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index e00aaa332e..0a74c9522f 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -56,10 +56,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) break; case TO_SPR(0, 17): /* SR */ - if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^ - (rb & (SR_IME | SR_DME | SR_SM))) { - tlb_flush(cs); - } cpu_set_sr(env, rb); break; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index b26c473870..59e2df01cf 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -59,7 +59,7 @@ static inline bool is_user(DisasContext *dc) #ifdef CONFIG_USER_ONLY return true; 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:18 -0500 Message-Id: <20180527141324.11937-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::235 Subject: [Qemu-devel] [PATCH 14/20] target/openrisc: Use identical sizes for ITLB and DTLB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The sizes are already the same, however, we can improve things if they are identical by design. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 10 ++++------ target/openrisc/machine.c | 4 ++-- target/openrisc/mmu.c | 4 ++-- target/openrisc/sys_helper.c | 16 ++++++++-------- 4 files changed, 16 insertions(+), 18 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index c48802ad8f..53abe965e8 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,10 +222,8 @@ enum { /* TLB size */ enum { - DTLB_SIZE = 64, - DTLB_MASK = (DTLB_SIZE-1), - ITLB_SIZE = 64, - ITLB_MASK = (ITLB_SIZE-1), + TLB_SIZE = 64, + TLB_MASK = TLB_SIZE - 1, }; /* TLB prot */ @@ -254,8 +252,8 @@ typedef struct OpenRISCTLBEntry { #ifndef CONFIG_USER_ONLY typedef struct CPUOpenRISCTLBContext { - OpenRISCTLBEntry itlb[ITLB_SIZE]; - OpenRISCTLBEntry dtlb[DTLB_SIZE]; + OpenRISCTLBEntry itlb[TLB_SIZE]; + OpenRISCTLBEntry dtlb[TLB_SIZE]; int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, hwaddr *physical, diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index b795b56dc6..3fc837b925 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -42,9 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { - VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), - VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), VMSTATE_END_OF_LIST() } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 11b8187cda..ee3016a8b9 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -41,7 +41,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, target_ulong address, int rw, bool supervisor) { int vpn = address >> TARGET_PAGE_BITS; - int idx = vpn & ITLB_MASK; + int idx = vpn & TLB_MASK; int right = 0; uint32_t mr = cpu->env.tlb.itlb[idx].mr; uint32_t tr = cpu->env.tlb.itlb[idx].tr; @@ -74,7 +74,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, target_ulong address, int rw, bool supervisor) { int vpn = address >> TARGET_PAGE_BITS; - int idx = vpn & DTLB_MASK; + int idx = vpn & TLB_MASK; int right = 0; uint32_t mr = cpu->env.tlb.dtlb[idx].mr; uint32_t tr = cpu->env.tlb.dtlb[idx].tr; diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 0a74c9522f..7254aa9830 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -79,7 +79,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) idx = (spr - 1024); env->shadow_gpr[idx / 32][idx % 32] = rb; - case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ + case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); mr = env->tlb.dtlb[idx].mr; if (mr & 1) { @@ -90,7 +90,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) } env->tlb.dtlb[idx].mr = rb; break; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ + case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); env->tlb.dtlb[idx].tr = rb; break; @@ -102,7 +102,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; - case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ + case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); mr = env->tlb.itlb[idx].mr; if (mr & 1) { @@ -113,7 +113,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) } env->tlb.itlb[idx].mr = rb; break; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ + case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); env->tlb.itlb[idx].tr = rb; break; @@ -246,11 +246,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, idx = (spr - 1024); return env->shadow_gpr[idx / 32][idx % 32]; - case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ + case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); return env->tlb.dtlb[idx].mr; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ + case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); return env->tlb.dtlb[idx].tr; @@ -262,11 +262,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; - case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ + case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); return env->tlb.itlb[idx].mr; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ + case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); return env->tlb.itlb[idx].tr; From patchwork Sun May 27 14:13:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137020 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1790858lji; Sun, 27 May 2018 07:23:26 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJFpWPbKKflO3pd5+ThwnDDQ3BMPj0hEBgKCV8xFfJ9RF9buptWiPrG4wKnOiySbaS/u5Le X-Received: by 2002:a37:b204:: with SMTP id b4-v6mr8831492qkf.149.1527431006660; Sun, 27 May 2018 07:23:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527431006; cv=none; d=google.com; s=arc-20160816; b=OUuPMOgJSDhe7JYT7dyH43Dga4cLy7TnAMBOodhRKl1iRf+YHnNXQESNwcokFgSxS+ sVKL2MvnzLQodQQQCzgbdUuN0QVfqAkaup2iPD4SZmgU7tSpzNYdKXzIpjRn63CCOt25 A6TNC71W+UC3A/jIBdHQMWCdSI5CjvJTegudLgZe61V7PQC/S2HZZ8p5fGhFDZ4atf4h 1gNYgHViNPLo5e0cV4I0ELogg82ut63Y7CQLCJcJjrwNOC9sYDX0aX1UL9Xe/XZvz5m9 HjrTxYUzCjec+Pqqp/kBWY1UyYnRitp94+KkXhbVBlGFy4KMHqkaqaTccokN0yP4xZPR l+QQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Ulh+EzcysOtJLTEaTwR+l2wPSZX/KDvqmQX2jTTu/AY=; b=skBmSiqCZSHeANqX+AHAsvhvtJN9PKNYkujGuCeK4qr5B5COuDH1jNb/8LGn+9Sprk c5MVNQe5VeVxmJrEn9TPDGoRDQELRzc5n3o4ZYwbEmYKtYrpm7DCes/xk6/+euvXSj++ 2bmVSysf+jb3qGuklObftwucIsbYPRIOsbG9lUzC8wllQI6L4YtjueA9AimwOazYRdOY SIxVFSm9Nq3SKI6s3jjEz9+PzTgLaAIsgjpAahTtOGvxW5rCh5arEuxKERXjjJgapPGE iWNmbC7qJ8wUx9/wHcWAnKGLpc827lhdJUEcv+rXVBkXRfyIZGzHdY+ax+PECWRtwEgv nnFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CnCO9JdT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:19 -0500 Message-Id: <20180527141324.11937-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::236 Subject: [Qemu-devel] [PATCH 15/20] target/openrisc: Stub out handle_mmu_fault for softmmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This hook is only used by CONFIG_USER_ONLY. Signed-off-by: Richard Henderson --- target/openrisc/mmu.c | 35 +++++------------------------------ 1 file changed, 5 insertions(+), 30 deletions(-) -- 2.17.0 diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index ee3016a8b9..2f1f16fd6b 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -177,42 +177,17 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, cpu->env.lock_addr = -1; } -#ifndef CONFIG_USER_ONLY int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { +#ifdef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); - int ret = 0; - hwaddr physical = 0; - int prot = 0; - - ret = get_phys_addr(cpu, &physical, &prot, address, rw); - - if (ret == TLBRET_MATCH) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); - ret = 0; - } else if (ret < 0) { - cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret); - ret = 1; - } - - return ret; -} + cpu_openrisc_raise_mmu_exception(cpu, address, rw, 0); + return 1; #else -int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - int ret = 0; - - cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret); - ret = 1; - - return ret; -} + g_assert_not_reached (); #endif +} #ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) From patchwork Sun May 27 14:13:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137029 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1796687lji; Sun, 27 May 2018 07:30:54 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIVuoLW0K60sre6ldsqkKQqrEf1H3Fx/jDaaD3ro7BerT05FOjMXKvp6Mqma/LyzQ9vUoQ3 X-Received: by 2002:aed:20e7:: with SMTP id 94-v6mr9253008qtb.19.1527431454108; Sun, 27 May 2018 07:30:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527431454; cv=none; d=google.com; s=arc-20160816; b=mRi/wAWaWjzf+qPQ4CymDRT1qh2x0F54xXFquEq/m0jBBbsmczN2uOO4VdGBF44P2C RvtVfOb73jN6RINQL5nw6cfS5iMRFccAsRWIS070uMpLpvJUCEFsLvQFpRlhX8fyWv6L NExAEup7TEyBIaZo0AQCTsLevGKtO+eCPAaDDQgSv2RJvtPeU4A9CdGkYQAgJvr3Xmi9 6/ZqY32elG1z3gSufQ/dKXkvxB8Vl/KxJl3G/l3fKGAvvn5hjJHmh4hgNiZrEZAp274I 5Qd3igbPgssEO+HCh7bEuplTv3xwMHqkwd6sxNlX6NqCTpw2tbo9YW0OFYh0a2sthFbw WyjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=mVb3t4+y7hnsheVsWbac+TnqOmfOqpORDJrwAHjqGAQ=; b=MxIKyv8+6C+XoWEmcAAQbyEzXcCrenQpJjDIzX6rltsq2B25LXeSKc4u27QAfRoOXs uu26xfp1yoEEsE2y6h9431FNSrD1BNKTOknGJwLBp5uMfeGlKVezrTnuaFixH4lpypQB NEudioid/y/vjwl82GubiCkNabFUCureRuYB9QxcEibBuNeZkU6h1Fmd0nNXao/m3a5L JXrWtamxmqPfReTYOXaoiiFx8L1SF14pm1UK1Uc//+QXwUQS0FaFl7nuleyX6X9SrC8K QX3aU5LJUVoc1WOMwNPtP1F7d+R77LtTgxhEvtrJMIA3KjKyhNZSH6UxkngdyO0Ump1t ol9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VoYPgJUm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:20 -0500 Message-Id: <20180527141324.11937-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::234 Subject: [Qemu-devel] [PATCH 16/20] target/openrisc: Log interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/openrisc/interrupt.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index e28042856a..138ad17f00 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -32,6 +32,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = &cpu->env; + int exception = cs->exception_index; env->epcr = env->pc; if (env->dflag) { @@ -41,12 +42,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } else { env->sr &= ~SR_DSX; } - if (cs->exception_index == EXCP_SYSCALL) { + if (exception == EXCP_SYSCALL) { env->epcr += 4; } /* When we have an illegal instruction the error effective address shall be set to the illegal instruction address. */ - if (cs->exception_index == EXCP_ILLEGAL) { + if (exception == EXCP_ILLEGAL) { env->eear = env->pc; } @@ -60,8 +61,27 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->pmr &= ~PMR_SME; env->lock_addr = -1; - if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { - hwaddr vect_pc = cs->exception_index << 8; + if (exception > 0 && exception < EXCP_NR) { + static const char * const int_name[EXCP_NR] = { + [EXCP_RESET] = "RESET", + [EXCP_BUSERR] = "BUSERR (bus error)", + [EXCP_DPF] = "DFP (data protection fault)", + [EXCP_IPF] = "IPF (code protection fault)", + [EXCP_TICK] = "TICK (timer interrupt)", + [EXCP_ALIGN] = "ALIGN", + [EXCP_ILLEGAL] = "ILLEGAL", + [EXCP_INT] = "INT (device interrupt)", + [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)", + [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)", + [EXCP_RANGE] = "RANGE", + [EXCP_SYSCALL] = "SYSCALL", + [EXCP_FPE] = "FPE", + [EXCP_TRAP] = "TRAP", + }; + + qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]); + + hwaddr vect_pc = exception << 8; if (env->cpucfgr & CPUCFGR_EVBARP) { vect_pc |= env->evbar; } @@ -70,7 +90,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } env->pc = vect_pc; } else { - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", exception); } #endif From patchwork Sun May 27 14:13:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137021 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1793062lji; Sun, 27 May 2018 07:26:16 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKQNr8sMSJzir2rezpwhBtcv99ECss4L7Wi6H7GmhLaOW/JJxyQl5J5HPTTpvceJE38KS+a X-Received: by 2002:a0c:96cf:: with SMTP id b15-v6mr9132819qvd.124.1527431176161; Sun, 27 May 2018 07:26:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527431176; cv=none; d=google.com; s=arc-20160816; b=Y1sAUo5CjYv3z/856RGVXlt69IKnW9P9/kjo8sw1Ov+kkP44/cNiTWytirw4PlGKnR JqJzdlNkwo2HzSD27IdC/cOAMaiGmJLT+fqVH0hUF2dw+jhRYZxnGSlIONodGD9BQ+6n OV618YyOevQ/yb9PC6v7dqFlgH2xG4SA0EmK4wsqLUNkFMP1DcBzeSBbQs0U6N4r9Jzk GLH3XOP5jQKscJ/9yu5DJNQ9P4MKqLC9NhKlzS71bjr376AbZcaq0pZ9sHdAI3hQfJZ0 8NkJzCJRK1TKd/Doejnv9B/qKOoQm2kfwfIzoSPMmtYf4uSre9+vUiyLJWQhnIFfUbAq LCsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=tvjSvxGn+nz0RcAR2Ze2jt1il5v9vY+Bsm/f1+/7924=; b=YyEf43m1Ie1xSiTZz62lVTjSsCPPbrJH2BVq3AocMHPthUVaYKWCn/rGrxiqFDYmJn EPs9jYm1EiLPBymZIUlw9POvVF0DHgsWRPGMKaFM3wKnVH2woa5O33Ht4JVb25vVJ3RG l7BpXFAX7c8wxaMWXxuNrSv6f+ufa+1WrpLtapeqXTOs1xvgZTR0LrXrRtAOXMY75HBq i9axwnK8oNDD/yKTt15KekQ9BcvR8OrieHnXD0jU2i4DZxoeXtkHv2ee1r7WPL1E08Hz /FRkXD4+KOSv2yjSSU2bHUAC9aaX1VxKLlz1ZNDHPIXwlAr0fPUt0bbt/+8jJk9mg8CR fAig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GrT73jl7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:21 -0500 Message-Id: <20180527141324.11937-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::229 Subject: [Qemu-devel] [PATCH 17/20] target/openrisc: Increase the TLB size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The architecture supports 128 TLB entries. There is no reason not to provide all of them. In the process we need to fix a bug that failed to parameterize the configuration register that tells the operating system the number of entries. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 2 +- target/openrisc/cpu.c | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) -- 2.17.0 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 53abe965e8..8035654087 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,7 +222,7 @@ enum { /* TLB size */ enum { - TLB_SIZE = 64, + TLB_SIZE = 128, TLB_MASK = TLB_SIZE - 1, }; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b2711a961e..75c83d15d1 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -53,8 +53,10 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; - cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); - cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); + cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) + | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); + cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) + | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; From patchwork Sun May 27 14:13:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137027 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1795133lji; Sun, 27 May 2018 07:28:58 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIRfgXP8m0206FVx+9qm7wkj+biBz7haJeEhsIlP0ofXti/UGOXIV5QDybPOsEn4RM6Fc0E X-Received: by 2002:ac8:72d0:: with SMTP id o16-v6mr9337946qtp.23.1527431338726; Sun, 27 May 2018 07:28:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527431338; cv=none; d=google.com; s=arc-20160816; b=fnz4Lr6UfK67w76jitcGP30Yg6Bq20B/vGCzty8vuQ1NhwO9DHyTPMGxsHJBvo6api nCnn2GXmjooSMuU2uxQVgBA5XJh43yJZCz3NjIj1WP08MKyVZbijgVeM5T3p9zFXiTI2 zHntWKjdVTtSK3L4p+jAh8LUKDUReHqKhCQ8pdEZzZrM/N36UDO+GxQxt8ZjZA6LjEFb Jovt9xbyQDwvaQOOUFkWUpguur5di7y/oGd7DuBt+trBjKBhsx7JKvOJKpVMhng+1s0g jkYhYp6aBOo/nPk902PKzz/Z4nCtugjjJwUyTMhw32GFEEmkMBK5p/Es0uPomh8mytk4 KsuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=jRziV57B8TnXQI4U5gjtWx3H+P+kICeXB5CDaglPqUM=; b=txKWLcGb9kCK7slUboTyv/gfogGmFfoER4zknG6yYoVuwAj0w0cBxU8xJprkXhxWnk Dhpa7kEsQYi+gxumokLoaVaIuGH6OZ2713si53OH7uLXGeetxKbopZUNza/3gKpbuQHL jScQcw6x2/FJdLn8u9sdJC3npf3/aba8JmMdFTqmBhwL8Nozb6gWpfjPMgl47a8wqF3u D53bgcGbnF5yxo6I+vAiji0n2JVZLMatE9G7bAaS/RfCF1PcP52X7ZCL4CQPaoUNzdf+ 8WlIelAf0qP1XYvqGDROTw/WxwjL8Wyp2JN4Jt+YdfGjfWhw/CbCmI29yj204QTKSoeJ 4/VA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=I8kpqJm3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:22 -0500 Message-Id: <20180527141324.11937-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH 18/20] target/openrisc: Reorg tlb lookup X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While openrisc has a split i/d tlb, qemu does not. Perform a lookup on both i & d tlbs in parallel and put the composite rights into qemu's tlb. This avoids ping-ponging the qemu tlb between EXEC and READ. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 8 -- target/openrisc/mmu.c | 254 +++++++++++++++--------------------------- 2 files changed, 90 insertions(+), 172 deletions(-) -- 2.17.0 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 8035654087..1efffa5269 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -237,14 +237,6 @@ enum { UXE = (1 << 7), }; -/* check if tlb available */ -enum { - TLBRET_INVALID = -3, - TLBRET_NOMATCH = -2, - TLBRET_BADADDR = -1, - TLBRET_MATCH = 0 -}; - typedef struct OpenRISCTLBEntry { uint32_t mr; uint32_t tr; diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 2f1f16fd6b..9a7170779d 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -29,148 +29,78 @@ #endif #ifndef CONFIG_USER_ONLY -static inline int get_phys_nommu(hwaddr *physical, int *prot, - target_ulong address) +static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, + target_ulong address) { - *physical = address; + *phys_addr = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TLBRET_MATCH; } -static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, - target_ulong address, int rw, bool supervisor) +static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot, + target_ulong addr, int need, bool super) { - int vpn = address >> TARGET_PAGE_BITS; - int idx = vpn & TLB_MASK; - int right = 0; - uint32_t mr = cpu->env.tlb.itlb[idx].mr; - uint32_t tr = cpu->env.tlb.itlb[idx].tr; + int idx = (addr >> TARGET_PAGE_BITS) & TLB_MASK; + uint32_t imr = cpu->env.tlb.itlb[idx].mr; + uint32_t itr = cpu->env.tlb.itlb[idx].tr; + uint32_t dmr = cpu->env.tlb.dtlb[idx].mr; + uint32_t dtr = cpu->env.tlb.dtlb[idx].tr; + int right, match, valid; - if ((mr >> TARGET_PAGE_BITS) != vpn) { - return TLBRET_NOMATCH; - } - if (!(mr & 1)) { - return TLBRET_INVALID; - } - if (supervisor) { - if (tr & SXE) { - right |= PAGE_EXEC; - } - } else { - if (tr & UXE) { - right |= PAGE_EXEC; + /* If the ITLB and DTLB indexes map to the same page, we want to + load all permissions all at once. If the destination pages do + not match, zap the one we don't need. */ + if (unlikely((itr ^ dtr) & TARGET_PAGE_MASK)) { + if (need & PAGE_EXEC) { + dmr = dtr = 0; + } else { + imr = itr = 0; } } - if ((rw & 2) && ((right & PAGE_EXEC) == 0)) { - return TLBRET_BADADDR; - } - *physical = (tr & TARGET_PAGE_MASK) | (address & (TARGET_PAGE_SIZE-1)); + /* Check if either of the entries matches the source address. */ + match = (imr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_EXEC; + match |= (dmr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_READ | PAGE_WRITE; + + /* Check if either of the entries is valid. */ + valid = imr & 1 ? PAGE_EXEC : 0; + valid |= dmr & 1 ? PAGE_READ | PAGE_WRITE : 0; + valid &= match; + + /* Collect the permissions from the entries. */ + right = itr & (super ? SXE : UXE) ? PAGE_EXEC : 0; + right |= dtr & (super ? SRE : URE) ? PAGE_READ : 0; + right |= dtr & (super ? SWE : UWE) ? PAGE_WRITE : 0; + right &= valid; + + /* Note that above we validated that itr and dtr match on page. + So oring them together changes nothing without having to + check which one we needed. We also want to store to these + variables even on failure, as it avoids compiler warnings. */ + *phys_addr = ((itr | dtr) & TARGET_PAGE_MASK) | (addr & ~TARGET_PAGE_MASK); *prot = right; - return TLBRET_MATCH; -} -static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, - target_ulong address, int rw, bool supervisor) -{ - int vpn = address >> TARGET_PAGE_BITS; - int idx = vpn & TLB_MASK; - int right = 0; - uint32_t mr = cpu->env.tlb.dtlb[idx].mr; - uint32_t tr = cpu->env.tlb.dtlb[idx].tr; + qemu_log_mask(CPU_LOG_MMU, + "MMU lookup: need %d match %d valid %d right %d -> %s\n", + need, match, valid, right, (need & right) ? "OK" : "FAIL"); - if ((mr >> TARGET_PAGE_BITS) != vpn) { - return TLBRET_NOMATCH; + /* Check the collective permissions are present. */ + if (likely(need & right)) { + return 0; /* success! */ } - if (!(mr & 1)) { - return TLBRET_INVALID; - } - if (supervisor) { - if (tr & SRE) { - right |= PAGE_READ; - } - if (tr & SWE) { - right |= PAGE_WRITE; - } + + /* Determine what kind of failure we have. */ + if (need & valid) { + return need & PAGE_EXEC ? EXCP_IPF : EXCP_DPF; } else { - if (tr & URE) { - right |= PAGE_READ; - } - if (tr & UWE) { - right |= PAGE_WRITE; - } + return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS; } - - if (!(rw & 1) && ((right & PAGE_READ) == 0)) { - return TLBRET_BADADDR; - } - if ((rw & 1) && ((right & PAGE_WRITE) == 0)) { - return TLBRET_BADADDR; - } - - *physical = (tr & TARGET_PAGE_MASK) | (address & (TARGET_PAGE_SIZE-1)); - *prot = right; - return TLBRET_MATCH; -} - -static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical, - int *prot, target_ulong address, int rw) -{ - bool supervisor = (cpu->env.sr & SR_SM) != 0; - int ret; - - /* Assume nommu results for a moment. */ - ret = get_phys_nommu(physical, prot, address); - - /* Overwrite with TLB lookup if enabled. */ - if (rw == MMU_INST_FETCH) { - if (cpu->env.sr & SR_IME) { - ret = get_phys_code(cpu, physical, prot, address, rw, supervisor); - } - } else { - if (cpu->env.sr & SR_DME) { - ret = get_phys_data(cpu, physical, prot, address, rw, supervisor); - } - } - - return ret; } #endif -static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, - target_ulong address, - int rw, int tlb_error) +static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, + int exception) { CPUState *cs = CPU(cpu); - int exception = 0; - - switch (tlb_error) { - default: - if (rw == 2) { - exception = EXCP_IPF; - } else { - exception = EXCP_DPF; - } - break; -#ifndef CONFIG_USER_ONLY - case TLBRET_BADADDR: - if (rw == 2) { - exception = EXCP_IPF; - } else { - exception = EXCP_DPF; - } - break; - case TLBRET_INVALID: - case TLBRET_NOMATCH: - /* No TLB match for a mapped address */ - if (rw == 2) { - exception = EXCP_ITLBMISS; - } else { - exception = EXCP_DTLBMISS; - } - break; -#endif - } cs->exception_index = exception; cpu->env.eear = address; @@ -182,7 +112,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, { #ifdef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); - cpu_openrisc_raise_mmu_exception(cpu, address, rw, 0); + raise_mmu_exception(cpu, address, EXCP_DPF); return 1; #else g_assert_not_reached (); @@ -193,27 +123,32 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); + int prot, excp, sr = cpu->env.sr; hwaddr phys_addr; - int prot; - int miss; - /* Check memory for any kind of address, since during debug the - gdb can ask for anything, check data tlb for address */ - miss = get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + switch (sr & (SR_DME | SR_IME)) { + case SR_DME | SR_IME: + /* The mmu is definitely enabled. */ + excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, + PROT_EXEC | PROT_READ | PROT_WRITE, + (sr & SR_SM) != 0); + return excp ? -1 : phys_addr; - /* Check instruction tlb */ - if (miss) { - miss = get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETCH); - } + default: + /* The mmu is partially enabled, and we don't really have + a "real" access type. Begin by trying the mmu, but if + that fails try again without. */ + excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, + PROT_EXEC | PROT_READ | PROT_WRITE, + (sr & SR_SM) != 0); + if (!excp) { + return phys_addr; + } + /* fallthru */ - /* Last, fall back to a plain address */ - if (miss) { - miss = get_phys_nommu(&phys_addr, &prot, addr); - } - - if (miss) { - return -1; - } else { + case 0: + /* The mmu is definitely disabled; lookups never fail. */ + get_phys_nommu(&phys_addr, &prot, addr); return phys_addr; } } @@ -222,37 +157,28 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); - int ret, prot = 0; - hwaddr physical = 0; + int prot, excp; + hwaddr phys_addr; if (mmu_idx == MMU_NOMMU_IDX) { - ret = get_phys_nommu(&physical, &prot, addr); + /* The mmu is disabled; lookups never fail. */ + get_phys_nommu(&phys_addr, &prot, addr); + excp = 0; } else { bool super = mmu_idx == MMU_SUPERVISOR_IDX; - if (access_type == MMU_INST_FETCH) { - ret = get_phys_code(cpu, &physical, &prot, addr, 2, super); - } else { - ret = get_phys_data(cpu, &physical, &prot, addr, - access_type == MMU_DATA_STORE, super); - } + int need = (access_type == MMU_INST_FETCH ? PROT_EXEC + : access_type == MMU_DATA_STORE ? PROT_WRITE + : PROT_READ); + excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); } - if (ret == TLBRET_MATCH) { - tlb_set_page(cs, addr & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); - } else if (ret < 0) { - int rw; - if (access_type == MMU_INST_FETCH) { - rw = 2; - } else if (access_type == MMU_DATA_STORE) { - rw = 1; - } else { - rw = 0; - } - cpu_openrisc_raise_mmu_exception(cpu, addr, rw, ret); - /* Raise Exception. */ + if (unlikely(excp)) { + raise_mmu_exception(cpu, addr, excp); cpu_loop_exit_restore(cs, retaddr); } + + tlb_set_page(cs, addr & TARGET_PAGE_MASK, + phys_addr & TARGET_PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); } #endif From patchwork Sun May 27 14:13:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 137023 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1793267lji; Sun, 27 May 2018 07:26:30 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIPO7jcShO5xFVOxFwwGIEjm7UyqkKIVTJwpvs+L2PEL16OwkKg+ZnvvAa1o9+VcfQyXwOB X-Received: by 2002:ac8:1bf6:: with SMTP id m51-v6mr9384869qtk.152.1527431190144; Sun, 27 May 2018 07:26:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527431190; cv=none; d=google.com; s=arc-20160816; b=CJCFNbVOLYUesHqUCJKDNRwwVGDq2aCATJKEYUBORwppex6dJZ+O/rfuottJKsolML uyb3CR7NbZNdQ0h6Ubd/OXon7qBGkP765uEq3P9bYHfi39+HSreZ3tF+sMadjlYRJOf9 LNzltf8PDmCWCiwPFGtaqcADT2K3zxbSNS1U2WZhwkZyuejIh/RDocxaBY5FkN77WXqA nHo/162dIOu4uMOmtZ1iog7ZCIV4cktFmQM+tMNTUuBQPWIjw/d9gm75CVFuRPVzNY0N wOlnvYuP1YvMwSLsvBCeip4O+BChP097P1TbaRRrNFZlE25HpBD49r0BNwOOlNCkucK3 9E9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=356CYkQHgEktazXd09Zm4xHU+UDMGKMvh8UmtPzxtRE=; b=ET7gIIJ5WajJOWY8C0e1FX74ZVbPsyCBJXfQDCjOJJwFqrqLNQRhMtlmjlB9hvpZY8 1IxZLviZa5VR8+WUliiOdh/lEDJKQp882JHf0H/qBMdJVNFHFlL1s0cnkId67TpucNzG A65PYNkZJ2NkVV40E9lJ545AUbOII7g7RFMedimWmtu1IGoCVn8VPu1sdS7P2i3XXg1a +RhwRmMNulVdUTfh2TwH4RWnixIw2/XDeiZ2QX2I3P6qHvnJFCNTfc+dsrZOLDuYzM06 pv5F4pB2Pzpgyr9naK14mXRtFsFzL9tIyAvSSy+NzEAU97Af1LMi3zgYFHSw1afxw8vE SrKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DK+gr02b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id b89-v6sm66680075pfd.85.2018.05.27.07.13.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 27 May 2018 07:13:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 27 May 2018 09:13:23 -0500 Message-Id: <20180527141324.11937-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180527141324.11937-1-richard.henderson@linaro.org> References: <20180527141324.11937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH 19/20] target/openrisc: Add print_insn_or1k X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than emit disassembly while translating, reuse the generated decoder to build a separate disassembler. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 1 + target/openrisc/cpu.c | 6 ++ target/openrisc/disas.c | 171 ++++++++++++++++++++++++++++++++++ target/openrisc/translate.c | 114 ----------------------- target/openrisc/Makefile.objs | 3 +- 5 files changed, 180 insertions(+), 115 deletions(-) create mode 100644 target/openrisc/disas.c -- 2.17.0 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 1efffa5269..f1b31bc24a 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -348,6 +348,7 @@ void openrisc_translate_init(void); int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); +int print_insn_or1k(bfd_vma addr, disassemble_info *info); #define cpu_list cpu_openrisc_list #define cpu_signal_handler cpu_openrisc_signal_handler diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 75c83d15d1..d1ef4c737c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -36,6 +36,11 @@ static bool openrisc_cpu_has_work(CPUState *cs) CPU_INTERRUPT_TIMER); } +static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) +{ + info->print_insn = print_insn_or1k; +} + /* CPUClass::reset() */ static void openrisc_cpu_reset(CPUState *s) { @@ -151,6 +156,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) #endif cc->gdb_num_core_regs = 32 + 3; cc->tcg_initialize = openrisc_translate_init; + cc->disas_set_info = openrisc_disas_set_info; } /* Sort alphabetically by type name, except for "any". */ diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c new file mode 100644 index 0000000000..db0caa1805 --- /dev/null +++ b/target/openrisc/disas.c @@ -0,0 +1,171 @@ +/* + * OpenRISC disassembler + * + * Copyright (c) 2018 Richard Henderson + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "disas/bfd.h" +#include "qemu/bitops.h" +#include "cpu.h" + +typedef disassemble_info DisasContext; + +/* Include the auto-generated decoder. */ +#include "decode.inc.c" + +#define output(mnemonic, format, ...) \ + info->fprintf_func(info->stream, "%-9s " format, \ + mnemonic, ##__VA_ARGS__) + +int print_insn_or1k(bfd_vma addr, disassemble_info *info) +{ + bfd_byte buffer[4]; + uint32_t insn; + int status; + + status = info->read_memory_func(addr, buffer, 4, info); + if (status != 0) + { + info->memory_error_func(status, addr, info); + return -1; + } + insn = bfd_getb32(buffer); + + if (!decode(info, insn)) { + output(".long", "%#08x", insn); + } + return 4; +} + +#define INSN(opcode, format, ...) \ +static bool trans_l_##opcode(disassemble_info *info, \ + arg_l_##opcode *a, uint32_t insn) \ +{ \ + output("l." #opcode, format, ##__VA_ARGS__); \ + return true; \ +} + +INSN(add, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(addc, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(sub, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(and, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(or, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(xor, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(sll, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(srl, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(sra, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(ror, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(exths, "r%d, r%d", a->d, a->a) +INSN(extbs, "r%d, r%d", a->d, a->a) +INSN(exthz, "r%d, r%d", a->d, a->a) +INSN(extbz, "r%d, r%d", a->d, a->a) +INSN(cmov, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(ff1, "r%d, r%d", a->d, a->a) +INSN(fl1, "r%d, r%d", a->d, a->a) +INSN(mul, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(mulu, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(div, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(divu, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(muld, "r%d, r%d", a->a, a->b) +INSN(muldu, "r%d, r%d", a->a, a->b) +INSN(j, "%d", a->n) +INSN(jal, "%d", a->n) +INSN(bf, "%d", a->n) +INSN(bnf, "%d", a->n) +INSN(jr, "r%d", a->b) +INSN(jalr, "r%d", a->b) +INSN(lwa, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lwz, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lws, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lbz, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lbs, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lhz, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lhs, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(swa, "%d(r%d), r%d", a->i, a->a, a->b) +INSN(sw, "%d(r%d), r%d", a->i, a->a, a->b) +INSN(sb, "%d(r%d), r%d", a->i, a->a, a->b) +INSN(sh, "%d(r%d), r%d", a->i, a->a, a->b) +INSN(nop, "") +INSN(addi, "r%d, r%d, %d", a->d, a->a, a->i) +INSN(addic, "r%d, r%d, %d", a->d, a->a, a->i) +INSN(muli, "r%d, r%d, %d", a->d, a->a, a->i) +INSN(maci, "r%d, %d", a->a, a->i) +INSN(andi, "r%d, r%d, %d", a->d, a->a, a->k) +INSN(ori, "r%d, r%d, %d", a->d, a->a, a->k) +INSN(xori, "r%d, r%d, %d", a->d, a->a, a->i) +INSN(mfspr, "r%d, r%d, %d", a->d, a->a, a->k) +INSN(mtspr, "r%d, r%d, %d", a->a, a->b, a->k) +INSN(mac, "r%d, r%d", a->a, a->b) +INSN(msb, "r%d, r%d", a->a, a->b) +INSN(macu, "r%d, r%d", a->a, a->b) +INSN(msbu, "r%d, r%d", a->a, a->b) +INSN(slli, "r%d, r%d, %d", a->d, a->a, a->l) +INSN(srli, "r%d, r%d, %d", a->d, a->a, a->l) +INSN(srai, "r%d, r%d, %d", a->d, a->a, a->l) +INSN(rori, "r%d, r%d, %d", a->d, a->a, a->l) +INSN(movhi, "r%d, %d", a->d, a->k) +INSN(macrc, "r%d", a->d) +INSN(sfeq, "r%d, r%d", a->a, a->b) +INSN(sfne, "r%d, r%d", a->a, a->b) +INSN(sfgtu, "r%d, r%d", a->a, a->b) +INSN(sfgeu, "r%d, r%d", a->a, a->b) +INSN(sfltu, "r%d, r%d", a->a, a->b) +INSN(sfleu, "r%d, r%d", a->a, a->b) +INSN(sfgts, "r%d, r%d", a->a, a->b) +INSN(sfges, "r%d, r%d", a->a, a->b) +INSN(sflts, "r%d, r%d", a->a, a->b) +INSN(sfles, "r%d, r%d", a->a, a->b) +INSN(sfeqi, "r%d, %d", a->a, a->i) +INSN(sfnei, "r%d, %d", a->a, a->i) +INSN(sfgtui, "r%d, %d", a->a, a->i) +INSN(sfgeui, "r%d, %d", a->a, a->i) +INSN(sfltui, "r%d, %d", a->a, a->i) +INSN(sfleui, "r%d, %d", a->a, a->i) +INSN(sfgtsi, "r%d, %d", a->a, a->i) +INSN(sfgesi, "r%d, %d", a->a, a->i) +INSN(sfltsi, "r%d, %d", a->a, a->i) +INSN(sflesi, "r%d, %d", a->a, a->i) +INSN(sys, "%d", a->k) +INSN(trap, "%d", a->k) +INSN(msync, "") +INSN(psync, "") +INSN(csync, "") +INSN(rfe, "") + +#define FP_INSN(opcode, suffix, format, ...) \ +static bool trans_lf_##opcode##_##suffix(disassemble_info *info, \ + arg_lf_##opcode##_##suffix *a, uint32_t insn) \ +{ \ + output("lf." #opcode "." #suffix, format, ##__VA_ARGS__); \ + return true; \ +} + +FP_INSN(add,s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(sub,s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(mul,s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(div,s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(rem,s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(itof,s, "r%d, r%d", a->d, a->a) +FP_INSN(ftoi,s, "r%d, r%d", a->d, a->a) +FP_INSN(madd,s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(sfeq,s, "r%d, r%d", a->a, a->b) +FP_INSN(sfne,s, "r%d, r%d", a->a, a->b) +FP_INSN(sfgt,s, "r%d, r%d", a->a, a->b) +FP_INSN(sfge,s, "r%d, r%d", a->a, a->b) +FP_INSN(sflt,s, "r%d, r%d", a->a, a->b) +FP_INSN(sfle,s, "r%d, r%d", a->a, a->b) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 59e2df01cf..fe9fa8d030 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -36,10 +36,6 @@ #include "trace-tcg.h" #include "exec/log.h" -#define LOG_DIS(str, ...) \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->base.pc_next, \ - ## __VA_ARGS__) - /* is_jmp field values */ #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ #define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */ @@ -440,7 +436,6 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) static bool trans_l_add(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.add r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -448,7 +443,6 @@ static bool trans_l_add(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_addc(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.addc r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -456,7 +450,6 @@ static bool trans_l_addc(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_sub(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.sub r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -464,7 +457,6 @@ static bool trans_l_sub(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_and(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.and r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -472,7 +464,6 @@ static bool trans_l_and(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_or(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.or r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -480,7 +471,6 @@ static bool trans_l_or(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_xor(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.xor r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -488,7 +478,6 @@ static bool trans_l_xor(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_sll(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.sll r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -496,7 +485,6 @@ static bool trans_l_sll(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_srl(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.srl r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -504,7 +492,6 @@ static bool trans_l_srl(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_sra(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.sra r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -512,7 +499,6 @@ static bool trans_l_sra(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_ror(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.ror r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -520,7 +506,6 @@ static bool trans_l_ror(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_exths(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.exths r%d, r%d\n", a->d, a->a); check_r0_write(a->d); tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]); return true; @@ -528,7 +513,6 @@ static bool trans_l_exths(DisasContext *dc, arg_da *a, uint32_t insn) static bool trans_l_extbs(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.extbs r%d, r%d\n", a->d, a->a); check_r0_write(a->d); tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]); return true; @@ -536,7 +520,6 @@ static bool trans_l_extbs(DisasContext *dc, arg_da *a, uint32_t insn) static bool trans_l_exthz(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.exthz r%d, r%d\n", a->d, a->a); check_r0_write(a->d); tcg_gen_ext16u_tl(cpu_R[a->d], cpu_R[a->a]); return true; @@ -544,7 +527,6 @@ static bool trans_l_exthz(DisasContext *dc, arg_da *a, uint32_t insn) static bool trans_l_extbz(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.extbz r%d, r%d\n", a->d, a->a); check_r0_write(a->d); tcg_gen_ext8u_tl(cpu_R[a->d], cpu_R[a->a]); return true; @@ -553,7 +535,6 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a, uint32_t insn) static bool trans_l_cmov(DisasContext *dc, arg_dab *a, uint32_t insn) { TCGv zero; - LOG_DIS("l.cmov r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); zero = tcg_const_tl(0); @@ -565,8 +546,6 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_ff1(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.ff1 r%d, r%d\n", a->d, a->a); - check_r0_write(a->d); tcg_gen_ctzi_tl(cpu_R[a->d], cpu_R[a->a], -1); tcg_gen_addi_tl(cpu_R[a->d], cpu_R[a->d], 1); @@ -575,8 +554,6 @@ static bool trans_l_ff1(DisasContext *dc, arg_da *a, uint32_t insn) static bool trans_l_fl1(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.fl1 r%d, r%d\n", a->d, a->a); - check_r0_write(a->d); tcg_gen_clzi_tl(cpu_R[a->d], cpu_R[a->a], TARGET_LONG_BITS); tcg_gen_subfi_tl(cpu_R[a->d], TARGET_LONG_BITS, cpu_R[a->d]); @@ -585,8 +562,6 @@ static bool trans_l_fl1(DisasContext *dc, arg_da *a, uint32_t insn) static bool trans_l_mul(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.mul r%d, r%d, r%d\n", a->d, a->a, a->b); - check_r0_write(a->d); gen_mul(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -594,8 +569,6 @@ static bool trans_l_mul(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_mulu(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.mulu r%d, r%d, r%d\n", a->d, a->a, a->b); - check_r0_write(a->d); gen_mulu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -603,8 +576,6 @@ static bool trans_l_mulu(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_div(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.div r%d, r%d, r%d\n", a->d, a->a, a->b); - check_r0_write(a->d); gen_div(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -612,8 +583,6 @@ static bool trans_l_div(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_divu(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.divu r%d, r%d, r%d\n", a->d, a->a, a->b); - check_r0_write(a->d); gen_divu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -621,14 +590,12 @@ static bool trans_l_divu(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_muld(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.muld r%d, r%d\n", a->a, a->b); gen_muld(dc, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_muldu(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.muldu r%d, r%d\n", a->a, a->b); gen_muldu(dc, cpu_R[a->a], cpu_R[a->b]); return true; } @@ -637,7 +604,6 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a, uint32_t insn) { target_ulong tmp_pc = dc->base.pc_next + a->n * 4; - LOG_DIS("l.j %d\n", a->n); tcg_gen_movi_tl(jmp_pc, tmp_pc); dc->jmp_pc_imm = tmp_pc; dc->delayed_branch = 2; @@ -649,7 +615,6 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a, uint32_t insn) target_ulong tmp_pc = dc->base.pc_next + a->n * 4; target_ulong ret_pc = dc->base.pc_next + 8; - LOG_DIS("l.jal %d\n", a->n); tcg_gen_movi_tl(cpu_R[9], ret_pc); /* Optimize jal being used to load the PC for PIC. */ if (tmp_pc != ret_pc) { @@ -677,21 +642,18 @@ static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) static bool trans_l_bf(DisasContext *dc, arg_l_bf *a, uint32_t insn) { - LOG_DIS("l.bf %d\n", a->n); do_bf(dc, a, TCG_COND_NE); return true; } static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a, uint32_t insn) { - LOG_DIS("l.bnf %d\n", a->n); do_bf(dc, a, TCG_COND_EQ); return true; } static bool trans_l_jr(DisasContext *dc, arg_l_jr *a, uint32_t insn) { - LOG_DIS("l.jr r%d\n", a->b); tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]); dc->delayed_branch = 2; return true; @@ -699,7 +661,6 @@ static bool trans_l_jr(DisasContext *dc, arg_l_jr *a, uint32_t insn) static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a, uint32_t insn) { - LOG_DIS("l.jalr r%d\n", a->b); tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]); tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8); dc->delayed_branch = 2; @@ -710,8 +671,6 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a, uint32_t insn) { TCGv ea; - LOG_DIS("l.lwa r%d, r%d, %d\n", a->d, a->a, a->i); - check_r0_write(a->d); ea = tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); @@ -735,42 +694,36 @@ static void do_load(DisasContext *dc, arg_load *a, TCGMemOp mop) static bool trans_l_lwz(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lwz r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_TEUL); return true; } static bool trans_l_lws(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lws r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_TESL); return true; } static bool trans_l_lbz(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lbz r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_UB); return true; } static bool trans_l_lbs(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lbs r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_SB); return true; } static bool trans_l_lhz(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lhz r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_TEUW); return true; } static bool trans_l_lhs(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lhs r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_TESW); return true; } @@ -780,8 +733,6 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a, uint32_t insn) TCGv ea, val; TCGLabel *lab_fail, *lab_done; - LOG_DIS("l.swa r%d, r%d, %d\n", a->a, a->b, a->i); - ea = tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); @@ -822,28 +773,24 @@ static void do_store(DisasContext *dc, arg_store *a, TCGMemOp mop) static bool trans_l_sw(DisasContext *dc, arg_store *a, uint32_t insn) { - LOG_DIS("l.sw r%d, r%d, %d\n", a->a, a->b, a->i); do_store(dc, a, MO_TEUL); return true; } static bool trans_l_sb(DisasContext *dc, arg_store *a, uint32_t insn) { - LOG_DIS("l.sb r%d, r%d, %d\n", a->a, a->b, a->i); do_store(dc, a, MO_UB); return true; } static bool trans_l_sh(DisasContext *dc, arg_store *a, uint32_t insn) { - LOG_DIS("l.sh r%d, r%d, %d\n", a->a, a->b, a->i); do_store(dc, a, MO_TEUW); return true; } static bool trans_l_nop(DisasContext *dc, arg_l_nop *a, uint32_t insn) { - LOG_DIS("l.nop %d\n", a->k); return true; } @@ -851,7 +798,6 @@ static bool trans_l_addi(DisasContext *dc, arg_rri *a, uint32_t insn) { TCGv t0; - LOG_DIS("l.addi r%d, r%d, %d\n", a->d, a->a, a->i); check_r0_write(a->d); t0 = tcg_const_tl(a->i); gen_add(dc, cpu_R[a->d], cpu_R[a->a], t0); @@ -863,7 +809,6 @@ static bool trans_l_addic(DisasContext *dc, arg_rri *a, uint32_t insn) { TCGv t0; - LOG_DIS("l.addic r%d, r%d, %d\n", a->d, a->a, a->i); check_r0_write(a->d); t0 = tcg_const_tl(a->i); gen_addc(dc, cpu_R[a->d], cpu_R[a->a], t0); @@ -875,7 +820,6 @@ static bool trans_l_muli(DisasContext *dc, arg_rri *a, uint32_t insn) { TCGv t0; - LOG_DIS("l.muli r%d, r%d, %d\n", a->d, a->a, a->i); check_r0_write(a->d); t0 = tcg_const_tl(a->i); gen_mul(dc, cpu_R[a->d], cpu_R[a->a], t0); @@ -887,7 +831,6 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci *a, uint32_t insn) { TCGv t0; - LOG_DIS("l.maci r%d, %d\n", a->a, a->i); t0 = tcg_const_tl(a->i); gen_mac(dc, cpu_R[a->a], t0); tcg_temp_free(t0); @@ -896,7 +839,6 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci *a, uint32_t insn) static bool trans_l_andi(DisasContext *dc, arg_rrk *a, uint32_t insn) { - LOG_DIS("l.andi r%d, r%d, %d\n", a->d, a->a, a->k); check_r0_write(a->d); tcg_gen_andi_tl(cpu_R[a->d], cpu_R[a->a], a->k); return true; @@ -904,7 +846,6 @@ static bool trans_l_andi(DisasContext *dc, arg_rrk *a, uint32_t insn) static bool trans_l_ori(DisasContext *dc, arg_rrk *a, uint32_t insn) { - LOG_DIS("l.ori r%d, r%d, %d\n", a->d, a->a, a->k); check_r0_write(a->d); tcg_gen_ori_tl(cpu_R[a->d], cpu_R[a->a], a->k); return true; @@ -912,7 +853,6 @@ static bool trans_l_ori(DisasContext *dc, arg_rrk *a, uint32_t insn) static bool trans_l_xori(DisasContext *dc, arg_rri *a, uint32_t insn) { - LOG_DIS("l.xori r%d, r%d, %d\n", a->d, a->a, a->i); check_r0_write(a->d); tcg_gen_xori_tl(cpu_R[a->d], cpu_R[a->a], a->i); return true; @@ -920,7 +860,6 @@ static bool trans_l_xori(DisasContext *dc, arg_rri *a, uint32_t insn) static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn) { - LOG_DIS("l.mfspr r%d, r%d, %d\n", a->d, a->a, a->k); check_r0_write(a->d); if (is_user(dc)) { @@ -936,8 +875,6 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn) static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) { - LOG_DIS("l.mtspr r%d, r%d, %d\n", a->a, a->b, a->k); - if (is_user(dc)) { gen_illegal_exception(dc); } else { @@ -973,35 +910,30 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) static bool trans_l_mac(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.mac r%d, r%d\n", a->a, a->b); gen_mac(dc, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_msb(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.msb r%d, r%d\n", a->a, a->b); gen_msb(dc, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_macu(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.mac r%d, r%d\n", a->a, a->b); gen_macu(dc, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.msb r%d, r%d\n", a->a, a->b); gen_msbu(dc, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn) { - LOG_DIS("l.slli r%d, r%d, %d\n", a->d, a->a, a->l); check_r0_write(a->d); tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1)); return true; @@ -1009,7 +941,6 @@ static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn) static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn) { - LOG_DIS("l.srli r%d, r%d, %d\n", a->d, a->a, a->l); check_r0_write(a->d); tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1)); return true; @@ -1017,7 +948,6 @@ static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn) static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn) { - LOG_DIS("l.srai r%d, r%d, %d\n", a->d, a->a, a->l); check_r0_write(a->d); tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1)); return true; @@ -1025,7 +955,6 @@ static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn) static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn) { - LOG_DIS("l.rori r%d, r%d, %d\n", a->d, a->a, a->l); check_r0_write(a->d); tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1)); return true; @@ -1033,7 +962,6 @@ static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn) static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn) { - LOG_DIS("l.movhi r%d, %d\n", a->d, a->k); check_r0_write(a->d); tcg_gen_movi_tl(cpu_R[a->d], a->k << 16); return true; @@ -1041,7 +969,6 @@ static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn) static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn) { - LOG_DIS("l.macrc r%d\n", a->d); check_r0_write(a->d); tcg_gen_trunc_i64_tl(cpu_R[a->d], cpu_mac); tcg_gen_movi_i64(cpu_mac, 0); @@ -1050,147 +977,126 @@ static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn) static bool trans_l_sfeq(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfeq r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfne(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfne r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfgtu r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfgeu r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfltu(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfltu r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfleu(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfleu r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfgts(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfgts r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfges(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfges r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sflts(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sflts r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfles(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfles r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfeqi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfnei(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfnei r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfgtui r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfgeui r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfltui(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfltui r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfleui(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfleui r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfgtsi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfgesi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfltsi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sflesi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sflesi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn) { - LOG_DIS("l.sys %d\n", a->k); tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_SYSCALL); dc->base.is_jmp = DISAS_NORETURN; @@ -1199,7 +1105,6 @@ static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn) static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn) { - LOG_DIS("l.trap %d\n", a->k); tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_TRAP); dc->base.is_jmp = DISAS_NORETURN; @@ -1208,27 +1113,22 @@ static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn) static bool trans_l_msync(DisasContext *dc, arg_l_msync *a, uint32_t insn) { - LOG_DIS("l.msync\n"); tcg_gen_mb(TCG_MO_ALL); return true; } static bool trans_l_psync(DisasContext *dc, arg_l_psync *a, uint32_t insn) { - LOG_DIS("l.psync\n"); return true; } static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn) { - LOG_DIS("l.csync\n"); return true; } static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn) { - LOG_DIS("l.rfe\n"); - if (is_user(dc)) { gen_illegal_exception(dc); } else { @@ -1271,56 +1171,48 @@ static void do_fpcmp(DisasContext *dc, arg_ab *a, static bool trans_lf_add_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.add.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_add_s); return true; } static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.sub.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_sub_s); return true; } static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.mul.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_mul_s); return true; } static bool trans_lf_div_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.div.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_div_s); return true; } static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.rem.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_rem_s); return true; } static bool trans_lf_itof_s(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("lf.itof.s r%d, r%d\n", a->d, a->a); do_fp2(dc, a, gen_helper_itofs); return true; } static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("lf.ftoi.s r%d, r%d\n", a->d, a->a); do_fp2(dc, a, gen_helper_ftois); return true; } static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.madd.s r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); gen_helper_float_madd_s(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); @@ -1330,42 +1222,36 @@ static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfeq.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_eq_s, false, false); return true; } static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfne.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_eq_s, true, false); return true; } static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfgt.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_lt_s, false, true); return true; } static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfge.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_le_s, false, true); return true; } static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sflt.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_lt_s, false, false); return true; } static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfle.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_le_s, false, false); return true; } diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs index 957ce02199..b5432f4684 100644 --- a/target/openrisc/Makefile.objs +++ b/target/openrisc/Makefile.objs @@ -1,5 +1,5 @@ obj-$(CONFIG_SOFTMMU) += machine.o -obj-y += cpu.o exception.o interrupt.o mmu.o translate.o +obj-y += cpu.o exception.o interrupt.o mmu.o translate.o disas.o obj-y += exception_helper.o fpu_helper.o \ interrupt_helper.o sys_helper.o obj-y += gdbstub.o @@ -12,3 +12,4 @@ target/openrisc/decode.inc.c: \ $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@) target/openrisc/translate.o: target/openrisc/decode.inc.c +target/openrisc/disas.o: target/openrisc/decode.inc.c From patchwork Sun May 27 14:13:24 2018 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 20/20] target/or1k: Add support in scripts/qemu-binfmt-conf.sh X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- scripts/qemu-binfmt-conf.sh | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) -- 2.17.0 diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh index 7ab7435fbd..75ed7c6b65 100755 --- a/scripts/qemu-binfmt-conf.sh +++ b/scripts/qemu-binfmt-conf.sh @@ -1,10 +1,10 @@ #!/bin/sh -# enable automatic i386/ARM/M68K/MIPS/SPARC/PPC/s390/HPPA/Xtensa/microblaze -# program execution by the kernel +# Enable automatic program execution by the kernel. qemu_target_list="i386 i486 alpha arm armeb sparc32plus ppc ppc64 ppc64le m68k \ mips mipsel mipsn32 mipsn32el mips64 mips64el \ -sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64 xtensa xtensaeb microblaze microblazeel" +sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64 xtensa xtensaeb \ +microblaze microblazeel or1k" i386_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00' i386_mask='\xff\xff\xff\xff\xff\xfe\xfe\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' @@ -124,6 +124,10 @@ microblazeel_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\ microblazeel_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' microblazeel_family=microblazeel +or1k_magic='\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x5c' +or1k_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff' +or1k_family=or1k + qemu_get_family() { cpu=${HOST_ARCH:-$(uname -m)} case "$cpu" in