From patchwork Fri Apr 2 10:11:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Syed Nayyar Waris X-Patchwork-Id: 414683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6DB5C433ED for ; Fri, 2 Apr 2021 10:11:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 966CB610E7 for ; Fri, 2 Apr 2021 10:11:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234397AbhDBKLo (ORCPT ); Fri, 2 Apr 2021 06:11:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229722AbhDBKLo (ORCPT ); Fri, 2 Apr 2021 06:11:44 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18C34C0613E6; Fri, 2 Apr 2021 03:11:42 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id t140so3285963pgb.13; Fri, 02 Apr 2021 03:11:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=uINt+NN92c/qqfcZODFiV431lREP2XSc10cIb3wY4cc=; b=l/fmTCDn13mLbCThcvC6o8U9EAGLpx5ASG68btJFTg+HocJJ0kP0nOt6taopeYMDB3 RdKOdDANC483leCBktWTrtX1VNOtbddTw1Oi+7qB/LczPzyHH4RBeSbVxqIdL16Tc4yt /RJpofJnpA5wgO3NecEYKlQi+jWHONp/cNM4AblrELIXeb4riFUc//slAfbiNU4BoLqN UajRyBO5G1qXQYOoXE0xA2NTyzHS9CsLRDy8OP8dmz8ddEFH+4PtD4HtYbdM3EKpzwFl ms1Tl3FWYdxTQmNUXoamORAZ8npktqBXeMVQTOASVOWAQBeUVyxYXgNAuZVWLZ4cho+T yxig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=uINt+NN92c/qqfcZODFiV431lREP2XSc10cIb3wY4cc=; b=Yf5bWJT8HW6WkDE2vy7Qvgz3hz7wzMup5+gPtylhirFQivc1qCNNNmCoeX3HLTY3ob Z5at5MZVy4sTy2Rwj5ypNgL+LLFFRkJYZUx0UqdYOGR5o4N99icFrR5uZA1wL4TRUFLN y+rsgSPmWjIL84BIadnTuo6YFgDmOR650JD00bYoqG163+zoayAnIdpetD6W77fJIa08 wV4734jFUsCyqIe6NCOVl7wODAZa/6wFTCxyRAof8l9CwOUYsU8lItoTTMjUFs+CK3X8 hlz5UKF5/xc2GgzxX6VLH3Yy9LYTmVxc34oAZXi2IOwlKvWPfu7SXocLhop8fb9qRQgu 7PJQ== X-Gm-Message-State: AOAM53147UNQ7atQaqRhu8kRIfd5vlYe1P3+yM0NLuV1FTw0mt77Tldy IMH/nMGz+v8lhFuq/kqBR0Q= X-Google-Smtp-Source: ABdhPJwYOkp3h/5YYuq7wFH6wtT41RcO8LQl85nhoCS0ohhE7PHiPkpZ9rNp9iCbGWqgyHPiyvbWzA== X-Received: by 2002:a62:6883:0:b029:220:4426:449c with SMTP id d125-20020a6268830000b02902204426449cmr11368828pfc.14.1617358301687; Fri, 02 Apr 2021 03:11:41 -0700 (PDT) Received: from syed ([223.225.111.29]) by smtp.gmail.com with ESMTPSA id v13sm7326337pfu.54.2021.04.02.03.11.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Apr 2021 03:11:41 -0700 (PDT) Date: Fri, 2 Apr 2021 15:41:24 +0530 From: Syed Nayyar Waris To: bgolaszewski@baylibre.com Cc: andriy.shevchenko@linux.intel.com, vilhelm.gray@gmail.com, michal.simek@xilinx.com, arnd@arndb.de, rrichter@marvell.com, linus.walleij@linaro.org, bgolaszewski@baylibre.com, yamada.masahiro@socionext.com, akpm@linux-foundation.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amit.kucheria@verdurent.com, linux-arch@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org Subject: [PATCH v4 1/3] gpiolib: Introduce the for_each_set_nbits macro Message-ID: <12102d94258fc6bd5c01800b7cea680fc51d8b93.1617357235.git.syednwaris@gmail.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This macro iterates for each group of bits (clump) with set bits, within a bitmap memory region. For each iteration, "start" is set to the bit offset of the found clump, while the respective clump value is stored to the location pointed by "clump". Additionally, the bitmap_get_value() and bitmap_set_value() functions are introduced to respectively get and set a value of n-bits in a bitmap memory region. The n-bits can have any size from 1 to BITS_PER_LONG. size less than 1 or more than BITS_PER_LONG causes undefined behaviour. Moreover, during setting value of n-bit in bitmap, if a situation arise that the width of next n-bit is exceeding the word boundary, then it will divide itself such that some portion of it is stored in that word, while the remaining portion is stored in the next higher word. Similar situation occurs while retrieving the value from bitmap. Cc: Linus Walleij Cc: Bartosz Gołaszewski Cc: Arnd Bergmann Cc: Andy Shevchenko Signed-off-by: Syed Nayyar Waris Acked-by: William Breathitt Gray --- drivers/gpio/gpiolib.c | 90 ++++++++++++++++++++++++++++++++++++++++++ drivers/gpio/gpiolib.h | 28 +++++++++++++ 2 files changed, 118 insertions(+) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 1427c1be749b..5576d1465c81 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -150,6 +150,96 @@ struct gpio_desc *gpiochip_get_desc(struct gpio_chip *gc, } EXPORT_SYMBOL_GPL(gpiochip_get_desc); +/** + * bitmap_get_value - get a value of n-bits from the memory region + * @map: address to the bitmap memory region + * @start: bit offset of the n-bit value + * @nbits: size of value in bits (must be between 1 and BITS_PER_LONG inclusive). + * + * Returns value of nbits located at the @start bit offset within the @map + * memory region. + */ +unsigned long bitmap_get_value(const unsigned long *map, + unsigned long start, + unsigned long nbits) +{ + const size_t index = BIT_WORD(start); + const unsigned long offset = start % BITS_PER_LONG; + const unsigned long ceiling = round_up(start + 1, BITS_PER_LONG); + const unsigned long space = ceiling - start; + unsigned long value_low, value_high; + + if (space >= nbits) + return (map[index] >> offset) & GENMASK(nbits - 1, 0); + else { + value_low = map[index] & BITMAP_FIRST_WORD_MASK(start); + value_high = map[index + 1] & BITMAP_LAST_WORD_MASK(start + nbits); + return (value_low >> offset) | (value_high << space); + } +} +EXPORT_SYMBOL_GPL(bitmap_get_value); + +/** + * bitmap_set_value - set value within a memory region + * @map: address to the bitmap memory region + * @nbits: size of map in bits + * @value: value of clump + * @value_width: size of value in bits (must be between 1 and BITS_PER_LONG inclusive) + * @start: bit offset of the value + */ +void bitmap_set_value(unsigned long *map, unsigned long nbits, + unsigned long value, unsigned long value_width, + unsigned long start) +{ + const unsigned long index = BIT_WORD(start); + const unsigned long length = BIT_WORD(nbits); + const unsigned long offset = start % BITS_PER_LONG; + const unsigned long ceiling = round_up(start + 1, BITS_PER_LONG); + const unsigned long space = ceiling - start; + + value &= GENMASK(value_width - 1, 0); + + if (space >= value_width) { + map[index] &= ~(GENMASK(value_width - 1, 0) << offset); + map[index] |= value << offset; + } else { + map[index + 0] &= ~BITMAP_FIRST_WORD_MASK(start); + map[index + 0] |= value << offset; + + if (index + 1 >= length) + return; + + map[index + 1] &= ~BITMAP_LAST_WORD_MASK(start + value_width); + map[index + 1] |= value >> space; + } +} +EXPORT_SYMBOL_GPL(bitmap_set_value); + +/** + * find_next_clump - find next clump with set bits in a memory region + * @clump: location to store copy of found clump + * @addr: address to base the search on + * @size: bitmap size in number of bits + * @offset: bit offset at which to start searching + * @clump_size: clump size in bits + * + * Returns the bit offset for the next set clump; the found clump value is + * copied to the location pointed by @clump. If no bits are set, returns @size. + */ +unsigned long find_next_clump(unsigned long *clump, const unsigned long *addr, + unsigned long size, unsigned long offset, + unsigned long clump_size) +{ + offset = find_next_bit(addr, size, offset); + if (offset == size) + return size; + + offset = rounddown(offset, clump_size); + *clump = bitmap_get_value(addr, offset, clump_size); + return offset; +} +EXPORT_SYMBOL_GPL(find_next_clump); + /** * desc_to_gpio - convert a GPIO descriptor to the integer namespace * @desc: GPIO descriptor diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h index 30bc3f80f83e..af79784dfce3 100644 --- a/drivers/gpio/gpiolib.h +++ b/drivers/gpio/gpiolib.h @@ -141,6 +141,34 @@ int gpio_set_debounce_timeout(struct gpio_desc *desc, unsigned int debounce); int gpiod_hog(struct gpio_desc *desc, const char *name, unsigned long lflags, enum gpiod_flags dflags); +unsigned long bitmap_get_value(const unsigned long *map, + unsigned long start, + unsigned long nbits); + +void bitmap_set_value(unsigned long *map, unsigned long nbits, + unsigned long value, unsigned long value_width, + unsigned long start); + +unsigned long find_next_clump(unsigned long *clump, const unsigned long *addr, + unsigned long size, unsigned long offset, + unsigned long clump_size); + +#define find_first_clump(clump, bits, size, clump_size) \ + find_next_clump((clump), (bits), (size), 0, (clump_size)) + +/** + * for_each_set_nbits - iterate over bitmap for each clump with set bits + * @start: bit offset to start search and to store the current iteration offset + * @clump: location to store copy of current 8-bit clump + * @bits: bitmap address to base the search on + * @size: bitmap size in number of bits + * @clump_size: clump size in bits + */ +#define for_each_set_nbits(start, clump, bits, size, clump_size) \ + for ((start) = find_first_clump(&(clump), (bits), (size), (clump_size)); \ + (start) < (size); \ + (start) = find_next_clump(&(clump), (bits), (size), (start) + (clump_size), (clump_size))) + /* * Return the GPIO number of the passed descriptor relative to its chip */ From patchwork Fri Apr 2 10:12:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Syed Nayyar Waris X-Patchwork-Id: 414682 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC8BDC433ED for ; Fri, 2 Apr 2021 10:12:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CBE39610CF for ; Fri, 2 Apr 2021 10:12:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229553AbhDBKM7 (ORCPT ); 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Fri, 02 Apr 2021 03:12:58 -0700 (PDT) Date: Fri, 2 Apr 2021 15:42:40 +0530 From: Syed Nayyar Waris To: bgolaszewski@baylibre.com Cc: andriy.shevchenko@linux.intel.com, vilhelm.gray@gmail.com, michal.simek@xilinx.com, arnd@arndb.de, rrichter@marvell.com, linus.walleij@linaro.org, bgolaszewski@baylibre.com, yamada.masahiro@socionext.com, akpm@linux-foundation.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amit.kucheria@verdurent.com, linux-arch@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org Subject: [PATCH v4 3/3] gpio: xilinx: Utilize generic bitmap_get_value and _set_value Message-ID: <00d085d4068be651c58a61564926d4f3d495ab80.1617357235.git.syednwaris@gmail.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch reimplements the xgpio_set_multiple() function in drivers/gpio/gpio-xilinx.c to use the new generic functions: bitmap_get_value() and bitmap_set_value(). The code is now simpler to read and understand. Moreover, instead of looping for each bit in xgpio_set_multiple() function, now we can check each channel at a time and save cycles. Cc: Bartosz Golaszewski Cc: Michal Simek Signed-off-by: Syed Nayyar Waris Acked-by: William Breathitt Gray --- drivers/gpio/gpio-xilinx.c | 60 +++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index b411d3156e0b..e0ad3a81f216 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -18,6 +18,7 @@ #include #include #include +#include "gpiolib.h" /* Register Offset Definitions */ #define XGPIO_DATA_OFFSET (0x0) /* Data register */ @@ -161,37 +162,36 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, { unsigned long flags; struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, 0); - int offset, i; - spin_lock_irqsave(&chip->gpio_lock, flags); - - /* Write to GPIO signals */ - for (i = 0; i < gc->ngpio; i++) { - if (*mask == 0) - break; - /* Once finished with an index write it out to the register */ - if (index != xgpio_index(chip, i)) { - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET, - chip->gpio_state[index]); - spin_unlock_irqrestore(&chip->gpio_lock, flags); - index = xgpio_index(chip, i); - spin_lock_irqsave(&chip->gpio_lock, flags); - } - if (__test_and_clear_bit(i, mask)) { - offset = xgpio_offset(chip, i); - if (test_bit(i, bits)) - chip->gpio_state[index] |= BIT(offset); - else - chip->gpio_state[index] &= ~BIT(offset); - } - } - - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); - - spin_unlock_irqrestore(&chip->gpio_lock, flags); + u32 *state = chip->gpio_state; + unsigned int *width = chip->gpio_width; + DECLARE_BITMAP(old, 64); + DECLARE_BITMAP(new, 64); + DECLARE_BITMAP(changed, 64); + + spin_lock_irqsave(&chip->gpio_lock, flags); + + /* Copy initial value of state bits into 'old' bit-wise */ + bitmap_set_value(old, 64, state[0], width[0], 0); + bitmap_set_value(old, 64, state[1], width[1], width[0]); + /* Copy value from 'old' into 'new' with mask applied */ + bitmap_replace(new, old, bits, mask, gc->ngpio); + + bitmap_from_arr32(old, state, 64); + /* Update 'state' */ + state[0] = bitmap_get_value(new, 0, width[0]); + state[1] = bitmap_get_value(new, width[0], width[1]); + bitmap_from_arr32(new, state, 64); + /* XOR operation sets only changed bits */ + bitmap_xor(changed, old, new, 64); + + if (((u32 *)changed)[0]) + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, state[0]); + if (((u32 *)changed)[1]) + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + + XGPIO_CHANNEL_OFFSET, state[1]); + + spin_unlock_irqrestore(&chip->gpio_lock, flags); } /**