From patchwork Fri Apr 2 15:01:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 414571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73046C433ED for ; Fri, 2 Apr 2021 15:01:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4EBCE6113E for ; Fri, 2 Apr 2021 15:01:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234976AbhDBPB6 (ORCPT ); Fri, 2 Apr 2021 11:01:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234857AbhDBPB5 (ORCPT ); Fri, 2 Apr 2021 11:01:57 -0400 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB3A9C06178A for ; Fri, 2 Apr 2021 08:01:54 -0700 (PDT) Received: by mail-pj1-x1031.google.com with SMTP id a22-20020a17090aa516b02900c1215e9b33so4709684pjq.5 for ; Fri, 02 Apr 2021 08:01:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I0ki0lC8MA7ZU5srSBRCAeZerDP7DRSW7mDv/jEyzhw=; b=Ci8D2AZt97zfkPOnjeTjLmWKK3FPXfgKRs0RwYNoxUSajta/NJhKWe7Ns+zEC48euD JH+MOnJJ1OeLDSpBTV+kPLNd8ENZgIOFhNtLMoykTNEv2l8JLxgufZCgm7nRYDw/+Q6R MoA9IQGpMwqEXkbbnJZQtZeUxPYkyLUHbFLH3Nw0D5eIno7GJhRRsbdFG9eXg4e5f6b/ hhq74R8qnEpbynsn5sdXPBVTL7thcMyJd0hoHyRQUp4cXyDWx7dJ9H02oE5G+POeHfqa 3mFb1QlQRF4RcrpgOUM5jGWyjEPO1M/7hOLH9vAqCO+hoMysKUb0CX8UnEdGlpr1RBgM CNUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I0ki0lC8MA7ZU5srSBRCAeZerDP7DRSW7mDv/jEyzhw=; b=EsGKgeyMOE/RKUYzR9LyPTyzAjA1dKOI5DJbmiRr4S2nQsMjJfg8dIhqjA9p5kJ6gj 8HKyJclUECy6pVH8F1opdUuF45LJQ0VPGb44lgNk3WlZXnlPJzoSkIyQB9DtzvVRYL+F MjarUPFvkZkmsTKvotX3kCzvmfz9IwYAYgPv8lCypXr7kRS7nv1MRt5aNBgTaYYnZqTu xKHVjtuT7dpLUiuqcNOw1tSm9KTTbSIteOQG2rLwAhTGQc8uRBcMB5LUxr+/7YGBzpd0 bVP1/II0gsEClhdrSWmpAZQ4FsT4cdtKWUMq94DkrieA0Z+rWB3reEWMtR3U5z5eD6le DTIA== X-Gm-Message-State: AOAM532vIDuGquftfu4kLYeSu72L2uK67TZBghdebtU964/Q81SfkUbG 5J7Aftlr5qCnpe8lJAHH/E7z X-Google-Smtp-Source: ABdhPJxYc8g1lG1UE/hCJUsbIYG48bPhURHEr7CPoRVJ52J7UlXJVrc71N7uNBiPeNTi7wq3vV2fXA== X-Received: by 2002:a17:902:ea0e:b029:e4:81d4:ddae with SMTP id s14-20020a170902ea0eb02900e481d4ddaemr13231221plg.12.1617375714447; Fri, 02 Apr 2021 08:01:54 -0700 (PDT) Received: from localhost.localdomain ([103.77.37.174]) by smtp.gmail.com with ESMTPSA id x7sm8773647pff.12.2021.04.02.08.01.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Apr 2021 08:01:54 -0700 (PDT) From: Manivannan Sadhasivam To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, boris.brezillon@collabora.com, Daniele.Palmas@telit.com, bjorn.andersson@linaro.org, Manivannan Sadhasivam , Rob Herring Subject: [PATCH v11 2/4] dt-bindings: mtd: Add a property to declare secure regions in NAND chips Date: Fri, 2 Apr 2021 20:31:26 +0530 Message-Id: <20210402150128.29128-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210402150128.29128-1-manivannan.sadhasivam@linaro.org> References: <20210402150128.29128-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On a typical end product, a vendor may choose to secure some regions in the NAND memory which are supposed to stay intact between FW upgrades. The access to those regions will be blocked by a secure element like Trustzone. So the normal world software like Linux kernel should not touch these regions (including reading). So let's add a property for declaring such secure regions so that the drivers can skip touching them. Reviewed-by: Rob Herring Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/mtd/nand-controller.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml index d0e422f4b3e0..678b39952502 100644 --- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml @@ -143,6 +143,13 @@ patternProperties: Ready/Busy pins. Active state refers to the NAND ready state and should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted. + secure-regions: + $ref: /schemas/types.yaml#/definitions/uint64-matrix + description: + Regions in the NAND chip which are protected using a secure element + like Trustzone. This property contains the start address and size of + the secure regions present. + required: - reg From patchwork Fri Apr 2 15:01:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 414378 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1479343jai; Fri, 2 Apr 2021 08:02:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJywUC2fl6KAdt4uueW4AX9B+Bx9OnNH+tnF2G0xRB5har7Hb3DU4EbWt5zDUqsUkvjjVOJr X-Received: by 2002:aca:4b03:: with SMTP id y3mr9647222oia.162.1617375727668; Fri, 02 Apr 2021 08:02:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617375727; cv=none; d=google.com; s=arc-20160816; b=WD309yEWULV580aRbkOfbruUVlJsAemAbN4URhbOGwZ/hO2u9Dcd8lAIM3YpDzYyUb Bh94Kb63/kB1EsQOLlHd+m5lpsrASvfgO9LcLKGGOjW+eAJV74iLrpZmWq+CflFACCSg MWOcGbyzWwZ9NyiLfkJbvHgN8Zbhi5gecidbCWdl5+V5Pqkkbqi21O2zbkPCn9ZTDkTt MIqoSH925XczfhkIIx749EVER5M9aA2zW0HM6bttUJAmwDwQuFX2sEm4ZHNNxIrea7Rt SE3XhTo0VgfwqOSNU8ctCooZom7fMucFPocqMr8IJLlMgqti5WM618LEjrMSw7efbS/h ieQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TWYjwlYcBYFHfUi9Dwn7UiPrXNJjNafuVdBu7SMjuLE=; b=d/dhWRZVj5PBuZrcgzbGGw2PHfBmKloLE4REmsbQAPsIdx8QlL22KQPwSaAjpkEgzS DDafCd6Z/s5mgvzjfjdouXMe0OZxfqpvI6R6aftWAUHnqHz4Mkv4U/WvuI3nLDEv+2R6 w1+wxBKdEdZssJyiieO17ctKc6ngs7l+hPGtigTKC19ySEBZ27EsY9MGcpurKEzltwiN JAkS5eDonwFhOIWaQ+KclfO/OF4i0fgnzGsAxhyNEgRZA3CE92Ia7w0xYXTyNs7AKo9i 44ZSHhdIMWtdIvSkACdRrqmXSB1evv7uplS7svrgaDegTySgnOvqLGhBYYooEKoRU5WB X4DA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Vcs11hph; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 4si9122999ois.89.2021.04.02.08.02.07; Fri, 02 Apr 2021 08:02:07 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Vcs11hph; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235151AbhDBPCF (ORCPT + 6 others); Fri, 2 Apr 2021 11:02:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235069AbhDBPCC (ORCPT ); Fri, 2 Apr 2021 11:02:02 -0400 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BC55C06178A for ; Fri, 2 Apr 2021 08:02:01 -0700 (PDT) Received: by mail-pg1-x52f.google.com with SMTP id f10so3701953pgl.9 for ; Fri, 02 Apr 2021 08:02:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TWYjwlYcBYFHfUi9Dwn7UiPrXNJjNafuVdBu7SMjuLE=; b=Vcs11hphs/nAkTxbteqUdyb/TCjrnE6RuKPNSVv/H2Rxzv3nU/+DgtFAQVphphlfWq TBrfNLVOf9hQAZwbx4zH8DobquGhESg1j8A/3jr6EXwHSUB0W12gGwWOyzaOu92i7OuJ p/D6/JlUQezFIMkYN2OjkYh1NDx1SYuvC8YWu4F95oLdFAWmpD/WZsR3Fp4khKLy9viT kaq5Aavwtsa+EJ0kNy+1T4HPIayK3kg3EcWm5byshsGznXRFgJK5hudD9GEzSoesc8w+ C9xHedw0iLLRD9QzP9O+b6lJhqShnpjI2A+P4qY6EmFTHZwLce54E2Ev9R1zXjmkFKnQ 57ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TWYjwlYcBYFHfUi9Dwn7UiPrXNJjNafuVdBu7SMjuLE=; b=VX50owwgV/xyzpXwmhtQK5Px3z32YAXGJsuzDh7Rbxx4C1T7VkMVzraAZyRU/JPQgT cP8PMhaD4LvcCS5aQ58JCSKJ6PMGoiURRxSHLbmAUq2fViOCy3BA/jzqXXWuq/jBuRXY j5/e3ApziRLNlo6GJl8uTog8s3oF8soIEell9mlUeuRPFDrbjctkwqyQSD2q6C5mvGRn 0mw4RXSiUZzLQdqo+vzuHAF1eLCMocJoNiTwe28Puj1+qdBN0neTd8Y4TJm/w+AvBwcf FjZwq/bzzV8z8Id9ZEsjEJ6U6QfmVHD1Kn2B1ipWbXlr0pL2OoUJ4h2J8GUWWaf5Y7xl qPqg== X-Gm-Message-State: AOAM5317UFwYm2K796aE3FxKhAlO59QhHMWil2smVlCGBtYfbVKKLcrW mTFB9Crldt3jCHbA+3VxojfX X-Received: by 2002:a63:510f:: with SMTP id f15mr12223126pgb.390.1617375720468; Fri, 02 Apr 2021 08:02:00 -0700 (PDT) Received: from localhost.localdomain ([103.77.37.174]) by smtp.gmail.com with ESMTPSA id x7sm8773647pff.12.2021.04.02.08.01.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Apr 2021 08:01:59 -0700 (PDT) From: Manivannan Sadhasivam To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, boris.brezillon@collabora.com, Daniele.Palmas@telit.com, bjorn.andersson@linaro.org, Manivannan Sadhasivam Subject: [PATCH v11 3/4] mtd: rawnand: Add support for secure regions in NAND memory Date: Fri, 2 Apr 2021 20:31:27 +0530 Message-Id: <20210402150128.29128-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210402150128.29128-1-manivannan.sadhasivam@linaro.org> References: <20210402150128.29128-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On a typical end product, a vendor may choose to secure some regions in the NAND memory which are supposed to stay intact between FW upgrades. The access to those regions will be blocked by a secure element like Trustzone. So the normal world software like Linux kernel should not touch these regions (including reading). The regions are declared using a NAND chip DT property, "secure-regions". So let's make use of this property in the raw NAND core and skip access to the secure regions present in a system. Signed-off-by: Manivannan Sadhasivam --- drivers/mtd/nand/raw/nand_base.c | 100 ++++++++++++++++++++++++++++++- include/linux/mtd/rawnand.h | 14 +++++ 2 files changed, 113 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index c33fa1b1847f..132ce73df76b 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -278,11 +278,48 @@ static int nand_block_bad(struct nand_chip *chip, loff_t ofs) return 0; } +/** + * nand_region_is_secured() - Check if the region is secured + * @chip: NAND chip object + * @offset: Offset of the region to check + * @size: Size of the region to check + * + * Checks if the region is secured by comparing the offset and size with the + * list of secure regions obtained from DT. Returns true if the region is + * secured else false. + */ +static bool nand_region_is_secured(struct nand_chip *chip, loff_t offset, u64 size) +{ + int i; + + /* Skip touching the secure regions if present */ + for (i = 0; i < chip->nr_secure_regions; i++) { + const struct nand_secure_region *region = &chip->secure_regions[i]; + + if (offset + size <= region->offset || + offset >= region->offset + region->size) + continue; + + pr_debug("%s: Region 0x%llx - 0x%llx is secured!", + __func__, offset, offset + size); + + return true; + } + + return false; +} + static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs) { + struct mtd_info *mtd = nand_to_mtd(chip); + if (chip->options & NAND_NO_BBM_QUIRK) return 0; + /* Check if the region is secured */ + if (nand_region_is_secured(chip, ofs, mtd->erasesize)) + return -EIO; + if (chip->legacy.block_bad) return chip->legacy.block_bad(chip, ofs); @@ -397,6 +434,10 @@ static int nand_do_write_oob(struct nand_chip *chip, loff_t to, return -EINVAL; } + /* Check if the region is secured */ + if (nand_region_is_secured(chip, to, ops->ooblen)) + return -EIO; + chipnr = (int)(to >> chip->chip_shift); /* @@ -3127,6 +3168,10 @@ static int nand_do_read_ops(struct nand_chip *chip, loff_t from, int retry_mode = 0; bool ecc_fail = false; + /* Check if the region is secured */ + if (nand_region_is_secured(chip, from, readlen)) + return -EIO; + chipnr = (int)(from >> chip->chip_shift); nand_select_target(chip, chipnr); @@ -3458,6 +3503,10 @@ static int nand_do_read_oob(struct nand_chip *chip, loff_t from, pr_debug("%s: from = 0x%08Lx, len = %i\n", __func__, (unsigned long long)from, readlen); + /* Check if the region is secured */ + if (nand_region_is_secured(chip, from, readlen)) + return -EIO; + stats = mtd->ecc_stats; len = mtd_oobavail(mtd, ops); @@ -3979,6 +4028,10 @@ static int nand_do_write_ops(struct nand_chip *chip, loff_t to, return -EINVAL; } + /* Check if the region is secured */ + if (nand_region_is_secured(chip, to, writelen)) + return -EIO; + column = to & (mtd->writesize - 1); chipnr = (int)(to >> chip->chip_shift); @@ -4180,6 +4233,10 @@ int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr, if (check_offs_len(chip, instr->addr, instr->len)) return -EINVAL; + /* Check if the region is secured */ + if (nand_region_is_secured(chip, instr->addr, instr->len)) + return -EIO; + /* Grab the lock and see if the device is available */ ret = nand_get_device(chip); if (ret) @@ -4995,6 +5052,31 @@ static bool of_get_nand_on_flash_bbt(struct device_node *np) return of_property_read_bool(np, "nand-on-flash-bbt"); } +static int of_get_nand_secure_regions(struct nand_chip *chip) +{ + struct device_node *dn = nand_get_flash_node(chip); + int nr_elem, i, j; + + nr_elem = of_property_count_elems_of_size(dn, "secure-regions", sizeof(u64)); + if (!nr_elem) + return 0; + + chip->nr_secure_regions = nr_elem / 2; + chip->secure_regions = kcalloc(chip->nr_secure_regions, sizeof(*chip->secure_regions), + GFP_KERNEL); + if (!chip->secure_regions) + return -ENOMEM; + + for (i = 0, j = 0; i < chip->nr_secure_regions; i++, j += 2) { + of_property_read_u64_index(dn, "secure-regions", j, + &chip->secure_regions[i].offset); + of_property_read_u64_index(dn, "secure-regions", j + 1, + &chip->secure_regions[i].size); + } + + return 0; +} + static int rawnand_dt_init(struct nand_chip *chip) { struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip)); @@ -5953,6 +6035,16 @@ static int nand_scan_tail(struct nand_chip *chip) goto err_free_interface_config; } + /* + * Look for secure regions in the NAND chip. These regions are supposed + * to be protected by a secure element like Trustzone. So the read/write + * accesses to these regions will be blocked in the runtime by this + * driver. + */ + ret = of_get_nand_secure_regions(chip); + if (ret) + goto err_free_interface_config; + /* Check, if we should skip the bad block table scan */ if (chip->options & NAND_SKIP_BBTSCAN) return 0; @@ -5960,10 +6052,13 @@ static int nand_scan_tail(struct nand_chip *chip) /* Build bad block table */ ret = nand_create_bbt(chip); if (ret) - goto err_free_interface_config; + goto err_free_secure_regions; return 0; +err_free_secure_regions: + kfree(chip->secure_regions); + err_free_interface_config: kfree(chip->best_interface_config); @@ -6051,6 +6146,9 @@ void nand_cleanup(struct nand_chip *chip) nanddev_cleanup(&chip->base); + /* Free secure regions data */ + kfree(chip->secure_regions); + /* Free bad block table memory */ kfree(chip->bbt); kfree(chip->data_buf); diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 6b3240e44310..17ddc900a1dc 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1036,6 +1036,16 @@ struct nand_manufacturer { void *priv; }; +/** + * struct nand_secure_region - NAND secure region structure + * @offset: Offset of the start of the secure region + * @size: Size of the secure region + */ +struct nand_secure_region { + u64 offset; + u64 size; +}; + /** * struct nand_chip - NAND Private Flash Chip Data * @base: Inherit from the generic NAND device @@ -1086,6 +1096,8 @@ struct nand_manufacturer { * NAND Controller drivers should not modify this value, but they're * allowed to read it. * @read_retries: The number of read retry modes supported + * @secure_regions: Structure containing the secure regions info + * @nr_secure_regions: Number of secure regions * @controller: The hardware controller structure which is shared among multiple * independent devices * @ecc: The ECC controller structure @@ -1135,6 +1147,8 @@ struct nand_chip { unsigned int suspended : 1; int cur_cs; int read_retries; + struct nand_secure_region *secure_regions; + u8 nr_secure_regions; /* Externals */ struct nand_controller *controller; From patchwork Fri Apr 2 15:01:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 414379 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1479437jai; Fri, 2 Apr 2021 08:02:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJze/1zSvhZ0VrK+wft5XWAJeHa6/2Y7AZ4vcN8P9EyUtX3Kd4OYV/sMG+hvmQgO8HFbLz5P X-Received: by 2002:a5d:654a:: with SMTP id z10mr15958712wrv.335.1617375734685; Fri, 02 Apr 2021 08:02:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617375734; cv=none; d=google.com; s=arc-20160816; b=ID2R5KpT8unHlWl5EoTHHW99DlGIfwgXHtI0GFeB39HsUTA+0XaMkxfOdXjD8eWEex 84BucGQmHNUr6GTFc62c4w2a9coxOISfmSLcYyDp0W7f3bFQdI9/jogibNdPT8co+E5Q U/vmdOKOZxyZb4Nqnp+/3JtyverTP5drnQY8TwTUAqsrG7qMX5BRWJjJAJnRuStTw9o3 Z2WAyPlX2Gtjd+7aonKLK2e51bU/Iv2kxm3Ah+S0bzYFy7MiJ3eWOBx6nLUy36eo171F uZgp41rjNn596as/EyBBRACFNEo1T/+Oa2BU5dTrKANDkYYgaZVIKrfKd5110yg5SnPJ dI+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ww076wtEw/l52B1eQC1HZmnMQQ8Ebtr9JfK+3ViX3so=; b=evHelnRiT4JQzVj4oO8CFHHuj9SPKei3NuSOptxfx5Z1HG1Emj2ffJHK7S+V2EG++2 NHomb7Oi2W2c79YVcP/AZyNj0OWQ+uraaPLlMeCtrYBUaIb4b42LQTXOcLOU/PruGIoC e87E871n2KHq/y+4DnIe/VbudSFso+8OyM04nh8f9XLOpWAWPXMMXQ1ZNMNeL6VC1owW HZuNwdYoDRuF19jseW57vhL4i7db0E+cGUoFfd1OCol3rnalhaHLuvkcvEVRkmp7lsQ9 AiqJ3eU+Fm50sGuIHOU93NFTVZWalu26lSrIh3+10uBer2H1/T+kMMWSLcNEBCiKp2W1 ZHLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ybrJ/XWa"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z5si9183462wro.380.2021.04.02.08.02.14; Fri, 02 Apr 2021 08:02:14 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ybrJ/XWa"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235069AbhDBPCM (ORCPT + 6 others); Fri, 2 Apr 2021 11:02:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235250AbhDBPCK (ORCPT ); Fri, 2 Apr 2021 11:02:10 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FBF4C06178C for ; Fri, 2 Apr 2021 08:02:07 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id v8so2622978plz.10 for ; Fri, 02 Apr 2021 08:02:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ww076wtEw/l52B1eQC1HZmnMQQ8Ebtr9JfK+3ViX3so=; b=ybrJ/XWa/mCxIE3noK0GCj+uKoLYgbMhcMQgqAAFk3B5fG/hCSYv/F1qtTUUcWn2Mu KxjVFEXJv/ORf4CfApwFggSqAln5Z3+I3OeriRpumvglfjwXC6h7dhcMnPmo07QJ/+ZG wwHjxZZb0wehKDxWPQ3AgMwikrdDxH05aNo11bZYQFDvjaEI1ie62PbcR0VTcNg5pz5n cAwjmX45Pn+yiGFbwQ3PqPvCRzA/Won4h4uiO+pCtAc2G9jgY63mG50TtcT9rQuodYpf XLU5cPfAZmlgju7jpwNLZsdsq3RtrSCd+icLLJESKQcSj5RD+fFev/lCAQ92Dm7dekXh GtPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ww076wtEw/l52B1eQC1HZmnMQQ8Ebtr9JfK+3ViX3so=; b=c9KES4DvDsESaKY1lXiMbJVRsUgEfrB1DqaXZh9WEHUvAUEslj0vl+tBpzM5+6TTGN Ggwpno8iYbas7esmsj3aZOGTwfCwOMpmtISYGKFA/YyaWraG7TeYnla+6VJeQAM7WsyI sQvOa5H7oEi6em4iia5qm83ZgYs9s7Pcx/Z7cNI+wdoEWcxt46ocVk1lCLMS9fO+W5rl VDOYDd0DNfSXihee+svKYAEun9cmJMu2Aeq3+4YiuOBts+4hVzCUW0cke9HyKQmmtKFi uU1KFSck8WRQhaZZNTiSdapoYLIlLOwilud+9lgXsj0C0RQrcbSj6b1NK3tzjuY3vdbl w0VQ== X-Gm-Message-State: AOAM5314Zw8ry6O2sZKqdzvIlb4IKf3mgpebrMhNW0rEuboqRP507Hro veNp6dhgbKPGRnIDNcF2YDX9 X-Received: by 2002:a17:90a:c249:: with SMTP id d9mr14444710pjx.104.1617375725992; Fri, 02 Apr 2021 08:02:05 -0700 (PDT) Received: from localhost.localdomain ([103.77.37.174]) by smtp.gmail.com with ESMTPSA id x7sm8773647pff.12.2021.04.02.08.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Apr 2021 08:02:05 -0700 (PDT) From: Manivannan Sadhasivam To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, boris.brezillon@collabora.com, Daniele.Palmas@telit.com, bjorn.andersson@linaro.org, Manivannan Sadhasivam Subject: [PATCH v11 4/4] mtd: rawnand: qcom: Add missing nand_cleanup() in error path Date: Fri, 2 Apr 2021 20:31:28 +0530 Message-Id: <20210402150128.29128-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210402150128.29128-1-manivannan.sadhasivam@linaro.org> References: <20210402150128.29128-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing nand_cleanup() in the alloc_bam_transaction() error path to cleanup the resources properly. Signed-off-by: Manivannan Sadhasivam --- drivers/mtd/nand/raw/qcom_nandc.c | 1 + 1 file changed, 1 insertion(+) -- 2.25.1 diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 87c23bb320bf..fe74cf3aece5 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2882,6 +2882,7 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, if (!nandc->bam_txn) { dev_err(nandc->dev, "failed to allocate bam transaction\n"); + nand_cleanup(chip); return -ENOMEM; } }