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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id 81sm6875972pfu.164.2021.04.01.20.56.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 20:56:12 -0700 (PDT) From: Shawn Guo To: Will Deacon Cc: Robin Murphy , Bjorn Andersson , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Shawn Guo Subject: [PATCH v2 1/3] ACPI/IORT: Consolidate use of SMMU device platdata Date: Fri, 2 Apr 2021 11:56:00 +0800 Message-Id: <20210402035602.9484-2-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210402035602.9484-1-shawn.guo@linaro.org> References: <20210402035602.9484-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently the platdata is being used in different way by SMMU and PMCG device. The former uses it for acpi_iort_node pointer passing, while the later uses it for model identifier. As it's been seen that the model identifier is useful for SMMU devices as well, let's consolidate the platdata use to get it accommodate both acpi_iort_node pointer and model identifier, so that all IORT devices (SMMU, SMMUv3 and PMCG) pass platdata in a consistent manner. With this change, model identifier is not specific to PMCG, so IORT_SMMU_V3_PMCG_GENERIC gets renamed to IORT_SMMU_GENERIC. While at it, the spaces used in model defines are converted to tabs. Signed-off-by: Shawn Guo --- drivers/acpi/arm64/iort.c | 31 ++++++++------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 +++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 9 ++++-- drivers/perf/arm_smmuv3_pmu.c | 8 ++++-- include/linux/acpi_iort.h | 11 ++++++-- 5 files changed, 36 insertions(+), 29 deletions(-) -- 2.17.1 diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 2494138a6905..e2a96d2d399a 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -1463,25 +1463,28 @@ static void __init arm_smmu_v3_pmcg_init_resources(struct resource *res, ACPI_EDGE_SENSITIVE, &res[2]); } -static struct acpi_platform_list pmcg_plat_info[] __initdata = { +static struct acpi_platform_list iort_plat_info[] __initdata = { /* HiSilicon Hip08 Platform */ {"HISI ", "HIP08 ", 0, ACPI_SIG_IORT, greater_than_or_equal, "Erratum #162001800", IORT_SMMU_V3_PMCG_HISI_HIP08}, { } }; -static int __init arm_smmu_v3_pmcg_add_platdata(struct platform_device *pdev) +static int __init iort_smmu_add_platdata(struct platform_device *pdev, + struct acpi_iort_node *node) { - u32 model; + struct iort_smmu_pdata pdata; int idx; - idx = acpi_match_platform_list(pmcg_plat_info); + pdata.node = node; + + idx = acpi_match_platform_list(iort_plat_info); if (idx >= 0) - model = pmcg_plat_info[idx].data; + pdata.model = iort_plat_info[idx].data; else - model = IORT_SMMU_V3_PMCG_GENERIC; + pdata.model = IORT_SMMU_GENERIC; - return platform_device_add_data(pdev, &model, sizeof(model)); + return platform_device_add_data(pdev, &pdata, sizeof(pdata)); } struct iort_dev_config { @@ -1494,7 +1497,6 @@ struct iort_dev_config { struct acpi_iort_node *node); int (*dev_set_proximity)(struct device *dev, struct acpi_iort_node *node); - int (*dev_add_platdata)(struct platform_device *pdev); }; static const struct iort_dev_config iort_arm_smmu_v3_cfg __initconst = { @@ -1516,7 +1518,6 @@ static const struct iort_dev_config iort_arm_smmu_v3_pmcg_cfg __initconst = { .name = "arm-smmu-v3-pmcg", .dev_count_resources = arm_smmu_v3_pmcg_count_resources, .dev_init_resources = arm_smmu_v3_pmcg_init_resources, - .dev_add_platdata = arm_smmu_v3_pmcg_add_platdata, }; static __init const struct iort_dev_config *iort_get_dev_cfg( @@ -1579,17 +1580,7 @@ static int __init iort_add_platform_device(struct acpi_iort_node *node, if (ret) goto dev_put; - /* - * Platform devices based on PMCG nodes uses platform_data to - * pass the hardware model info to the driver. For others, add - * a copy of IORT node pointer to platform_data to be used to - * retrieve IORT data information. - */ - if (ops->dev_add_platdata) - ret = ops->dev_add_platdata(pdev); - else - ret = platform_device_add_data(pdev, &node, sizeof(node)); - + ret = iort_smmu_add_platdata(pdev, node); if (ret) goto dev_put; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 8ca7415d785d..91c9a74d8ac6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3397,9 +3397,13 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev, { struct acpi_iort_smmu_v3 *iort_smmu; struct device *dev = smmu->dev; + struct iort_smmu_pdata *pdata = dev_get_platdata(dev); struct acpi_iort_node *node; - node = *(struct acpi_iort_node **)dev_get_platdata(dev); + if (pdata == NULL) + return -ENODEV; + + node = pdata->node; /* Retrieve SMMUv3 specific data */ iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index d8c6bfde6a61..d53ab3927a30 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1991,11 +1991,16 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev, struct arm_smmu_device *smmu) { struct device *dev = smmu->dev; - struct acpi_iort_node *node = - *(struct acpi_iort_node **)dev_get_platdata(dev); + struct iort_smmu_pdata *pdata = dev_get_platdata(dev); + struct acpi_iort_node *node; struct acpi_iort_smmu *iort_smmu; int ret; + if (pdata == NULL) + return -ENODEV; + + node = pdata->node; + /* Retrieve SMMU1/2 specific data */ iort_smmu = (struct acpi_iort_smmu *)node->node_data; diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index 74474bb322c3..77fcf5e7413a 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -747,17 +747,19 @@ static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu) static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu) { - u32 model; + struct iort_smmu_pdata *pdata = dev_get_platdata(smmu_pmu->dev); - model = *(u32 *)dev_get_platdata(smmu_pmu->dev); + if (pdata == NULL) + goto done; - switch (model) { + switch (pdata->model) { case IORT_SMMU_V3_PMCG_HISI_HIP08: /* HiSilicon Erratum 162001800 */ smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY; break; } +done: dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options); } diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 1a12baa58e40..678cdf036948 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -15,12 +15,17 @@ #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL) /* - * PMCG model identifiers for use in smmu pmu driver. Please note + * Model identifiers for use in SMMU drivers. Please note * that this is purely for the use of software and has nothing to * do with hardware or with IORT specification. */ -#define IORT_SMMU_V3_PMCG_GENERIC 0x00000000 /* Generic SMMUv3 PMCG */ -#define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */ +#define IORT_SMMU_GENERIC 0x00000000 /* Generic SMMU */ +#define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */ + +struct iort_smmu_pdata { + struct acpi_iort_node *node; + u32 model; +}; int iort_register_domain_token(int trans_id, phys_addr_t base, struct fwnode_handle *fw_node); From patchwork Fri Apr 2 03:56:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 414304 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1103169jai; Thu, 1 Apr 2021 20:56:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzBRVA1ZDPotv0gwhBt799grqZAuAQuPGLZJf++1hxblv1CY9Apco/0btACVr6ZlUMm0Uen X-Received: by 2002:aa7:c1d0:: with SMTP id d16mr13204753edp.153.1617335778472; Thu, 01 Apr 2021 20:56:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617335778; cv=none; d=google.com; s=arc-20160816; b=vAU06AYzD8j1thO+bpKQLMdf9OaRcLy0Kqc3TDFVpVyRvZZvgqTj3R+Q2b7MMfpPiZ lEm1T8jKeSnhh07go2WJOsjX+ALHZTKdXEazCu2wvPLLDWUuQkGuvSQRTQU0DPLyxMlD vXBmpopznrIXV40nHc71/7TEOurzMlg1D1F1EGYlbPuiYUa20Gw/dQeVVJ3afIL6Q1Cb 6ue+cPAsMA/ZiFOanbnqt17LQmjrK5I4SZK+ufg6pPRyrBdmPVhuh5Z6dJJgcxSbd6GP LLEeFsycAF6loQWPFoHhDLckrlLnmm5x16fDjLtQhu33knpgVYAaKK728eMekBNS15t6 Rt2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=/1tfZ3KHdBRbQ7iOu9GTGKGQQTHAyTZW2kSrQXENCl0=; b=n7zkDK/IPgp1yKfKmBXAb12C8vOYUvaGTo5hkL/IFDP0vgzB2HXidLwKjDFtwl0ic+ yLMKl8pW9U2rZjFH/7Y80WrvdXQSkAJ6KvgZRIOwu6xoqTUIIl81Qibjd1wrZoMX6h4/ BZ9BnrU/HAVCOF9h2Fh/gqJBgu32Ol92I4JKaQWPAjnKEsxcDR7rixPpCXuWzTnQKeRo N8tdziiL9fLvefeThS3FTLvf2H077rBRC3+AUd9DpvrK2n6pTsa3X8s36PyHadAOc5+B cdx3eEwQM3unk7jFZtFwHaXE2+EobtPaNJGLkkEDV+wzvu/LczaVsv0UHX1DeFx2Bx7I ArTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xy6IMHoI; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id 81sm6875972pfu.164.2021.04.01.20.56.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 20:56:15 -0700 (PDT) From: Shawn Guo To: Will Deacon Cc: Robin Murphy , Bjorn Andersson , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Shawn Guo Subject: [PATCH v2 2/3] ACPI/IORT: Add Qualcomm Snapdragon platforms to iort_plat_info[] Date: Fri, 2 Apr 2021 11:56:01 +0800 Message-Id: <20210402035602.9484-3-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210402035602.9484-1-shawn.guo@linaro.org> References: <20210402035602.9484-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SMMU driver on Qualcomm Snapdragon platforms needs to hook up some QCOM specific arm_smmu_impl. Define model identifier for QCOM SMMU and add Qualcomm SC8180X platform to iort_plat_info[], so that SMMU driver can detect the model and handle QCOM specific arm_smmu_impl. Some device chooses to use manufacturer name in IORT table, like Lenovo Flex 5G, while others use SoC vendor name, such as Microsoft Surface Pro X and Samsung Galaxy Book S. Signed-off-by: Shawn Guo --- drivers/acpi/arm64/iort.c | 5 +++++ include/linux/acpi_iort.h | 1 + 2 files changed, 6 insertions(+) -- 2.17.1 diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index e2a96d2d399a..f88b8c0a7d84 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -1467,6 +1467,11 @@ static struct acpi_platform_list iort_plat_info[] __initdata = { /* HiSilicon Hip08 Platform */ {"HISI ", "HIP08 ", 0, ACPI_SIG_IORT, greater_than_or_equal, "Erratum #162001800", IORT_SMMU_V3_PMCG_HISI_HIP08}, + /* Qualcomm Snapdragon Platform */ + { "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, + "QCOM SMMU", IORT_SMMU_QCOM }, + { "QCOM ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, + "QCOM SMMU", IORT_SMMU_QCOM }, { } }; diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 678cdf036948..66c859ea2abf 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -21,6 +21,7 @@ */ #define IORT_SMMU_GENERIC 0x00000000 /* Generic SMMU */ #define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */ +#define IORT_SMMU_QCOM 0x00000002 /* QCOM SMMU */ struct iort_smmu_pdata { struct acpi_iort_node *node; From patchwork Fri Apr 2 03:56:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 414305 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1103194jai; Thu, 1 Apr 2021 20:56:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw66kM/xo335eQQUBQO6Ivm8zw0qcbLYujUz/0IcND+uNa/bWEN+zjdw51DJT1DRNT4Jp8O X-Received: by 2002:a17:907:788e:: with SMTP id ku14mr12588175ejc.17.1617335783474; Thu, 01 Apr 2021 20:56:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617335783; cv=none; d=google.com; s=arc-20160816; b=0grijJ29NG3EVhz7fCuPEI8MHpV2kR8w0QkwXsROVNEweaESsa0i+ZCn3LX74xB8Wr juBKvS99j47TAoRbN4LuQnKf+nyDDlQkY+3ZEdVtaIMpGNIhwg5itkNm8DcnxU6Mknlt hZjtYVKW/J88edHZ+1b++PTpx7fEw4LwsLpqYvarf56Qi3vRvpmcr6UmYgi7oulXDsMG x887XUSe67lJsmdE306u47mafB+kD4bu+FU7HAxuT85BPm/7wZVEgOqfVNJyv1iTUpDh HqFW2B4e2UUZisQte3c6iciMwHBtIJq39yYnGlmwOwVYOuA1NyXoh9lfKNNRul1auNZj +pyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=3nQhD90sdJSzQdgo78ZKmX3OfUzD+szW/4QnSrBPjH4=; b=hVVbuj8w9S29vu5NCoKLEGAjHaldvfM8yq0BfY9VuAHNrxHgTVcX2zWD8AwGgjA/zz I0Ia5jglhCy9x/nadU/f205tG5LJFBEZjXeXutqbQ3+hxZ4TvP0OvPHMO9VMRiyNb4u/ +mVZ9lJadpwJNgtPCM5ROXGvUtfLI4hq2vowJ45H6d3x0IhkvpeBfN0MPwtPuQAbcYCx 4vSq7XgaCuRomvSmbb1gSDQbg+Oo4xQog739x9e89Uf+zJsv21euz8KBtkL881hMLOnS CIy42vXVk9Rz8MU0oimoSQT5ueOe3xOg5aZ39fdG63IeWYhe0t1z8RJtkRF13L+Oy0kb 4O1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P3kuftwO; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id 81sm6875972pfu.164.2021.04.01.20.56.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 20:56:18 -0700 (PDT) From: Shawn Guo To: Will Deacon Cc: Robin Murphy , Bjorn Andersson , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Shawn Guo Subject: [PATCH v2 3/3] iommu/arm-smmu-qcom: hook up qcom_smmu_impl for ACPI boot Date: Fri, 2 Apr 2021 11:56:02 +0800 Message-Id: <20210402035602.9484-4-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210402035602.9484-1-shawn.guo@linaro.org> References: <20210402035602.9484-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The hookup with qcom_smmu_impl is required to do ACPI boot on SC8180X based devices like Lenovo Flex 5G laptop and Microsoft Surface Pro X. Check IORT SMMU model identifier and create qcom_smmu_impl accordingly. (np == NULL) is used to check ACPI boot, because fwnode of SMMU device is a static allocation and thus helpers like has_acpi_companion() don't work here. Signed-off-by: Shawn Guo --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 82c7edc6e025..7ced0f93bc99 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -3,6 +3,7 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -340,6 +341,14 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) { const struct device_node *np = smmu->dev->of_node; + if (np == NULL) { + /* ACPI boot */ + struct iort_smmu_pdata *pdata = dev_get_platdata(smmu->dev); + + if (pdata && pdata->model == IORT_SMMU_QCOM) + return qcom_smmu_create(smmu, &qcom_smmu_impl); + } + if (of_match_node(qcom_smmu_impl_of_match, np)) return qcom_smmu_create(smmu, &qcom_smmu_impl);