From patchwork Fri May 25 12:50:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 136858 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp3545562lji; Fri, 25 May 2018 05:50:55 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpMVluf41VuRfxd2L2sRj6YLj+qIUEHGq6P1yNPVxhFd6RRhdjRaKXTDy6i3Swd25F/9Ji1 X-Received: by 2002:aa7:8009:: with SMTP id j9-v6mr2489212pfi.52.1527252654897; Fri, 25 May 2018 05:50:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527252654; cv=none; d=google.com; s=arc-20160816; b=mbX6AoSM5OhA5l0MkbLkt8l18nvpES4cO82yVzxyraUNqRvLrFjwOtL6EGo3rD0o4K TQy0nxi/CCidN6eBvbMgsAwKAYQSWX2PeOFdbzS83COtW/s3cLzb/rHsVp4L6cYFUjRx Kb3wU8ybbIbBucdgSN0oT99pGy9w/0IpNDgnKJVXI5Yy6fDtW29eviCvqwOJ3kkyY91a FYurbTxtNMn2p7ZSQjA5kWk0XP2iS+knfVreVXifARNATDlzPcAqyn6KBxn6exCFN9/n 7b408FyDRS/chSpka4MJ8u+mVTInUXOJy0bLPug/Y0ATIp6q6yLwlRv912MOVANSkIJV Me0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=O/yTdQPVMJILUgw3VoDzLotKcAuwyreX7IswwefdbaI=; b=Xy+CoaAbF8CUUTJipskhTs5isG7lStXLVH1l8FeyQLVROUQq907OWRkvyoiGLQkzRz iBR/RBO2DTFGJdyph0rv81sRr1AAtHLGrcTgy1bAzY9PHnsRwiaNELhydzCimV/CQKN8 S7D4TU7oyWe5iYw6tJHPhzIn9QRIjrr7VsZAyitsDjD0z7H1hNmd8h7gQD8iEGcXBgtZ +uppcFqB6QVLhoUT04PcZgR1wo6flQGBy3bcXHDmMZ0KHHB1rUHzLdFitKBn1bVQwTca l4FkbZdGuYGIsA8p+2HgTO6ZNESN6wkfJMT9ZvC31azs/pC9v4en68scR35nwspWhpLp qpVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O3OspeR6; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f131-v6si22924772pfc.316.2018.05.25.05.50.54; Fri, 25 May 2018 05:50:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O3OspeR6; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935747AbeEYMuw (ORCPT + 9 others); Fri, 25 May 2018 08:50:52 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:55907 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935375AbeEYMuu (ORCPT ); Fri, 25 May 2018 08:50:50 -0400 Received: by mail-wm0-f66.google.com with SMTP id a8-v6so14079109wmg.5 for ; Fri, 25 May 2018 05:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=O/yTdQPVMJILUgw3VoDzLotKcAuwyreX7IswwefdbaI=; b=O3OspeR67BYH5ldglDSRbZy2BSreOyBf6pDM+zG7L1o/NUd68MubiaydaMEZRJswdP d504Nc8viXfGHAPyhTadGnrsnRpX+PJ0AJDMeJB+M90MYD2Ik42Uo3aYvm6CAODtxvxy WwNgKTnlK8+yrpqedS4e0HJhtaLhuA/CTTWtQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=O/yTdQPVMJILUgw3VoDzLotKcAuwyreX7IswwefdbaI=; b=gSoPhaV0ItZtUo2p0Cx4ZAijbC/Wtj3INQ0SrmVHL9qq+JAjPvf7wiZFZXFxOxtJTS 0P9IubY3Q79yCy4tjpHBxaRIMbNQPTGpyctWps0kq88FfkDYSsjbgPUmnEVjmsycHObu f5ufTqChavum3ZgblVXYMe2+/wpDGWUFm5cGAoXbhsk26q//2kP2PgW0bSkUZzudOYBk Yn+DQ6TLOv8scqDcZLFdX15JFfB/Bx8n/U4Wax0mM5v/5eFe5tlWNFFVEEXbQUHTBByi b+OYrJSOA4ycidCWZOGCrpHqsiEFYeVgbJIogSO1jLveNPgSTs63wXZcvVmEtqrpp/vg 5dHA== X-Gm-Message-State: ALKqPwdh3ntpfFZ+8Bkc3zF9oUiM9zy1CS2vNT/uSSm83MB7RT0DiyAJ hxkH43ftRoj7eKFdtu0ehcacY6a7ZZI= X-Received: by 2002:a1c:ea1a:: with SMTP id i26-v6mr1839093wmh.11.1527252648953; Fri, 25 May 2018 05:50:48 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id p7-v6sm22923840wrj.85.2018.05.25.05.50.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 May 2018 05:50:48 -0700 (PDT) From: Ard Biesheuvel To: netdev@vger.kernel.org Cc: davem@davemloft.net, Ard Biesheuvel , Robin Murphy , Jassi Brar , Masahisa Kojima , Ilias Apalodimas Subject: [PATCH] net: netsec: reduce DMA mask to 40 bits Date: Fri, 25 May 2018 14:50:37 +0200 Message-Id: <20180525125037.779-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The netsec network controller IP can drive 64 address bits for DMA, and the DMA mask is set accordingly in the driver. However, the SynQuacer SoC, which is the only silicon incorporating this IP at the moment, integrates this IP in a manner that leaves address bits [63:40] unconnected. Up until now, this has not resulted in any problems, given that the DDR controller doesn't decode those bits to begin with. However, recent firmware updates for platforms incorporating this SoC allow the IOMMU to be enabled, which does decode address bits [47:40], and allocates top down from the IOVA space, producing DMA addresses that have bits set that have been left unconnected. Both the DT and ACPI (IORT) descriptions of the platform take this into account, and only describe a DMA address space of 40 bits (using either dma-ranges DT properties, or DMA address limits in IORT named component nodes). However, even though our IOMMU and bus layers may take such limitations into account by setting a narrower DMA mask when creating the platform device, the netsec probe() entrypoint follows the common practice of setting the DMA mask uncondionally, according to the capabilities of the IP block itself rather than to its integration into the chip. It is currently unclear what the correct fix is here. We could hack around it by only setting the DMA mask if it deviates from its default value of DMA_BIT_MASK(32). However, this makes it impossible for the bus layer to use DMA_BIT_MASK(32) as the bus limit, and so it appears that a more comprehensive approach is required to take DMA limits imposed by the SoC as a whole into account. In the mean time, let's limit the DMA mask to 40 bits. Given that there is currently only one SoC that incorporates this IP, this is a reasonable approach that can be backported to -stable and buys us some time to come up with a proper fix going forward. Fixes: 533dd11a12f6 ("net: socionext: Add Synquacer NetSec driver") Cc: Robin Murphy Cc: Jassi Brar Cc: Masahisa Kojima Cc: Ilias Apalodimas Signed-off-by: Ard Biesheuvel --- Please cc to -stable (v4.16+) drivers/net/ethernet/socionext/netsec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.0 Reviewed-by: Robin Murphy diff --git a/drivers/net/ethernet/socionext/netsec.c b/drivers/net/ethernet/socionext/netsec.c index f4c0b02ddad8..59fbf74dcada 100644 --- a/drivers/net/ethernet/socionext/netsec.c +++ b/drivers/net/ethernet/socionext/netsec.c @@ -1674,8 +1674,8 @@ static int netsec_probe(struct platform_device *pdev) if (ret) goto unreg_napi; - if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) - dev_warn(&pdev->dev, "Failed to enable 64-bit DMA\n"); + if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40))) + dev_warn(&pdev->dev, "Failed to set DMA mask\n"); ret = register_netdev(ndev); if (ret) {