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envelope-from=haibo.xu@linaro.org; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, richard.henderson@linaro.org, abologna@redhat.com, Haibo Xu , philmd@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Haibo Xu --- linux-headers/asm-arm64/kvm.h | 2 ++ linux-headers/linux/kvm.h | 1 + 2 files changed, 3 insertions(+) -- 2.17.1 diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h index b6a0eaa32a..77b995a26c 100644 --- a/linux-headers/asm-arm64/kvm.h +++ b/linux-headers/asm-arm64/kvm.h @@ -106,6 +106,7 @@ struct kvm_regs { #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ +#define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */ struct kvm_vcpu_init { __u32 target; @@ -334,6 +335,7 @@ struct kvm_vcpu_events { #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 +#define KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ 9 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 020b62a619..ce4630c4db 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1056,6 +1056,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_ENFORCE_PV_FEATURE_CPUID 190 #define KVM_CAP_SYS_HYPERV_CPUID 191 #define KVM_CAP_DIRTY_LOG_RING 192 +#define KVM_CAP_ARM_EL2 193 #ifdef KVM_CAP_IRQ_ROUTING From patchwork Thu Apr 1 10:40:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 413575 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp438478jai; 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envelope-from=haibo.xu@linaro.org; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, richard.henderson@linaro.org, abologna@redhat.com, Haibo Xu , philmd@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Haibo Xu --- target/arm/kvm64.c | 5 +++++ target/arm/kvm_arm.h | 13 +++++++++++++ 2 files changed, 18 insertions(+) -- 2.17.1 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index dff85f6db9..9cacaf2eb8 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -721,6 +721,11 @@ bool kvm_arm_steal_time_supported(void) return kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); } +bool kvm_arm_el2_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL2); +} + QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 34f8daa377..7d7fc7981b 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -285,6 +285,14 @@ void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp); */ bool kvm_arm_steal_time_supported(void); +/** + * kvm_arm_el2_supported: + * + * Returns: true if KVM can enable el2(nested virtualization) + * and false otherwise. + */ +bool kvm_arm_el2_supported(void); + /** * kvm_arm_aarch32_supported: * @@ -398,6 +406,11 @@ static inline bool kvm_arm_steal_time_supported(void) return false; } +static inline bool kvm_arm_el2_supported(void) +{ + return false; +} + /* * These functions should never actually be called without KVM support. */ From patchwork Thu Apr 1 10:40:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 413578 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp439923jai; 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Signed-off-by: Haibo Xu --- target/arm/cpu.c | 11 ++++++++++ target/arm/cpu.h | 4 ++++ target/arm/cpu64.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ae04884408..30cc330f50 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1349,6 +1349,17 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) return; } } + + /* + * Currently, vCPU feature 'el2' only supported in KVM mode. + */ + if (kvm_enabled()) { + arm_cpu_el2_finalize(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + } } if (kvm_enabled()) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 193a49ec7f..19fa9cfbfd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -203,10 +203,12 @@ typedef struct { # define ARM_MAX_VQ 16 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); +void arm_cpu_el2_finalize(ARMCPU *cpu, Error **errp); #else # define ARM_MAX_VQ 1 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } +static inline void arm_cpu_el2_finalize(ARMCPU *cpu, Error **errp) { } #endif typedef struct ARMVectorReg { @@ -1058,6 +1060,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64); void aarch64_add_sve_properties(Object *obj); +void aarch64_add_el2_properties(Object *obj); /* * SVE registers are encoded in KVM's memory in an endianness-invariant format. @@ -1089,6 +1092,7 @@ static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n, bool a) { } static inline void aarch64_add_sve_properties(Object *obj) { } +static inline void aarch64_add_el2_properties(Object *obj) { } #endif void aarch64_sync_32_to_64(CPUARMState *env); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0a9e968c9..3f3f2c5495 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -603,6 +603,58 @@ static Property arm_cpu_pauth_property = static Property arm_cpu_pauth_impdef_property = DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); +void arm_cpu_el2_finalize(ARMCPU *cpu, Error **errp) +{ + if (cpu->has_el2) { + if (!kvm_enabled() || !kvm_arm_el2_supported()) { + error_setg(errp, "'el2' cannot be enabled on this host"); + return; + } + } + + if (cpu->has_el2) { + set_feature(&cpu->env, ARM_FEATURE_EL2); + } else { + unset_feature(&cpu->env, ARM_FEATURE_EL2); + } +} + +static bool arm_get_el2(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + return cpu->has_el2; +} + +static void arm_set_el2(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + if (value) { + if (!kvm_enabled() || !kvm_arm_el2_supported()) { + error_setg(errp, "'el2' cannot be enabled on this host"); + return; + } + set_feature(&cpu->env, ARM_FEATURE_EL2); + } else { + unset_feature(&cpu->env, ARM_FEATURE_EL2); + } + + cpu->has_el2 = value; +} + +void aarch64_add_el2_properties(Object *obj) +{ + /* + * vCPU feature 'el2' is only available in KVM mode, and is + * disabled by default to keep in line with that in TCG mode. + */ + ARM_CPU(obj)->has_el2 = false; + object_property_add_bool(obj, "el2", arm_get_el2, arm_set_el2); + object_property_set_description(obj, "el2", "Set off to disable " + "nested virtulization."); +} + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; From patchwork Thu Apr 1 10:40:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 413573 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp437249jai; Thu, 1 Apr 2021 03:42:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyq1RGmdKo7a7O0k6cqhuVfo6BTwPlv/GBSHtPi+aQzCntm5aRd1weisUXc6dS+6y7jfJaN X-Received: by 2002:a6b:661a:: with SMTP id a26mr6046684ioc.124.1617273733582; Thu, 01 Apr 2021 03:42:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617273733; cv=none; d=google.com; s=arc-20160816; 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[209.51.188.17]) by mx.google.com with ESMTPS id p8si4108633ilm.53.2021.04.01.03.42.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 01 Apr 2021 03:42:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cEOgnCkF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lRumD-0007ak-1X for patch@linaro.org; Thu, 01 Apr 2021 06:42:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46738) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lRulK-00077i-Kw for qemu-devel@nongnu.org; Thu, 01 Apr 2021 06:41:18 -0400 Received: from mail-ot1-x32f.google.com ([2607:f8b0:4864:20::32f]:41503) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lRulI-0002Pi-Ow for qemu-devel@nongnu.org; Thu, 01 Apr 2021 06:41:18 -0400 Received: by mail-ot1-x32f.google.com with SMTP id l12-20020a9d6a8c0000b0290238e0f9f0d8so1681719otq.8 for ; Thu, 01 Apr 2021 03:41:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZOQB26mZhLmXCQu+JfKJIpuDxvkGsibNUVfx4FrnidQ=; b=cEOgnCkFngCcBDovQ0d30yVK1Z1NZCncTf6hUxqx3v+dJzXrrgNdqilRaZcnb7lYhQ pGEhtJbr2Pa2RfOKbURro47fhxQCJ8T0u4garYxmJ6nvucZGxofsfngTyIVFDVN6OQ/0 gSR7jGHCY0c6kpn5Z8kj5/w1GgrQxKD8heymweLpFMqBYGT8fLDTz7OJjK8OdJ4s4OPy 6dcneIdcNnh4JR+iRS/9dW7hgWE6fnWm6mb3toWlonb4/OccEDRFTugwquC56OyQ525n tgNTVK/hxgoJWC6TMYvSD5ZWXdNbzdgyNmVbNlRW+63mqr3VfU8hRIcl1ZEBotXWLc8t Ssqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZOQB26mZhLmXCQu+JfKJIpuDxvkGsibNUVfx4FrnidQ=; b=YPaAgMpWShgV6r8MHFRKB6SDPSyQ42zIX8nUgyOn5rY5R5Apd0E8N+71U9Mza0B647 I7XBdK2pmA2UnK8nNKNfFBsph7NJN0x3ttKONw60hB1r2Fusm3pREweNKxWyCCbG+u/A oHq/115lzzNdACsl4AXY6jyI1tMYwOKclGIrFjGkQoyxlegj1PsvgC7Pnucjh1pGOQJT RY2sWD0dmItjCfOZ8ZmRXDeOczJFtlddol5An05x30+sCQ+ojNAOJ+obh4P66SDi98VV DGzktDpoV9KXQHOIcov0T5XPg/iTqf0g3dz1RBbStuU/QaVQsmDoiJoGmx9s70E6ENeR /8Ww== X-Gm-Message-State: AOAM532jJLFijYCSSQL62ljrI3kWuWKfbr8mtN88AEOlLalUjlLBs/8z 8+/IBwFD/N0gzKYpLQ62xHwwOyv5P+zZeow= X-Received: by 2002:a9d:740a:: with SMTP id n10mr6385570otk.27.1617273675553; Thu, 01 Apr 2021 03:41:15 -0700 (PDT) Received: from localhost.localdomain ([147.75.106.138]) by smtp.gmail.com with ESMTPSA id a6sm1069066otq.79.2021.04.01.03.41.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 03:41:15 -0700 (PDT) From: Haibo Xu To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [PATCH v2 4/6] hw/intc/arm_gicv3: Enable support for setting vGIC maintenance IRQ Date: Thu, 1 Apr 2021 10:40:56 +0000 Message-Id: <49a4944e2f148c56938380b981afe154b7a8b7ee.1617272690.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=haibo.xu@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, richard.henderson@linaro.org, abologna@redhat.com, Haibo Xu , philmd@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Using the new VGIC KVM device attribute to set the maintenance IRQ. This is fixed to use IRQ 25(PPI 9), as a platform decision matching the arm64 SBSA recommendation. Signed-off-by: Haibo Xu --- hw/arm/virt.c | 5 +++++ hw/intc/arm_gicv3_common.c | 1 + hw/intc/arm_gicv3_kvm.c | 16 ++++++++++++++++ include/hw/intc/arm_gicv3_common.h | 1 + 4 files changed, 23 insertions(+) -- 2.17.1 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index aa2bbd14e0..92d46ebcfe 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -663,6 +663,11 @@ static void create_gic(VirtMachineState *vms) qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); } + + if (kvm_irqchip_in_kernel()) { + bool el2 = object_property_get_bool(OBJECT(first_cpu), "el2", NULL); + qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", el2); + } } else { if (!kvm_irqchip_in_kernel()) { qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 58ef65f589..3ac10c8e61 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -495,6 +495,7 @@ static Property arm_gicv3_common_properties[] = { DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0), + DEFINE_PROP_BOOL("has-virtualization-extensions", GICv3State, virt_extn, 0), DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions, redist_region_count, qdev_prop_uint32, uint32_t), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 65a4c880a3..1e1ca66e2c 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -826,6 +826,22 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); + if (s->virt_extn) { + bool maint_irq_allowed; + uint32_t maint_irq = 25; + + maint_irq_allowed = + kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, 0); + if (!maint_irq_allowed) { + error_setg(errp, "VGICv3 setting maintenance IRQ are not " + "supported by this host kernel"); + return; + } + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, + 0, &maint_irq, true, &error_abort); + } + kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0); diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index 91491a2f66..921ddc2c5f 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -220,6 +220,7 @@ struct GICv3State { uint32_t num_irq; uint32_t revision; bool security_extn; + bool virt_extn; bool irq_reset_nonsecure; bool gicd_no_migration_shift_bug; From patchwork Thu Apr 1 10:40:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 413576 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp438767jai; Thu, 1 Apr 2021 03:44:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyYvcQ17LHhrTdMlRcX8b/D6yRG2NqscEvBJ0swefefjdUJORU9afzQXstwagxvCGxkIilL X-Received: by 2002:a92:6810:: with SMTP id d16mr6442098ilc.88.1617273871489; Thu, 01 Apr 2021 03:44:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617273871; cv=none; d=google.com; s=arc-20160816; b=ouc6oIpO3xq74XXO6N3CtMj8n/NmS8XfseiCZidAkjYLI/IjEI41PIyImfRna3Vurj bycqYW+QCFU6UKKO0ZmBzosFlTJsYNZeaXBw7CtgJg5QHznsBK/luboa84/O3yKpJfSB jNwrN/Dv1zQJIbqfEOL3OrxSMFCkuMI8uAbEs4oEyfjNGHr7+u2XIKoY/W++7OORyrDi C+QBM/ZTTqsCsKiHUFPYcBGd6Sp8Jk/VA1tEpbQkhGx4IdiBaRPkiNXElejO2nWPy/91 IHJ5Cso7x3c3wyiqQWkVExOD5O86ycIJ2sWIhLLuCstwzATOMUNItQIqNIu1h0hWgJ22 P/Ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7GP5EWBOufrga+3kB4LulNdONpwe1B1Vve3c5Unp/SM=; b=09hbDQjF/mPl2w8moX/tzA5pxXQbvpteND3QCzBIwW8RqG/BrnYJSAUlGAc6u/kQ9Q 4//ENAnIJii2Ffmz6B7ixVYBctUh71dPt8cS+iAQhoXSOQ5CuMYFQTpuAF9MqCb+6A1u AI4wSjTrMCSFZ59cjbOrrNj1TqfsSgx48BZsp+sjHJk4E2JrDZaYrhKTsnwiTKpPGZqE OREGGaK4KTtUoFYMoLpQE4WulOgwD9qF5UECqu0QP4xFC+NhHqFgrvG5EQBdkz9MfV8f N/4waQeCjsNll6U4iX9iovr4k9wNpJP1gqobpEA7HwijcdOQyAa2u9SwWCV78lu7cKxK IW9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=N8s3Vyqa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x6si4718326ilv.134.2021.04.01.03.44.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 01 Apr 2021 03:44:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=N8s3Vyqa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lRuoQ-0002E3-SE for patch@linaro.org; Thu, 01 Apr 2021 06:44:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lRulL-0007BD-UY for qemu-devel@nongnu.org; Thu, 01 Apr 2021 06:41:19 -0400 Received: from mail-ot1-x333.google.com ([2607:f8b0:4864:20::333]:33481) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lRulJ-0002Q8-SS for qemu-devel@nongnu.org; Thu, 01 Apr 2021 06:41:19 -0400 Received: by mail-ot1-x333.google.com with SMTP id s11-20020a056830124bb029021bb3524ebeso1762092otp.0 for ; Thu, 01 Apr 2021 03:41:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7GP5EWBOufrga+3kB4LulNdONpwe1B1Vve3c5Unp/SM=; b=N8s3VyqaA5j1K7gTuKQyZ3SwynhIrvrdaHQu0PtzeaOvtj2bxCwNErcsd+tjj80giN nNJ7ZO+NRfkMihBBGpXa8s7L4FgVFIk69th5ZObD7Z7u5Lhk7K8gnVD7aDkRas8OQ+Jo YBh3ICwegcaw98mXexDWCFNY+XF6sY4C8V7cuGiDUe41/0PewAuXWDhPeOq9Kf88n7AV Q+ZQZLrPSbLWJJeW7RZGp5BWEmtqcz1jciLuUZNqo95ZzdvEsFgzJ94m/gkgwMCKcX6k bRTMXTI/VW4Wh4JZIDG9wP8EFqiE57BJGGXzeS9kXLyzojAvlZmYZkI3MsblvvnLfAZa pQNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7GP5EWBOufrga+3kB4LulNdONpwe1B1Vve3c5Unp/SM=; b=RbMAi/JIbV3BezXaK86wF25z5a0wzMEQWMwVK2IPNIW5W8fASoSPXJNkrbeqyczrhB bLwNCpatGNOSHm7t5IZe8pYU+SI7VeS7NjafCgsvNp6ZZfubXSCCXnEWQJrpjb7OoS45 RY1GemZkP8aVDfxGAJ2qfOBOVjTyQ9J5FlquSd6h5DhCdHEkMvezlwXbAtD79Bjb2BSm sAkUo/Fn3++H33qR67wULKr7hjcJBkb4vx8a+7KlOX4NQRoa4H2vZm+rH54CRMHrJqW2 5RREadu03FY3Ga8syh0i6MsaYf3uMSPmkwu4i5SANLrcQ/3DDTTiDo3B4kOPUPrdGWga soIg== X-Gm-Message-State: AOAM5331xYvvj8ObHypSsuiEstrFWok+k9Y1WXjs0T0eWHgU3B0fo3OT m3/iWCOeAT4Y3JAMbmbOeKT5DPTZTuPdNGY= X-Received: by 2002:a05:6830:14d2:: with SMTP id t18mr2404432otq.50.1617273676505; Thu, 01 Apr 2021 03:41:16 -0700 (PDT) Received: from localhost.localdomain ([147.75.106.138]) by smtp.gmail.com with ESMTPSA id a6sm1069066otq.79.2021.04.01.03.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 03:41:16 -0700 (PDT) From: Haibo Xu To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [PATCH v2 5/6] target/arm/cpu: Enable 'el2' to work with host/max cpu Date: Thu, 1 Apr 2021 10:40:57 +0000 Message-Id: <37df1b1872f15086dd1d066e53dc1eedaf114051.1617272690.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=haibo.xu@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, richard.henderson@linaro.org, abologna@redhat.com, Haibo Xu , philmd@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Turn off the 'el2' cpu property by default to keep in line with that in TCG mode, i.e. we can now use '-cpu max|host,el2=on' to enable the nested virtualization. Signed-off-by: Haibo Xu --- hw/arm/virt.c | 14 ++++++++++---- target/arm/cpu.c | 3 ++- target/arm/cpu64.c | 1 + target/arm/kvm64.c | 10 ++++++++++ 4 files changed, 23 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 92d46ebcfe..74340e21bd 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -454,6 +454,7 @@ static void fdt_add_gic_node(VirtMachineState *vms) { MachineState *ms = MACHINE(vms); char *nodename; + bool has_el2 = object_property_get_bool(OBJECT(first_cpu), "el2", NULL); vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); @@ -491,7 +492,7 @@ static void fdt_add_gic_node(VirtMachineState *vms) 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); } - if (vms->virt) { + if (vms->virt || has_el2) { qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, GIC_FDT_IRQ_FLAGS_LEVEL_HI); @@ -1911,8 +1912,8 @@ static void machvirt_init(MachineState *machine) } if (vms->virt && kvm_enabled()) { - error_report("mach-virt: KVM does not support providing " - "Virtualization extensions to the guest CPU"); + error_report("mach-virt: VM 'virtualization' feature is not supported " + "in KVM mode, please use CPU feature 'el2' instead"); exit(1); } @@ -1950,11 +1951,16 @@ static void machvirt_init(MachineState *machine) object_property_set_bool(cpuobj, "has_el3", false, NULL); } - if (!vms->virt && object_property_find(cpuobj, "has_el2")) { + if (!vms->virt && !kvm_enabled() && + object_property_find(cpuobj, "has_el2")) { object_property_set_bool(cpuobj, "has_el2", false, NULL); } if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { + if (kvm_enabled() && ARM_CPU(cpuobj)->has_el2) { + vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; + } + object_property_set_int(cpuobj, "psci-conduit", vms->psci_conduit, NULL); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 30cc330f50..9530a2c4bf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1099,7 +1099,7 @@ static Property arm_cpu_rvbar_property = #ifndef CONFIG_USER_ONLY static Property arm_cpu_has_el2_property = - DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); + DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, false); static Property arm_cpu_has_el3_property = DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); @@ -2018,6 +2018,7 @@ static void arm_host_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); + aarch64_add_el2_properties(obj); } arm_cpu_post_init(obj); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3f3f2c5495..ae8811d09e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -666,6 +666,7 @@ static void aarch64_max_initfn(Object *obj) if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); + aarch64_add_el2_properties(obj); } else { uint64_t t; uint32_t u; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 9cacaf2eb8..7bf892404f 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -500,6 +500,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) */ int fdarray[3]; bool sve_supported; + bool el2_supported; uint64_t features = 0; uint64_t t; int err; @@ -646,6 +647,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; + el2_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_EL2) > 0; kvm_arm_destroy_scratch_host_vcpu(fdarray); @@ -660,6 +662,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ahcf->isar.id_aa64pfr0 = t; } + /* Use the ARM_FEATURE_EL2 bit to keep inline with that in TCG mode. */ + if (el2_supported) { + features |= 1ULL << ARM_FEATURE_EL2; + } + /* * We can assume any KVM supporting CPU is at least a v8 * with VFPv4+Neon; this in turn implies most of the other @@ -861,6 +868,9 @@ int kvm_arch_init_vcpu(CPUState *cs) assert(kvm_arm_sve_supported()); cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE; } + if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_HAS_EL2; + } /* Do KVM_ARM_VCPU_INIT ioctl */ ret = kvm_arm_vcpu_init(cs); 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Date: Thu, 1 Apr 2021 10:40:58 +0000 Message-Id: <50db1700b4df48acbecfda077b2220a0e3cf6b49.1617272690.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=haibo.xu@linaro.org; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, richard.henderson@linaro.org, abologna@redhat.com, Haibo Xu , philmd@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Haibo Xu --- target/arm/monitor.c | 2 +- tests/qtest/arm-cpu-features.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/monitor.c b/target/arm/monitor.c index 80c64fa355..6c39238925 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -90,7 +90,7 @@ QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); * then the order that considers those dependencies must be used. */ static const char *cpu_model_advertised_features[] = { - "aarch64", "pmu", "sve", + "aarch64", "pmu", "sve", "el2", "sve128", "sve256", "sve384", "sve512", "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 8252b85bb8..be07bf0c76 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -509,6 +509,7 @@ static void test_query_cpu_model_expansion_kvm(const void *data) if (g_str_equal(qtest_get_arch(), "aarch64")) { bool kvm_supports_steal_time; bool kvm_supports_sve; + bool kvm_supports_el2; char max_name[8], name[8]; uint32_t max_vq, vq; uint64_t vls; @@ -533,10 +534,12 @@ static void test_query_cpu_model_expansion_kvm(const void *data) */ assert_has_feature(qts, "host", "kvm-steal-time"); assert_has_feature(qts, "host", "sve"); + assert_has_feature(qts, "host", "el2"); resp = do_query_no_props(qts, "host"); kvm_supports_steal_time = resp_get_feature(resp, "kvm-steal-time"); kvm_supports_sve = resp_get_feature(resp, "sve"); + kvm_supports_el2 = resp_get_feature(resp, "el2"); vls = resp_get_sve_vls(resp); qobject_unref(resp); @@ -602,11 +605,17 @@ static void test_query_cpu_model_expansion_kvm(const void *data) } else { g_assert(vls == 0); } + + if (kvm_supports_el2) { + assert_set_feature(qts, "host", "el2", false); + assert_set_feature(qts, "host", "el2", true); + } } else { assert_has_not_feature(qts, "host", "aarch64"); assert_has_not_feature(qts, "host", "pmu"); assert_has_not_feature(qts, "host", "sve"); assert_has_not_feature(qts, "host", "kvm-steal-time"); + assert_has_not_feature(qts, "host", "el2"); } qtest_quit(qts);