From patchwork Wed Mar 31 08:28:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 413058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 033B2C433E3 for ; Wed, 31 Mar 2021 08:29:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C5330619EF for ; Wed, 31 Mar 2021 08:29:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232035AbhCaI3C (ORCPT ); Wed, 31 Mar 2021 04:29:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230385AbhCaI3B (ORCPT ); Wed, 31 Mar 2021 04:29:01 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0B58C061574; Wed, 31 Mar 2021 01:29:00 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id il9-20020a17090b1649b0290114bcb0d6c2so805109pjb.0; Wed, 31 Mar 2021 01:29:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F5NUtjS6dxfsjXtQ30HdpWBe6Y3/aPDV1SqF5ADpjiM=; b=ny/yYl4F1Pyjiht+n0Z24bFu+natEzx53+EwmBOKQUC4py/lz2p099lks0VXZZ3ys9 KCXCofA4wVF5O1KIu4J/+VjdDZSCRIN6ZJpEcPXX6YzOh6lqjhieWlrOL7gPIMlyHKDq rujclv32Xv4aMtRAFb+vFoaoQEjEcwdE4JxVR6ZMUp4n42zFSH0PE053KswNQE/ikc/P BWpgyRGlL7RBK6bN3JNibVK7dVgfpWhNNmXpRs5QTCDLsIAxDeex+1p1Vjmx4lw5HfUD vWyYFRKbayN356VvQZsquLoGNjkTV4HejAwO3/9/pNEI6y/IeSNPqeIHQg7BgQImgxQv dAZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F5NUtjS6dxfsjXtQ30HdpWBe6Y3/aPDV1SqF5ADpjiM=; b=B71Ow6qQBTMSH/nHHkloKqM8nIMAsHUyXhBa05tvGsQuOvXp2s/5Dr6ummhERhK4EV qDm5sK6SobeqewtzaRBUe6981mebCpvVLC83u1oOdh+2c+iwigVqjsq+lM/bcJxzkGGf mHcTjl4G0yEwx8CWA8YLVWS9XIYup9d7Ber6UXNHCvPYViFI7ic08dvYpAgUkpUK+Ra3 A+2KP9zsX1xsXDBJCjHplLFRXWHZLnIFigLBzeQPNBaNmY95DQKLzaOe9VWXL8s9lQIn 8OmLGXi9Seq6MV8phDkpxyRw1QUUTY4G/rgYonn0sAC4Yd4yoh+JWBu8fPu3xW4/ZR8z cuow== X-Gm-Message-State: AOAM532E7IKnEgBMFCdCdjg8qOaJrqUraXki5V37LfNZpEyfdYVlG0VZ TpXAUzU6Kp1C0f5hMW2g9F8= X-Google-Smtp-Source: ABdhPJxbhPeX1fiW16IOjwj6m0w3Xq2M7a5cxBDHcx304ac76E5RljQgbU9jENBAgd7Chi3afCKj1Q== X-Received: by 2002:a17:90a:17ea:: with SMTP id q97mr2466688pja.71.1617179340565; Wed, 31 Mar 2021 01:29:00 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id v1sm1420991pjt.1.2021.03.31.01.28.55 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Mar 2021 01:29:00 -0700 (PDT) From: dillon.minfei@gmail.com To: robh@kernel.org, valentin.caron@foss.st.com, Alexandre.torgue@foss.st.com, rong.a.chen@intel.com, a.fatoum@pengutronix.de, mcoquelin.stm32@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, afzal.mohd.ma@gmail.com, gregkh@linuxfoundation.org, erwan.leray@foss.st.com, erwan.leray@st.com, linux-serial@vger.kernel.org, lkp@intel.com, patrice.chotard@foss.st.com, corbet@lwn.net, linux-doc@vger.kernel.org, pali@kernel.org, mchehab+huawei@kernel.org, andrew@lunn.ch Cc: dillon min Subject: [PATCH v9 1/6] Documentation: arm: stm32: Add stm32h750 value line doc Date: Wed, 31 Mar 2021 16:28:40 +0800 Message-Id: <1617179325-6383-2-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617179325-6383-1-git-send-email-dillon.minfei@gmail.com> References: <1617179325-6383-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min This patchset add support for soc stm32h750, stm32h750 has mirror different from stm32h743 item stm32h743 stm32h750 flash size: 2MiB 128KiB adc: none 3 crypto-hash: none aes/hamc/des/tdes/md5/sha detail information can be found at: https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html Signed-off-by: dillon min --- v9: no changes Documentation/arm/index.rst | 1 + Documentation/arm/stm32/stm32h750-overview.rst | 34 ++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 Documentation/arm/stm32/stm32h750-overview.rst diff --git a/Documentation/arm/index.rst b/Documentation/arm/index.rst index b4bea32472b6..d4f34ae9e6f4 100644 --- a/Documentation/arm/index.rst +++ b/Documentation/arm/index.rst @@ -52,6 +52,7 @@ SoC-specific documents stm32/stm32f746-overview stm32/overview stm32/stm32h743-overview + stm32/stm32h750-overview stm32/stm32f769-overview stm32/stm32f429-overview stm32/stm32mp157-overview diff --git a/Documentation/arm/stm32/stm32h750-overview.rst b/Documentation/arm/stm32/stm32h750-overview.rst new file mode 100644 index 000000000000..0e51235c9547 --- /dev/null +++ b/Documentation/arm/stm32/stm32h750-overview.rst @@ -0,0 +1,34 @@ +================== +STM32H750 Overview +================== + +Introduction +------------ + +The STM32H750 is a Cortex-M7 MCU aimed at various applications. +It features: + +- Cortex-M7 core running up to @480MHz +- 128K internal flash, 1MBytes internal RAM +- FMC controller to connect SDRAM, NOR and NAND memories +- Dual mode QSPI +- SD/MMC/SDIO support +- Ethernet controller +- USB OTFG FS & HS controllers +- I2C, SPI, CAN busses support +- Several 16 & 32 bits general purpose timers +- Serial Audio interface +- LCD controller +- HDMI-CEC +- SPDIFRX +- DFSDM + +Resources +--------- + +Datasheet and reference manual are publicly available on ST website (STM32H750_). + +.. _STM32H750: https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html + +:Authors: Dillon Min + From patchwork Wed Mar 31 08:28:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 413057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83D30C433E1 for ; Wed, 31 Mar 2021 08:30:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 417A8619DE for ; Wed, 31 Mar 2021 08:30:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234320AbhCaI3f (ORCPT ); Wed, 31 Mar 2021 04:29:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229759AbhCaI3M (ORCPT ); Wed, 31 Mar 2021 04:29:12 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06E2DC061574; Wed, 31 Mar 2021 01:29:12 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id 11so14002967pfn.9; Wed, 31 Mar 2021 01:29:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yYcmuaKyWQVYgeDBaXgwWfqSiRPjBpJWbzyk9syLfWM=; b=UGjfiDcLXZUztzpTNszbW2Gv0ziAPZy0k3ANBlWzNq0xgbHFC7WQL4+3sVU+s3HSpJ mNPGxRXeCkbPlCauWSs1rmHkZIPgj48u52MFNaCR+QIvZWr9D6thEVnEkSeb0qMT0PK/ 6MXDIdbDnyTcKPZNSxpOWwmJIGlF0vSHKnkevOGcIfmjKtzcahN0rBONVRrvRrTaPOlx 6z7S9EBHIbb3LeUN2EqDKAifn38KTMJ30jsGjbCBVNtBOevIAljoRI8j6Ld1tyZF09Xz wz5LCvC+JOea/s6Ej+groLiMVFClzcLMXIDcXx1iv71YzO7FRgu82xPPcB7M/goBQwWz CtOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yYcmuaKyWQVYgeDBaXgwWfqSiRPjBpJWbzyk9syLfWM=; b=sDEo2yeHBa1e0MifDk1bhEGO7CopT2zAWj88tC8Pq37W0eu9A9OThN2j4tNiaXyq4p 6+IAKkkusrTTaDjrtRnrWSqZYxDRIsu2WyZQlWOtPdSh8iZV74EPcvR8a4XivNQCiN1g eMDz7+HyTae7sugyR2KABQtTj5AzltxgfRpEQYs/PSamyyeAr3RHPJbv0FvWl4wsRo+7 jOeLebkg+Ha5Q+AxleewABkKuI01iH+f2Nii82MhJVcZYsqf2Ng8EaHYlJxluC6fpXSe McVuuOALPmEvH5+qGxfJThyDTwysY0tas9f2mjQANX6N4WsKefXu1WTcjwIlJxkEIa4e EDNA== X-Gm-Message-State: AOAM533qZJ26bnKr1c/k9s1w+lyXOYT+n7Hbbzgh4cBNTyjoiRDc6jvf KZyfrfcb92vB8hc6oP1xSA1JNB5HpWYw4cIA X-Google-Smtp-Source: ABdhPJxNpWulnbS0kaIrJx1AjCtXIsrtTiLG+4npKed8fEJi+CgU7ClQ5PIX8lFMx+72RXoHFevpng== X-Received: by 2002:a65:430b:: with SMTP id j11mr2250746pgq.143.1617179351430; Wed, 31 Mar 2021 01:29:11 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id v1sm1420991pjt.1.2021.03.31.01.29.06 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Mar 2021 01:29:11 -0700 (PDT) From: dillon.minfei@gmail.com To: robh@kernel.org, valentin.caron@foss.st.com, Alexandre.torgue@foss.st.com, rong.a.chen@intel.com, a.fatoum@pengutronix.de, mcoquelin.stm32@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, afzal.mohd.ma@gmail.com, gregkh@linuxfoundation.org, erwan.leray@foss.st.com, erwan.leray@st.com, linux-serial@vger.kernel.org, lkp@intel.com, patrice.chotard@foss.st.com, corbet@lwn.net, linux-doc@vger.kernel.org, pali@kernel.org, mchehab+huawei@kernel.org, andrew@lunn.ch Cc: dillon min Subject: [PATCH v9 3/6] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750 Date: Wed, 31 Mar 2021 16:28:42 +0800 Message-Id: <1617179325-6383-4-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617179325-6383-1-git-send-email-dillon.minfei@gmail.com> References: <1617179325-6383-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min This patch is intend to add support stm32h750 value line, just add stm32h7-pinctrl.dtsi for extending, with following changes: - rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi - update stm32h743i-{dico/eval}.dtsi to include stm32h7-pinctrl.dtsi - add dts binding usart3, uart4 usart3/uart4 pinctrl in stm32h7-pinctrl.dtsi usart3/uart4 register in stm32h743.dtsi - add dts binding sdmmc2 sdmmc2 pinctrl in stm32h7-pinctrl.dtsi sdmmc2 register in stm32h743.dtsi - add spi1_pins pinctrl in stm32h7-pinctrl.dtsi - move 'pin-controller' from stm32h7-pinctrl.dtsi to stm32h743.dtsi, to fix make dtbs_check warrnings arch/arm/boot/dts/stm32h750i-art-pi.dt.yaml: soc: 'i2c@40005C00', 'i2c@58001C00' do not match any of the regexes: '@(0|[1-9a-f][0-9a-f]*)$', '^[^@]+$', 'pinctrl-[0-9]+' - add gpio{a..k} entries in stm32h743.dtsi Signed-off-by: dillon min --- v9: - move gpio{a..k} entries from stm32h7-pinctrl.dtsi to stm32h743.dtsi arch/arm/boot/dts/stm32h7-pinctrl.dtsi | 275 +++++++++++++++++++++++++++ arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 306 ------------------------------- arch/arm/boot/dts/stm32h743.dtsi | 176 +++++++++++++++++- arch/arm/boot/dts/stm32h743i-disco.dts | 2 +- arch/arm/boot/dts/stm32h743i-eval.dts | 2 +- 5 files changed, 451 insertions(+), 310 deletions(-) create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi delete mode 100644 arch/arm/boot/dts/stm32h743-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi new file mode 100644 index 000000000000..7fc62e5b1d3e --- /dev/null +++ b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi @@ -0,0 +1,275 @@ +/* + * Copyright 2017 - Alexandre Torgue + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +&pinctrl { + + i2c1_pins_a: i2c1-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + ethernet_rmii: rmii-0 { + pins { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + + usart1_pins: usart1-0 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart2_pins: usart2-0 { + pins1 { + pinmux = ; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart3_pins: usart3-0 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + uart4_pins: uart4-0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + usbotg_hs_pins_a: usbotg-hs-0 { + pins { + pinmux = , /* ULPI_NXT */ + , /* ULPI_DIR> */ + , /* ULPI_STP> */ + , /* ULPI_CK> */ + , /* ULPI_D0> */ + , /* ULPI_D1> */ + , /* ULPI_D2> */ + , /* ULPI_D3> */ + , /* ULPI_D4> */ + , /* ULPI_D5> */ + , /* ULPI_D6> */ + ; /* ULPI_D7> */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + spi1_pins: spi1-0 { + pins1 { + pinmux = , + /* SPI1_CLK */ + ; + /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; + /* SPI1_MISO */ + bias-disable; + }; + }; +}; + diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi deleted file mode 100644 index fa5dcb6a5fdd..000000000000 --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - soc { - pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32h743-pinctrl"; - ranges = <0 0x58020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@58020000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA_CK>; - st,bank-name = "GPIOA"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiob: gpio@58020400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc GPIOB_CK>; - st,bank-name = "GPIOB"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioc: gpio@58020800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc GPIOC_CK>; - st,bank-name = "GPIOC"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiod: gpio@58020c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc GPIOD_CK>; - st,bank-name = "GPIOD"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioe: gpio@58021000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOE_CK>; - st,bank-name = "GPIOE"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiof: gpio@58021400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc GPIOF_CK>; - st,bank-name = "GPIOF"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiog: gpio@58021800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc GPIOG_CK>; - st,bank-name = "GPIOG"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioh: gpio@58021c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc GPIOH_CK>; - st,bank-name = "GPIOH"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioi: gpio@58022000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOI_CK>; - st,bank-name = "GPIOI"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioj: gpio@58022400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc GPIOJ_CK>; - st,bank-name = "GPIOJ"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiok: gpio@58022800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc GPIOK_CK>; - st,bank-name = "GPIOK"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c1_pins_a: i2c1-0 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - ethernet_rmii: rmii-0 { - pins { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - ; /* SDMMC1_CK */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - pins2{ - pinmux = ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_dir_pins_a: sdmmc1-dir-0 { - pins1 { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - ; /* SDMMC1_CDIR */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - pins2{ - pinmux = ; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - , /* SDMMC1_CDIR */ - ; /* SDMMC1_CKIN */ - }; - }; - - usart1_pins: usart1-0 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart2_pins: usart2-0 { - pins1 { - pinmux = ; /* USART2_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART2_RX */ - bias-disable; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = , /* ULPI_NXT */ - , /* ULPI_DIR> */ - , /* ULPI_STP> */ - , /* ULPI_CK> */ - , /* ULPI_D0> */ - , /* ULPI_D1> */ - , /* ULPI_D2> */ - , /* ULPI_D3> */ - , /* ULPI_D4> */ - , /* ULPI_D5> */ - , /* ULPI_D6> */ - ; /* ULPI_D7> */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 4ebffb0a45a3..06d43e60d06c 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -135,6 +135,22 @@ clocks = <&rcc USART2_CK>; }; + usart3: serial@40004800 { + compatible = "st,stm32h7-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + status = "disabled"; + clocks = <&rcc USART3_CK>; + }; + + uart4: serial@40004c00 { + compatible = "st,stm32h7-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + status = "disabled"; + clocks = <&rcc UART4_CK>; + }; + i2c1: i2c@40005400 { compatible = "st,stm32f7-i2c"; #address-cells = <1>; @@ -159,7 +175,7 @@ status = "disabled"; }; - i2c3: i2c@40005C00 { + i2c3: i2c@40005c00 { compatible = "st,stm32f7-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -368,6 +384,20 @@ max-frequency = <120000000>; }; + sdmmc2: mmc@48022400 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x48022400 0x400>; + interrupts = <124>; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC2_CK>; + clock-names = "apb_pclk"; + resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + }; + exti: interrupt-controller@58000000 { compatible = "st,stm32h7-exti"; interrupt-controller; @@ -392,7 +422,7 @@ status = "disabled"; }; - i2c4: i2c@58001C00 { + i2c4: i2c@58001c00 { compatible = "st,stm32f7-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -555,6 +585,148 @@ snps,pbl = <8>; status = "disabled"; }; + + gpioa: gpio@58020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc GPIOA_CK>; + st,bank-name = "GPIOA"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@58020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc GPIOB_CK>; + st,bank-name = "GPIOB"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@58020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc GPIOC_CK>; + st,bank-name = "GPIOC"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@58020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc GPIOD_CK>; + st,bank-name = "GPIOD"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@58021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc GPIOE_CK>; + st,bank-name = "GPIOE"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@58021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc GPIOF_CK>; + st,bank-name = "GPIOF"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@58021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc GPIOG_CK>; + st,bank-name = "GPIOG"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@58021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc GPIOH_CK>; + st,bank-name = "GPIOH"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@58022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc GPIOI_CK>; + st,bank-name = "GPIOI"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@58022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc GPIOJ_CK>; + st,bank-name = "GPIOJ"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@58022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc GPIOK_CK>; + st,bank-name = "GPIOK"; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; + + pinctrl: pin-controller@58020000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32h743-pinctrl"; + ranges = <0 0x58020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + pins-are-numbered; + }; }; }; diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts index e446d311c520..59e01ce10318 100644 --- a/arch/arm/boot/dts/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/stm32h743i-disco.dts @@ -42,7 +42,7 @@ /dts-v1/; #include "stm32h743.dtsi" -#include "stm32h743-pinctrl.dtsi" +#include "stm32h7-pinctrl.dtsi" / { model = "STMicroelectronics STM32H743i-Discovery board"; diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts index 8f398178f5e5..38cc7faf6884 100644 --- a/arch/arm/boot/dts/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/stm32h743i-eval.dts @@ -42,7 +42,7 @@ /dts-v1/; #include "stm32h743.dtsi" -#include "stm32h743-pinctrl.dtsi" +#include "stm32h7-pinctrl.dtsi" / { model = "STMicroelectronics STM32H743i-EVAL board"; From patchwork Wed Mar 31 08:28:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 413056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BA3FC433E9 for ; Wed, 31 Mar 2021 08:30:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 00879619DB for ; Wed, 31 Mar 2021 08:30:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234385AbhCaI3h (ORCPT ); Wed, 31 Mar 2021 04:29:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233140AbhCaI32 (ORCPT ); Wed, 31 Mar 2021 04:29:28 -0400 Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAF46C061574; Wed, 31 Mar 2021 01:29:27 -0700 (PDT) Received: by mail-pg1-x52b.google.com with SMTP id p12so9032948pgj.10; Wed, 31 Mar 2021 01:29:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GeaHQT584yJS6al/D36INfw/UWOuETaMHBUlhwpXItw=; b=VcfHHqi9f0y4MFgC5bZrE+KiYMyVH2qWFzw3v7k5kiy0yQxGuQRUsvrLJE1LUpQIJ5 a6aAO1w0BJ9VUbkmOhEcb+C0z/kH6MPc36u715MDWkPuYIpfKHBlFahNpjYOowmbdGI4 /wlGkTy4iSkel1KXggsL9/v2nc61ZODHO3zpKpN45YAtjT2j8mHghdhtuId9plqHauTg w/nq8qgtw7dVeKTUrOFTLaHhayI+UqTQy6cvP7qQ5OZVTCgMq1ii7Ewx2SpuNgdRmXys RFtG/posXytKUrMClfkt+y/3N6z91DqJ8uCfFpWTfE7exl6gD66XgmIIOlSQdonWfcGl JVDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GeaHQT584yJS6al/D36INfw/UWOuETaMHBUlhwpXItw=; b=GGv8wBmoicgWLWrzHwG6vjAITveCsXVlCW+vri7J6GB8bF6B8ldIpW+qU2B2Mkas1v DW5ITEO2JwUvRJH94ubEuGvVl3sNj26NYS2rH7xOzV+/A55Ser/C8VdHqY6XM1enhyfQ SCpeb9j58sa7I5tgmOfoNBJF/LR0+ervj27Kd8pk6iMsrWZorq72rzBnFkvBH/OaFW5+ rPHyuSJJQCdxWWwvS5O1S2r0r2AOYOytGyuq6cIlyn+WWmw5mSaPGXJlQVXzBhK+x/vh MoMeqYGenH5p8bJgVJtXoJ2qz3fp6ae1xz5t4cXBArcnY/4slYI85n0x2cRsoAe3R/Ft UWig== X-Gm-Message-State: AOAM533tzzd6pS5parQY3UhhOAVfqfFbxM47fUDGnkKK+JVPGqvnt/Ht LjGl95Qi+1akzVZ8aSAuyAg= X-Google-Smtp-Source: ABdhPJwB7vaNXAVDacTO37U5OfOzmFEGWb5cs+DY68MHB9+uO3kj8ytq7mr2cNLvyJ4wyNdIO7e09g== X-Received: by 2002:a05:6a00:2cd:b029:1f4:c3db:4191 with SMTP id b13-20020a056a0002cdb02901f4c3db4191mr1869209pft.71.1617179367324; Wed, 31 Mar 2021 01:29:27 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id v1sm1420991pjt.1.2021.03.31.01.29.22 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Mar 2021 01:29:26 -0700 (PDT) From: dillon.minfei@gmail.com To: robh@kernel.org, valentin.caron@foss.st.com, Alexandre.torgue@foss.st.com, rong.a.chen@intel.com, a.fatoum@pengutronix.de, mcoquelin.stm32@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, afzal.mohd.ma@gmail.com, gregkh@linuxfoundation.org, erwan.leray@foss.st.com, erwan.leray@st.com, linux-serial@vger.kernel.org, lkp@intel.com, patrice.chotard@foss.st.com, corbet@lwn.net, linux-doc@vger.kernel.org, pali@kernel.org, mchehab+huawei@kernel.org, andrew@lunn.ch Cc: dillon min Subject: [PATCH v9 6/6] dt-bindings: serial: stm32: Use 'type: object' instead of false for 'additionalProperties' Date: Wed, 31 Mar 2021 16:28:45 +0800 Message-Id: <1617179325-6383-7-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617179325-6383-1-git-send-email-dillon.minfei@gmail.com> References: <1617179325-6383-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min To use additional properties 'bluetooth' on serial, need replace false with 'type: object' for 'additionalProperties' to make it as a node, else will run into dtbs_check warnings. 'arch/arm/boot/dts/stm32h750i-art-pi.dt.yaml: serial@40004800: 'bluetooth' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: af1c2d81695b ("dt-bindings: serial: Convert STM32 UART to json-schema") Reported-by: kernel test robot Tested-by: Valentin Caron Signed-off-by: dillon min Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/1616757302-7889-8-git-send-email-dillon.minfei@gmail.com Signed-off-by: dillon min --- v9: no changes, this patch was merged to tty-next by Greg Kroah-Hartman Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 8631678283f9..865be05083c3 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -80,7 +80,8 @@ required: - interrupts - clocks -additionalProperties: false +additionalProperties: + type: object examples: - |