From patchwork Wed Mar 31 15:16:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 412884 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp579777jai; Wed, 31 Mar 2021 08:17:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzpFY1NX6xMdwc8ftMUPJqEZRu+WWJaejCNiAxFB1owxnHdkrNQm/beSNAxmfGd9GGgXhwo X-Received: by 2002:a17:906:1a44:: with SMTP id j4mr4105596ejf.401.1617203850769; Wed, 31 Mar 2021 08:17:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617203850; cv=none; d=google.com; s=arc-20160816; b=TB3pMNUiDffNfaYASesMwBTXFS25pMO0QwH6Qui/Jfdi6XJD8C4LTIkEifw6Hxb8PP ylRDdmXIIMnKOCwHr4Lnv3dqECwJhSFjxoyxXVKBjKEkX/JtycIgd1gj9vtx//+Lxnh+ 4kLNtu4NBp36oM58ktkB4fjNAmgfLqG+2ixZ/TOePgwyJteMwXK7iqgl/ZK9zT1LWbC3 slzpYncXFDslDp5MSeGcQu0EBb1CfwQivDLeyMe/9YvWt7gxeQs39xPXoWph6WDdBT5V 0I0yYKB3H48ncOnJXTIG3xBV47gYb3RBqjYOWyAzODTjrbJXtryBkVg6kvlsafi4vawv cvxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=szrnHwOMXqsq40OfwiBkaChIfbhw+vSJppKz2hMlXUk=; b=wClrqoTQxHUn4oCL+ieQC6wPhOFybxn/ffIp02BpR+fWZXdp4+Hzs8qXLkWjibEdgf 2czioPrnlBhz4N8h4+d+uDT4FS9u+DzYgPwz1RJssB80TM9F7bt+QZXF19DBFauD8Iyi 2gnIFnFkhhf3Cy4BFkPagt9Dq6TZziaemKfrz2L/s2/2fFMFvs9ItklBZemMWq7n/OyT 2SDBPdp6GU2FDqgn9+u25WYGy4WxYQCMFOrdeOCmUCytH2/HRpyGYeyS5qq9RRGz3rZ9 wVCeqPOCzu5NOF4J9jU/heyj3MUgywDaU3Bx6yUUJ40mU8pwRiC/i+WgCjauAUVOvdEZ URnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=upQXAejz; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j26si1905057ejs.484.2021.03.31.08.17.30; Wed, 31 Mar 2021 08:17:30 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=upQXAejz; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235665AbhCaPQ4 (ORCPT + 6 others); Wed, 31 Mar 2021 11:16:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236030AbhCaPQ2 (ORCPT ); Wed, 31 Mar 2021 11:16:28 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 516B4C061574 for ; Wed, 31 Mar 2021 08:16:28 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id 184so24267076ljf.9 for ; Wed, 31 Mar 2021 08:16:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=szrnHwOMXqsq40OfwiBkaChIfbhw+vSJppKz2hMlXUk=; b=upQXAejzgPv+H4nLxw/TZdHhITf90bSgJFKa7jsA2hwGQ0Co08D9NbJ7vpwSfieCxT W9SJsoqINMcJKyP7t8jEn65cpyr92l/K392htdyFqtDpkHdMU7Uf6wfqkrp6rKVQTOAS C5aKz71YSobND7VImIowzM7/XxmGFAC4pCe1IbXWE4xiy3KIYFwz0di0+0hPzWu/isKy 8gHi+KX6+y4BbSj8oAoBg7//e6VE+ucQHfNMCVDgOeYdqWfH4k4UxRPcQ88alkuasM2i BCOaswei+RhwPZ7+8oDcbHTIoBJEXUbM+c3EZ3BeIA3gotrS9irg6aR9NfpeFFLjqSvC frvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=szrnHwOMXqsq40OfwiBkaChIfbhw+vSJppKz2hMlXUk=; b=fFpKgHmmx9PbR6YpWB8ftTnwSnw+dRWctyxpGwdCACOQhnLEsTTSrFSiA/2KQqp0qd 7vwbeDm/38WGDjnYicu3mQQtaydK0RPk1jXfJBzb4aUyDjhqad4u0LZpi/lkNW5ITIi9 cXuZwD0ZktjLEks7OEMw2UQnN6AB+8sRLLtCeVDe2tnjB+6qsVt1uOj/FEiJ7izZEa47 R923palhx0tSGVmXyApmefMN7JSRSdksR0Ofgu8RY7NwSU7hhm0s4sx/vmrt5RPffX96 odEWeE5qjJ+xdpJIvyge6jAvvDL/Wgg77NEbuUrkczeNxZi9zC5CJUwbp2aChYryNPTw rmUA== X-Gm-Message-State: AOAM530iaBaE/DIVrjsGHkpEZC9yZz6+YSduLF6IMic9Hk1Xebmkazj+ F5zO2JyvL8EQDcZoND63lbRc8w== X-Received: by 2002:a2e:8959:: with SMTP id b25mr2480146ljk.245.1617203786452; Wed, 31 Mar 2021 08:16:26 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id t201sm266738lff.70.2021.03.31.08.16.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 08:16:26 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Cc: Manu Gautam , Stephen Boyd , Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Stephen Boyd , Sandeep Maheswaram , Rob Herring Subject: [PATCH v6 1/7] dt-bindings: phy: qcom, qmp-usb3-dp-phy: move usb3 compatibles back to qcom, qmp-phy.yaml Date: Wed, 31 Mar 2021 18:16:08 +0300 Message-Id: <20210331151614.3810197-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210331151614.3810197-1-dmitry.baryshkov@linaro.org> References: <20210331151614.3810197-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The commit 724fabf5df13 ("dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information") has support for DP part of USB3+DP combo PHYs. However this change is not backwards compatible, placing additional requirements onto qcom,sc7180-qmp-usb3-phy and qcom,sdm845-qmp-usb3-phy device nodes (to include separate DP part, etc). However the aforementioned nodes do not inclue DP part, they strictly follow the schema defined in the qcom,qmp-phy.yaml file. Move those compatibles, leaving qcom,qmp-usb3-dp-phy.yaml to describe only real "combo" USB3+DP device nodes. Fixes: 724fabf5df13 ("dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information") Cc: Stephen Boyd Cc: Sandeep Maheswaram Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 626447fee092..7808ec8bc712 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -25,11 +25,13 @@ properties: - qcom,msm8998-qmp-pcie-phy - qcom,msm8998-qmp-ufs-phy - qcom,msm8998-qmp-usb3-phy + - qcom,sc7180-qmp-usb3-phy - qcom,sc8180x-qmp-ufs-phy - qcom,sc8180x-qmp-usb3-phy - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy - qcom,sdm845-qmp-ufs-phy + - qcom,sdm845-qmp-usb3-phy - qcom,sdm845-qmp-usb3-uni-phy - qcom,sm8150-qmp-ufs-phy - qcom,sm8150-qmp-usb3-phy diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml index 33974ad10afe..62c0179d1765 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml @@ -14,9 +14,7 @@ properties: compatible: enum: - qcom,sc7180-qmp-usb3-dp-phy - - qcom,sc7180-qmp-usb3-phy - qcom,sdm845-qmp-usb3-dp-phy - - qcom,sdm845-qmp-usb3-phy reg: items: - description: Address and length of PHY's USB serdes block. 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Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring Reviewed-by: Bjorn Andersson --- Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml index 62c0179d1765..217aa6c91893 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml @@ -15,6 +15,7 @@ properties: enum: - qcom,sc7180-qmp-usb3-dp-phy - qcom,sdm845-qmp-usb3-dp-phy + - qcom,sm8250-qmp-usb3-dp-phy reg: items: - description: Address and length of PHY's USB serdes block. From patchwork Wed Mar 31 15:16:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 413020 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08E33C43611 for ; Wed, 31 Mar 2021 15:17:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E42CE61077 for ; Wed, 31 Mar 2021 15:17:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236259AbhCaPQ6 (ORCPT ); Wed, 31 Mar 2021 11:16:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236228AbhCaPQa (ORCPT ); Wed, 31 Mar 2021 11:16:30 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66C81C061764 for ; Wed, 31 Mar 2021 08:16:29 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id b4so29670019lfi.6 for ; Wed, 31 Mar 2021 08:16:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v03saRp/WhgRD5q+jtfmlvYSag8e2e59zjMW6jOssB8=; b=nz/PJrhVJ6zogp2nNFR9iuYpN5nGeiHZpfjTFws4oipoFjIbbPHkiTzuqW9Xok0DGW 7HgdgKSOZd68xWbo7725Zn3s3HpezvpP5U7vJ8ezjhh/WzieyTd+KA8e2tnUG4CfuXDQ UcRG9mh+bd02M77GeWSzPdrke6+rKSgSvIi1MfgSb3XAPMEbNCLxicIrPNBLBvZZNacV wueveq79g/k6I7MjJfYj4d+adjr+s9I8uAgMrjM0CitBy1dKu1andwGOYHiz5Zk29M26 YyRI+1KXOXmiaB89J+fl2kBAoWIVyALn5eG5tjQit3L9QjWbg4oqZII2N1aCwS8KT8lS Nkiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v03saRp/WhgRD5q+jtfmlvYSag8e2e59zjMW6jOssB8=; b=lj3C5xgI7dYt/bQtZ7InVCO2MhEqLDZueQdJXVnVoVb9p2pKAyt4NGOafbw+xDqE8C nclkyf3ZZX6bY4Pw4LsazQSPUsFQswtBLUSiQGcG+Yh8D3BDcxLpYbPAKP9U0BbIfU81 fm2wDHHidAqd3euzrKNfvj3bPsnszN2vB+RffwONbqUJNSwLTlNMoZL4T8F+AQKyi9jb 1HCcPBY+Quml72fR8ik3MpqRhF1QMwFf0tbEKsXJYas6y3LoDVDGueOJ7l0Jhw70D8Hg 89i8pa2mJkRZBSqIOmu2Pa/pAUKxsKX65dg8rhY4jrrwaJowOGnjXUzurGI2iYFms7nT ZKpw== X-Gm-Message-State: AOAM532kriuvCiW8EAns4SC6+t01MuWUXHx/VSfKnzAn4zCV0Qa5QOLP R/dCxRBjCDYIFnvJ+91xnkKKyw== X-Google-Smtp-Source: ABdhPJyzCpftsmXdsKgo5Q9u7rxYmSiXKAkzlJ5clMmhqTLJUUBheo3v4+25qHuMkdvIN9NTi5Czvg== X-Received: by 2002:a19:380a:: with SMTP id f10mr2496178lfa.294.1617203787824; Wed, 31 Mar 2021 08:16:27 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id t201sm266738lff.70.2021.03.31.08.16.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 08:16:27 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Cc: Manu Gautam , Stephen Boyd , Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 3/7] phy: qcom-qmp: move DP functions to callbacks Date: Wed, 31 Mar 2021 18:16:10 +0300 Message-Id: <20210331151614.3810197-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210331151614.3810197-1-dmitry.baryshkov@linaro.org> References: <20210331151614.3810197-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation to adding support for V4 DP PHY move DP functions to callbacks at struct qmp_phy_cfg. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp.c | 73 ++++++++++++++++++++--------- 1 file changed, 51 insertions(+), 22 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 1c79a713780d..854f6ff7faef 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -2268,6 +2268,8 @@ static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), }; +struct qmp_phy; + /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { /* phy-type - PCIE/UFS/USB */ @@ -2307,6 +2309,12 @@ struct qmp_phy_cfg { const struct qmp_phy_init_tbl *serdes_tbl_hbr3; int serdes_tbl_hbr3_num; + /* DP PHY callbacks */ + int (*configure_dp_phy)(struct qmp_phy *qphy); + void (*configure_dp_tx)(struct qmp_phy *qphy); + int (*calibrate_dp_phy)(struct qmp_phy *qphy); + void (*dp_aux_init)(struct qmp_phy *qphy); + /* clock ids to be requested */ const char * const *clk_list; int num_clks; @@ -2423,6 +2431,11 @@ struct qcom_qmp { struct reset_control *ufs_reset; }; +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); + static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) { u32 reg; @@ -2871,6 +2884,11 @@ static const struct qmp_phy_cfg sc7180_dpphy_cfg = { .has_phy_dp_com_ctrl = true, .is_dual_lane_phy = true, + + .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, + .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, + .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, + .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, }; static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { @@ -3332,7 +3350,7 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) return 0; } -static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy) +static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) { writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, @@ -3403,7 +3421,7 @@ static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { { 0x1f, 0xff, 0xff, 0xff } }; -static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy) +static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) { const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; unsigned int v_level = 0, p_level = 0; @@ -3451,21 +3469,7 @@ static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy) writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); } -static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) -{ - const struct phy_configure_opts_dp *dp_opts = &opts->dp; - struct qmp_phy *qphy = phy_get_drvdata(phy); - - memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); - if (qphy->dp_opts.set_voltages) { - qcom_qmp_phy_configure_dp_tx(qphy); - qphy->dp_opts.set_voltages = 0; - } - - return 0; -} - -static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy) +static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) { const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; @@ -3561,9 +3565,8 @@ static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy) * We need to calibrate the aux setting here as many times * as the caller tries */ -static int qcom_qmp_dp_phy_calibrate(struct phy *phy) +static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) { - struct qmp_phy *qphy = phy_get_drvdata(phy); static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; u8 val; @@ -3576,6 +3579,32 @@ static int qcom_qmp_dp_phy_calibrate(struct phy *phy) return 0; } +static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) +{ + const struct phy_configure_opts_dp *dp_opts = &opts->dp; + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; + + memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); + if (qphy->dp_opts.set_voltages) { + cfg->configure_dp_tx(qphy); + qphy->dp_opts.set_voltages = 0; + } + + return 0; +} + +static int qcom_qmp_dp_phy_calibrate(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; + + if (cfg->calibrate_dp_phy) + return cfg->calibrate_dp_phy(qphy); + + return 0; +} + static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; @@ -3748,7 +3777,7 @@ static int qcom_qmp_phy_init(struct phy *phy) return ret; if (cfg->type == PHY_TYPE_DP) - qcom_qmp_phy_dp_aux_init(qphy); + cfg->dp_aux_init(qphy); return 0; } @@ -3802,7 +3831,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) /* Configure special DP tx tunings */ if (cfg->type == PHY_TYPE_DP) - qcom_qmp_phy_configure_dp_tx(qphy); + cfg->configure_dp_tx(qphy); qcom_qmp_phy_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); @@ -3821,7 +3850,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) /* Configure link rate, swing, etc. */ if (cfg->type == PHY_TYPE_DP) { - qcom_qmp_phy_configure_dp_phy(qphy); + cfg->configure_dp_phy(qphy); } else { qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); if (cfg->pcs_tbl_sec) From patchwork Wed Mar 31 15:16:11 2021 Content-Type: text/plain; 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To simplify V4 code, rename all common registers. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp.c | 50 ++++++++++++++--------------- drivers/phy/qualcomm/phy-qcom-qmp.h | 37 ++++++++++----------- 2 files changed, 44 insertions(+), 43 deletions(-) -- 2.30.2 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 854f6ff7faef..e1dbc9d936e7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -3354,20 +3354,20 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) { writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, - qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + qphy->pcs + QSERDES_DP_PHY_PD_CTL); /* Turn on BIAS current for PHY/PLL */ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, - qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + qphy->pcs + QSERDES_DP_PHY_PD_CTL); writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | @@ -3375,16 +3375,16 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); - writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0); - writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); - writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); - writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3); - writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4); - writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5); - writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6); - writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7); - writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8); - writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9); + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); + writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); + writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); qphy->dp_aux_cfg = 0; writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | @@ -3494,9 +3494,9 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); */ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; - writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); - writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); + writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); @@ -3526,11 +3526,11 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); - writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); - writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); - writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG); - writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); - writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); @@ -3541,7 +3541,7 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) 10000)) return -ETIMEDOUT; - writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, status, @@ -3550,9 +3550,9 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) 10000)) return -ETIMEDOUT; - writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); udelay(2000); - writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, status, @@ -3574,7 +3574,7 @@ static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); val = cfg1_settings[qphy->dp_aux_cfg]; - writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); return 0; } @@ -3922,7 +3922,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy) if (cfg->type == PHY_TYPE_DP) { /* Assert DP PHY power down */ - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); } else { /* PHY reset */ if (!cfg->no_pcs_sw_reset) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 71ce3aa174ae..981d8ee891c0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -349,13 +349,13 @@ #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 -/* Only for QMP V3 PHY - DP PHY registers */ -#define QSERDES_V3_DP_PHY_REVISION_ID0 0x000 -#define QSERDES_V3_DP_PHY_REVISION_ID1 0x004 -#define QSERDES_V3_DP_PHY_REVISION_ID2 0x008 -#define QSERDES_V3_DP_PHY_REVISION_ID3 0x00c -#define QSERDES_V3_DP_PHY_CFG 0x010 -#define QSERDES_V3_DP_PHY_PD_CTL 0x018 +/* QMP PHY - DP PHY registers */ +#define QSERDES_DP_PHY_REVISION_ID0 0x000 +#define QSERDES_DP_PHY_REVISION_ID1 0x004 +#define QSERDES_DP_PHY_REVISION_ID2 0x008 +#define QSERDES_DP_PHY_REVISION_ID3 0x00c +#define QSERDES_DP_PHY_CFG 0x010 +#define QSERDES_DP_PHY_PD_CTL 0x018 # define DP_PHY_PD_CTL_PWRDN 0x001 # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 @@ -363,18 +363,19 @@ # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 -#define QSERDES_V3_DP_PHY_MODE 0x01c -#define QSERDES_V3_DP_PHY_AUX_CFG0 0x020 -#define QSERDES_V3_DP_PHY_AUX_CFG1 0x024 -#define QSERDES_V3_DP_PHY_AUX_CFG2 0x028 -#define QSERDES_V3_DP_PHY_AUX_CFG3 0x02c -#define QSERDES_V3_DP_PHY_AUX_CFG4 0x030 -#define QSERDES_V3_DP_PHY_AUX_CFG5 0x034 -#define QSERDES_V3_DP_PHY_AUX_CFG6 0x038 -#define QSERDES_V3_DP_PHY_AUX_CFG7 0x03c -#define QSERDES_V3_DP_PHY_AUX_CFG8 0x040 -#define QSERDES_V3_DP_PHY_AUX_CFG9 0x044 +#define QSERDES_DP_PHY_MODE 0x01c +#define QSERDES_DP_PHY_AUX_CFG0 0x020 +#define QSERDES_DP_PHY_AUX_CFG1 0x024 +#define QSERDES_DP_PHY_AUX_CFG2 0x028 +#define QSERDES_DP_PHY_AUX_CFG3 0x02c +#define QSERDES_DP_PHY_AUX_CFG4 0x030 +#define QSERDES_DP_PHY_AUX_CFG5 0x034 +#define QSERDES_DP_PHY_AUX_CFG6 0x038 +#define QSERDES_DP_PHY_AUX_CFG7 0x03c +#define QSERDES_DP_PHY_AUX_CFG8 0x040 +#define QSERDES_DP_PHY_AUX_CFG9 0x044 +/* Only for QMP V3 PHY - DP PHY registers */ #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 # define PHY_AUX_STOP_ERR_MASK 0x01 # define PHY_AUX_DEC_ERR_MASK 0x02 From patchwork Wed Mar 31 15:16:13 2021 Content-Type: text/plain; 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[23.128.96.18]) by mx.google.com with ESMTP id j26si1905057ejs.484.2021.03.31.08.17.38; Wed, 31 Mar 2021 08:17:38 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lM50oytr; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236248AbhCaPRB (ORCPT + 6 others); Wed, 31 Mar 2021 11:17:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236245AbhCaPQd (ORCPT ); Wed, 31 Mar 2021 11:16:33 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE4BCC061760 for ; Wed, 31 Mar 2021 08:16:31 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id d12so8608862lfv.11 for ; Wed, 31 Mar 2021 08:16:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SmxIAdsrO4AgDCAX3+XBJ4r3+d8Vawzl+TBPeB7hZmY=; b=lM50oytrwY6820uCVWhN3Xgux4/CS1zLxbDA7casJCBo2vs+VEInatulHQMjvMuf+i YjijfBihlfXwIhOJny0I9uHCncyo5qpdQCX25utcuExFeVw0uZFqj1KxpM9L+QLqCZfU elPHXtXWUq74JCEfhYxvq8UeKIgZAfLgvT1n9bjYcvytABWQtp6krsGIR+Mkl3TZH8Xc A0SDS+JNSuKZGFhiNjAU2AXap/kR29+nUZxRCdpa/FJsjShNNTfvbClV61zRAVL8FmA+ YJmQIlS2tFTsqgIX2gSquKagwoePlTqiMEzF883YP+BxSsMHWSSriOICdAgYItqfdjOd fijQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SmxIAdsrO4AgDCAX3+XBJ4r3+d8Vawzl+TBPeB7hZmY=; b=IqfdRZg137AEydTsTO6Ed2hT5ZdRvU1zPFTvtZrvNSgkUU+Vr3on+3e6b1r1oHJJEl MBDkvG1Wc8s6mtuASjIxk0QfWR4BEQktvm1c3vRaKvWJvYWjrqgygwgnCJ5tJ5sGOPFo 2+02lXfwYfPBT1Xyrz9Iy+XSW9Nr9L9IrX532T5mxphhSgYbqSrHClDTgiFoHjfKXPis 0HtmOdcW+bfmy1TZg+fMb2NhIXrgNHICUXo/VVsB83JbTnYS/NI7ole4mMB3ICY6hzDp GthCxHqyzN+7PE5UVWbKNFPw+YgD+ZsHBnQQciMWbERPYCo3fPj/928VN17aEtCkV2LB oI0g== X-Gm-Message-State: AOAM533CAtT5cJp6IQUg6g2p6TMe7jVTkcQfyptLedRLU7Ax7pzwiLvX 5L5PobwD/L82h31w8lHB6Oezrg== X-Received: by 2002:ac2:5f0a:: with SMTP id 10mr2685067lfq.415.1617203790111; Wed, 31 Mar 2021 08:16:30 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id t201sm266738lff.70.2021.03.31.08.16.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 08:16:29 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Cc: Manu Gautam , Stephen Boyd , Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 6/7] arm64: dts: qcom: sm8250: switch usb1 qmp phy to USB3+DP mode Date: Wed, 31 Mar 2021 18:16:13 +0300 Message-Id: <20210331151614.3810197-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210331151614.3810197-1-dmitry.baryshkov@linaro.org> References: <20210331151614.3810197-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org USB1 QMP PHY is not just a USB3 PHY, but USB3+DP PHY. Change device tree nodes accordingly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) -- 2.30.2 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 947e1accae3a..0f79e6885004 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2097,12 +2097,11 @@ usb_2_hsphy: phy@88e4000 { }; usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sm8250-qmp-usb3-phy"; + compatible = "qcom,sm8250-qmp-usb3-dp-phy"; reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - reg-names = "reg-base", "dp_com"; + <0 0x088e8000 0 0x40>, + <0 0x088ea000 0 0x200>; status = "disabled"; - #clock-cells = <1>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -2116,7 +2115,7 @@ usb_1_qmpphy: phy@88e9000 { <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: lanes@88e9200 { + usb_1_ssphy: usb3-phy@88e9200 { reg = <0 0x088e9200 0 0x200>, <0 0x088e9400 0 0x200>, <0 0x088e9c00 0 0x400>, @@ -2128,6 +2127,20 @@ usb_1_ssphy: lanes@88e9200 { clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; }; + + dp_phy: dp-phy@88ea200 { + reg = <0 0x088ea200 0 0x200>, + <0 0x088ea400 0 0x200>, + <0 0x088eac00 0 0x400>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>, + <0 0x088eaa00 0 0x100>; + #phy-cells = <0>; + #clock-cells = <1>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; }; usb_2_qmpphy: phy@88eb000 {