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Wed, 23 May 2018 11:00:19 +0000 (GMT) X-AuditID: cbfec7f2-5ffe19c000011644-c9-5b0549c4cb85 Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id DE.1F.04178.2C9450B5; Wed, 23 May 2018 12:00:18 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P96002I9H8D5900@eusync4.samsung.com>; Wed, 23 May 2018 12:00:18 +0100 (BST) From: Marek Szyprowski To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 2/3] arm64: dts: exynos: Add more clocks to Exynos5433 Decon/DeconTV Date: Wed, 23 May 2018 13:00:01 +0200 Message-id: <20180523110002.25512-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.0 In-reply-to: <20180523110002.25512-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrMIsWRmVeSWpSXmKPExsWy7djP87pHPFmjDU4tULa4te4cq8XGGetZ La58fc9mMen+BBaL8+c3sFvMOL+PyWLtkbtA1uSXbA4cHptWdbJ53O8+zuTRt2UVo8fnTXIB LFFcNimpOZllqUX6dglcGcfafAu2C1TsmhzRwLiJt4uRk0NCwERiY89Bti5GLg4hgRWMEueW zGWEcD4zSry5tJYNpqrtVhMrRGIZo8TBp8tYIJwGJolJi76xg1SxCRhKdL3tAusQEXCTaDo8 E6yDGaRoYssCsCJhgTCJ+9OesYDYLAKqEp8OTWIFsXkFbCWuznnNBLFOXuLZ9Hlg9ZwCdhLL 7m5hAhkkIfCTVWLH9PlQN7lINC1dDdUgLPHq+BZ2CFtGorPjIFCcA8gul/h3Igsi3MIosfab PoRtLXH4+EWwvcwCfBKTtk1nhijnlehoE4Io8ZB4fPwC1ERHiYMfL0HDaCIwWFpXs01glFrA yLCKUTy1tDg3PbXYMC+1XK84Mbe4NC9dLzk/dxMjMCpP/zv+aQfj10tJhxgFOBiVeHgDRFii hVgTy4orcw8xSnAwK4nwnvoDFOJNSaysSi3Kjy8qzUktPsQozcGiJM4bp1EXJSSQnliSmp2a WpBaBJNl4uCUamCccK9C3sfZ8wan/eHqBIaZ5tO2mB16eTHn6wWPPdw709d/uPI5rKEye7tE S7/GRDvpB3MvHFpRopX/b9vW70zqvCeqnNSsEyuTEj5E6S/5XHnx6r7VS/zMpfjlJB+u2pv4 2Orkm3lBN6W0av9KBO3I//+i7932xXnmEZfP2GuxnlNZ2nfCYulZJZbijERDLeai4kQAqWgJ i8YCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpjluLIzCtJLcpLzFFi42I5/e/4Nd1DnqzRBi3XbCxurTvHarFxxnpW iytf37NZTLo/gcXi/PkN7BYzzu9jslh75C6QNfklmwOHx6ZVnWwe97uPM3n0bVnF6PF5k1wA SxSXTUpqTmZZapG+XQJXxrE234LtAhW7Jkc0MG7i7WLk5JAQMJFou9XE2sXIxSEksIRR4vS2 /2wQThOTRNeli6wgVWwChhJdb7vYQGwRATeJpsMzwTqYQYqutO1kB0kIC4RJ3J/2jAXEZhFQ lfh0aBJYM6+ArcTVOa+ZINbJSzybPg+snlPATmLZ3S1gcSGgmo1XNrBMYORZwMiwilEktbQ4 Nz232FCvODG3uDQvXS85P3cTIzB0th37uXkH46WNwYcYBTgYlXh4V4ixRAuxJpYVV+YeYpTg YFYS4T31ByjEm5JYWZValB9fVJqTWnyIUZqDRUmc97xBZZSQQHpiSWp2ampBahFMlomDU6qB kWe60n4WVtfUfFO5hI3uE6etzbrEc3ORzjPtV6f/SewT0lm/7xfrl5TkuCu3JOOS67c8CD8+ z3UX07QDO5PKP0dazBJ6pdunMVf9+73KQ68WHLC184vhNpP6KZGoVGW80MCq1bx528Gar1FT eT4bpa8sn2uivTi3tkL1sfCaKd/EldYLGLmdVmIpzkg01GIuKk4EAMfJ+m8ZAgAA X-CMS-MailID: 20180523110019eucas1p129c05410595a3c256c474551cec401a3 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180523110019eucas1p129c05410595a3c256c474551cec401a3 X-RootMTR: 20180523110019eucas1p129c05410595a3c256c474551cec401a3 References: <20180523110002.25512-1-m.szyprowski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bartlomiej Zolnierkiewicz , Seung-Woo Kim , Krzysztof Kozlowski , Marek Szyprowski MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add all '1x' clocks to decon and decontv devices. Enabling those clocks is needed to get proper display on hardware windows no 4 and 5. Signed-off-by: Marek Szyprowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 0ec44180d1b7..038c99792ccb 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -829,11 +829,16 @@ <&cmu_disp CLK_ACLK_SMMU_DECON0X>, <&cmu_disp CLK_ACLK_XIU_DECON0X>, <&cmu_disp CLK_PCLK_SMMU_DECON0X>, + <&cmu_disp CLK_ACLK_SMMU_DECON1X>, + <&cmu_disp CLK_ACLK_XIU_DECON1X>, + <&cmu_disp CLK_PCLK_SMMU_DECON1X>, <&cmu_disp CLK_SCLK_DECON_VCLK>, <&cmu_disp CLK_SCLK_DECON_ECLK>; clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", "pclk_smmu_decon0x", - "sclk_decon_vclk", "sclk_decon_eclk"; + "aclk_smmu_decon1x", "aclk_xiu_decon1x", + "pclk_smmu_decon1x", "sclk_decon_vclk", + "sclk_decon_eclk"; power-domains = <&pd_disp>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = , @@ -866,11 +871,16 @@ <&cmu_disp CLK_ACLK_SMMU_TV0X>, <&cmu_disp CLK_ACLK_XIU_TV0X>, <&cmu_disp CLK_PCLK_SMMU_TV0X>, + <&cmu_disp CLK_ACLK_SMMU_TV1X>, + <&cmu_disp CLK_ACLK_XIU_TV1X>, + <&cmu_disp CLK_PCLK_SMMU_TV1X>, <&cmu_disp CLK_SCLK_DECON_TV_VCLK>, <&cmu_disp CLK_SCLK_DECON_TV_ECLK>; clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", "pclk_smmu_decon0x", - "sclk_decon_vclk", "sclk_decon_eclk"; + "aclk_smmu_decon1x", "aclk_xiu_decon1x", + "pclk_smmu_decon1x", "sclk_decon_vclk", + "sclk_decon_eclk"; samsung,disp-sysreg = <&syscon_disp>; power-domains = <&pd_disp>; interrupt-names = "fifo", "vsync", "lcd_sys";