From patchwork Tue Mar 30 08:58:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 413120 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 254D9C433DB for ; Tue, 30 Mar 2021 08:59:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F0DAC6195D for ; Tue, 30 Mar 2021 08:59:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231699AbhC3I7H (ORCPT ); Tue, 30 Mar 2021 04:59:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231589AbhC3I6f (ORCPT ); Tue, 30 Mar 2021 04:58:35 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 920B3C061762; Tue, 30 Mar 2021 01:58:35 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id ay2so5806296plb.3; Tue, 30 Mar 2021 01:58:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v9G2KuPIg00fMkHFtxzc36ViAJiRyj7R2G3zNb7KNvo=; b=hPsn56mwY+F0xi8rkTRM9xqDEsa2cBbCaN0oUfCF37/qW4kLGxOzvWJvKRHx7NvvyC SmV4dAzrGLeOVnlg72NqYGXZJJgXXd2OwJuBEMR/xeULu8iwMsKDSnrU/QIaLaXDNuf2 yzL4irYPCDLf+oJuzeLhwuZnH2blmdviTXjkyTetHHngdYr0KRgslMkrcFCNDKLyGWnC xav0MGI/F7jekmFUcm6zApkqi2ZzSZCEYdw/e8TtxwmJ1K9bVV7K1hoUqQCswDugT9gx LOoRn3yQzQspSmC70c6MxE4uOt0xgLlGG+AiEykzvRXr/hUulMhorKvjll4FdvBfXESY 8S+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v9G2KuPIg00fMkHFtxzc36ViAJiRyj7R2G3zNb7KNvo=; b=kVuXzAze7PZYIQad1jpyKwIs/3EAVHfqn0CELgtdRKhwlV9/AliTiKSYKNjXxOnIQN 2HWUXysU55IYoCsaWr91shQWsOb0Tn0+eZGcTPYEPFmUVztB/MtmOZZHyTiVUphtlg73 H14g5SjWoOoMEbIe1vD1OQoLw0yqlIy/wKb+Azk5N97cpYnJeJCpxhU5ens6kocvN3MO GQTiEN2FWPm/KbN+bs4xctqvQOAkWhSNn2UjRWjg9eozyUjFyEsYU+aeWrUcGEmfNR6n t6QnYgrIM5RQ0O8aJo0er0wUCyMhj8pF/AAw7EAtSSfxPvoOfRFsyL9374VVpLNXWGUO LqyQ== X-Gm-Message-State: AOAM532jhJqOMx5N0Mmrqy3OvimzNkcc54iTztzXrSwm1P8QvbaR6HXC ufT2LT3UNhRd4tMi1phbFeg= X-Google-Smtp-Source: ABdhPJxe3KK+4Nqy5pQI1XwboPWMy5d6xSYu8sF6E23d0LEZA2IVhbeDRqckAk3uauw67+swQjM1Tw== X-Received: by 2002:a17:902:7407:b029:e4:9b2c:528b with SMTP id g7-20020a1709027407b02900e49b2c528bmr32968487pll.6.1617094715188; Tue, 30 Mar 2021 01:58:35 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id y8sm20952642pfp.140.2021.03.30.01.58.31 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Mar 2021 01:58:34 -0700 (PDT) From: dillon.minfei@gmail.com To: robh@kernel.org, valentin.caron@foss.st.com, Alexandre.torgue@foss.st.com, rong.a.chen@intel.com, a.fatoum@pengutronix.de, mcoquelin.stm32@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, afzal.mohd.ma@gmail.com, gregkh@linuxfoundation.org, erwan.leray@foss.st.com, erwan.leray@st.com, linux-serial@vger.kernel.org, lkp@intel.com, patrice.chotard@foss.st.com Cc: dillon min Subject: [PATCH v8 1/6] Documentation: arm: stm32: Add stm32h750 value line doc Date: Tue, 30 Mar 2021 16:58:19 +0800 Message-Id: <1617094704-10040-2-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617094704-10040-1-git-send-email-dillon.minfei@gmail.com> References: <1617094704-10040-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min This patchset add support for soc stm32h750, stm32h750 has mirror different from stm32h743 item stm32h743 stm32h750 flash size: 2MiB 128KiB adc: none 3 crypto-hash: none aes/hamc/des/tdes/md5/sha detail information can be found at: https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html Signed-off-by: dillon min --- v8: no changes Documentation/arm/index.rst | 1 + Documentation/arm/stm32/stm32h750-overview.rst | 34 ++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 Documentation/arm/stm32/stm32h750-overview.rst diff --git a/Documentation/arm/index.rst b/Documentation/arm/index.rst index b4bea32472b6..d4f34ae9e6f4 100644 --- a/Documentation/arm/index.rst +++ b/Documentation/arm/index.rst @@ -52,6 +52,7 @@ SoC-specific documents stm32/stm32f746-overview stm32/overview stm32/stm32h743-overview + stm32/stm32h750-overview stm32/stm32f769-overview stm32/stm32f429-overview stm32/stm32mp157-overview diff --git a/Documentation/arm/stm32/stm32h750-overview.rst b/Documentation/arm/stm32/stm32h750-overview.rst new file mode 100644 index 000000000000..0e51235c9547 --- /dev/null +++ b/Documentation/arm/stm32/stm32h750-overview.rst @@ -0,0 +1,34 @@ +================== +STM32H750 Overview +================== + +Introduction +------------ + +The STM32H750 is a Cortex-M7 MCU aimed at various applications. +It features: + +- Cortex-M7 core running up to @480MHz +- 128K internal flash, 1MBytes internal RAM +- FMC controller to connect SDRAM, NOR and NAND memories +- Dual mode QSPI +- SD/MMC/SDIO support +- Ethernet controller +- USB OTFG FS & HS controllers +- I2C, SPI, CAN busses support +- Several 16 & 32 bits general purpose timers +- Serial Audio interface +- LCD controller +- HDMI-CEC +- SPDIFRX +- DFSDM + +Resources +--------- + +Datasheet and reference manual are publicly available on ST website (STM32H750_). + +.. _STM32H750: https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html + +:Authors: Dillon Min + From patchwork Tue Mar 30 08:58:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 413119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25C59C433E6 for ; Tue, 30 Mar 2021 08:59:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EC06F6195D for ; Tue, 30 Mar 2021 08:59:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231704AbhC3I7I (ORCPT ); Tue, 30 Mar 2021 04:59:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231668AbhC3I6k (ORCPT ); Tue, 30 Mar 2021 04:58:40 -0400 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFBD8C061762; Tue, 30 Mar 2021 01:58:39 -0700 (PDT) Received: by mail-pj1-x102d.google.com with SMTP id j6-20020a17090adc86b02900cbfe6f2c96so7326457pjv.1; Tue, 30 Mar 2021 01:58:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iREGzC2sZl/DyY2RLlvOKGuuLCaggN30UKHaeQRB7RQ=; b=dR1izMvh+/HTAyMkC6XOLt24pm2NywT4UmnbWq6sLnIhPLKctYtF2kra5Y0DJnyV24 VuaF4FOJOK80+NWhxME51lwuFt5on1y5gvOgu6/n1bNzFdFA4G3AIL+bpXm6YwbfWp5m 5j9XxGsVlqW88+jMBIBD42oDHP0F2QfccNsFEBQACV45x5oem6t0vgBWIZHOHyZ9Vqa+ JoB7Ftb+V7kwOzCgiExKhChEuGESkWpqznZ84Ifjaa3bsQpsRDNLCH+kgZ+rCJsUVmYY wyKJhPUNAXyf0PaLqPuKBL90AjFrSoMcVoGb3gQmQ5feB6lU2EleFDq7W9WixHjPBcXH HkWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iREGzC2sZl/DyY2RLlvOKGuuLCaggN30UKHaeQRB7RQ=; b=Ea6ivxNUFP3/acQodVYF8FfvjpwaGA537gRGL4RgcTUQPMcsXAPlxOGV0xl2fcbrNL toAMZ6xupJnUIXyx2SzYLATrP9VmppjAGDCQqeykNpfZvrTbExIzATrooRo/2IYNIeNz F+vvakGLQWpdpRrbYZMAxtQugmzFMLvikxOmgX2NlNgCPgC+ahEoRn17pJ0AXH/0T+N2 l72pcr07d+x5c+ZrPVIrOFf0ElERdfYQ3RVRvw9uqA8sFqGq9eOYMx5VR9d/I+Klk4OD F6szupiHlz70NJnON5VqlSLIFEA9Gn3/sXTGBW6NPMzN08aLOZbVIrzDE+0kM3ME9QGL AZ7A== X-Gm-Message-State: AOAM532HoVxLkDaPN47nEGMVw8D90kNpyGpFVwA5OsdRlqJgS1QjwsC4 Ucpua9EhIY09UXpd7go/+Nk= X-Google-Smtp-Source: ABdhPJzviLeP5ntIfm2q5brVsYs5JCoAYowXWGq+Nm1e70jjBVNbuBrt0B331QtPpsVbs2jdumfu8g== X-Received: by 2002:a17:902:8497:b029:e6:f01d:9c9f with SMTP id c23-20020a1709028497b02900e6f01d9c9fmr32689394plo.7.1617094719480; Tue, 30 Mar 2021 01:58:39 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id y8sm20952642pfp.140.2021.03.30.01.58.35 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Mar 2021 01:58:39 -0700 (PDT) From: dillon.minfei@gmail.com To: robh@kernel.org, valentin.caron@foss.st.com, Alexandre.torgue@foss.st.com, rong.a.chen@intel.com, a.fatoum@pengutronix.de, mcoquelin.stm32@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, afzal.mohd.ma@gmail.com, gregkh@linuxfoundation.org, erwan.leray@foss.st.com, erwan.leray@st.com, linux-serial@vger.kernel.org, lkp@intel.com, patrice.chotard@foss.st.com Cc: dillon min Subject: [PATCH v8 2/6] dt-bindings: arm: stm32: Add compatible strings for ART-PI board Date: Tue, 30 Mar 2021 16:58:20 +0800 Message-Id: <1617094704-10040-3-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617094704-10040-1-git-send-email-dillon.minfei@gmail.com> References: <1617094704-10040-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min Art-pi based on stm32h750xbh6, with following resources: -8MiB QSPI flash -16MiB SPI flash -32MiB SDRAM -AP6212 wifi, bt, fm detail information can be found at: https://art-pi.gitee.io/website/ Signed-off-by: dillon min Acked-by: Rob Herring --- v8: no changes Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index e7525a3395e5..306e7551ad39 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -53,6 +53,10 @@ properties: - const: st,stm32h743 - items: - enum: + - st,stm32h750i-art-pi + - const: st,stm32h750 + - items: + - enum: - shiratech,stm32mp157a-iot-box # IoT Box - shiratech,stm32mp157a-stinger96 # Stinger96 - st,stm32mp157c-ed1 From patchwork Tue Mar 30 08:58:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 411878 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A176C433EA for ; Tue, 30 Mar 2021 08:59:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 63BDE6195C for ; Tue, 30 Mar 2021 08:59:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231709AbhC3I7I (ORCPT ); Tue, 30 Mar 2021 04:59:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231680AbhC3I6o (ORCPT ); Tue, 30 Mar 2021 04:58:44 -0400 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 931FAC061762; Tue, 30 Mar 2021 01:58:44 -0700 (PDT) Received: by mail-pg1-x534.google.com with SMTP id p12so6598006pgj.10; Tue, 30 Mar 2021 01:58:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZyyxRBNip2ishJwLHrUpp1dW9UpCqi+c/FCO1KJC3Ok=; b=ITSMV/NNzKfzpT5pqrn4fw2H0+FRYyxk62sazG1nx3AeY9RxYvmJS+l4uQGZm7D9Ne mC9gvHuSjcKZcO+oeWKGayzubboemUy4ftuY/Evh6c1ufBY49Sf27jbYQC2nHBmwxr0G KXzONw5PVdvEJ2M1Nx7iZRYxpKtRqj4CaxoqPq7jmYzkYpANtKlDIKbfij3JgI+af7Ft TGSTCIk7Ga4VXlksbyY1Q/oDrc+dr59dDr/iM+Uya3mCin+QwkzRnqRHniAYU+hxMioO H0cAZiyeuHjjZ59WK1lGeHS7hcR68TKqIlDh3MEbCf945ZdrcUYJvf+2g1Kg32Pu+e26 9YeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZyyxRBNip2ishJwLHrUpp1dW9UpCqi+c/FCO1KJC3Ok=; b=fMb9j1ge70sjwzvm5wRKxtH1nmPg/ji6A7FAD7XybfZ1pPm/RT2zV1Ts//es+Mtx/9 f9cUgyxm6qKY0RKZE8GhSL93OSshfJnrX3FQ2ByFXoIXg/QnUFdr+f/JWeQ2n18BGKYo imcLToNZIX+N5IaudKdsbdLMZeBeGA+vwW+1hpserm6ysBKNfj9zCqRt8avC8mPz3n5s UH8cSciEWSTCB/bVZyr6bQUYVY8NgqhqHV1qWIjx2mIPkoZDYXIdHM9wQMUxGn6Fp6lW gCD0Ibz27edh//YqaMDX2M/UgJvQLZWWtL/DeX+Ko0Uz1yEJkCTYa+2UcoqWkmTfzZJ3 4E8w== X-Gm-Message-State: AOAM531GAQL82dPUphD9jjnNNxEl3asE0HafPdT1u3gvyvPgNvg31BQW xs8S71VUfxftED5GajiVrfI= X-Google-Smtp-Source: ABdhPJyvwM99/8Pl725Shx1bFyLGLLc821De0YU8cDqMUONzXeNPcV++xAoaBiT8l2La/xdlNi0Vvw== X-Received: by 2002:a05:6a00:13a3:b029:203:5c4d:7a22 with SMTP id t35-20020a056a0013a3b02902035c4d7a22mr28687313pfg.22.1617094723978; Tue, 30 Mar 2021 01:58:43 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id y8sm20952642pfp.140.2021.03.30.01.58.39 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Mar 2021 01:58:43 -0700 (PDT) From: dillon.minfei@gmail.com To: robh@kernel.org, valentin.caron@foss.st.com, Alexandre.torgue@foss.st.com, rong.a.chen@intel.com, a.fatoum@pengutronix.de, mcoquelin.stm32@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, afzal.mohd.ma@gmail.com, gregkh@linuxfoundation.org, erwan.leray@foss.st.com, erwan.leray@st.com, linux-serial@vger.kernel.org, lkp@intel.com, patrice.chotard@foss.st.com Cc: dillon min Subject: [PATCH v8 3/6] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750 Date: Tue, 30 Mar 2021 16:58:21 +0800 Message-Id: <1617094704-10040-4-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617094704-10040-1-git-send-email-dillon.minfei@gmail.com> References: <1617094704-10040-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min This patch is intend to add support stm32h750 value line, just add stm32h7-pinctrl.dtsi for extending, with following changes: - rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi - update stm32h743i-{dico/eval}.dtsi to include stm32h7-pinctrl.dtsi - add dts binding usart3, uart4 usart3/uart4 pinctrl in stm32h7-pinctrl.dtsi usart3/uart4 register in stm32h743.dtsi - add dts binding sdmmc2 sdmmc2 pinctrl in stm32h7-pinctrl.dtsi sdmmc2 register in stm32h743.dtsi - add spi1_pins pinctrl in stm32h7-pinctrl.dtsi - move 'pin-controller' from stm32h7-pinctrl.dtsi to stm32h743.dtsi, to fix make dtbs_check warrnings arch/arm/boot/dts/stm32h750i-art-pi.dt.yaml: soc: 'i2c@40005C00', 'i2c@58001C00' do not match any of the regexes: '@(0|[1-9a-f][0-9a-f]*)$', '^[^@]+$', 'pinctrl-[0-9]+' Signed-off-by: dillon min --- v8: - drop '[PATCH v7 3/6] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750' - stm32h743-pinctrl.dtsi file - move compatible string "st,stm32h743-pinctrl" from stm32h7-pinctrl.dtsi to stm32h743.dtsi - update stm32h743i-{dico/eval}.dtsi to include stm32h7-pinctrl.dtsi - move file stm32h743.dtsi submit position to [PATCH V8 3/6] arch/arm/boot/dts/stm32h7-pinctrl.dtsi | 341 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 306 --------------------------- arch/arm/boot/dts/stm32h743.dtsi | 165 ++++++++++++++- arch/arm/boot/dts/stm32h743i-disco.dts | 2 +- arch/arm/boot/dts/stm32h743i-eval.dts | 2 +- 5 files changed, 506 insertions(+), 310 deletions(-) create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi delete mode 100644 arch/arm/boot/dts/stm32h743-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi new file mode 100644 index 000000000000..a5c295eca081 --- /dev/null +++ b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi @@ -0,0 +1,341 @@ +/* + * Copyright 2017 - Alexandre Torgue + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +&pinctrl { + + gpioa: gpio@58020000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@58020400 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@58020800 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@58020c00 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@58021000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@58021400 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@58021800 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@58021c00 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@58022000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@58022400 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@58022800 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; + + i2c1_pins_a: i2c1-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + ethernet_rmii: rmii-0 { + pins { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + + usart1_pins: usart1-0 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart2_pins: usart2-0 { + pins1 { + pinmux = ; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart3_pins: usart3-0 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + uart4_pins: uart4-0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + usbotg_hs_pins_a: usbotg-hs-0 { + pins { + pinmux = , /* ULPI_NXT */ + , /* ULPI_DIR> */ + , /* ULPI_STP> */ + , /* ULPI_CK> */ + , /* ULPI_D0> */ + , /* ULPI_D1> */ + , /* ULPI_D2> */ + , /* ULPI_D3> */ + , /* ULPI_D4> */ + , /* ULPI_D5> */ + , /* ULPI_D6> */ + ; /* ULPI_D7> */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + spi1_pins: spi1-0 { + pins1 { + pinmux = , + /* SPI1_CLK */ + ; + /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; + /* SPI1_MISO */ + bias-disable; + }; + }; +}; + diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi deleted file mode 100644 index fa5dcb6a5fdd..000000000000 --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include - -/ { - soc { - pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32h743-pinctrl"; - ranges = <0 0x58020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@58020000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA_CK>; - st,bank-name = "GPIOA"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiob: gpio@58020400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc GPIOB_CK>; - st,bank-name = "GPIOB"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioc: gpio@58020800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc GPIOC_CK>; - st,bank-name = "GPIOC"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiod: gpio@58020c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc GPIOD_CK>; - st,bank-name = "GPIOD"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioe: gpio@58021000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOE_CK>; - st,bank-name = "GPIOE"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiof: gpio@58021400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc GPIOF_CK>; - st,bank-name = "GPIOF"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiog: gpio@58021800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc GPIOG_CK>; - st,bank-name = "GPIOG"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioh: gpio@58021c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc GPIOH_CK>; - st,bank-name = "GPIOH"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioi: gpio@58022000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOI_CK>; - st,bank-name = "GPIOI"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioj: gpio@58022400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc GPIOJ_CK>; - st,bank-name = "GPIOJ"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiok: gpio@58022800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc GPIOK_CK>; - st,bank-name = "GPIOK"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c1_pins_a: i2c1-0 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - ethernet_rmii: rmii-0 { - pins { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - ; /* SDMMC1_CK */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - pins2{ - pinmux = ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_dir_pins_a: sdmmc1-dir-0 { - pins1 { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - ; /* SDMMC1_CDIR */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - pins2{ - pinmux = ; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - , /* SDMMC1_CDIR */ - ; /* SDMMC1_CKIN */ - }; - }; - - usart1_pins: usart1-0 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart2_pins: usart2-0 { - pins1 { - pinmux = ; /* USART2_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART2_RX */ - bias-disable; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = , /* ULPI_NXT */ - , /* ULPI_DIR> */ - , /* ULPI_STP> */ - , /* ULPI_CK> */ - , /* ULPI_D0> */ - , /* ULPI_D1> */ - , /* ULPI_D2> */ - , /* ULPI_D3> */ - , /* ULPI_D4> */ - , /* ULPI_D5> */ - , /* ULPI_D6> */ - ; /* ULPI_D7> */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 4ebffb0a45a3..b58cae967b2a 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -135,6 +135,22 @@ clocks = <&rcc USART2_CK>; }; + usart3: serial@40004800 { + compatible = "st,stm32h7-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + status = "disabled"; + clocks = <&rcc USART3_CK>; + }; + + uart4: serial@40004c00 { + compatible = "st,stm32h7-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + status = "disabled"; + clocks = <&rcc UART4_CK>; + }; + i2c1: i2c@40005400 { compatible = "st,stm32f7-i2c"; #address-cells = <1>; @@ -159,7 +175,7 @@ status = "disabled"; }; - i2c3: i2c@40005C00 { + i2c3: i2c@40005c00 { compatible = "st,stm32f7-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -368,6 +384,20 @@ max-frequency = <120000000>; }; + sdmmc2: mmc@48022400 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x48022400 0x400>; + interrupts = <124>; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC2_CK>; + clock-names = "apb_pclk"; + resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + }; + exti: interrupt-controller@58000000 { compatible = "st,stm32h7-exti"; interrupt-controller; @@ -392,7 +422,7 @@ status = "disabled"; }; - i2c4: i2c@58001C00 { + i2c4: i2c@58001c00 { compatible = "st,stm32f7-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -555,6 +585,137 @@ snps,pbl = <8>; status = "disabled"; }; + + pinctrl: pin-controller@58020000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32h743-pinctrl"; + ranges = <0 0x58020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + pins-are-numbered; + + gpioa: gpio@58020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc GPIOA_CK>; + st,bank-name = "GPIOA"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpiob: gpio@58020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc GPIOB_CK>; + st,bank-name = "GPIOB"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpioc: gpio@58020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc GPIOC_CK>; + st,bank-name = "GPIOC"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpiod: gpio@58020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc GPIOD_CK>; + st,bank-name = "GPIOD"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpioe: gpio@58021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc GPIOE_CK>; + st,bank-name = "GPIOE"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpiof: gpio@58021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc GPIOF_CK>; + st,bank-name = "GPIOF"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpiog: gpio@58021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc GPIOG_CK>; + st,bank-name = "GPIOG"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpioh: gpio@58021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc GPIOH_CK>; + st,bank-name = "GPIOH"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpioi: gpio@58022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc GPIOI_CK>; + st,bank-name = "GPIOI"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpioj: gpio@58022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc GPIOJ_CK>; + st,bank-name = "GPIOJ"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpiok: gpio@58022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc GPIOK_CK>; + st,bank-name = "GPIOK"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts index e446d311c520..59e01ce10318 100644 --- a/arch/arm/boot/dts/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/stm32h743i-disco.dts @@ -42,7 +42,7 @@ /dts-v1/; #include "stm32h743.dtsi" -#include "stm32h743-pinctrl.dtsi" +#include "stm32h7-pinctrl.dtsi" / { model = "STMicroelectronics STM32H743i-Discovery board"; diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts index 8f398178f5e5..38cc7faf6884 100644 --- a/arch/arm/boot/dts/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/stm32h743i-eval.dts @@ -42,7 +42,7 @@ /dts-v1/; #include "stm32h743.dtsi" -#include "stm32h743-pinctrl.dtsi" +#include "stm32h7-pinctrl.dtsi" / { model = "STMicroelectronics STM32H743i-EVAL board"; From patchwork Tue Mar 30 08:58:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 411880 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9357C433E4 for ; Tue, 30 Mar 2021 08:59:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BB7446198A for ; Tue, 30 Mar 2021 08:59:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231715AbhC3I7K (ORCPT ); Tue, 30 Mar 2021 04:59:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231684AbhC3I6s (ORCPT ); Tue, 30 Mar 2021 04:58:48 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7381C061762; Tue, 30 Mar 2021 01:58:48 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id 11so11683829pfn.9; Tue, 30 Mar 2021 01:58:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l40L85yjOAF1nMjx7IR1eqOyevgxGfAORpjk7JeQePU=; b=DAnHGbBQe/cRUeQb9G+oQfqXLp37LHSokZLXilL7ZII51fG9eOpi+4hVDI+ggjQalI uPyvyLbbb+v2qqnCR4afL9dfwy9/CDC4Dj1CD4rjbyFyT/bsnnoKJ88HDz13Ejc6+dqi EVTj+2VBX4ISH0hIMfl+51dmsegAs5gy8RNMN6sNpDAGF5gVXiuw8WxlmN7i1x3TGRPQ F45w4m3fN4yC+t6A5O7G6sgjU4Px8JbA4jj2yL98gTnoddthlS4PUMpUIt3aKbe6iPM9 qjCZUTTiQ3cxOCic/PwYKfEOTYgWF025TRbaak7RMcz6wSZ67PHqcUn4uZsHHh7NoOaj O0JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l40L85yjOAF1nMjx7IR1eqOyevgxGfAORpjk7JeQePU=; b=uTl1P56qdxvMQ5cKWjeeHWsfcreT/77jrhhuBh4pI3OImjTjUAKJPuiq2OeFydrnCr nx/k6cFJ7wonsSM9ecVGKpL59cMDivgf29ifR+4IBc0aTri/ox2pewzvuYaxkW1gpD3P uYJgy/bbiEUinxGFu7adAJFc7DwydCWKiRC3nJ4Vi1UcXAuYG6uQp6QxXlYaYLzzCkOg 0+UqOqDtXeu80NH0wzvVeTGoUdtUo/MTSgMYNRVtMzKBP/SNjlabYhYadfr93wUz1TH+ RJQEGTUjjj8pfNAa9mSf6dZroso8ilmwoBjW9uZ8QStSDv5oQ7SKDa2nezC6GRFYBldT YcGQ== X-Gm-Message-State: AOAM531ogxS85h8OdVBT0i0lnEg+Iyp81a2JdXjbLOviMEpSaxf6BQib 1J3oVqgRiA8Nqm+aw6DcdEs= X-Google-Smtp-Source: ABdhPJzp0OZqbrC42l6F/8me/1akRAMkUI0IZO4k0EidXWF4ZKtX4Mf8+Kps3Su4R9ZV6ZJHjCxKbA== X-Received: by 2002:a62:e119:0:b029:1f8:9345:a099 with SMTP id q25-20020a62e1190000b02901f89345a099mr29752361pfh.21.1617094728280; Tue, 30 Mar 2021 01:58:48 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id y8sm20952642pfp.140.2021.03.30.01.58.44 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Mar 2021 01:58:48 -0700 (PDT) From: dillon.minfei@gmail.com To: robh@kernel.org, valentin.caron@foss.st.com, Alexandre.torgue@foss.st.com, rong.a.chen@intel.com, a.fatoum@pengutronix.de, mcoquelin.stm32@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, afzal.mohd.ma@gmail.com, gregkh@linuxfoundation.org, erwan.leray@foss.st.com, erwan.leray@st.com, linux-serial@vger.kernel.org, lkp@intel.com, patrice.chotard@foss.st.com Cc: dillon min Subject: [PATCH v8 4/6] ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6 Date: Tue, 30 Mar 2021 16:58:22 +0800 Message-Id: <1617094704-10040-5-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617094704-10040-1-git-send-email-dillon.minfei@gmail.com> References: <1617094704-10040-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min This patchset has following changes: - introduce stm32h750.dtsi to support stm32h750 value line - add stm32h750i-art-pi.dtb (arch/arm/boot/dts/Makefile) - add stm32h750-art-pi.dts to support art-pi board art-pi board component: - 8MiB qspi flash - 16MiB spi flash - 32MiB sdram - ap6212 wifi&bt&fm the detail board information can be found at: https://art-pi.gitee.io/website/ Signed-off-by: dillon min --- v8: - move file stm32h743.dtsi submit position to [PATCH V8 3/6] arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32h750.dtsi | 6 + arch/arm/boot/dts/stm32h750i-art-pi.dts | 229 ++++++++++++++++++++++++++++++++ 3 files changed, 236 insertions(+) create mode 100644 arch/arm/boot/dts/stm32h750.dtsi create mode 100644 arch/arm/boot/dts/stm32h750i-art-pi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8e5d4ab4e75e..a19c5ab9df84 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1071,6 +1071,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32746g-eval.dtb \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ + stm32h750i-art-pi.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ diff --git a/arch/arm/boot/dts/stm32h750.dtsi b/arch/arm/boot/dts/stm32h750.dtsi new file mode 100644 index 000000000000..41e3b1e3a874 --- /dev/null +++ b/arch/arm/boot/dts/stm32h750.dtsi @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */ + +#include "stm32h743.dtsi" + + diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts new file mode 100644 index 000000000000..9bb73bb61901 --- /dev/null +++ b/arch/arm/boot/dts/stm32h750i-art-pi.dts @@ -0,0 +1,229 @@ +/* + * Copyright 2021 - Dillon Min + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * For art-pi board resources, you can refer to link: + * https://art-pi.gitee.io/website/ + */ + +/dts-v1/; +#include "stm32h750.dtsi" +#include "stm32h7-pinctrl.dtsi" +#include +#include + +/ { + model = "RT-Thread STM32H750i-ART-PI board"; + compatible = "st,stm32h750i-art-pi", "st,stm32h750"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:2000000n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x2000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + no-map; + size = <0x100000>; + linux,dma-default; + }; + }; + + aliases { + serial0 = &uart4; + serial1 = &usart3; + }; + + leds { + compatible = "gpio-leds"; + led-red { + gpios = <&gpioi 8 0>; + }; + led-green { + gpios = <&gpioc 15 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + +&mac { + status = "disabled"; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + dmas = <&dmamux1 37 0x400 0x05>, + <&dmamux1 38 0x400 0x05>; + dma-names = "rx", "tx"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + + partition@0 { + label = "root filesystem"; + reg = <0 0x1000000>; + }; + }; +}; + +&usart2 { + pinctrl-0 = <&usart2_pins>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins>; + dmas = <&dmamux1 45 0x400 0x05>, + <&dmamux1 46 0x400 0x05>; + dma-names = "rx", "tx"; + st,hw-flow-ctrl; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>; + max-speed = <115200>; + }; +}; + +&uart4 { + pinctrl-0 = <&uart4_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + + From patchwork Tue Mar 30 08:58:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 411879 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B34AFC433E9 for ; Tue, 30 Mar 2021 08:59:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A00F261959 for ; Tue, 30 Mar 2021 08:59:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231721AbhC3I7K (ORCPT ); Tue, 30 Mar 2021 04:59:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231629AbhC3I6x (ORCPT ); Tue, 30 Mar 2021 04:58:53 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEE95C061762; Tue, 30 Mar 2021 01:58:52 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id v8so5809038plz.10; Tue, 30 Mar 2021 01:58:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FUmJbGGhJ0M8BOof8LnXQJFcnuGvgG4sMjXT3YiPkS4=; b=tWWjc17CwkjTu7PLrTye0AARaJrJSAObQBbyUVq5qn/DG/aZm9LaaBgVWrIR1Pcg4V LEIu3DaRdLNHNyBJbINXKfuRXtJCAb+vGDsECaCoYZP5uj0b3egrAjhfjtmZqU+CFttS WbimF8Ko3WiejsftdeZNEL0Al/OEDzBvWU38Ej/sNyuxkaTBhVQ8T4RpljBvY90fRyiJ Bai8eCzP4efucCLRCLoZQwA1MjFUYUzkMgw66TVPuCQAxee6so91ncR/qXEgh+jldwQb X71uxSm8VlVvvzaIZ1AOY0hCkQSHSD/PHfrjj1vMHuezODgcp0yQdZBKme4qZy3nWsUi /utw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FUmJbGGhJ0M8BOof8LnXQJFcnuGvgG4sMjXT3YiPkS4=; b=XNnCtw0pSTU1fuqesw8PRvGtj6uY14Mp9PPEwbgj+Hmk4bLAG/VmuTgWEbBZYaaxSX 0bwkWLk/GYaOqCp+8QBjmQWyFOiZsAGz8xrJJ993zipUJ1nQc01WeX7OAg9TS2ZbdeM0 LVm2F6SvHqNhtov9ud/p2UdRPtsZH95GQjd7Sx94tW9+Fn+2FX5JKuAQpYrVw2w9E3Xi O0UrZudXBPlz4kYCzpefcICX0zqjvORuqGr4wHL7K5dtgCHXpoK+gfqe22Do5kIkV+Lq 2zHPaqaWnKedVOCjC2jNOK0d6iL1M+13Hi4DzlU/eCHqWT4Wq0Xocj59rsIyijtV0asJ M5Cw== X-Gm-Message-State: AOAM533MtWjhFFw2NvUYHmZev/YTbs1GC9B+gFUOFGfwO4FHhFfbiMhn vkbhWSvs9VMaI8zZ15JuEBo= X-Google-Smtp-Source: ABdhPJxoK0LnTrxg0IQQDSduBRY1DwM9p7bY7psUqjidgg8DbkkuBfvtcB4b+hXzvtpQJpZA6pKOpg== X-Received: by 2002:a17:90a:cf8f:: with SMTP id i15mr3343412pju.22.1617094732561; Tue, 30 Mar 2021 01:58:52 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id y8sm20952642pfp.140.2021.03.30.01.58.48 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Mar 2021 01:58:52 -0700 (PDT) From: dillon.minfei@gmail.com To: robh@kernel.org, valentin.caron@foss.st.com, Alexandre.torgue@foss.st.com, rong.a.chen@intel.com, a.fatoum@pengutronix.de, mcoquelin.stm32@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, afzal.mohd.ma@gmail.com, gregkh@linuxfoundation.org, erwan.leray@foss.st.com, erwan.leray@st.com, linux-serial@vger.kernel.org, lkp@intel.com, patrice.chotard@foss.st.com Cc: dillon min Subject: [PATCH v8 5/6] ARM: stm32: Add a new SOC - STM32H750 Date: Tue, 30 Mar 2021 16:58:23 +0800 Message-Id: <1617094704-10040-6-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617094704-10040-1-git-send-email-dillon.minfei@gmail.com> References: <1617094704-10040-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min The STM32H750 is a Cortex-M7 MCU running at 480MHz and containing 128KBytes internal flash, 1MiB SRAM. Signed-off-by: dillon min --- v8: no changes arch/arm/mach-stm32/board-dt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c index 011d57b488c2..a766310d8dca 100644 --- a/arch/arm/mach-stm32/board-dt.c +++ b/arch/arm/mach-stm32/board-dt.c @@ -17,6 +17,7 @@ static const char *const stm32_compat[] __initconst = { "st,stm32f746", "st,stm32f769", "st,stm32h743", + "st,stm32h750", "st,stm32mp157", NULL }; From patchwork Tue Mar 30 08:58:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 413118 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A656FC433EB for ; Tue, 30 Mar 2021 08:59:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8AB3961996 for ; Tue, 30 Mar 2021 08:59:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231549AbhC3I7L (ORCPT ); Tue, 30 Mar 2021 04:59:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231686AbhC3I65 (ORCPT ); Tue, 30 Mar 2021 04:58:57 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3220AC061762; Tue, 30 Mar 2021 01:58:57 -0700 (PDT) Received: by mail-pf1-x433.google.com with SMTP id m11so11677556pfc.11; Tue, 30 Mar 2021 01:58:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F9tSrsqSDZKawmCDjVV+tzhmJdPbgKPqMa/CwWx5jps=; b=C0EXNuAjqJ0RYeS2/x/rgzfMvYBNcw7W0kjMnzwTG3Uo4kuGO6m+vVr0bd09QrFmhO /GI6tMuLAxdgtMJAn49vD7jxqQFbEjGZVf7WDLiJt7p43hqdXP03jErWYqDoBtUiezhN /OmmOSIWHQTjljntLn7nveNxNhYaqd2c/hVfUbCREPF/j6LJ4Q6StVtS23DXrNKS6SzZ vW0i8WLRZdbF7bqcVdZZz1CQ/GRLo4W7KI5dpfGcxnvK90paeAz42woR5uU5ai20PmWR 8+XQExdk2coXf1D+jE4e7Y864IaC9mdsvSGwrtTHCQZbPdzSuV8+JQvP8YS6N+OaefTy PFfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F9tSrsqSDZKawmCDjVV+tzhmJdPbgKPqMa/CwWx5jps=; b=st5Kc7Yy1Yhxsy2yzF8uzV+2PQCNiaPcC8nG6yU2DBQGowErUd+E4xGtDOJksN17Ed t04puVtemBg+Bp5dcrEUeeCVw0ybo//X3w6j7A7f5Uyp035glo9JUgCWlsKGnj330Pjd yV3PSzzrpKOJbQRkzfO9I8oTFOqLEn17/edNbLYbg3TRcbbPdsX671DamuArr71zeXpU kYBzDkGVDuC8INW+u/4FKvavWzc7I8YKKEIMnPSp22GIqUplHgUCVUPpyY5r1s0S2OBQ pKpI23NDaHA6xRbSRy9xrIS+/Ls4WmluQU9//YPEdpqnm9cn0jTP/Flg+evh5KJeQokW QpVA== X-Gm-Message-State: AOAM532LHml6EX8aOWczU8LldSNYQZHskwFPISK/Y8WhdLnNdA2cqU1L xrZn7eKXJMGLls5Lj80wkIE= X-Google-Smtp-Source: ABdhPJz4JEITEdJIKes5VdRLdLAriYxA0JWe625kgdkuzO430nqFP/o7RLuxlnIZtT/OtWNqDsHohQ== X-Received: by 2002:a62:800c:0:b029:203:6990:78e2 with SMTP id j12-20020a62800c0000b0290203699078e2mr29079533pfd.3.1617094736831; Tue, 30 Mar 2021 01:58:56 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id y8sm20952642pfp.140.2021.03.30.01.58.52 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Mar 2021 01:58:56 -0700 (PDT) From: dillon.minfei@gmail.com To: robh@kernel.org, valentin.caron@foss.st.com, Alexandre.torgue@foss.st.com, rong.a.chen@intel.com, a.fatoum@pengutronix.de, mcoquelin.stm32@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, afzal.mohd.ma@gmail.com, gregkh@linuxfoundation.org, erwan.leray@foss.st.com, erwan.leray@st.com, linux-serial@vger.kernel.org, lkp@intel.com, patrice.chotard@foss.st.com Cc: dillon min Subject: [PATCH v8 6/6] dt-bindings: serial: stm32: Use 'type: object' instead of false for 'additionalProperties' Date: Tue, 30 Mar 2021 16:58:24 +0800 Message-Id: <1617094704-10040-7-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617094704-10040-1-git-send-email-dillon.minfei@gmail.com> References: <1617094704-10040-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: dillon min To use additional properties 'bluetooth' on serial, need replace false with 'type: object' for 'additionalProperties' to make it as a node, else will run into dtbs_check warnings. 'arch/arm/boot/dts/stm32h750i-art-pi.dt.yaml: serial@40004800: 'bluetooth' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: af1c2d81695b ("dt-bindings: serial: Convert STM32 UART to json-schema") Reported-by: kernel test robot Tested-by: Valentin Caron Signed-off-by: dillon min Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/1616757302-7889-8-git-send-email-dillon.minfei@gmail.com Signed-off-by: dillon min --- v8: no changes, this patch was merged to tty-next by Greg Kroah-Hartman Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 8631678283f9..865be05083c3 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -80,7 +80,8 @@ required: - interrupts - clocks -additionalProperties: false +additionalProperties: + type: object examples: - |