From patchwork Tue Mar 30 23:04:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 411830 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A24E6C433E5 for ; Tue, 30 Mar 2021 23:06:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6E4C3619CF for ; Tue, 30 Mar 2021 23:06:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233083AbhC3XFa (ORCPT ); Tue, 30 Mar 2021 19:05:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233092AbhC3XFT (ORCPT ); Tue, 30 Mar 2021 19:05:19 -0400 Received: from mail-qt1-x82d.google.com (mail-qt1-x82d.google.com [IPv6:2607:f8b0:4864:20::82d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84B5EC061762; Tue, 30 Mar 2021 16:05:18 -0700 (PDT) Received: by mail-qt1-x82d.google.com with SMTP id s2so13155299qtx.10; Tue, 30 Mar 2021 16:05:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hM3oGGoU1XkWBbm6zDENhRNBn2pOgCUo+5XYNt0fTmQ=; b=tAvQD6Or/Bw9+JB2UesVPL106yzmM4wE+EMgRYlM42jvxraIBaGX8i+kjuc6sVVBbj lqyuB1MXOImr7IB4NquJrZRrJxsYcWHGxI1RkqIN5wCvzQxH8f4HVstbNBY1PdEBPBIZ rLEfE9BNfJOKmATdTTKqipLW8JRjvK228nuplkGK5ybvHCsRGEmPSqRRzpD1tDw1TtnS umkvhdD8qG5k4ow4vgWG36qnMPh/Bv27KqPBT2kjqxAktc1okulguZnNDZROiaXjgWwZ n3dvOf+jtUhsaAT5wbjfqxAJmV0LhvWlwsVHlImm5BLhYiF1MQHKEjZZKL0IE3VW52ot D7Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hM3oGGoU1XkWBbm6zDENhRNBn2pOgCUo+5XYNt0fTmQ=; b=m+eNWlnqQ5aLh9HGhaBRoCMalvCnTThW9IkwKUqaGcJSvGtjAKGKIEfICqZrRbw8Ep Nt2D2Os+ZQUW1l+pGWdtcsY2Rngg1A5L9jQIUlZWGvvGeqPFiHG/KEGAOqSyo60/HuYB dPG1+Re9hudHQpM36ugBdxABhOJtSPs6zf5KzvfI0/AEPUKNtng6uhJEmM9P/2p9uyo+ 19/WwHxicuWViacNCl7hGbykUiAKIYhM8DRFMBAc72QdMTF1an5Hit4gmBITRXeFYydG anp215dj4+yhaYXQCaQsgNWavljL7JD2rw8UsWZM/OmVbyUsHPk8tYRaFmIz4EQfSZnE vzcQ== X-Gm-Message-State: AOAM531pOJ7LO26ZTSPZZSyY3USbpFQEUkaS9jGtFjRrCFFmbzn8PiSz D+DEDfqfNrsZDNJzk2dQrTk= X-Google-Smtp-Source: ABdhPJzH6PK1fDnceudOBLmD65OS7s8i8QLKp/hZ3qUZ9FrX8lYCTQEnq80jRmGj1/h97TBzv9HX2w== X-Received: by 2002:ac8:7951:: with SMTP id r17mr127118qtt.207.1617145517487; Tue, 30 Mar 2021 16:05:17 -0700 (PDT) Received: from localhost.localdomain (109-252-193-98.dynamic.spd-mgts.ru. [109.252.193.98]) by smtp.gmail.com with ESMTPSA id 10sm160061qkc.83.2021.03.30.16.05.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Mar 2021 16:05:17 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , Rob Herring Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 1/6] dt-bindings: memory: tegra20: emc: Replace core regulator with power domain Date: Wed, 31 Mar 2021 02:04:40 +0300 Message-Id: <20210330230445.26619-2-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210330230445.26619-1-digetx@gmail.com> References: <20210330230445.26619-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Power domain fits much better than a voltage regulator in regards to a proper hardware description and from a software perspective as well. Hence replace the core regulator with the power domain. Note that this doesn't affect any existing DTBs because we haven't started to use the regulator yet, and thus, it's okay to change it. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index cc443fcf4bec..d2250498c36d 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -23,7 +23,7 @@ For each opp entry in 'operating-points-v2' table: matches, the OPP gets enabled. Optional properties: -- core-supply: Phandle of voltage regulator of the SoC "core" power domain. +- power-domains: Phandle of the SoC "core" power domain. Child device nodes describe the memory settings for different configurations and clock rates. @@ -48,7 +48,7 @@ Example: interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; nvidia,memory-controller = <&mc>; - core-supply = <&core_vdd_reg>; + power-domains = <&domain>; operating-points-v2 = <&opp_table>; } From patchwork Tue Mar 30 23:04:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 411831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 521A8C433E0 for ; Tue, 30 Mar 2021 23:06:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1D8BC619CF for ; Tue, 30 Mar 2021 23:06:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233139AbhC3XFb (ORCPT ); Tue, 30 Mar 2021 19:05:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233093AbhC3XFU (ORCPT ); Tue, 30 Mar 2021 19:05:20 -0400 Received: from mail-qk1-x732.google.com (mail-qk1-x732.google.com [IPv6:2607:f8b0:4864:20::732]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F88CC061574; Tue, 30 Mar 2021 16:05:20 -0700 (PDT) Received: by mail-qk1-x732.google.com with SMTP id 7so17620203qka.7; Tue, 30 Mar 2021 16:05:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vD7aA50daokeImwQI/Xuv/wV35uFSogSSArZHXkVpXw=; b=MqAir8VAOaL65B4g4ozKoGcvXhnOh/80s/TvA2rdwPF8krxAlGRhiMEq0ngiPLdb+A VdT1kXFKLA4n4+n+ZA/rMF6Ak3fwvpLHTAyPBqlxaQlpe4HHe38O5q2VY3W1W7pgtXS8 2JC+tpstL+OQzP6v8LsGuTkE+ww0+WYVgUTO/EdWXLdGRoAC1qGn8KT3guxnpmoGuVB+ Vy7KWIX8T5XqherHj4V8RWyPm07wR5h5q0lOtxFztPWqQiFR+ykqjLRdIydFT22zo6wD 1nz8FaRTHH3CaQEMdPy5LiTBeiueY4rFPABW7pcmwtniqP/7WjKctwgw36gvDeDCJIV5 1gjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vD7aA50daokeImwQI/Xuv/wV35uFSogSSArZHXkVpXw=; b=bD0GmaegB1VMQhoPBIli+XPeZge+OHlFu8WJu0Ai/u6dqON47xUAMfPdglAZnay69f 4ffl1Edu+N08Sbk9/VCJKN6pJ0I/FsbxX0SQcUXxQNtxIo57Jade8jiTrV0DVmh5VHzn NzypiVf4xhYSw5MYZiY2HpiR3saU+Zhc7czjWblr7oqAppLnNS8pNIE1WZFrkKL7dR2d hff6ljegI87iyD5kksU69oycZsi8B56bhzOMVhQesyMx3rm9+jqhbQAtiuH027LPMgAU dZ7eSkaFxuVpOo3WiARH5vt4jHud2Rmj8M4LZrgwlMOShZFJ/dj3aNVSPP+stiJzfxUr m2SQ== X-Gm-Message-State: AOAM532jzlISBd43xLukjsKxWu6Flez2mY4n+CiKoADgegDbJWgRiSAv IFAhfiKO6D9Z1pdF8Wyt1nmj5EV6SYI= X-Google-Smtp-Source: ABdhPJwKDAX9PJmdWpyX7H4JrqUrvt8DXbd3FGqPIdAaJcaGE5kGnEbINmXluuR/7TSeRzEnzLcGmA== X-Received: by 2002:a37:7985:: with SMTP id u127mr587652qkc.333.1617145519481; Tue, 30 Mar 2021 16:05:19 -0700 (PDT) Received: from localhost.localdomain (109-252-193-98.dynamic.spd-mgts.ru. [109.252.193.98]) by smtp.gmail.com with ESMTPSA id 10sm160061qkc.83.2021.03.30.16.05.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Mar 2021 16:05:19 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , Rob Herring Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 2/6] dt-bindings: memory: tegra30: emc: Replace core regulator with power domain Date: Wed, 31 Mar 2021 02:04:41 +0300 Message-Id: <20210330230445.26619-3-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210330230445.26619-1-digetx@gmail.com> References: <20210330230445.26619-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Power domain fits much better than a voltage regulator in regards to a proper hardware description and from a software perspective as well. Hence replace the core regulator with the power domain. Note that this doesn't affect any existing DTBs because we haven't started to use the regulator yet, and thus, it's okay to change it. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring --- .../bindings/memory-controllers/nvidia,tegra30-emc.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index 0a2e2c0d0fdd..fb6af14cb49c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -39,9 +39,10 @@ properties: description: Phandle of the Memory Controller node. - core-supply: + power-domains: + maxItems: 1 description: - Phandle of voltage regulator of the SoC "core" power domain. + Phandle of the SoC "core" power domain. operating-points-v2: description: @@ -241,7 +242,7 @@ examples: nvidia,memory-controller = <&mc>; operating-points-v2 = <&dvfs_opp_table>; - core-supply = <&vdd_core>; + power-domains = <&domain>; #interconnect-cells = <0>; From patchwork Tue Mar 30 23:04:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 413073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA697C433E6 for ; Tue, 30 Mar 2021 23:06:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 885C3619CA for ; Tue, 30 Mar 2021 23:06:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233152AbhC3XFb (ORCPT ); Tue, 30 Mar 2021 19:05:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233095AbhC3XFW (ORCPT ); Tue, 30 Mar 2021 19:05:22 -0400 Received: from mail-qk1-x736.google.com (mail-qk1-x736.google.com [IPv6:2607:f8b0:4864:20::736]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CA5DC061574; Tue, 30 Mar 2021 16:05:22 -0700 (PDT) Received: by mail-qk1-x736.google.com with SMTP id c4so17628347qkg.3; Tue, 30 Mar 2021 16:05:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Imb+SxWawi3m+n6OniYBVnsTMCYaEIQpp22RBVSMzAM=; b=Itbh3/9/RALYOzdolSO2nsBLW03gGJ1fQEUQA46bC214y2FEovgqv45PtwlB9sJIKi ZdW4Yo00WQUwLi7kDUUTn01POJqLPczxv4eW36SCgsESTRYu/sFQgUXp58Y3uyLu1Kba 5/jVnnykfSMxASShe6Qdo89itr8Q4tYE/Dx3whG41qll1ZiKoV0iAtMuHc6EjQQBU+6P lfh52Pgch3A4XHZTUtMJPIx7ZOZ4k2VDp5CLEPjkqc+pV44d0EGCBDeDq9vSIBaFkCLn g5fTZx1codAPxLCKVUgjw2nEcmueOh38+19/1UyD+OHlmIjW/YYvDTA7H+aCOOHdbGTa pQ/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Imb+SxWawi3m+n6OniYBVnsTMCYaEIQpp22RBVSMzAM=; b=at2iR9jFO8sFNY0LYY4U1CTSu9qY1YZAMqiv5idvyW9e0K+p9ywc6PU2DOVXC6y7I3 ZXKm7jcezmdSkkPxRMz6Yd8e8DDTdn0urLjKvV2wmXZ17e5VPrJ6DD8e63BGCtuPHLYZ sVBBOVp+KSzl0vCuGeLhmgpipZ+GKQRwCZHmxNh7YSSqyXTMwczqBvovZ+GsYndCAABh RZPl6AK70GI86+gXy5xi9YHIop6KuhM6kH9Ea5mDDZ6GfdhvmPB0mIYh2ovc5+jF3ksp X9b0qBqW4zeed293AjkkoPRAcLfSm5dRwZrxuhBeMDmgFhtLMYsfJu44m9J/5HZh3x0E OSNA== X-Gm-Message-State: AOAM5301YGEicHn0vkcEI7sdmirazA6WSH7wIBZXeo2tGffxdJpNxoRK 9dojimQC+jal06611KUa1IU= X-Google-Smtp-Source: ABdhPJxrUJ+ar8QyG4UdQ3cyz0VLG3P5m+8L9hEXsgj+6piU1K5OPjBdKOef9lGY8RwkexA9hbe+Kw== X-Received: by 2002:ae9:d60a:: with SMTP id r10mr559154qkk.411.1617145521509; Tue, 30 Mar 2021 16:05:21 -0700 (PDT) Received: from localhost.localdomain (109-252-193-98.dynamic.spd-mgts.ru. [109.252.193.98]) by smtp.gmail.com with ESMTPSA id 10sm160061qkc.83.2021.03.30.16.05.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Mar 2021 16:05:21 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , Rob Herring Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 3/6] dt-bindings: memory: tegra124: emc: Replace core regulator with power domain Date: Wed, 31 Mar 2021 02:04:42 +0300 Message-Id: <20210330230445.26619-4-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210330230445.26619-1-digetx@gmail.com> References: <20210330230445.26619-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Power domain fits much better than a voltage regulator in regards to a proper hardware description and from a software perspective as well. Hence replace the core regulator with the power domain. Note that this doesn't affect any existing DTBs because we haven't started to use the regulator yet, and thus, it's okay to change it. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring --- .../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 09bde65e1955..9163c3f12a85 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -37,9 +37,10 @@ properties: description: phandle of the memory controller node - core-supply: + power-domains: + maxItems: 1 description: - Phandle of voltage regulator of the SoC "core" power domain. + Phandle of the SoC "core" power domain. operating-points-v2: description: @@ -370,7 +371,7 @@ examples: nvidia,memory-controller = <&mc>; operating-points-v2 = <&dvfs_opp_table>; - core-supply = <&vdd_core>; + power-domains = <&domain>; #interconnect-cells = <0>; From patchwork Tue Mar 30 23:04:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 411829 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B8A8C433E8 for ; Tue, 30 Mar 2021 23:06:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DB161619D0 for ; Tue, 30 Mar 2021 23:06:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233161AbhC3XFc (ORCPT ); Tue, 30 Mar 2021 19:05:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233096AbhC3XFY (ORCPT ); Tue, 30 Mar 2021 19:05:24 -0400 Received: from mail-qv1-xf2f.google.com (mail-qv1-xf2f.google.com [IPv6:2607:f8b0:4864:20::f2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4870EC061574; Tue, 30 Mar 2021 16:05:24 -0700 (PDT) Received: by mail-qv1-xf2f.google.com with SMTP id iu14so3482273qvb.4; Tue, 30 Mar 2021 16:05:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=peNVppBARBLCgsqxF1x4RU4hqaSXt28ZBbCndisB5s4=; b=DzywFBD7aIQ/JFHzKhgp8UZpn8iOFAHufzCmo1JT9JggzOEMQQdgCTX8og+X4GQvLv lQ5JmfXXrsy5XLyEgPNjRdanWeMZRcgNb0vjHbuEPTbNHTnuvzSuVgvL/0Z/Ofc5fICr oXDYK/GvCS38A2R1gOI+/RNaMhMd3TvpXChKCPMdPpl7zSo05XjRHe3WeSTATNTZp4iR EOxf33QZ6CrlEKQ8N6ZxnPptBmPqa7dnaw4E2pQ77tOaDe9nc1iVSKChBWFH1FxseNSU SeoCQOqCLUHVpMMjM75IwhpNw72zFNNwFIthipvRPDnesVoUtHSKl7H/qzZdgSQg5KR9 oJuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=peNVppBARBLCgsqxF1x4RU4hqaSXt28ZBbCndisB5s4=; b=aXY6y1ZmqpIEGwkoCHGGd7b4YXXRrUuAaRqZ62lHFW7N+kABdmsap1zlCGld7Msi8u 2QmiQwe6SGBKZe89ncgIVQWIhckzGWzsepBnY0shGLEzKYCRJrZtqa5j4AQXlwO8N4vA KKPoNWBaSV/t0rxcyjk35ruqR+K9v1QM3P/vDtuRRPg5J2qlf3wA8NSH/bFDRK7FVgd2 L1kCwEV/viJYSE4x3tJqxYiXYflfbUw3bxbxpOAu2vy15rwsf2V99KwA1kLV4cUplAsT AKOqB/5WdB8seGO91HDLJPdv4oYjLnxPRL3B4Z8zlNnBqTZjq3CaQUvs61FgnkhxUD/B 1uWg== X-Gm-Message-State: AOAM530Ow5IudFfX7qqy/LIqOtgzVnGONIeEOYBNEdLjaKiBHKDT48n1 xUl+XuPLj1rBLVGKwPVyJVY= X-Google-Smtp-Source: ABdhPJxpasvWrmRcSQ4o9Xg1VSS7GifN1kEt8IsiqWxKeS4ox9X97hHWJlCoTbQNeP7B4NrLlnTP6g== X-Received: by 2002:ad4:44a9:: with SMTP id n9mr530985qvt.60.1617145523527; Tue, 30 Mar 2021 16:05:23 -0700 (PDT) Received: from localhost.localdomain (109-252-193-98.dynamic.spd-mgts.ru. [109.252.193.98]) by smtp.gmail.com with ESMTPSA id 10sm160061qkc.83.2021.03.30.16.05.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Mar 2021 16:05:23 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , Rob Herring Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 4/6] dt-bindings: memory: tegra20: mc: Convert to schema Date: Wed, 31 Mar 2021 02:04:43 +0300 Message-Id: <20210330230445.26619-5-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210330230445.26619-1-digetx@gmail.com> References: <20210330230445.26619-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Tegra20 Memory Controller binding to schema. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring --- .../memory-controllers/nvidia,tegra20-mc.txt | 40 ---------- .../memory-controllers/nvidia,tegra20-mc.yaml | 79 +++++++++++++++++++ 2 files changed, 79 insertions(+), 40 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt deleted file mode 100644 index 739b7c6f2e26..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt +++ /dev/null @@ -1,40 +0,0 @@ -NVIDIA Tegra20 MC(Memory Controller) - -Required properties: -- compatible : "nvidia,tegra20-mc-gart" -- reg : Should contain 2 register ranges: physical base address and length of - the controller's registers and the GART aperture respectively. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - mc: the module's clock input -- interrupts : Should contain MC General interrupt. -- #reset-cells : Should be 1. This cell represents memory client module ID. - The assignments may be found in header file - or in the TRM documentation. -- #iommu-cells: Should be 0. This cell represents the number of cells in an - IOMMU specifier needed to encode an address. GART supports only a single - address space that is shared by all devices, therefore no additional - information needed for the address encoding. -- #interconnect-cells : Should be 1. This cell represents memory client. - The assignments may be found in header file . - -Example: - mc: memory-controller@7000f000 { - compatible = "nvidia,tegra20-mc-gart"; - reg = <0x7000f000 0x400 /* controller registers */ - 0x58000000 0x02000000>; /* GART aperture */ - clocks = <&tegra_car TEGRA20_CLK_MC>; - clock-names = "mc"; - interrupts = ; - #reset-cells = <1>; - #iommu-cells = <0>; - #interconnect-cells = <1>; - }; - - video-codec@6001a000 { - compatible = "nvidia,tegra20-vde"; - ... - resets = <&mc TEGRA20_MC_RESET_VDE>; - iommus = <&mc>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml new file mode 100644 index 000000000000..55caf6905399 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 SoC Memory Controller + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +description: | + The Tegra20 Memory Controller merges request streams from various client + interfaces into request stream(s) for the various memory target devices, + and returns response data to the various clients. The Memory Controller + has a configurable arbitration algorithm to allow the user to fine-tune + performance among the various clients. + + Tegra20 Memory Controller includes the GART (Graphics Address Relocation + Table) which allows Memory Controller to provide a linear view of a + fragmented memory pages. + +properties: + compatible: + const: nvidia,tegra20-mc-gart + + reg: + items: + - description: controller registers + - description: GART registers + + clocks: + maxItems: 1 + + clock-names: + items: + - const: mc + + interrupts: + maxItems: 1 + + "#reset-cells": + const: 1 + + "#iommu-cells": + const: 0 + + "#interconnect-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#reset-cells" + - "#iommu-cells" + - "#interconnect-cells" + +additionalProperties: false + +examples: + - | + memory-controller@7000f000 { + compatible = "nvidia,tegra20-mc-gart"; + reg = <0x7000f000 0x400>, /* Controller registers */ + <0x58000000 0x02000000>; /* GART aperture */ + clocks = <&clock_controller 32>; + clock-names = "mc"; + + interrupts = <0 77 4>; + + #iommu-cells = <0>; + #reset-cells = <1>; + #interconnect-cells = <1>; + }; From patchwork Tue Mar 30 23:04:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 413072 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 510D8C433EC for ; Tue, 30 Mar 2021 23:06:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2BB07619D3 for ; Tue, 30 Mar 2021 23:06:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233167AbhC3XFc (ORCPT ); Tue, 30 Mar 2021 19:05:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233111AbhC3XF0 (ORCPT ); Tue, 30 Mar 2021 19:05:26 -0400 Received: from mail-qk1-x72f.google.com (mail-qk1-x72f.google.com [IPv6:2607:f8b0:4864:20::72f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D78EC061574; Tue, 30 Mar 2021 16:05:26 -0700 (PDT) Received: by mail-qk1-x72f.google.com with SMTP id x14so17594079qki.10; Tue, 30 Mar 2021 16:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5K8PCF7MYaBtFzeoqNgbQi81SsoCGPlROI9MnNWlo4w=; b=qh5i7C7q5RL3UPw0bnN6NL1AgcepeZmqMReDaUIKwTd22vnUurv56k7xGBsgAYSbm+ GbuEKB4M4zFURg51GzhHakYkZ3ur68+6k3z3aBMI4bW5SWRnRe2dclZd2CWYlzmCWGmm F8mbCKkBs8EN1qKyNj0hG1AwAAvtoWfUSEnKn085n/GQiWkZo51F+uLykqM5VNJg83Cq iuOXBB4x3UDESAcAUB9nd4+/Ug9ijiVYKkaP7Sm9hJRDSAnDsqJ596KNYvxm4AoCgBiy jE2kvXm6H7rEaMlHiFr+jrja+VI0GSNirA6Z2yk2JkoWs5D3dKB1c3Tm2wjYVxnTCkpP ZSUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5K8PCF7MYaBtFzeoqNgbQi81SsoCGPlROI9MnNWlo4w=; b=b1tdcPPlPnPdojrHL+rw54HDiqB1YmbiGA4Jtj/tKBtNhY7RhCld6UWb9gSA+VNC0y TdVSsMMds9S9OrkXsBHkDhEzf8LwVR3W2gY/mHXbU9pUBwIbtV8QThrLyW9FNy6TsLY3 yEt/hZBJ70Zg3gtdtDK+R+mI1ZFmyljGYGgmngXv32znM1Rig1v+MKzjwvOvUtZs36xD DeVLHeCtvQBUItgtn2W/GzoZPLiARjHhN2w2aY2RDqzBK6bb3X/NeFuBgKzPhS6ZsvTT 67shPTQeNZ8BurpIyikKpry6sX6KE3njMWPg1bmWDni3syvdZzpDiLGWT7pa6XBBiJeG PxzQ== X-Gm-Message-State: AOAM530/wosl0hMvPkI/jzEtKvN7+AE2ItnFRNH0NT+Ci3Z0HFgAMcbj xynR9DlR/K6XJWQD6LXbTYkeLUewclk= X-Google-Smtp-Source: ABdhPJzVR0NQwkihfW7JXUj+TPFj9c+Mr5f6K/e4I6HiyM0AluJi9Wd1/k1tAuH/YKpGSdZuyH/nZg== X-Received: by 2002:a05:620a:24cc:: with SMTP id m12mr611996qkn.496.1617145525578; Tue, 30 Mar 2021 16:05:25 -0700 (PDT) Received: from localhost.localdomain (109-252-193-98.dynamic.spd-mgts.ru. [109.252.193.98]) by smtp.gmail.com with ESMTPSA id 10sm160061qkc.83.2021.03.30.16.05.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Mar 2021 16:05:25 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , Rob Herring Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 5/6] dt-bindings: memory: tegra20: emc: Convert to schema Date: Wed, 31 Mar 2021 02:04:44 +0300 Message-Id: <20210330230445.26619-6-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210330230445.26619-1-digetx@gmail.com> References: <20210330230445.26619-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Tegra20 External Memory Controller binding to schema. Signed-off-by: Dmitry Osipenko --- .../memory-controllers/nvidia,tegra20-emc.txt | 130 -------- .../nvidia,tegra20-emc.yaml | 294 ++++++++++++++++++ 2 files changed, 294 insertions(+), 130 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt deleted file mode 100644 index d2250498c36d..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ /dev/null @@ -1,130 +0,0 @@ -Embedded Memory Controller - -Properties: -- name : Should be emc -- #address-cells : Should be 1 -- #size-cells : Should be 0 -- compatible : Should contain "nvidia,tegra20-emc". -- reg : Offset and length of the register set for the device -- nvidia,use-ram-code : If present, the sub-nodes will be addressed - and chosen using the ramcode board selector. If omitted, only one - set of tables can be present and said tables will be used - irrespective of ram-code configuration. -- interrupts : Should contain EMC General interrupt. -- clocks : Should contain EMC clock. -- nvidia,memory-controller : Phandle of the Memory Controller node. -- #interconnect-cells : Should be 0. -- operating-points-v2: See ../bindings/opp/opp.txt for details. - -For each opp entry in 'operating-points-v2' table: -- opp-supported-hw: One bitfield indicating SoC process ID mask - - A bitwise AND is performed against this value and if any bit - matches, the OPP gets enabled. - -Optional properties: -- power-domains: Phandle of the SoC "core" power domain. - -Child device nodes describe the memory settings for different configurations and clock rates. - -Example: - - opp_table: opp-table { - compatible = "operating-points-v2"; - - opp@36000000 { - opp-microvolt = <950000 950000 1300000>; - opp-hz = /bits/ 64 <36000000>; - }; - ... - }; - - memory-controller@7000f400 { - #address-cells = < 1 >; - #size-cells = < 0 >; - #interconnect-cells = <0>; - compatible = "nvidia,tegra20-emc"; - reg = <0x7000f400 0x400>; - interrupts = <0 78 0x04>; - clocks = <&tegra_car TEGRA20_CLK_EMC>; - nvidia,memory-controller = <&mc>; - power-domains = <&domain>; - operating-points-v2 = <&opp_table>; - } - - -Embedded Memory Controller ram-code table - -If the emc node has the nvidia,use-ram-code property present, then the -next level of nodes below the emc table are used to specify which settings -apply for which ram-code settings. - -If the emc node lacks the nvidia,use-ram-code property, this level is omitted -and the tables are stored directly under the emc node (see below). - -Properties: - -- name : Should be emc-tables -- nvidia,ram-code : the binary representation of the ram-code board strappings - for which this node (and children) are valid. - - - -Embedded Memory Controller configuration table - -This is a table containing the EMC register settings for the various -operating speeds of the memory controller. They are always located as -subnodes of the emc controller node. - -There are two ways of specifying which tables to use: - -* The simplest is if there is just one set of tables in the device tree, - and they will always be used (based on which frequency is used). - This is the preferred method, especially when firmware can fill in - this information based on the specific system information and just - pass it on to the kernel. - -* The slightly more complex one is when more than one memory configuration - might exist on the system. The Tegra20 platform handles this during - early boot by selecting one out of possible 4 memory settings based - on a 2-pin "ram code" bootstrap setting on the board. The values of - these strappings can be read through a register in the SoC, and thus - used to select which tables to use. - -Properties: -- name : Should be emc-table -- compatible : Should contain "nvidia,tegra20-emc-table". -- reg : either an opaque enumerator to tell different tables apart, or - the valid frequency for which the table should be used (in kHz). -- clock-frequency : the clock frequency for the EMC at which this - table should be used (in kHz). -- nvidia,emc-registers : a 46 word array of EMC registers to be programmed - for operation at the 'clock-frequency' setting. - The order and contents of the registers are: - RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, - WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, - PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, - TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, - ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, - ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, - CFG_CLKTRIM_1, CFG_CLKTRIM_2 - - emc-table@166000 { - reg = <166000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 166000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; - - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 333000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml new file mode 100644 index 000000000000..f25264cd9217 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml @@ -0,0 +1,294 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 SoC External Memory Controller + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +description: | + The External Memory Controller (EMC) interfaces with the off-chip SDRAM to + service the request stream sent from Memory Controller. The EMC also has + various performance-affecting settings beyond the obvious SDRAM configuration + parameters and initialization settings. Tegra20 EMC supports multiple JEDEC + standard protocols: DDR1, LPDDR2 and DDR2. + +properties: + compatible: + const: nvidia,tegra20-emc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#interconnect-cells": + const: 0 + + nvidia,memory-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of the Memory Controller node. + + power-domains: + maxItems: 1 + description: + Phandle of the SoC "core" power domain. + + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, which + is a bitfield indicating SoC process ID mask. + + nvidia,use-ram-code: + type: boolean + description: + If present, the emc-tables@ sub-nodes will be addressed. + +patternProperties: + "^emc-table@[0-9]+$": + type: object + properties: + compatible: + const: nvidia,tegra20-emc-table + + clock-frequency: + description: + Memory clock rate in kHz. + minimum: 1000 + maximum: 900000 + + reg: + maxItems: 1 + description: + Either an opaque enumerator to tell different tables apart, or + the valid frequency for which the table should be used (in kHz). + + nvidia,emc-registers: + description: + EMC timing characterization data. These are the registers + (see section "15.4.1 EMC Registers" in the TRM) whose values + need to be specified, according to the board documentation. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: EMC_RC + - description: EMC_RFC + - description: EMC_RAS + - description: EMC_RP + - description: EMC_R2W + - description: EMC_W2R + - description: EMC_R2P + - description: EMC_W2P + - description: EMC_RD_RCD + - description: EMC_WR_RCD + - description: EMC_RRD + - description: EMC_REXT + - description: EMC_WDV + - description: EMC_QUSE + - description: EMC_QRST + - description: EMC_QSAFE + - description: EMC_RDV + - description: EMC_REFRESH + - description: EMC_BURST_REFRESH_NUM + - description: EMC_PDEX2WR + - description: EMC_PDEX2RD + - description: EMC_PCHG2PDEN + - description: EMC_ACT2PDEN + - description: EMC_AR2PDEN + - description: EMC_RW2PDEN + - description: EMC_TXSR + - description: EMC_TCKE + - description: EMC_TFAW + - description: EMC_TRPAB + - description: EMC_TCLKSTABLE + - description: EMC_TCLKSTOP + - description: EMC_TREFBW + - description: EMC_QUSE_EXTRA + - description: EMC_FBIO_CFG6 + - description: EMC_ODT_WRITE + - description: EMC_ODT_READ + - description: EMC_FBIO_CFG5 + - description: EMC_CFG_DIG_DLL + - description: EMC_DLL_XFORM_DQS + - description: EMC_DLL_XFORM_QUSE + - description: EMC_ZCAL_REF_CNT + - description: EMC_ZCAL_WAIT_CNT + - description: EMC_AUTO_CAL_INTERVAL + - description: EMC_CFG_CLKTRIM_0 + - description: EMC_CFG_CLKTRIM_1 + - description: EMC_CFG_CLKTRIM_2 + + required: + - clock-frequency + - compatible + - reg + - nvidia,emc-registers + + additionalProperties: false + + "^emc-tables@[a-z0-9-]+$": + type: object + properties: + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Value of RAM_CODE this timing set is used for. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^emc-table@[0-9]+$": + type: object + properties: + compatible: + const: nvidia,tegra20-emc-table + + clock-frequency: + description: + Memory clock rate in kHz. + minimum: 1000 + maximum: 900000 + + reg: + maxItems: 1 + description: + Either an opaque enumerator to tell different tables apart, or + the valid frequency for which the table should be used (in kHz). + + nvidia,emc-registers: + description: + EMC timing characterization data. These are the registers + (see section "15.4.1 EMC Registers" in the TRM) whose values + need to be specified, according to the board documentation. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: EMC_RC + - description: EMC_RFC + - description: EMC_RAS + - description: EMC_RP + - description: EMC_R2W + - description: EMC_W2R + - description: EMC_R2P + - description: EMC_W2P + - description: EMC_RD_RCD + - description: EMC_WR_RCD + - description: EMC_RRD + - description: EMC_REXT + - description: EMC_WDV + - description: EMC_QUSE + - description: EMC_QRST + - description: EMC_QSAFE + - description: EMC_RDV + - description: EMC_REFRESH + - description: EMC_BURST_REFRESH_NUM + - description: EMC_PDEX2WR + - description: EMC_PDEX2RD + - description: EMC_PCHG2PDEN + - description: EMC_ACT2PDEN + - description: EMC_AR2PDEN + - description: EMC_RW2PDEN + - description: EMC_TXSR + - description: EMC_TCKE + - description: EMC_TFAW + - description: EMC_TRPAB + - description: EMC_TCLKSTABLE + - description: EMC_TCLKSTOP + - description: EMC_TREFBW + - description: EMC_QUSE_EXTRA + - description: EMC_FBIO_CFG6 + - description: EMC_ODT_WRITE + - description: EMC_ODT_READ + - description: EMC_FBIO_CFG5 + - description: EMC_CFG_DIG_DLL + - description: EMC_DLL_XFORM_DQS + - description: EMC_DLL_XFORM_QUSE + - description: EMC_ZCAL_REF_CNT + - description: EMC_ZCAL_WAIT_CNT + - description: EMC_AUTO_CAL_INTERVAL + - description: EMC_CFG_CLKTRIM_0 + - description: EMC_CFG_CLKTRIM_1 + - description: EMC_CFG_CLKTRIM_2 + + required: + - clock-frequency + - compatible + - reg + - nvidia,emc-registers + + additionalProperties: false + + required: + - nvidia,ram-code + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - nvidia,memory-controller + - "#interconnect-cells" + - operating-points-v2 + +additionalProperties: false + +examples: + - | + external-memory-controller@7000f400 { + compatible = "nvidia,tegra20-emc"; + reg = <0x7000f400 0x400>; + interrupts = <0 78 4>; + clocks = <&clock_controller 57>; + + nvidia,memory-controller = <&mc>; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; + + #interconnect-cells = <0>; + + nvidia,use-ram-code; + + emc-tables@0 { + nvidia,ram-code = <0>; + #address-cells = <1>; + #size-cells = <0>; + + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <333000>; + nvidia,emc-registers = <0x00000018 0x00000033 + 0x00000012 0x00000004 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000bff + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xf0440303 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; 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[109.252.193.98]) by smtp.gmail.com with ESMTPSA id 10sm160061qkc.83.2021.03.30.16.05.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Mar 2021 16:05:27 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , Rob Herring Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 6/6] memory: tegra: Print out info-level once per driver probe Date: Wed, 31 Mar 2021 02:04:45 +0300 Message-Id: <20210330230445.26619-7-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210330230445.26619-1-digetx@gmail.com> References: <20210330230445.26619-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Probing of EMC drivers may be deferred and in this case we get duplicated info messages during kernel boot. Use dev_info_once() helper to silence the duplicated messages. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra124-emc.c | 12 ++++++------ drivers/memory/tegra/tegra20-emc.c | 20 ++++++++++---------- drivers/memory/tegra/tegra30-emc.c | 18 +++++++++--------- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index 874e1a0f23cd..5699d909abc2 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -905,7 +905,7 @@ static int emc_init(struct tegra_emc *emc) else emc->dram_bus_width = 32; - dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); + dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK; emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; @@ -1419,8 +1419,8 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc) goto put_hw_table; } - dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", - hw_version, clk_get_rate(emc->clk) / 1000000); + dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", + hw_version, clk_get_rate(emc->clk) / 1000000); /* first dummy rate-set initializes voltage state */ err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); @@ -1475,9 +1475,9 @@ static int tegra_emc_probe(struct platform_device *pdev) if (err) return err; } else { - dev_info(&pdev->dev, - "no memory timings for RAM code %u found in DT\n", - ram_code); + dev_info_once(&pdev->dev, + "no memory timings for RAM code %u found in DT\n", + ram_code); } err = emc_init(emc); diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index d653a6be8d7f..da8a0da8da79 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -411,12 +411,12 @@ static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, NULL); - dev_info(emc->dev, - "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", - emc->num_timings, - tegra_read_ram_code(), - emc->timings[0].rate / 1000000, - emc->timings[emc->num_timings - 1].rate / 1000000); + dev_info_once(emc->dev, + "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", + emc->num_timings, + tegra_read_ram_code(), + emc->timings[0].rate / 1000000, + emc->timings[emc->num_timings - 1].rate / 1000000); return 0; } @@ -429,7 +429,7 @@ tegra_emc_find_node_by_ram_code(struct device *dev) int err; if (of_get_child_count(dev->of_node) == 0) { - dev_info(dev, "device-tree doesn't have memory timings\n"); + dev_info_once(dev, "device-tree doesn't have memory timings\n"); return NULL; } @@ -496,7 +496,7 @@ static int emc_setup_hw(struct tegra_emc *emc) else emc->dram_bus_width = 32; - dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); + dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); return 0; } @@ -931,8 +931,8 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc) goto put_hw_table; } - dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", - hw_version, clk_get_rate(emc->clk) / 1000000); + dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", + hw_version, clk_get_rate(emc->clk) / 1000000); /* first dummy rate-set initializes voltage state */ err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 6985da0ffb35..829f6d673c96 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -998,12 +998,12 @@ static int emc_load_timings_from_dt(struct tegra_emc *emc, if (err) return err; - dev_info(emc->dev, - "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", - emc->num_timings, - tegra_read_ram_code(), - emc->timings[0].rate / 1000000, - emc->timings[emc->num_timings - 1].rate / 1000000); + dev_info_once(emc->dev, + "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", + emc->num_timings, + tegra_read_ram_code(), + emc->timings[0].rate / 1000000, + emc->timings[emc->num_timings - 1].rate / 1000000); return 0; } @@ -1015,7 +1015,7 @@ static struct device_node *emc_find_node_by_ram_code(struct device *dev) int err; if (of_get_child_count(dev->of_node) == 0) { - dev_info(dev, "device-tree doesn't have memory timings\n"); + dev_info_once(dev, "device-tree doesn't have memory timings\n"); return NULL; } @@ -1503,8 +1503,8 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc) goto put_hw_table; } - dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", - hw_version, clk_get_rate(emc->clk) / 1000000); + dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", + hw_version, clk_get_rate(emc->clk) / 1000000); /* first dummy rate-set initializes voltage state */ err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));