From patchwork Mon Mar 29 16:42:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 411090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16E3AC433DB for ; Mon, 29 Mar 2021 16:47:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DAB5761985 for ; Mon, 29 Mar 2021 16:47:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231197AbhC2Qr1 (ORCPT ); Mon, 29 Mar 2021 12:47:27 -0400 Received: from smtp-17.italiaonline.it ([213.209.10.17]:38095 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229479AbhC2QrT (ORCPT ); Mon, 29 Mar 2021 12:47:19 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id Quy8lKyqctpGHQuyHliOlE; Mon, 29 Mar 2021 18:42:33 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1617036153; bh=urzH31Z57u5IKC1xQOvu0WiSuxDteA7bOWqFQMrqKOk=; h=From; b=Xj+svwGxLf6g9Wmp//oITka6x+fqjD//DD6WNz27vXHXoRxYVubRYmEHiwJXYWF2a CHMkTnRZgitjv6hJKOASLvM1IRrFapywk20GR1WrixGxqV40h8SPyhyyQp7ccN96gl WYsPFYm97mdkRhJ7oneJHaqW+KusMf9s6UF/42o1x03aMFGnaRiMp+7PLXTwIYeVwy 6hjctYa99qC5ULF6O3ZH7D9umyBNmKDPgZVDmGVtBHpynl8E5SnjZ40Nz7AATlpYI4 e7hzEGooJ5ZN8kNfD6ZHDmtha45c2hbAKGTIj5EwrltbPBf1/tvWcJhWvHH4lgciTt JOqBdtSuf+PXw== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=60620379 cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=Bl6OLPU8nqzXNm5YYFQA:9 a=fCgQI5UlmZDRPDxm0A3o:22 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Grygorii Strashko , Dario Binacchi , Lee Jones , Michael Turquette , Stephen Boyd , Tero Kristo , linux-clk@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v3 1/4] clk: ti: fix typo in routine description Date: Mon, 29 Mar 2021 18:42:18 +0200 Message-Id: <20210329164222.26794-2-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329164222.26794-1-dariobin@libero.it> References: <20210329164222.26794-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfIn27ZCUTmtRp+5x956SWoq43721p+yw9pLk/daDddlqNQ/gz0EePul9ixgUr+xfaol7JtaGqlt16lM+6lUrob04UJPZ1187PdtRMIG9GhvLriHyJWcj vOaA0ECpRQE5zy06Uo1ctYjWpibCahNpI1C177MEuGwHbSKCtevpGCrTWgRyVseut/qj3exhiKZw2hBE1asjHiOVWNUHedEhy5jhSs8izY5iB4KLsDO9h3OG ue5MMUZc/DumTwSF+bXVeKV0XBwocM0+V3iPt5AFOD6Um1aA+1xFYRv0VGyiIGrDX1KUHglBz1uCM6rirRIgj8KpUV6hT6u8GmZt3ywzvn1Pm7wHNJfbOna4 hE/k8zd3Dmkb8fdS0wQ2ZGkKotm8S0YmL2+8ZCbFe4L+PVc9rBi340nntOPrBcHxbpsXT8368waw+ORBHG0QEPAtxYip1AkYLM40OxgyZ1RIZ+UvKE1dMEQr GcXcShJSEu0hzq8n/VsuDOPeQKW4dZYelICsGg== Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Replace _omap3_noncore_dpll_program with omap3_noncore_dpll_program. Signed-off-by: Dario Binacchi Reviewed-by: Stephen Boyd --- (no changes since v1) drivers/clk/ti/dpll3xxx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c index 6097b099a5df..94d5b5fe9a2b 100644 --- a/drivers/clk/ti/dpll3xxx.c +++ b/drivers/clk/ti/dpll3xxx.c @@ -292,7 +292,7 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) } /** - * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly + * omap3_noncore_dpll_program - set non-core DPLL M,N values directly * @clk: struct clk * of DPLL to set * @freqsel: FREQSEL value to set * From patchwork Mon Mar 29 16:42:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 411089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5F9EC433E5 for ; Mon, 29 Mar 2021 16:51:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A315B6198E for ; Mon, 29 Mar 2021 16:51:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230495AbhC2QvN (ORCPT ); Mon, 29 Mar 2021 12:51:13 -0400 Received: from smtp-17-i2.italiaonline.it ([213.209.12.17]:51490 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230323AbhC2Qup (ORCPT ); Mon, 29 Mar 2021 12:50:45 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id Quy8lKyqctpGHQuyIliOli; Mon, 29 Mar 2021 18:42:34 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1617036154; bh=CrKShqEBNERCGbMjDPhba4sclJ+Oc3QI/7X+s8tPzg8=; h=From; b=DL6HiJxE/Kw4hwO+ZJSbUxNXrze1Oa6v35dm8Jvvi82zv5Z1glA7Z7eXk9awrkSf7 8xFsn3CC96XicAPm1732eUJCAb7C5Fa7bInWSL7tM8Fsmu+CuYUcQs8oGEIiCZch1M yDOReAV0a67vyZR+6HA4eBx1ya2MM+QmZffBjHBpSnvUqCezbLyO9pKEBejSVEEaTJ 8Wd3T0qY7YXwkycYWKMgZLC81hvTS46LNT0CSN55/8tsVzpnAtu7LNKMq7zQQKxoMK 2vAO9ZVegx24GqYPEx3LTwjRxDh9gOcWxMux+r01lY+Ja06ihBbNSUmhwdob4CSCV1 SBA3oCBkvP7iw== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6062037a cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=2KMo9-giAAAA:8 a=jCmRPZ0w5czJu0AXxT0A:9 a=2pGyGSWy5nf2n_rBi4rp:22 a=UeCTMeHK7YUBiLmz_SX7:22 a=fCgQI5UlmZDRPDxm0A3o:22 a=pHzHmUro8NiASowvMSCR:22 a=xoEH_sTeL_Rfw54TyV31:22 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Grygorii Strashko , Dario Binacchi , =?utf-8?q?Beno=C3=AEt_Cousson?= , Rob Herring , Tony Lindgren , devicetree@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v3 3/4] ARM: dts: am33xx-clocks: add spread spectrum support Date: Mon, 29 Mar 2021 18:42:20 +0200 Message-Id: <20210329164222.26794-4-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329164222.26794-1-dariobin@libero.it> References: <20210329164222.26794-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfOR5sfuN7CDFFUQ88TsfF0HHMJBZaMkZQKbATvMx0SfTeVaDp7fVsaCecIeyLBX8/d+G1bstcZDBADy2NQJIrQIptnGEweg1OqaE4mJjica+kR8FyFLb /AmZxcJHouBpWLUiZ5mUizeJOATj8KKHjfr3K3UHGLz2FiulZO3rJmbARCXty3Gx0Hq1EGoK23EhhXdjWuKubVdCF3PL4Z2h+up08N3uSNzotfvXWbN1YsYB Yv2DyW6geKfO8IwFL/eaAd4EnZ057kJzisqZkqLMT5iETMhWynGAA3Gc5gzvimZwki9mtYbCZ+M+CUf+CiaSj0x8tYzp22TmK7NvBiPWJ2Mmj7DZf20JOVAd LLltkryBzP/gagF2hI4j/Rn3KgO00TkkcbkTT0y4P5DIfBcbgg1yZqVFrRWbH/pet6mc1mtn15g7Y6PMyu8SEkVeD9zrtJGtwtSgQ+FfPl++ixbeWo2YFSCI padWBKiLpifWKLGw Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Registers for adjusting the spread spectrum clocking (SSC) have been added. As reported by the TI spruh73x RM, SSC is supported only for LCD and MPU PLLs. Signed-off-by: Dario Binacchi Acked-by: Tony Lindgren --- Changes in v3: - Add Tony Lindgren acked tag. Changes in v2: - Remove SSC registers from dpll_core_ck@490 node (SSC is not supported) - Add SSC registers to dpll_mpu_ck@488 node. arch/arm/boot/dts/am33xx-clocks.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index dced92a8970e..a02e0b1229a4 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -204,7 +204,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0488>, <0x0420>, <0x042c>; + reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { @@ -244,7 +244,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0498>, <0x0448>, <0x0454>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; }; dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {