From patchwork Mon Mar 29 01:59:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 411088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD001C433E3 for ; Mon, 29 Mar 2021 02:00:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9A1D561958 for ; Mon, 29 Mar 2021 02:00:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230331AbhC2CAL (ORCPT ); Sun, 28 Mar 2021 22:00:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230303AbhC2B7r (ORCPT ); Sun, 28 Mar 2021 21:59:47 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75F2CC061764 for ; Sun, 28 Mar 2021 18:59:47 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id h20so3663580plr.4 for ; Sun, 28 Mar 2021 18:59:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lEonPZwEeXmihKSqYcFtnrjNQ7/tLKbXJpP3Rx+HiqM=; b=F23cGbG1YwLdAFMDZO0iYBH+K1d7cy6+GJAoRwQhgiDV6iW+BNyqo+iYPnqYQUOTQ2 tfj14BHwgnjBcjAQ4cw70MDvX88g+74TtcbfnNSE+dyubGZEY+Uf9+OMpM5R1TQYzDi8 uFK/zUUDomBnWEtnEY4WbAGVHyJRfqhlCZAN0J/KVj/k9maJlzhNu3wYCgVktMOYlNfx E8fzVcfAWuVzW2WYuSS3BbED01DkDpLjNgmR5M/vzla9E7bH2jTv1P3BrbweArvDM/W3 TOfzt356v3DpyQ1NRMnJ7svnGW10AIZL4dWAxPjngFvx7atofvsiD74RveOKU/3QbU86 RDeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lEonPZwEeXmihKSqYcFtnrjNQ7/tLKbXJpP3Rx+HiqM=; b=PRz67EC4jHkSfvhI0qdvz0Z0W85tb7WeUL8ru8v7yfxL8UrpqnHLikCZqRVVHE/lPI 7L1aFyMBLQ1YQlOau3HNuSI0iQhNkpN2oBZW5i4jU2S9sUee7Gn36OcuNNhNyQ1Ky4WP /ZCUFzf6r7fRljOadopejaaQM9KYaYpaYzFVIxHbpZbe4cIZ2f2L3deglszXOX70PpxA o/GYyHZCRf+6aOqimWFsXtvMRXut8SiIlTYKTq+WIJW6sIkJS4WBYZfcq4BCc2YJ+Rsl d+vnwik76CUFqKBEfxPs15G2Sxai9HZdQpENf7+FF5zBXYIn53pXeG7Y5Bps1xmFIMu1 gqew== X-Gm-Message-State: AOAM531wDncc6fGbKqEPwqJq24TR1aFKUkMe8tLAtQ3/kV4iCdVCRqvC e4B135Pjr7MIYp6l8o5ShrHqkA== X-Google-Smtp-Source: ABdhPJxcWKYSx3w7OxCzzLFtQDbCo5dvZARVQLq0d3ra/WqqivMK3AukxhkoGQW2jbtlRAqfLkfLrw== X-Received: by 2002:a17:902:7792:b029:e6:caba:f836 with SMTP id o18-20020a1709027792b02900e6cabaf836mr26264364pll.41.1616983186960; Sun, 28 Mar 2021 18:59:46 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id w37sm14728027pgl.13.2021.03.28.18.59.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Mar 2021 18:59:46 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, brad@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 01/13] gpio: Add Elba SoC gpio driver for spi cs control Date: Sun, 28 Mar 2021 18:59:26 -0700 Message-Id: <20210329015938.20316-2-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329015938.20316-1-brad@pensando.io> References: <20210329015938.20316-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This GPIO driver is for the Pensando Elba SoC which provides control of four chip selects on two SPI busses. Signed-off-by: Brad Larson --- drivers/gpio/Kconfig | 6 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-elba-spics.c | 114 +++++++++++++++++++++++++++++++++ 3 files changed, 121 insertions(+) create mode 100644 drivers/gpio/gpio-elba-spics.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e3607ec4c2e8..4720459b24f5 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -241,6 +241,12 @@ config GPIO_EIC_SPRD help Say yes here to support Spreadtrum EIC device. +config GPIO_ELBA_SPICS + bool "Pensando Elba SPI chip-select" + depends on (ARCH_PENSANDO_ELBA_SOC || COMPILE_TEST) + help + Say yes here to support the Penasndo Elba SoC SPI chip-select driver + config GPIO_EM tristate "Emma Mobile GPIO" depends on (ARCH_EMEV2 || COMPILE_TEST) && OF_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c58a90a3c3b1..c5c7acad371b 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o +obj-$(CONFIG_GPIO_ELBA_SPICS) += gpio-elba-spics.o obj-$(CONFIG_GPIO_EM) += gpio-em.o obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o diff --git a/drivers/gpio/gpio-elba-spics.c b/drivers/gpio/gpio-elba-spics.c new file mode 100644 index 000000000000..351bbaeea033 --- /dev/null +++ b/drivers/gpio/gpio-elba-spics.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pensando Elba SoC SPI chip select driver + * + * Copyright (c) 2020-2021, Pensando Systems Inc. + */ + +#include +#include +#include +#include +#include +//#include +#include +#include +#include + +/* + * pin: 3 2 | 1 0 + * bit: 7------6------5------4----|---3------2------1------0 + * cs1 cs1_ovr cs0 cs0_ovr | cs1 cs1_ovr cs0 cs0_ovr + * ssi1 | ssi0 + */ +#define SPICS_PIN_SHIFT(pin) (2 * (pin)) +#define SPICS_MASK(pin) (0x3 << SPICS_PIN_SHIFT(pin)) +#define SPICS_SET(pin, val) ((((val) << 1) | 0x1) << SPICS_PIN_SHIFT(pin)) + +struct elba_spics_priv { + void __iomem *base; + spinlock_t lock; + struct gpio_chip chip; +}; + +static int elba_spics_get_value(struct gpio_chip *chip, unsigned int pin) +{ + return -ENOTSUPP; +} + +static void elba_spics_set_value(struct gpio_chip *chip, + unsigned int pin, int value) +{ + struct elba_spics_priv *p = gpiochip_get_data(chip); + unsigned long flags; + u32 tmp; + + /* select chip select from register */ + spin_lock_irqsave(&p->lock, flags); + tmp = readl_relaxed(p->base); + tmp = (tmp & ~SPICS_MASK(pin)) | SPICS_SET(pin, value); + writel_relaxed(tmp, p->base); + spin_unlock_irqrestore(&p->lock, flags); +} + +static int elba_spics_direction_input(struct gpio_chip *chip, unsigned int pin) +{ + return -ENOTSUPP; +} + +static int elba_spics_direction_output(struct gpio_chip *chip, + unsigned int pin, int value) +{ + elba_spics_set_value(chip, pin, value); + return 0; +} + +static int elba_spics_probe(struct platform_device *pdev) +{ + struct elba_spics_priv *p; + struct resource *res; + int ret = 0; + + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); + if (!p) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + p->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(p->base)) + return PTR_ERR(p->base); + spin_lock_init(&p->lock); + platform_set_drvdata(pdev, p); + + p->chip.ngpio = 4; /* 2 cs pins for spi0, and 2 for spi1 */ + p->chip.base = -1; + p->chip.direction_input = elba_spics_direction_input; + p->chip.direction_output = elba_spics_direction_output; + p->chip.get = elba_spics_get_value; + p->chip.set = elba_spics_set_value; + p->chip.label = dev_name(&pdev->dev); + p->chip.parent = &pdev->dev; + p->chip.owner = THIS_MODULE; + + ret = devm_gpiochip_add_data(&pdev->dev, &p->chip, p); + if (ret) + dev_err(&pdev->dev, "unable to add gpio chip\n"); + return ret; +} + +static const struct of_device_id elba_spics_of_match[] = { + { .compatible = "pensando,elba-spics" }, + {} +}; + +static struct platform_driver elba_spics_driver = { + .probe = elba_spics_probe, + .driver = { + .name = "pensando-elba-spics", + .of_match_table = elba_spics_of_match, + }, +}; +module_platform_driver(elba_spics_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Pensando Elba SoC SPI chip-select driver"); From patchwork Mon Mar 29 01:59:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 411087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2627C433EC for ; Mon, 29 Mar 2021 02:00:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AE92561927 for ; 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Sun, 28 Mar 2021 18:59:48 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, brad@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/13] spi: cadence-quadspi: Add QSPI support for Pensando Elba SoC Date: Sun, 28 Mar 2021 18:59:27 -0700 Message-Id: <20210329015938.20316-3-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329015938.20316-1-brad@pensando.io> References: <20210329015938.20316-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add QSPI controller support for Pensando Elba SoC Signed-off-by: Brad Larson --- drivers/spi/spi-cadence-quadspi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 52ddb3255d88..4aacb0b2dbc7 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1353,6 +1353,7 @@ static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) cqspi->rx_chan = dma_request_chan_by_mask(&mask); if (IS_ERR(cqspi->rx_chan)) { int ret = PTR_ERR(cqspi->rx_chan); + cqspi->rx_chan = NULL; return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); } @@ -1633,6 +1634,10 @@ static const struct cqspi_driver_platdata intel_lgm_qspi = { .quirks = CQSPI_DISABLE_DAC_MODE, }; +static const struct cqspi_driver_platdata pen_cdns_qspi = { + .quirks = CQSPI_NEEDS_WR_DELAY | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1650,6 +1655,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,lgm-qspi", .data = &intel_lgm_qspi, }, + { + .compatible = "pensando,cdns-qspi", + .data = &pen_cdns_qspi, + }, { /* end of table */ } }; From patchwork Mon Mar 29 01:59:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 411084 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2115BC4332E for ; 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Sun, 28 Mar 2021 18:59:49 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id w37sm14728027pgl.13.2021.03.28.18.59.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Mar 2021 18:59:49 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, brad@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 03/13] spi: dw: Add support for Pensando Elba SoC SPI Date: Sun, 28 Mar 2021 18:59:28 -0700 Message-Id: <20210329015938.20316-4-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329015938.20316-1-brad@pensando.io> References: <20210329015938.20316-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The Pensando Elba SoC uses a GPIO based chip select for two DW SPI busses with each bus having two chip selects. Signed-off-by: Brad Larson --- drivers/spi/spi-dw-mmio.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 17c06039a74d..c323a5ceecb8 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -56,7 +56,7 @@ struct dw_spi_mscc { /* * The Designware SPI controller (referred to as master in the documentation) * automatically deasserts chip select when the tx fifo is empty. The chip - * selects then needs to be either driven as GPIOs or, for the first 4 using the + * selects then needs to be either driven as GPIOs or, for the first 4 using * the SPI boot controller registers. the final chip select is an OR gate * between the Designware SPI controller and the SPI boot controller. */ @@ -237,6 +237,31 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev, return 0; } +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws = spi_master_get_devdata(spi->master); + + if (!enable) { + /* + * Using a GPIO-based chip-select, the DW SPI + * controller still needs its own CS bit selected + * to start the serial engine. On Elba the specific + * CS doesn't matter to start the serial engine, + * so using CS0. + */ + dw_writel(dws, DW_SPI_SER, BIT(0)); + } else { + dw_writel(dws, DW_SPI_SER, 0); + } +} + +static int dw_spi_elba_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + dwsmmio->dws.set_cs = dw_spi_elba_set_cs; + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -351,6 +376,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible = "pensando,elba-spi", .data = dw_spi_elba_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); From patchwork Mon Mar 29 01:59:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 412120 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E622C433E9 for ; Mon, 29 Mar 2021 02:00:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1C1AB6195E for ; Mon, 29 Mar 2021 02:00:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230385AbhC2CAM (ORCPT ); Sun, 28 Mar 2021 22:00:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230377AbhC2B7v (ORCPT ); Sun, 28 Mar 2021 21:59:51 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BED13C0613B6 for ; Sun, 28 Mar 2021 18:59:51 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id v8so3660497plz.10 for ; Sun, 28 Mar 2021 18:59:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5evIgUHLH3iE2TL4J3188f+WN89LXupcPiWpSn3upRg=; b=mkI2MNoS6Q/el56D1urQ3F/hxkgi9Cc4jGujWEDbWa8KukNyFknpaqsBvLradFPCCh 82Ajpw67gaE153YzbCFi+OZ7H3Y/JMaHNrphjBkXxNEJclXuWsBO0Qw/xBNAf3FMELPL vwNOq6BkK8fRMhkZeUp6pLGT6wsCBweI1AEYLBLoQHMObN4PMcxw+5XAw6BFLi7RR7NR 8WaQ3l00nfuAHdb7GqPsXpyNFWE/ooiXYRksjlFwUKfw07uzx5TNIujOO8DZA20mKAor XhqIQuWMRN58d4Yhdyaisit7OyaUddCcZfH4JFlvCd0DiTwSHzCpqqHtU1E3IRb67s5/ J8/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5evIgUHLH3iE2TL4J3188f+WN89LXupcPiWpSn3upRg=; b=ZqO2p7btkO0njad6nXeg/c3RdvabCRsebisvURY1USJmGGoMwUDaTmp1Fhwd1/+/HC WjL6HbEsrW21xh3JBXNHgczBt2wjyCQr0xkcwq4HWbm0Oj0Mn6gY8Kh/fjsF0uDPOoG+ 1yfr4IHnbpWjBzmpqj76V/7uXV7Eir9iip2i7YhPv8JSS6dRojgv7rQGSMh2C4ZM8Dxa +J4ZQApQsTyYvhXyY2nniAqwjl2cD0eErzNW0POxKV1ehyQ8ZzyJWy8/UK2YKinEA2+k C9ZJPnnq1e/fmp+4y8l1vHjdBcIjikk/oMkZRhUVhc1D1qYq0piDWyTMONUIXxnQW5Qp 2m3Q== X-Gm-Message-State: AOAM530Ecpri+oWqwyrO12dQ+jAQjWrGORPmMaG4tMtCCfwC6WKW2rHM j9l7ufqtZSzhBaH8mhRxw8AEdw== X-Google-Smtp-Source: ABdhPJzWcGlzZINaB0Jap/R7CzqpkSL0r8aRD9sbvqRTrnAhOddv0gNrJo7sUNFfZii8t877KZMCiQ== X-Received: by 2002:a17:90a:77c5:: with SMTP id e5mr6189926pjs.189.1616983191306; Sun, 28 Mar 2021 18:59:51 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id w37sm14728027pgl.13.2021.03.28.18.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Mar 2021 18:59:50 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, brad@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/13] spidev: Add Pensando CPLD compatible Date: Sun, 28 Mar 2021 18:59:29 -0700 Message-Id: <20210329015938.20316-5-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329015938.20316-1-brad@pensando.io> References: <20210329015938.20316-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Pensando Elba SoC platforms have a SPI connected CPLD for platform management. Signed-off-by: Brad Larson --- drivers/spi/spidev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 8cb4d923aeaa..8b285852ce82 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -683,6 +683,7 @@ static const struct of_device_id spidev_dt_ids[] = { { .compatible = "dh,dhcom-board" }, { .compatible = "menlo,m53cpld" }, { .compatible = "cisco,spi-petra" }, + { .compatible = "pensando,cpld" }, {}, }; MODULE_DEVICE_TABLE(of, spidev_dt_ids); From patchwork Mon Mar 29 01:59:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 412119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20E1EC433F4 for ; Mon, 29 Mar 2021 02:00:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F17DA61954 for ; Mon, 29 Mar 2021 02:00:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230394AbhC2CAN (ORCPT ); Sun, 28 Mar 2021 22:00:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230390AbhC2B7x (ORCPT ); Sun, 28 Mar 2021 21:59:53 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C993C0613B6 for ; Sun, 28 Mar 2021 18:59:53 -0700 (PDT) Received: by mail-pf1-x433.google.com with SMTP id v10so3518590pfn.5 for ; Sun, 28 Mar 2021 18:59:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jl5EwsHPoR0E1Cvd52To3G+T9f6JpE7DGjLFM2XS1JA=; b=Xv4YLPj5nGA/bHrmR3TIhqfeIzhXwg/sv7TawubLExWW7lA3+UCK/O54yrMGa2OF1s 4bXOeLt6ZwuUxGxZrJutf0F+QC8slDqcNtYOLVLcD09PtUp8e7+Fkgiz9meTDOln/OAq NmdPxGoU6liA00pa2UjS9lI9r0BmbT1EvVunpGORyikJQzSvL0x5tZjQd0Jsm1ZWsX2A hrik1dfJwKxNKUxhhjknlUFGHd6UiqfdO+qd5nK3tkTV8fLhk4jM/3+1vwNoOciXhbTz cmltyZH5lISz6AnQvdLQ++jG9Naqktyu/qNFcGzDkYsz+yHkoR3XLsKQd7dDc7BL3LeM SqoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jl5EwsHPoR0E1Cvd52To3G+T9f6JpE7DGjLFM2XS1JA=; b=c/iW1F60+scTBIuQfqV8sIHQ4jul+BdmyMmaqa38RFSaZ6axoOTD3WnL6QO2EoFgNE 22AL3wDlfm97+P+Cu2yvh0OtxucLk8rUgsnPTqs2WX+CELu/2TpYfrF9t8y8l4it3FxU qgHN5hv3dmGO+KM0fVUDrKlQxoZhFtU6rQ9s25cHGnBgiOR1E+WOeaE6FV/o2JY/Ys8b Yj8ayN3LGXYds9c0Y/7q3lZPfrie0ruCzrHlyOlBJj1kIe7dyZBjNgHf3y38B1dq+/eZ 5QeJUDbIkOuD171HbMMpP8IcaT8fhITzPsQAUcKsM/IwcLR3DRXNq6/w171FC88L91bO Wf3A== X-Gm-Message-State: AOAM532WKANOS37m6+n6C5LSf5XZ9TNJYDS5GGgNMGr4TLUvlkVtA+ll DHpMlopqBk91vsDCJ7JkU8Mz7g== X-Google-Smtp-Source: ABdhPJyn7KYl7bWQv8li1GpJ0ICUHhxTocoFJqlOMGIlCCg5Yip8rlb6YKWw2lUDchNd4yAVKrFVrw== X-Received: by 2002:a63:eb50:: with SMTP id b16mr21502929pgk.270.1616983192740; Sun, 28 Mar 2021 18:59:52 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id w37sm14728027pgl.13.2021.03.28.18.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Mar 2021 18:59:52 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, brad@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/13] mmc: sdhci-cadence: Add Pensando Elba SoC support Date: Sun, 28 Mar 2021 18:59:30 -0700 Message-Id: <20210329015938.20316-6-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329015938.20316-1-brad@pensando.io> References: <20210329015938.20316-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add support for Pensando Elba SoC which explicitly controls byte-lane enables on writes. Refactor to allow platform specific write ops. Signed-off-by: Brad Larson --- drivers/mmc/host/Kconfig | 15 +++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-cadence-elba.c | 137 ++++++++++++++++++++++++++ drivers/mmc/host/sdhci-cadence.c | 81 ++++++++------- drivers/mmc/host/sdhci-cadence.h | 68 +++++++++++++ 5 files changed, 260 insertions(+), 42 deletions(-) create mode 100644 drivers/mmc/host/sdhci-cadence-elba.c create mode 100644 drivers/mmc/host/sdhci-cadence.h diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index b236dfe2e879..65ea323c06f2 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -250,6 +250,21 @@ config MMC_SDHCI_CADENCE If unsure, say N. +config MMC_SDHCI_CADENCE_ELBA + tristate "SDHCI support for the Pensando/Cadence SD/SDIO/eMMC controller" + depends on ARCH_PENSANDO_ELBA_SOC + depends on MMC_SDHCI + depends on OF + depends on MMC_SDHCI_CADENCE + depends on MMC_SDHCI_PLTFM + select MMC_SDHCI_IO_ACCESSORS + help + This selects the Pensando/Cadence SD/SDIO/eMMC controller. + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_SDHCI_CNS3XXX tristate "SDHCI support on the Cavium Networks CNS3xxx SoC" depends on ARCH_CNS3XXX || COMPILE_TEST diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 6df5c4774260..f2a6d50e64de 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -80,6 +80,7 @@ obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o +obj-$(CONFIG_MMC_SDHCI_CADENCE_ELBA) += sdhci-cadence-elba.o obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF) += sdhci-esdhc-mcf.o obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o diff --git a/drivers/mmc/host/sdhci-cadence-elba.c b/drivers/mmc/host/sdhci-cadence-elba.c new file mode 100644 index 000000000000..ec23f43de407 --- /dev/null +++ b/drivers/mmc/host/sdhci-cadence-elba.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2020 Pensando Systems, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sdhci-pltfm.h" +#include "sdhci-cadence.h" + +// delay regs address +#define SDIO_REG_HRS4 0x10 +#define REG_DELAY_HS 0x00 +#define REG_DELAY_DEFAULT 0x01 +#define REG_DELAY_UHSI_SDR50 0x04 +#define REG_DELAY_UHSI_DDR50 0x05 + +static void elba_write_l(struct sdhci_host *host, u32 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + unsigned long flags; + + spin_lock_irqsave(&priv->wrlock, flags); + writel(0x78, priv->ctl_addr); + writel(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_w(struct sdhci_host *host, u16 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + unsigned long flags; + u32 m = (reg & 0x3); + u32 msk = (0x3 << (m)); + + spin_lock_irqsave(&priv->wrlock, flags); + writel(msk << 3, priv->ctl_addr); + writew(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_b(struct sdhci_host *host, u8 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + unsigned long flags; + u32 m = (reg & 0x3); + u32 msk = (0x1 << (m)); + + spin_lock_irqsave(&priv->wrlock, flags); + writel(msk << 3, priv->ctl_addr); + writeb(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_priv_write_l(struct sdhci_cdns_priv *priv, + u32 val, void __iomem *reg) +{ + unsigned long flags; + + spin_lock_irqsave(&priv->wrlock, flags); + writel(0x78, priv->ctl_addr); + writel(val, reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static const struct sdhci_ops sdhci_elba_ops = { + .write_l = elba_write_l, + .write_w = elba_write_w, + .write_b = elba_write_b, + .set_clock = sdhci_set_clock, + .get_timeout_clock = sdhci_cdns_get_timeout_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, +}; + +static void sd4_set_dlyvr(struct sdhci_host *host, + unsigned char addr, unsigned char data) +{ + unsigned long dlyrv_reg; + + dlyrv_reg = ((unsigned long)data << 8); + dlyrv_reg |= addr; + + // set data and address + writel(dlyrv_reg, host->ioaddr + SDIO_REG_HRS4); + dlyrv_reg |= (1uL << 24uL); + // send write request + writel(dlyrv_reg, host->ioaddr + SDIO_REG_HRS4); + dlyrv_reg &= ~(1uL << 24); + // clear write request + writel(dlyrv_reg, host->ioaddr + SDIO_REG_HRS4); +} + +static void phy_config(struct sdhci_host *host) +{ + sd4_set_dlyvr(host, REG_DELAY_DEFAULT, 0x04); + sd4_set_dlyvr(host, REG_DELAY_HS, 0x04); + sd4_set_dlyvr(host, REG_DELAY_UHSI_SDR50, 0x06); + sd4_set_dlyvr(host, REG_DELAY_UHSI_DDR50, 0x16); +} + +static int elba_drv_init(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + struct resource *iomem; + void __iomem *ioaddr; + + host->mmc->caps |= (MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA); + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!iomem) + return -ENOMEM; + ioaddr = devm_ioremap_resource(&pdev->dev, iomem); + if (IS_ERR(ioaddr)) + return PTR_ERR(ioaddr); + priv->ctl_addr = ioaddr; + priv->priv_write_l = elba_priv_write_l; + spin_lock_init(&priv->wrlock); + writel(0x78, priv->ctl_addr); + phy_config(host); + return 0; +} + +const struct sdhci_cdns_drv_data sdhci_elba_drv_data = { + .init = elba_drv_init, + .pltfm_data = { + .ops = &sdhci_elba_ops, + }, +}; diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 6f2de54a5987..d1ae996c3824 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -14,6 +14,7 @@ #include #include "sdhci-pltfm.h" +#include "sdhci-cadence.h" /* HRS - Host Register Set (specific to Cadence) */ #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ @@ -59,23 +60,6 @@ */ #define SDHCI_CDNS_MAX_TUNING_LOOP 40 -struct sdhci_cdns_phy_param { - u8 addr; - u8 data; -}; - -struct sdhci_cdns_priv { - void __iomem *hrs_addr; - bool enhanced_strobe; - unsigned int nr_phy_params; - struct sdhci_cdns_phy_param phy_params[]; -}; - -struct sdhci_cdns_phy_cfg { - const char *property; - u8 addr; -}; - static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, @@ -104,17 +88,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); - writel(tmp, reg); + sdhci_cdns_priv_writel(priv, tmp, reg); tmp |= SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + sdhci_cdns_priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); if (ret) return ret; tmp &= ~SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + sdhci_cdns_priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), 0, 10); @@ -167,14 +151,7 @@ static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv) return 0; } -static void *sdhci_cdns_priv(struct sdhci_host *host) -{ - struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); - - return sdhci_pltfm_priv(pltfm_host); -} - -static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host) +unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host) { /* * Cadence's spec says the Timeout Clock Frequency is the same as the @@ -191,7 +168,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode) tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); tmp &= ~SDHCI_CDNS_HRS06_MODE; tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); + sdhci_cdns_priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); } static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) @@ -223,7 +200,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) */ for (i = 0; i < 2; i++) { tmp |= SDHCI_CDNS_HRS06_TUNE_UP; - writel(tmp, reg); + sdhci_cdns_priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), @@ -272,10 +249,13 @@ static int sdhci_cdns_execute_tuning(struct sdhci_host *host, u32 opcode) return -EIO; } + dev_info(mmc_dev(host->mmc), "tuning val %d streak end %d max %d\n", + end_of_streak - max_streak / 2, end_of_streak, max_streak); + return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2); } -static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, +void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); @@ -318,13 +298,17 @@ static const struct sdhci_ops sdhci_cdns_ops = { .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, }; -static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = { - .ops = &sdhci_cdns_ops, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { + .pltfm_data = { + .ops = &sdhci_cdns_ops, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, }; -static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { - .ops = &sdhci_cdns_ops, +static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = { + .pltfm_data = { + .ops = &sdhci_cdns_ops, + }, }; static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, @@ -350,7 +334,7 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; - const struct sdhci_pltfm_data *data; + const struct sdhci_cdns_drv_data *data; struct sdhci_pltfm_host *pltfm_host; struct sdhci_cdns_priv *priv; struct clk *clk; @@ -369,10 +353,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev) data = of_device_get_match_data(dev); if (!data) - data = &sdhci_cdns_pltfm_data; + data = &sdhci_cdns_drv_data; nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node); - host = sdhci_pltfm_init(pdev, data, + host = sdhci_pltfm_init(pdev, &data->pltfm_data, struct_size(priv, phy_params, nr_phy_params)); if (IS_ERR(host)) { ret = PTR_ERR(host); @@ -389,11 +373,18 @@ static int sdhci_cdns_probe(struct platform_device *pdev) host->ioaddr += SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe = sdhci_cdns_hs400_enhanced_strobe; - sdhci_enable_v4_mode(host); - __sdhci_read_caps(host, &version, NULL, NULL); sdhci_get_of_property(pdev); + if (data->init) { + ret = data->init(pdev); + if (ret) + goto free; + } + + sdhci_enable_v4_mode(host); + __sdhci_read_caps(host, &version, NULL, NULL); + ret = mmc_of_parse(host->mmc); if (ret) goto free; @@ -453,8 +444,14 @@ static const struct dev_pm_ops sdhci_cdns_pm_ops = { static const struct of_device_id sdhci_cdns_match[] = { { .compatible = "socionext,uniphier-sd4hc", - .data = &sdhci_cdns_uniphier_pltfm_data, + .data = &sdhci_cdns_uniphier_drv_data, }, +#ifdef CONFIG_MMC_SDHCI_CADENCE_ELBA + { + .compatible = "pensando,elba-emmc", + .data = &sdhci_elba_drv_data + }, +#endif { .compatible = "cdns,sd4hc" }, { /* sentinel */ } }; diff --git a/drivers/mmc/host/sdhci-cadence.h b/drivers/mmc/host/sdhci-cadence.h new file mode 100644 index 000000000000..bf48e8d13430 --- /dev/null +++ b/drivers/mmc/host/sdhci-cadence.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + */ + +#ifndef _SDHCI_CADENCE_H_ +#define _SDHCI_CADENCE_H_ + +struct sdhci_cdns_phy_param { + u8 addr; + u8 data; +}; + +struct sdhci_cdns_priv { + void __iomem *hrs_addr; +#ifdef CONFIG_MMC_SDHCI_CADENCE_ELBA + void __iomem *ctl_addr; /* write control */ + spinlock_t wrlock; /* write lock */ +#endif + bool enhanced_strobe; + void (*priv_write_l)(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg); /* for cadence-elba.c */ + unsigned int nr_phy_params; + struct sdhci_cdns_phy_param phy_params[]; +}; + +struct sdhci_cdns_phy_cfg { + const char *property; + u8 addr; +}; + +struct sdhci_cdns_drv_data { + int (*init)(struct platform_device *pdev); + const struct sdhci_pltfm_data pltfm_data; +}; + +static inline void *sdhci_cdns_priv(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + + return sdhci_pltfm_priv(pltfm_host); +} + +/* + * The Pensando Elba SoC explicitly controls byte-lane enables on writes, + * which includes writes to the HRS registers. + * sdhci_cdns_priv_writel() is used in the common sdhci-cadence.c code + * to write HRS registers, and this function dispatches to the specific + * code. + */ +static inline void sdhci_cdns_priv_writel(struct sdhci_cdns_priv *priv, + u32 val, void __iomem *reg) +{ + if (unlikely(priv->priv_write_l)) + priv->priv_write_l(priv, val, reg); + else + writel(val, reg); +} + +#ifdef CONFIG_MMC_SDHCI_CADENCE_ELBA +extern const struct sdhci_cdns_drv_data sdhci_elba_drv_data; +#endif + +unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host); +void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, unsigned int timing); + +#endif From patchwork Mon Mar 29 01:59:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 411086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F004C43445 for ; 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Sun, 28 Mar 2021 18:59:54 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id w37sm14728027pgl.13.2021.03.28.18.59.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Mar 2021 18:59:53 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, brad@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/13] arm64: Add config for Pensando SoC platforms Date: Sun, 28 Mar 2021 18:59:31 -0700 Message-Id: <20210329015938.20316-7-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329015938.20316-1-brad@pensando.io> References: <20210329015938.20316-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add ARCH_PENSANDO configuration option for Pensando SoC based platforms. Signed-off-by: Brad Larson --- arch/arm64/Kconfig.platforms | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index cdfd5fed457f..803e7cf1df55 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -210,6 +210,11 @@ config ARCH_MXC This enables support for the ARMv8 based SoCs in the NXP i.MX family. +config ARCH_PENSANDO + bool "Pensando Platforms" + help + This enables support for the ARMv8 based Pensando chipsets + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB From patchwork Mon Mar 29 01:59:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 412117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4DB8C43459 for ; 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Sun, 28 Mar 2021 18:59:55 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id w37sm14728027pgl.13.2021.03.28.18.59.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Mar 2021 18:59:55 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, brad@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/13] arm64: dts: Add Pensando Elba SoC support Date: Sun, 28 Mar 2021 18:59:32 -0700 Message-Id: <20210329015938.20316-8-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329015938.20316-1-brad@pensando.io> References: <20210329015938.20316-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add Pensando common and Elba SoC specific device nodes Signed-off-by: Brad Larson --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/pensando/Makefile | 6 + arch/arm64/boot/dts/pensando/elba-16core.dtsi | 170 ++++++++++ .../boot/dts/pensando/elba-asic-common.dtsi | 112 +++++++ arch/arm64/boot/dts/pensando/elba-asic.dts | 7 + .../boot/dts/pensando/elba-flash-parts.dtsi | 78 +++++ arch/arm64/boot/dts/pensando/elba.dtsi | 310 ++++++++++++++++++ 7 files changed, 684 insertions(+) create mode 100644 arch/arm64/boot/dts/pensando/Makefile create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index f1173cd93594..c85db0a097fe 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -19,6 +19,7 @@ subdir-y += marvell subdir-y += mediatek subdir-y += microchip subdir-y += nvidia +subdir-y += pensando subdir-y += qcom subdir-y += realtek subdir-y += renesas diff --git a/arch/arm64/boot/dts/pensando/Makefile b/arch/arm64/boot/dts/pensando/Makefile new file mode 100644 index 000000000000..0c2c0961e64a --- /dev/null +++ b/arch/arm64/boot/dts/pensando/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PENSANDO_ELBA_SOC) += elba-asic.dtb + +always-y := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/pensando/elba-16core.dtsi b/arch/arm64/boot/dts/pensando/elba-16core.dtsi new file mode 100644 index 000000000000..a6c47899b69a --- /dev/null +++ b/arch/arm64/boot/dts/pensando/elba-16core.dtsi @@ -0,0 +1,170 @@ + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; + }; + cluster1 { + core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; + }; + cluster2 { + core0 { cpu = <&cpu8>; }; + core1 { cpu = <&cpu9>; }; + core2 { cpu = <&cpu10>; }; + core3 { cpu = <&cpu11>; }; + }; + cluster3 { + core0 { cpu = <&cpu12>; }; + core1 { cpu = <&cpu13>; }; + core2 { cpu = <&cpu14>; }; + core3 { cpu = <&cpu15>; }; + }; + }; + + // CLUSTER 0 + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x0>; + enable-method = "spin-table"; + next-level-cache = <&l2_0>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x1>; + enable-method = "spin-table"; + next-level-cache = <&l2_0>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x2>; + enable-method = "spin-table"; + next-level-cache = <&l2_0>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x3>; + enable-method = "spin-table"; + next-level-cache = <&l2_0>; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + }; + + // CLUSTER 1 + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x100>; + enable-method = "spin-table"; + next-level-cache = <&l2_1>; + }; + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x101>; + enable-method = "spin-table"; + next-level-cache = <&l2_1>; + }; + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x102>; + enable-method = "spin-table"; + next-level-cache = <&l2_1>; + }; + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x103>; + enable-method = "spin-table"; + next-level-cache = <&l2_1>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + }; + + // CLUSTER 2 + cpu8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x200>; + enable-method = "spin-table"; + next-level-cache = <&l2_2>; + }; + cpu9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x201>; + enable-method = "spin-table"; + next-level-cache = <&l2_2>; + }; + cpu10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x202>; + enable-method = "spin-table"; + next-level-cache = <&l2_2>; + }; + cpu11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x203>; + enable-method = "spin-table"; + next-level-cache = <&l2_2>; + }; + + l2_2: l2-cache2 { + compatible = "cache"; + }; + + // CLUSTER 3 + cpu12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x300>; + enable-method = "spin-table"; + next-level-cache = <&l2_3>; + }; + cpu13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x301>; + enable-method = "spin-table"; + next-level-cache = <&l2_3>; + }; + cpu14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x302>; + enable-method = "spin-table"; + next-level-cache = <&l2_3>; + }; + cpu15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x303>; + enable-method = "spin-table"; + next-level-cache = <&l2_3>; + }; + + l2_3: l2-cache3 { + compatible = "cache"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi new file mode 100644 index 000000000000..7de2c35e7fcc --- /dev/null +++ b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi @@ -0,0 +1,112 @@ + +/ { + model = "Elba ASIC Board"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + spi1 = &qspi; + }; + + chosen { + stdout-path = "serial0:19200n8"; + }; +}; + +&ahb_clk { + clock-frequency = <400000000>; +}; + +&emmc_clk { + clock-frequency = <200000000>; +}; + +&flash_clk { + clock-frequency = <400000000>; +}; + +&ref_clk { + clock-frequency = <156250000>; +}; + +&qspi { + status = "okay"; + flash0: mt25q@0 { + compatible = "jdec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + cdns,read-delay = <0>; + cdns,tshsl-ns = <0>; + cdns,tsd2d-ns = <0>; + cdns,tchsh-ns = <0>; + cdns,tslch-ns = <0>; + }; +}; + +&gpio0 { + status = "ok"; +}; + +&emmc { + bus-width = <8>; + status = "ok"; +}; + +&wdt0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + tmp451@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + }; + tps53659@62 { + compatible = "ti,tps53659"; + reg = <0x62>; + }; + pcf85263@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&spi0 { + num-cs = <4>; + cs-gpios = <&spics 0 0>, <&spics 1 0>, <&porta 1 0>, <&porta 7 0>; + status = "okay"; + spi@0 { + compatible = "pensando,cpld"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12000000>; + reg = <0>; + }; + spi@1 { + compatible = "pensando,cpld"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12000000>; + reg = <1>; + }; + spi@2 { + compatible = "pensando,cpld-rd1173"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12000000>; + reg = <2>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; + spi@3 { + compatible = "pensando,cpld"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <12000000>; + reg = <3>; + }; +}; diff --git a/arch/arm64/boot/dts/pensando/elba-asic.dts b/arch/arm64/boot/dts/pensando/elba-asic.dts new file mode 100644 index 000000000000..d074b1f1574a --- /dev/null +++ b/arch/arm64/boot/dts/pensando/elba-asic.dts @@ -0,0 +1,7 @@ + +/dts-v1/; + +#include "elba.dtsi" +#include "elba-16core.dtsi" +#include "elba-asic-common.dtsi" +#include "elba-flash-parts.dtsi" diff --git a/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi new file mode 100644 index 000000000000..7fff1d653592 --- /dev/null +++ b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi @@ -0,0 +1,78 @@ +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "flash"; + reg = <0x00010000 0x0fff0000>; + }; + partition@f0000 { + label = "golduenv"; + reg = <0x000f0000 0x00010000>; + }; + partition@100000 { + label = "boot0"; + reg = <0x00100000 0x00080000>; + }; + partition@180000 { + label = "golduboot"; + reg = <0x00180000 0x00200000>; + }; + partition@400000 { + label = "goldfw"; + reg = <0x00400000 0x03c00000>; + }; + partition@4010000 { + label = "fwmap"; + reg = <0x04010000 0x00020000>; + }; + partition@4030000 { + label = "fwsel"; + reg = <0x04030000 0x00020000>; + }; + partition@4090000 { + label = "bootlog"; + reg = <0x04090000 0x00020000>; + }; + partition@40b0000 { + label = "panicbuf"; + reg = <0x040b0000 0x00020000>; + }; + partition@40d0000 { + label = "uservars"; + reg = <0x040d0000 0x00020000>; + }; + partition@4200000 { + label = "uboota"; + reg = <0x04200000 0x00400000>; + }; + partition@4600000 { + label = "ubootb"; + reg = <0x04600000 0x00400000>; + }; + partition@4a00000 { + label = "mainfwa"; + reg = <0x04a00000 0x01000000>; + }; + partition@5a00000 { + label = "mainfwb"; + reg = <0x05a00000 0x01000000>; + }; + partition@8000000 { + label = "diagfw"; + reg = <0x08000000 0x07fe0000>; + }; + partition@ffe0000 { + label = "ubootenv"; + reg = <0x0ffe0000 0x00010000>; + }; + }; +}; + +&soc { + panicdump@740b0000 { + compatible = "pensando,capri-crash"; + reg = <0x0 0x740b0000 0x0 0x00020000>; + }; +}; diff --git a/arch/arm64/boot/dts/pensando/elba.dtsi b/arch/arm64/boot/dts/pensando/elba.dtsi new file mode 100644 index 000000000000..6f6cfab2b502 --- /dev/null +++ b/arch/arm64/boot/dts/pensando/elba.dtsi @@ -0,0 +1,310 @@ + +/* + * Copyright (c) 2019, Pensando Systems Inc. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "dt-bindings/interrupt-controller/arm-gic.h" + +/ { + compatible = "pensando,elba"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + ahb_clk: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + emmc_clk: oscillator2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + flash_clk: oscillator3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + ref_clk: oscillator4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + /* Common UIO device for MSI drivers */ + uio_penmsi { + compatible = "pensando,uio_penmsi"; + name = "uio_penmsi"; + }; + + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x800000 0x0 0x200000>, // GICD + <0x0 0xa00000 0x0 0x200000>; // GICR + interrupts = ; + + its: interrupt-controller@820000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x820000 0x0 0x10000>; + socionext,synquacer-pre-its = + <0xc00000 0x1000000>; + }; + }; + + /* + * Until we know the interrupt domain following this, we + * are forced to use this is the place where interrupts from + * PCI converge. In the ideal case, we use one domain higher, + * where the PCI-ness has been shed. + */ + pxc0_intr: intc@20102200 { + compatible = "pensando,soc-ictlr-csrintr"; + interrupt-controller; + reg = <0x0 0x20102200 0x0 0x4>; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-names = "pxc0_intr"; + }; + + uart0: serial@4800 { + device_type = "serial"; + compatible = "ns16550a"; + reg = <0x0 0x4800 0x0 0x100>; + clocks = <&ref_clk>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + qspi: spi@2400 { + compatible = "pensando,cdns-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2400 0x0 0x400>, + <0x0 0x7fff0000 0x0 0x1000>; + interrupts = ; + clocks = <&flash_clk>; + cdns,fifo-depth = <1024>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x7fff0000>; + status = "disabled"; + }; + + gpio0: gpio@4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x4000 0x0 0x78>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + portb: gpio-controller@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; + + i2c0: i2c@400 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x400 0x0 0x100>; + clocks = <&ahb_clk>; + #address-cells = <1>; + #size-cells = <0>; + i2c-sda-hold-time-ns = <480>; + snps,sda-timeout-ms = <750>; + interrupts = ; + status = "disabled"; + }; + + /* UIO device using interrupt line PCIEMAC */ + pciemac@20102200 { + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + + compatible = "pensando,uio_pciemac"; + register-type = "csr-interrupt"; + interrupt-parent = <&pxc0_intr>; + interrupts = ; + reg = <0x0 0x20102200 0x0 0x10>; /* pxc0_intr */ + + enable_csr_paddr = <0x0 0x20102200 0x0 0x10>; + enable_mask = <(1 << 0)>; + }; + + /* MSI UIO device 1 */ + uio_penmsi1@520000 { + compatible = "pensando,uio_penmsi1"; + reg = <0x0 0x520000 0x0 0x10000>; + msi-parent = <&its 0xa>; + num-interrupts = <16>; /* # MSI interrupts to get */ + }; + + spics: spics@307c2468 { + compatible = "pensando,elba-spics"; + reg = <0x0 0x307c2468 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; + + spi0: spi@2800 { + compatible = "pensando,elba-spi"; + reg = <0x0 0x2800 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <2>; + status = "disabled"; + }; + + wdt0: watchdog@1400 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x1400 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + wdt1: watchdog@1800 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x1800 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + wdt2: watchdog@1c00 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x1c00 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + wdt3: watchdog@2000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x2000 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + + emmc: mmc@30440000 { + compatible = "pensando,elba-emmc", "cdns,sd4hc"; + clocks = <&emmc_clk>; + interrupts = ; + reg = <0x0 0x30440000 0x0 0x10000 + 0x0 0x30480044 0x0 0x4>; + cdns,phy-input-delay-sd-highspeed = <0x4>; + cdns,phy-input-delay-legacy = <0x4>; + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>; + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>; + cdns,mmc-ddr-1_8v; + status = "disabled"; + } ; + + pcie@307c2480 { + compatible = "pensando,pcie"; + reg = <0x0 0x307c2480 0x0 0x4 /* MS CFG_WDT */ + 0x0 0x00001400 0x0 0x10 /* WDT0 */ + 0x0 0x20000000 0x0 0x00380000>; /* PXB Base */ + }; + + panic: panicdump@0 { + compatible = "pensando,pen-crash"; + status = "disabled"; + }; + + bsm@307c2080 { + compatible = "pensando,bsm"; + reg = <0x0 0x307c2080 0x0 0x4>; + }; + }; + mnet0: mnet0 { + compatible = "pensando,mnet"; + msi-parent = <&its 0x0>; + }; + mnet1: mnet1 { + compatible = "pensando,mnet"; + msi-parent = <&its 0x1>; + }; + mnet2: mnet2 { + compatible = "pensando,mnet"; + msi-parent = <&its 0x2>; + }; + mnet3: mnet3 { + compatible = "pensando,mnet"; + msi-parent = <&its 0x3>; + }; + mnet4: mnet4 { + compatible = "pensando,mnet"; + msi-parent = <&its 0x4>; + }; + mnet5: mnet5 { + compatible = "pensando,mnet"; + msi-parent = <&its 0x5>; + }; + mnet6: mnet6 { + compatible = "pensando,mnet"; + msi-parent = <&its 0x6>; + }; + mnet7: mnet7 { + compatible = "pensando,mnet"; + msi-parent = <&its 0x7>; + }; + mnet8: mnet8 { + compatible = "pensando,mnet"; + msi-parent = <&its 0x8>; + }; + mnet9: mnet9 { + compatible = "pensando,mnet"; + msi-parent = <&its 0x9>; + }; +}; From patchwork Mon Mar 29 01:59:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 411085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89698C4345E for ; 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Sun, 28 Mar 2021 18:59:57 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id w37sm14728027pgl.13.2021.03.28.18.59.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Mar 2021 18:59:56 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, brad@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 08/13] dt-bindings: Add pensando vendor prefix Date: Sun, 28 Mar 2021 18:59:33 -0700 Message-Id: <20210329015938.20316-9-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329015938.20316-1-brad@pensando.io> References: <20210329015938.20316-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add vendor prefix for Pensando Systems, Inc. Signed-off-by: Brad Larson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index f6064d84a424..9a21d780c5e1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -850,6 +850,8 @@ patternProperties: description: Parallax Inc. "^pda,.*": description: Precision Design Associates, Inc. + "^pensando,.*": + description: Pensando Systems Inc. "^pericom,.*": description: Pericom Technology Inc. "^pervasive,.*": From patchwork Mon Mar 29 01:59:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 411082 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44E67C433E0 for ; Mon, 29 Mar 2021 02:01:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 212B761948 for ; Mon, 29 Mar 2021 02:01:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231382AbhC2CAn (ORCPT ); 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Sun, 28 Mar 2021 18:59:58 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, brad@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/13] dt-bindings: mmc: Add Pensando Elba SoC binding Date: Sun, 28 Mar 2021 18:59:34 -0700 Message-Id: <20210329015938.20316-10-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329015938.20316-1-brad@pensando.io> References: <20210329015938.20316-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Pensando Elba ARM 64-bit SoC is integrated with this IP Signed-off-by: Brad Larson Acked-by: Rob Herring --- Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml index af7442f73881..3e8eb3254b99 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - socionext,uniphier-sd4hc + - pensando,elba-emmc - const: cdns,sd4hc reg: From patchwork Mon Mar 29 01:59:35 2021 Content-Type: text/plain; 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Signed-off-by: Brad Larson --- .../bindings/spi/cadence-quadspi.txt | 68 -------- .../bindings/spi/cadence-quadspi.yaml | 153 ++++++++++++++++++ 2 files changed, 153 insertions(+), 68 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt deleted file mode 100644 index 8ace832a2d80..000000000000 --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt +++ /dev/null @@ -1,68 +0,0 @@ -* Cadence Quad SPI controller - -Required properties: -- compatible : should be one of the following: - Generic default - "cdns,qspi-nor". - For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". - For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". - For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor". -- reg : Contains two entries, each of which is a tuple consisting of a - physical address and length. The first entry is the address and - length of the controller register set. The second entry is the - address and length of the QSPI Controller data area. -- interrupts : Unit interrupt specifier for the controller interrupt. -- clocks : phandle to the Quad SPI clock. -- cdns,fifo-depth : Size of the data FIFO in words. -- cdns,fifo-width : Bus width of the data FIFO in bytes. -- cdns,trigger-address : 32-bit indirect AHB trigger address. - -Optional properties: -- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. -- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch - the read data rather than the QSPI clock. Make sure that QSPI return - clock is populated on the board before using this property. - -Optional subnodes: -Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional -custom properties: -- cdns,read-delay : Delay for read capture logic, in clock cycles -- cdns,tshsl-ns : Delay in nanoseconds for the length that the master - mode chip select outputs are de-asserted between - transactions. -- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being - de-activated and the activation of another. -- cdns,tchsh-ns : Delay in nanoseconds between last bit of current - transaction and deasserting the device chip select - (qspi_n_ss_out). -- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low - and first bit transfer. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include either "qspi" and/or "qspi-ocp". - -Example: - - qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; - interrupts = <0 151 4>; - clocks = <&qspi_clk>; - cdns,is-decoded-cs; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; - reset-names = "qspi", "qspi-ocp"; - - flash0: n25q00@0 { - ... - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml new file mode 100644 index 000000000000..94d631045153 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/cadence-quadspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence Quad SPI controller + +maintainers: + - Ramuthevar Vadivel Murugan + - Brad Larson + +properties: + compatible: + contains: + enum: + - cdns,qspi-nor # Generic default + - ti,k2g-qspi # TI 66AK2G SoC + - ti,am654-ospi # TI AM654 SoC + - intel,lgm-qspi # Intel LGM SoC + - pensando,cdns-qspi # Pensando Elba SoC + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + minItems: 2 + maxItems: 2 + description: | + Contains two entries, each of which is a tuple consisting of a + physical address and length. The first entry is the address and + length of the controller register set. The second entry is the + address and length of the QSPI Controller data area. + + interrupts: + maxItems: 1 + description: Unit interrupt specifier for the controller interrupt + + clocks: + description: phandle to the Quad SPI clock + + cdns,fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Size of the data FIFO in words + + cdns,fifo-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Bus width of the data FIFO in bytes + + cdns,trigger-address: + $ref: /schemas/types.yaml#/definitions/uint32 + description: 32-bit indirect AHB trigger address + + cdns,is-decoded-cs: + $ref: /schemas/types.yaml#/definitions/flag + description: Flag to indicate whether decoder is used or not + + cdns,rclk-en: + description: + Flag to indicate that QSPI return clock is used to latch the + read data rather than the QSPI clock. Make sure that QSPI return + clock is populated on the board before using this property + $ref: /schemas/types.yaml#/definitions/flag + + # Subnodes of the Cadence Quad SPI controller are spi slave nodes + # with additional custom properties + cdns,read-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Delay for read capture logic, in clock cycles + + cdns,tshsl-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay in nanoseconds for the length that the master mode chip + select outputs are de-asserted between transactions + + cdns,tsd2d-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay in nanoseconds between one chip select being de-activated + and the activation of another. + + cdns,tchsh-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay in nanoseconds between last bit of current transaction and + deasserting the device chip select (qspi_n_ss_out). + + cdns,tslch-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay in nanoseconds between setting qspi_n_ss_out low and first + bit transfer. + + resets: + items: + - description: qspi reset + - description: qspi-ocp reset + + reset-names: + items: + - const: qspi + - const: qspi-ocp + +required: + - compatible + - reg + - interrupts + - clocks + - cdns,fifo-depth + - cdns,fifo-width + - cdns,trigger-address + +patternProperties: + "^.*@[0-9]+$": + type: object + +additionalProperties: false + +examples: + - | + #include + qspi: spi@ff705000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + cdns,is-decoded-cs; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; + reset-names = "qspi", "qspi-ocp"; + + flash0: mt25q@0 { + compatible = "jdec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + cdns,read-delay = <0>; + cdns,tshsl-ns = <0>; + cdns,tsd2d-ns = <0>; + cdns,tchsh-ns = <0>; + cdns,tslch-ns = <0>; + }; + }; From patchwork Mon Mar 29 01:59:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 412116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A47D9C43603 for ; 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Sun, 28 Mar 2021 19:00:01 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id w37sm14728027pgl.13.2021.03.28.19.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Mar 2021 19:00:01 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, brad@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 11/13] dt-bindings: gpio: Add Pensando Elba SoC support Date: Sun, 28 Mar 2021 18:59:36 -0700 Message-Id: <20210329015938.20316-12-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329015938.20316-1-brad@pensando.io> References: <20210329015938.20316-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The Pensando Elba SoC gpio driver provides control of four chip selects on two SPI busses. Signed-off-by: Brad Larson --- .../bindings/gpio/pensando,elba-spics.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/pensando,elba-spics.yaml diff --git a/Documentation/devicetree/bindings/gpio/pensando,elba-spics.yaml b/Documentation/devicetree/bindings/gpio/pensando,elba-spics.yaml new file mode 100644 index 000000000000..c93b481d4ad3 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/pensando,elba-spics.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/pensando,elba-spics.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pensando Elba SPI Chip Select Driver + +description: | + The Pensando Elba SoC provides four SPI bus chip selects. + +maintainers: + - Brad Larson + +properties: + $nodename: + pattern: "^spics@[0-9a-f]+$" + + compatible: + const: pensando,elba-spics + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + spics: spics@307c2468 { + compatible = "pensando,elba-spics"; + reg = <0x0 0x307c2468 0x0 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; + }; From patchwork Mon Mar 29 01:59:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 411083 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97FCAC43600 for ; Mon, 29 Mar 2021 02:00:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 821E761942 for ; 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Sun, 28 Mar 2021 19:00:02 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, brad@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 12/13] MAINTAINERS: Add entry for PENSANDO Date: Sun, 28 Mar 2021 18:59:37 -0700 Message-Id: <20210329015938.20316-13-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329015938.20316-1-brad@pensando.io> References: <20210329015938.20316-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add entry for PENSANDO maintainer and files Signed-off-by: Brad Larson --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fb2a3633b719..272c7a7fde75 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2246,6 +2246,15 @@ S: Maintained W: http://hackndev.com F: arch/arm/mach-pxa/palmz72.* +ARM/PENSANDO SUPPORT +M: Brad Larson +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/*/pensando* +F: arch/arm64/boot/dts/pensando/ +F: drivers/gpio/gpio-elba-spics.c +F: drivers/mmc/host/sdhci-cadence-elba.c + ARM/PLEB SUPPORT M: Peter Chubb S: Maintained From patchwork Mon Mar 29 01:59:38 2021 Content-Type: text/plain; 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Signed-off-by: Brad Larson --- drivers/gpio/gpio-elba-spics.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-elba-spics.c b/drivers/gpio/gpio-elba-spics.c index 351bbaeea033..c0dce5333f35 100644 --- a/drivers/gpio/gpio-elba-spics.c +++ b/drivers/gpio/gpio-elba-spics.c @@ -6,11 +6,10 @@ */ #include -#include +#include #include #include #include -//#include #include #include #include