From patchwork Mon Mar 29 19:45:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 410904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31B95C433E3 for ; Mon, 29 Mar 2021 19:47:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 03BB0619A0 for ; Mon, 29 Mar 2021 19:47:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231758AbhC2TrR (ORCPT ); Mon, 29 Mar 2021 15:47:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231547AbhC2Tq7 (ORCPT ); Mon, 29 Mar 2021 15:46:59 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B46A1C061756; Mon, 29 Mar 2021 12:46:58 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id u10so17280228lju.7; Mon, 29 Mar 2021 12:46:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U9m/vE1DNphlJsrYchwoexwhY0Aq5nAA6kFZ0qFRU/c=; b=urDD6gw9VyK6JzSc7OkfGqU6GGBWbk7dG4CsL8sUd+aqLVPMrTYdkikyM/1bQFy77q Cbdsi8/wSL4TqNEiIys7E7b6UQN1m36dKkjagcmU5ZIgrtrQcWP4DuZlnO8t/XBfLabF Uj5Yto7RTKEBb0opkDe9vIFPY9grlf/jOu/Q7bkUp2CNjME7aAVWJBXg4WeI1BMR95E/ nSuveIkSw4Y+ajMHbqec2Y3lMJZW5xHjA3R+nuO7NflWUWLUpp31czn3R1Mgp8VZxf67 8BHCmi54OdwmBq6QY4ILah31OfOVMS+YiNXFyqY7/ow08+7QYocIOsSZmMcPpz+/opUp LUQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U9m/vE1DNphlJsrYchwoexwhY0Aq5nAA6kFZ0qFRU/c=; b=KJqPBTKhynYjU5vsI9QNwS/MUs57pelYVt4vx330iLoIvGTt31uaGb2TGf/qmzWzCU lAb/hfESWaOmvib+sk4rZg8d9gxH7HD1KcYYYxtjMVP7jh4Ns3KwdH8hQMtnSo5gIdbz 5+9xObop7WpHg0j5vRqUdBm5DsSaPiUwyYObZVmKyhThuC1pleCqA/YmAQfqAre2yW+d TUQLrWhs0ft1nukiZ5qIVX6FDpDdd/c6e7VnLd7MZCDtuFs+fSFAsBUO8vEjSCLXrbHo w59Zb7mIGNvdKSEyr8hyTngyCXg/upBMP1YqgF8jYXTHHfYTvR4W+tafz3uNSVHjZPKL Ec9Q== X-Gm-Message-State: AOAM530l0FLJpYg3te80iaRcvxaoZMalJur3PM2UAS6uO4boa/2JuojQ 02U8rFYF8vsOMSs8wlJ898g= X-Google-Smtp-Source: ABdhPJxEE3REID3XCkqHkD+RLcCPqrnLL9TrPskDPfrUNLQFTH4rc9Fl/wKimpYEH6vuqB+2wwn0gQ== X-Received: by 2002:a05:651c:d0:: with SMTP id 16mr18916830ljr.296.1617047217278; Mon, 29 Mar 2021 12:46:57 -0700 (PDT) Received: from localhost.localdomain ([2a00:1370:814d:b259:a10:76ff:fe69:21b6]) by smtp.gmail.com with ESMTPSA id p24sm1927693lfj.76.2021.03.29.12.46.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Mar 2021 12:46:57 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , Rob Herring Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 3/6] dt-bindings: memory: tegra124: emc: Replace core regulator with power domain Date: Mon, 29 Mar 2021 22:45:59 +0300 Message-Id: <20210329194602.17049-4-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210329194602.17049-1-digetx@gmail.com> References: <20210329194602.17049-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Power domain fits much better than a voltage regulator in regards to a proper hardware description and from a software perspective as well. Hence replace the core regulator with the power domain. Note that this doesn't affect any existing DTBs because we haven't started to use the regulator yet, and thus, it's okay to change it. Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 09bde65e1955..a7483547ccf8 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -37,9 +37,10 @@ properties: description: phandle of the memory controller node - core-supply: + power-domains: + $ref: /schemas/types.yaml#/definitions/phandle description: - Phandle of voltage regulator of the SoC "core" power domain. + Phandle of the SoC "core" power domain. operating-points-v2: description: @@ -370,7 +371,7 @@ examples: nvidia,memory-controller = <&mc>; operating-points-v2 = <&dvfs_opp_table>; - core-supply = <&vdd_core>; + power-domains = <&domain>; #interconnect-cells = <0>; From patchwork Mon Mar 29 19:46:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 410903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B029AC433EA for ; Mon, 29 Mar 2021 19:47:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5F9CE61987 for ; Mon, 29 Mar 2021 19:47:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231772AbhC2TrR (ORCPT ); Mon, 29 Mar 2021 15:47:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231672AbhC2Tq7 (ORCPT ); Mon, 29 Mar 2021 15:46:59 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E138C061574; Mon, 29 Mar 2021 12:46:59 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id 184so17235996ljf.9; Mon, 29 Mar 2021 12:46:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XH/LVCqLvCaL2Ayt4SmQEAxMJCJ53uI079V0Vyuggh8=; b=VhENSp/tJZc0DN6Gk82B52Fv+PMB9qHt1GQB0Ro+910HbafzWgS9jc3UQyPHNgT4Pq 0yxh7L1NKxY3FZL9pb/wJCNQuywigHTis84iLvjWw3hABLw9RrNrynxCs/oKWwXlKfn2 aLKvXOSg7/tv9mDHFSKtTTv2RNX67Yvp047PMW9hAB9sdADmRBpqK2ors0r9+6PJtV9q GvQVUsd/8o+d2LgSYepmICDVIHtJNehjgJKBWHM3BQwo9sVsK5fGK4ga9yS9/5o3NVke eEcjWsLnN9NowY3vWSU2l44yBQ3Fsle2VpWj3p33F4pvMbyEAtsQMVSCPUzsWWYRnrF5 xCCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XH/LVCqLvCaL2Ayt4SmQEAxMJCJ53uI079V0Vyuggh8=; b=dWKpwPu45Ll8EbAXgO3AaUe9xttcANMw3Os/4BHSc4hKuUpyjJ3Y0n8nANA47ZnS9E kGxigBWha4DDqxr22fZFzIvPRru+FPiDW8ld2a4U6Kw8xJl1B3K2dT/ZLmM6ksVssIbx hn0E660sx7/OFuWMkPlH5IFNubPeeaInBJRFc+mZPWGFPgspYFXVLpwFik7cjE2l7QeQ Z7ys5nsWFvMliaOER6hmpj9X1KrOAS7IwIfnrnH8wi3c1vgzZN15e/jh0dkGach2c7R6 hbYxnpe3O6aCFarbCZG1g3Xq81ypz3ICqzNcWtUKi3MlQ7lrSviJwRwDu2w00nAkhHjc YEYQ== X-Gm-Message-State: AOAM5309DAZxxhibWQazF3AIjQsQ/tNLRMpV3Yxe0ClBuwTY+/H7+OI7 aatnhAK4ybVkBIiFS5TTtiA= X-Google-Smtp-Source: ABdhPJwzdhGXspTbFGLqYBOm9p8+rW7I842LUQ3AzB1oyuQKFAbL7baolDzVa5NnDoaiAPPgsTG8IQ== X-Received: by 2002:a2e:9204:: with SMTP id k4mr18358977ljg.203.1617047218073; Mon, 29 Mar 2021 12:46:58 -0700 (PDT) Received: from localhost.localdomain ([2a00:1370:814d:b259:a10:76ff:fe69:21b6]) by smtp.gmail.com with ESMTPSA id p24sm1927693lfj.76.2021.03.29.12.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Mar 2021 12:46:57 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , Rob Herring Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 4/6] dt-bindings: memory: tegra20: mc: Convert to schema Date: Mon, 29 Mar 2021 22:46:00 +0300 Message-Id: <20210329194602.17049-5-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210329194602.17049-1-digetx@gmail.com> References: <20210329194602.17049-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Tegra20 Memory Controller binding to schema. Signed-off-by: Dmitry Osipenko --- .../memory-controllers/nvidia,tegra20-mc.txt | 40 ---------- .../memory-controllers/nvidia,tegra20-mc.yaml | 78 +++++++++++++++++++ 2 files changed, 78 insertions(+), 40 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt deleted file mode 100644 index 739b7c6f2e26..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt +++ /dev/null @@ -1,40 +0,0 @@ -NVIDIA Tegra20 MC(Memory Controller) - -Required properties: -- compatible : "nvidia,tegra20-mc-gart" -- reg : Should contain 2 register ranges: physical base address and length of - the controller's registers and the GART aperture respectively. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - mc: the module's clock input -- interrupts : Should contain MC General interrupt. -- #reset-cells : Should be 1. This cell represents memory client module ID. - The assignments may be found in header file - or in the TRM documentation. -- #iommu-cells: Should be 0. This cell represents the number of cells in an - IOMMU specifier needed to encode an address. GART supports only a single - address space that is shared by all devices, therefore no additional - information needed for the address encoding. -- #interconnect-cells : Should be 1. This cell represents memory client. - The assignments may be found in header file . - -Example: - mc: memory-controller@7000f000 { - compatible = "nvidia,tegra20-mc-gart"; - reg = <0x7000f000 0x400 /* controller registers */ - 0x58000000 0x02000000>; /* GART aperture */ - clocks = <&tegra_car TEGRA20_CLK_MC>; - clock-names = "mc"; - interrupts = ; - #reset-cells = <1>; - #iommu-cells = <0>; - #interconnect-cells = <1>; - }; - - video-codec@6001a000 { - compatible = "nvidia,tegra20-vde"; - ... - resets = <&mc TEGRA20_MC_RESET_VDE>; - iommus = <&mc>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml new file mode 100644 index 000000000000..c5731fa41e83 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 SoC Memory Controller + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +description: | + The Tegra20 Memory Controller merges request streams from various client + interfaces into request stream(s) for the various memory target devices, + and returns response data to the various clients. The Memory Controller + has a configurable arbitration algorithm to allow the user to fine-tune + performance among the various clients. + + Tegra20 Memory Controller includes the GART (Graphics Address Relocation + Table) which allows Memory Controller to provide a linear view of a + fragmented memory pages. + +properties: + compatible: + const: nvidia,tegra20-mc-gart + + reg: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: mc + + interrupts: + maxItems: 1 + + "#reset-cells": + const: 1 + + "#iommu-cells": + const: 0 + + "#interconnect-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#reset-cells" + - "#iommu-cells" + - "#interconnect-cells" + +additionalProperties: false + +examples: + - | + memory-controller@7000f000 { + compatible = "nvidia,tegra20-mc"; + reg = <0x7000f000 0x400>, /* Controller registers */ + <0x58000000 0x02000000>; /* GART aperture */ + clocks = <&clock_controller 32>; + clock-names = "mc"; + + interrupts = <0 77 4>; + + #iommu-cells = <0>; + #reset-cells = <1>; + #interconnect-cells = <1>; + };