From patchwork Fri May 18 06:26:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 136245 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp840996lji; Thu, 17 May 2018 23:27:38 -0700 (PDT) X-Google-Smtp-Source: AB8JxZodYeTO4Rr+E0vbUKc4vk29V0kCQ+O5smpIhgzx1AWy/IvF5sriAUCqEMwwaNFA+kcekU7/ X-Received: by 2002:a63:be4b:: with SMTP id g11-v6mr6519296pgo.41.1526624858258; Thu, 17 May 2018 23:27:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526624858; cv=none; d=google.com; s=arc-20160816; b=XdOTsCRBzKP9LVzvzGX43/Cqso1dKcA9ixvrWBZXndw2NlQTF3rAwylbFVEQqH9mTV L+RxWyjytQIeadVjnJDiVLxZJGZ/jaQIeKAqv8koU0d3pHaZfwo3OrlQN5rV6Y2spP/v wCOfrpltBr9lcgdCSSIfwKmjWJD9Yom4/KwVz50DLNUon8jQsOCYnNw/2fBoEqC7AYxo TMvVrb4zDwQm2SwWCayOzGCreauGnCltdQBVPHkFKzqtKCcc+r/jZB7oKIP9LuFJfugD 8o9dinrZU1ThOuIgv26TioubeA/d+EtrQnqFK//tiOEgPFI8WrngOw+I4bmlnAUslWdi DqpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=nTiw+f5+gsdqj+kWCtq8rekmxjC90c6YvOzWJLB+vwo=; b=Cx9T7bdGguc1Xkfbw7i2L3ms2EoZfhsuTgvcnxjzGQszkGdbzLboEevos475uo+ENA 0SmDzyUsHAiZEXLRjblltkdinvhidh/EiGKdwhCDJ5Btw6uXmIiPo9MWLDoFp17wBte+ Dgv7Ph4oTANfUNJNl+08cx6dDy85cB6jjm2RaJ2Q6TFWlLUTYJ+QAA3ltoQkqL0LBOIP fexKQmfB91rkxMlYwQQb3mHF0hZGFSetmsDOmXd08jfMjjvFHlMQFrNL9z59L0Vq+fPF 4v524XQiiyl5J/HllVeBghb13rwCCPXj7v4DC5djCxR21ONYsqIWsj7OZu9fC2Qamixr N2Yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HGajjgPa; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id b72-v6sm14157432pfm.69.2018.05.17.23.26.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 May 2018 23:26:42 -0700 (PDT) From: Bjorn Andersson To: Vinayak Holikatti , "James E.J. Bottomley" , "Martin K. Petersen" Cc: Andy Gross , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , linux-scsi@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 1/3] scsi: ufs: Extract devfreq registration Date: Thu, 17 May 2018 23:26:36 -0700 Message-Id: <20180518062638.31777-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180518062638.31777-1-bjorn.andersson@linaro.org> References: <20180518062638.31777-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Failing to register with devfreq leaves hba->devfreq assigned, which causes the error path to dereference the ERR_PTR(). Rather than bolting on more conditionals, move the call of devm_devfreq_add_device() into it's own function and only update hba->devfreq once it's successfully registered. The subsequent patch builds upon this to make UFS actually work again, as it's been broken since f1d981eaecf8 ("PM / devfreq: Use the available min/max frequency") Also switch to use DEVFREQ_GOV_SIMPLE_ONDEMAND constant. Reviewed-by: Chanwoo Choi Signed-off-by: Bjorn Andersson --- Changes since v2: - Use DEVFREQ_GOV_SIMPLE_ONDEMAND, per Chanwoo's recommendation - Picked up Chanwoo's R-b Changes since v1: - None drivers/scsi/ufs/ufshcd.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) -- 2.17.0 diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 00e79057f870..f04902a066cb 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -1287,6 +1287,26 @@ static struct devfreq_dev_profile ufs_devfreq_profile = { .get_dev_status = ufshcd_devfreq_get_dev_status, }; +static int ufshcd_devfreq_init(struct ufs_hba *hba) +{ + struct devfreq *devfreq; + int ret; + + devfreq = devm_devfreq_add_device(hba->dev, + &ufs_devfreq_profile, + DEVFREQ_GOV_SIMPLE_ONDEMAND, + NULL); + if (IS_ERR(devfreq)) { + ret = PTR_ERR(devfreq); + dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); + return ret; + } + + hba->devfreq = devfreq; + + return 0; +} + static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba) { unsigned long flags; @@ -6439,16 +6459,9 @@ static int ufshcd_probe_hba(struct ufs_hba *hba) sizeof(struct ufs_pa_layer_attr)); hba->clk_scaling.saved_pwr_info.is_valid = true; if (!hba->devfreq) { - hba->devfreq = devm_devfreq_add_device(hba->dev, - &ufs_devfreq_profile, - "simple_ondemand", - NULL); - if (IS_ERR(hba->devfreq)) { - ret = PTR_ERR(hba->devfreq); - dev_err(hba->dev, "Unable to register with devfreq %d\n", - ret); + ret = ufshcd_devfreq_init(hba); + if (ret) goto out; - } } hba->clk_scaling.is_allowed = true; } From patchwork Fri May 18 06:26:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 136244 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp840796lji; Thu, 17 May 2018 23:27:20 -0700 (PDT) X-Google-Smtp-Source: AB8JxZobKTRAXCMmuq/sS0XDm8Xt2yN310jPaOoqgBGrFRVxEpWKCc7cxtn0ck+UqqePli8qBYSI X-Received: by 2002:a62:cca:: with SMTP id 71-v6mr8067184pfm.61.1526624840458; Thu, 17 May 2018 23:27:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526624840; cv=none; d=google.com; s=arc-20160816; b=QrjgW61SQ6FFYJX2MllK81uRzk9dDGG4gU0xSxrm7ytQValPXarEE/4BMcGmEpHO5H wGoclGyRDUzJTLbXZXa7bHwn/hamlfSvrtaTD/x8SrNo+96+viigEw8DCDQ7DekT3yeo uCLHgNRrhuJbYvuLFPkCl8StlDPQDfqioas5wzWp9I9o/qsNkXtwnVnE9L8SyxqNihf0 WT2l8B5Ope0BxBqqxbHbWw++W2LzCUGJZpV0D6H8QwIZ1IDP6b/F2ZT8ZXiprsfivrdl fwHd0QFv7IcdIKyb2H0G0z1bxJS+xkF8W2Kf8CzXobffjzGxpP4F+kwJ5mcmhrPevjNX EFiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=x3HtiB1+TT4cmZucVxmOPHWDo6i+KZrYRTmInJpZN54=; b=Y7TmZgOc3ZV0K7zl33Hv0hh7DfstMa94N8ZBcgW+iuLghhZnSSCLD4Eeb+qVZWG6oD 3KK3MMuWK6KS3zwdpDkelXxML7T8SUCIWB0LJtkXYD747JaagebDonNs3EbvZ7VRO0r8 TyEfJBQSwbwmhnWUZ5dt8H2gF4vjoxHU5Clq2UDj1MxIvxHgD3Q0PZSZOIbsd347dHq/ Dxe52pxxpv7vjwmNrQmXF/t+kLPyQkS8ie1Yf+z/ZXZ85JwoaAC92SjURbL7EUj+DGDj UtT38KUYle5VZt4dmYIGPcg0NBT1InBKMScyMsXr6l6NOajzkboPVDyrZ2GZ9/+/cFz2 RCPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VyHu7K3l; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id b72-v6sm14157432pfm.69.2018.05.17.23.26.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 May 2018 23:26:44 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] arm64: dts: qcom: msm8996: Add ufs related nodes Date: Thu, 17 May 2018 23:26:38 -0700 Message-Id: <20180518062638.31777-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180518062638.31777-1-bjorn.andersson@linaro.org> References: <20180518062638.31777-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the UFS QMP phy node and the UFS host controller node, now that we have working UFS and the necessary clocks in place. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 8 ++ arch/arm64/boot/dts/qcom/msm8996.dtsi | 85 ++++++++++++++++++++ 2 files changed, 93 insertions(+) -- 2.17.0 diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 8be666ea92bd..00e3ecd1180a 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -122,6 +122,14 @@ status = "okay"; }; + phy@627000 { + status = "okay"; + }; + + ufshc@624000 { + status = "okay"; + }; + phy@34000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 37b7152cb064..221bb3d383c5 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -633,6 +633,91 @@ #interrupt-cells = <4>; }; + ufsphy: phy@627000 { + compatible = "qcom,msm8996-ufs-phy-qmp-14nm"; + reg = <0x627000 0xda8>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + vdda-phy-supply = <&pm8994_l28>; + vdda-pll-supply = <&pm8994_l12>; + + vdda-phy-max-microamp = <18380>; + vdda-pll-max-microamp = <9440>; + + vddp-ref-clk-supply = <&pm8994_l25>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + + clock-names = "ref_clk_src", "ref_clk"; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_UFS_CLKREF_CLK>; + status = "disabled"; + + power-domains = <&gcc UFS_GDSC>; + }; + + ufshc@624000 { + compatible = "qcom,ufshc"; + reg = <0x624000 0x2500>; + interrupts = ; + + phys = <&ufsphy>; + phy-names = "ufsphy"; + + vcc-supply = <&pm8994_l20>; + vccq-supply = <&pm8994_l25>; + vccq2-supply = <&pm8994_s4>; + + vcc-max-microamp = <600000>; + vccq-max-microamp = <450000>; + vccq2-max-microamp = <450000>; + + clock-names = + "core_clk_src", + "core_clk", + "bus_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro_src", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&gcc UFS_AXI_CLK_SRC>, + <&gcc GCC_UFS_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, + <&gcc GCC_AGGRE2_UFS_AXI_CLK>, + <&gcc GCC_UFS_AHB_CLK>, + <&gcc UFS_ICE_CORE_CLK_SRC>, + <&gcc GCC_UFS_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_ICE_CORE_CLK>, + <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; + freq-table-hz = + <100000000 200000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <150000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + lanes-per-direction = <1>; + status = "disabled"; + + ufs_variant { + compatible = "qcom,ufs_variant"; + }; + }; + mmcc: clock-controller@8c0000 { compatible = "qcom,mmcc-msm8996"; #clock-cells = <1>;