From patchwork Thu Mar 25 06:54:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 409451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9C8DC433E1 for ; Thu, 25 Mar 2021 06:56:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9E72761A35 for ; Thu, 25 Mar 2021 06:56:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229730AbhCYGzg (ORCPT ); Thu, 25 Mar 2021 02:55:36 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:38484 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229548AbhCYGzU (ORCPT ); Thu, 25 Mar 2021 02:55:20 -0400 X-UUID: 99f378f4f3bc403ab5ff05afd09e0d9e-20210325 X-UUID: 99f378f4f3bc403ab5ff05afd09e0d9e-20210325 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1032022078; Thu, 25 Mar 2021 14:55:10 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 25 Mar 2021 14:55:08 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 25 Mar 2021 14:55:08 +0800 From: Chunfeng Yun To: Vinod Koul , Matthias Brugger CC: Chunfeng Yun , Kishon Vijay Abraham I , Rob Herring , Chun-Kuang Hu , Philipp Zabel , Cawa Cheng , CK Hu , Daniel Kurtz , Jie Qiu , , , , , stable Subject: [PATCH RESEND v5 04/12] arm64: dts: mt8173: fix property typo of 'phys' in dsi node Date: Thu, 25 Mar 2021 14:54:50 +0800 Message-ID: <20210325065458.43363-4-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210325065458.43363-1-chunfeng.yun@mediatek.com> References: <20210325065458.43363-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Use 'phys' instead of 'phy'. Fixes: 81ad4dbaf7af ("arm64: dts: mt8173: Add display subsystem related nodes") Cc: stable Reviewed-by: Chun-Kuang Hu Signed-off-by: Chunfeng Yun --- v5: merged into this series, add Reviewed-by CK --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 7fa870e4386a..ecb37a7e6870 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1235,7 +1235,7 @@ <&mmsys CLK_MM_DSI1_DIGITAL>, <&mipi_tx1>; clock-names = "engine", "digital", "hs"; - phy = <&mipi_tx1>; + phys = <&mipi_tx1>; phy-names = "dphy"; status = "disabled"; };