From patchwork Thu Mar 25 13:12:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 409328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA23DC433E2 for ; Thu, 25 Mar 2021 13:14:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B535161A26 for ; Thu, 25 Mar 2021 13:14:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230460AbhCYNNj (ORCPT ); Thu, 25 Mar 2021 09:13:39 -0400 Received: from mail.kernel.org ([198.145.29.99]:52530 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230241AbhCYNN3 (ORCPT ); Thu, 25 Mar 2021 09:13:29 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 28B1A61A26; Thu, 25 Mar 2021 13:13:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1616678009; bh=aEIqfBLBfaoi2rijCx0Z6Sl+e1sdvPs+1ZbqOwzkQ84=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K9oydgcSdl18RA3B1fEXHs7lk20xSaBCWCCQFlT3TrsM5YsAt/u4q36GlmTtV5R9v luyl1W8s1GqltacZgJCjpwgnVfVHCVwZeVqFMYQuGzn7hAzE77e+dnnL4OtgcACm59 XV0z78wvhulC/43hNydQLx+GFM0Wn7It8UbnpA6YbrSIt70fWiGywiFZbYqgrSU5Ga xrAwbgpIavf/bxQB+Tsa67HoMBuD3GVpuKE5a9QN+8PvFfm+4birgfxMhmJ/vqYnBO espxOdcEAR3r/XHYw9+53kNNHNJf47JS5LA+vI7jqsNZqA2D08BASad6aN0SHM8fbq lmNuwpZFuv7Qg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: netdev@vger.kernel.org, Andrew Lunn , "David S . Miller" , Florian Fainelli , Heiner Kallweit , Russell King , kuba@kernel.org Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH net-next v2 03/12] net: phy: marvell10g: allow 5gbase-r and usxgmii Date: Thu, 25 Mar 2021 14:12:41 +0100 Message-Id: <20210325131250.15901-4-kabel@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210325131250.15901-1-kabel@kernel.org> References: <20210325131250.15901-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This modes are also supported by this PHYs. Signed-off-by: Marek Behún --- drivers/net/phy/marvell10g.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index f2f0da9717be..881a0717846e 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -462,9 +462,11 @@ static int mv3310_config_init(struct phy_device *phydev) /* Check that the PHY interface type is compatible */ if (phydev->interface != PHY_INTERFACE_MODE_SGMII && phydev->interface != PHY_INTERFACE_MODE_2500BASEX && + phydev->interface != PHY_INTERFACE_MODE_5GBASER && phydev->interface != PHY_INTERFACE_MODE_XAUI && phydev->interface != PHY_INTERFACE_MODE_RXAUI && - phydev->interface != PHY_INTERFACE_MODE_10GBASER) + phydev->interface != PHY_INTERFACE_MODE_10GBASER && + phydev->interface != PHY_INTERFACE_MODE_USXGMII) return -ENODEV; phydev->mdix_ctrl = ETH_TP_MDI_AUTO; @@ -599,6 +601,7 @@ static void mv3310_update_interface(struct phy_device *phydev) if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || phydev->interface == PHY_INTERFACE_MODE_2500BASEX || + phydev->interface == PHY_INTERFACE_MODE_5GBASER || phydev->interface == PHY_INTERFACE_MODE_10GBASER) && phydev->link) { /* The PHY automatically switches its serdes interface (and @@ -611,6 +614,9 @@ static void mv3310_update_interface(struct phy_device *phydev) case SPEED_10000: phydev->interface = PHY_INTERFACE_MODE_10GBASER; break; + case SPEED_5000: + phydev->interface = PHY_INTERFACE_MODE_5GBASER; + break; case SPEED_2500: phydev->interface = PHY_INTERFACE_MODE_2500BASEX; break; From patchwork Thu Mar 25 13:12:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 409327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1333C433E1 for ; Thu, 25 Mar 2021 13:14:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD1DF619A3 for ; Thu, 25 Mar 2021 13:14:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230332AbhCYNNm (ORCPT ); Thu, 25 Mar 2021 09:13:42 -0400 Received: from mail.kernel.org ([198.145.29.99]:52544 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230348AbhCYNNb (ORCPT ); Thu, 25 Mar 2021 09:13:31 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id F3E4D619FE; Thu, 25 Mar 2021 13:13:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1616678011; bh=TLzjIiMW8gsFW9CarK+CjX5T4n1cnXSM8MHtXQS/g7s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d0r0KGH5DXHduUL6PGdWGkU8F9mUNRUJ86na4z1krZ4UdlIQ8U458605bW5jVWz5b r00bG1Ine1ky05r4vxiXBzpDhjFNYkRGSLJNqPCwUhU+aoGSCL7up0GhbkfHesCc6l cT00U5+tCTZwqZUqtvzxUCF+56FEdf12mhcxli9+CdPYzymH0+g3/TFMeU1CJTo25q hgejyMMmZlLOFMQ7C7X0y/4jZgu8obJip/kR/85708c7JvfcqGh+Wfg8ScwZsmbS4s eDw3DHc4pjgN1DcjHIzOvqpbOR+p2vX2iFHYLUHQizMlLIZIPom7rnSVKaHrU8l8pH RGrcTwdlOSgGw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: netdev@vger.kernel.org, Andrew Lunn , "David S . Miller" , Florian Fainelli , Heiner Kallweit , Russell King , kuba@kernel.org Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH net-next v2 04/12] net: phy: marvell10g: indicate 88X33X0 only port control registers Date: Thu, 25 Mar 2021 14:12:42 +0100 Message-Id: <20210325131250.15901-5-kabel@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210325131250.15901-1-kabel@kernel.org> References: <20210325131250.15901-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Indicate via register names registers that are only valid for 88X33X0, not for 88E21X0. Signed-off-by: Marek Behún --- drivers/net/phy/marvell10g.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 881a0717846e..7552a658a513 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -78,10 +78,10 @@ enum { /* Vendor2 MMD registers */ MV_V2_PORT_CTRL = 0xf001, - MV_V2_PORT_CTRL_SWRST = BIT(15), - MV_V2_PORT_CTRL_PWRDOWN = BIT(11), - MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7, - MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6, + MV_V2_PORT_CTRL_PWRDOWN = BIT(11), + MV_V2_33X0_PORT_CTRL_SWRST = BIT(15), + MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7, + MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6, /* Temperature control/read registers (88X3310 only) */ MV_V2_TEMP_CTRL = 0xf08a, MV_V2_TEMP_CTRL_MASK = 0xc000, @@ -268,7 +268,7 @@ static int mv3310_power_up(struct phy_device *phydev) return ret; return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, - MV_V2_PORT_CTRL_SWRST); + MV_V2_33X0_PORT_CTRL_SWRST); } static int mv3310_reset(struct phy_device *phydev, u32 unit) @@ -479,8 +479,8 @@ static int mv3310_config_init(struct phy_device *phydev) val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); if (val < 0) return val; - priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) == - MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH); + priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) == + MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH); /* Enable EDPD mode - saving 600mW */ return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); From patchwork Thu Mar 25 13:12:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 409326 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F6F7C433E0 for ; Thu, 25 Mar 2021 13:14:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3027861A2D for ; Thu, 25 Mar 2021 13:14:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230481AbhCYNOH (ORCPT ); Thu, 25 Mar 2021 09:14:07 -0400 Received: from mail.kernel.org ([198.145.29.99]:52622 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230358AbhCYNNf (ORCPT ); Thu, 25 Mar 2021 09:13:35 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id A0786619EE; Thu, 25 Mar 2021 13:13:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1616678015; bh=I4nxHoJrkAa+c0GD2PcJsIKsqldCGduF2pxnr5ItC2U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vQ8M48xkhJEEGScggkhOB7naUmBtJ+xUGYk7D3NIedVBuLLynVKp1/cUtCDt5mlbo s1VCQP+tzSIZlXYHiWqRGl/omjGaq7T5sM92ivVFrZ0cXejXwdhkt6MkqulHMrtR5I dsJNw03n5GO+7adXm32m3BPhmQtobn77hcv+il4STaiDCl8mGhsDcAG1Z8TTTp9TPc 15vNgx4g4P19reTnwddm3GU1xv/CiUoX7X9BJmalXBJfoiIbRZfYZ2ykZoi/uLNuaM e44c/jVFI1NUjpP81LPcaaXp5lr5/7kQw8TpY2lbmc0nEPJq/bTPvPbi2gwbH2OBqV JMF0Dtr4iMQeg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: netdev@vger.kernel.org, Andrew Lunn , "David S . Miller" , Florian Fainelli , Heiner Kallweit , Russell King , kuba@kernel.org Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH net-next v2 06/12] net: phy: marvell10g: add MACTYPE definitions for 88E21XX Date: Thu, 25 Mar 2021 14:12:44 +0100 Message-Id: <20210325131250.15901-7-kabel@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210325131250.15901-1-kabel@kernel.org> References: <20210325131250.15901-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add all MACTYPE definitions for 88E2110, 88E2180, 88E2111 and 88E2181. Signed-off-by: Marek Behún --- drivers/net/phy/marvell10g.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 7d9a45437b69..556c9b43860e 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -35,6 +35,15 @@ enum { MV_PMA_FW_VER0 = 0xc011, MV_PMA_FW_VER1 = 0xc012, + MV_PMA_21X0_PORT_CTRL = 0xc04a, + MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15), + MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7, + MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0, + MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1, + MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2, + MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4, + MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5, + MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6, MV_PMA_BOOT = 0xc050, MV_PMA_BOOT_FATAL = BIT(0), From patchwork Thu Mar 25 13:12:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 409325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C157C433E2 for ; Thu, 25 Mar 2021 13:14:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 54F0B619CB for ; Thu, 25 Mar 2021 13:14:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230523AbhCYNOM (ORCPT ); Thu, 25 Mar 2021 09:14:12 -0400 Received: from mail.kernel.org ([198.145.29.99]:52726 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230078AbhCYNNl (ORCPT ); Thu, 25 Mar 2021 09:13:41 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 271BB619FE; Thu, 25 Mar 2021 13:13:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1616678020; bh=Dh8a329t1G45WAPNL3cfzHwBiAaBysqzITPpx1n4aHw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XYvNH4zcRKt/M1MEeQ0AQyF8tUVqf00OwUXG5tMHrUEH5M4m33YNtN2dTeuguHbbF wGWJJF1ZrcAOOS9wsdWpMx3JcuyxFmrP/douYljnNCRPK5OGMwpKuvpYsiUo0rBvQp SF8oGOKoDNmOwUhDYD4sjM7eAfhX0E68y3/cA5725eQJCb1HGa50i9V6/fp0PvlQrP OdruZzoS2RwSIB2gUUgIr8+Lbw74XDKAZUhtm/Wtgc9Pg9P82XxYlj2EDZG/LDK2wj I3N3ZyTy0hqJzk8C4uH6Hv4bGz0Mwh5vc3fuL7YcBlF2xype2IzWczfzTySER6elNq Vuypee3V0bMug== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: netdev@vger.kernel.org, Andrew Lunn , "David S . Miller" , Florian Fainelli , Heiner Kallweit , Russell King , kuba@kernel.org Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH net-next v2 09/12] net: phy: marvell10g: support other MACTYPEs Date: Thu, 25 Mar 2021 14:12:47 +0100 Message-Id: <20210325131250.15901-10-kabel@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210325131250.15901-1-kabel@kernel.org> References: <20210325131250.15901-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Currently the only "changing" MACTYPE we support is when the PHY changes between 10gbase-r / 5gbase-r / 2500base-x / sgmii Add support for xaui / 5gbase-r / 2500base-x / sgmii rxaui / 5gbase-r / 2500base-x / sgmii Signed-off-by: Marek Behún --- drivers/net/phy/marvell10g.c | 95 +++++++++++++++++++++++------------- 1 file changed, 60 insertions(+), 35 deletions(-) diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 025473512581..6df67c12f012 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -524,10 +524,21 @@ static int mv2110_init_interface(struct phy_device *phydev) mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK; - if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) { + if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) priv->rate_match = true; + + if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII || + (priv->model == MV_MODEL_88E218X && + (mactype == MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII || + mactype == MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII))) + priv->const_interface = PHY_INTERFACE_MODE_USXGMII; + else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) priv->const_interface = PHY_INTERFACE_MODE_10GBASER; - } + else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER || + mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN) + priv->const_interface = PHY_INTERFACE_MODE_NA; + else + return -EINVAL; return 0; } @@ -549,13 +560,23 @@ static int mv3310_init_interface(struct phy_device *phydev) priv->model == MV_MODEL_88X3310)) priv->rate_match = true; - if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) + if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII) + priv->const_interface = PHY_INTERFACE_MODE_USXGMII; + else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH || + mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN || + mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER) priv->const_interface = PHY_INTERFACE_MODE_10GBASER; - else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH) + else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH || + mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI || + (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN && + priv->model == MV_MODEL_88X3340)) priv->const_interface = PHY_INTERFACE_MODE_RXAUI; else if (priv->model == MV_MODEL_88X3310 && - mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH) + (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH || + mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI)) priv->const_interface = PHY_INTERFACE_MODE_XAUI; + else + return -EINVAL; return 0; } @@ -585,8 +606,10 @@ static int mv3310_config_init(struct phy_device *phydev) err = mv2110_init_interface(phydev); else err = mv3310_init_interface(phydev); - if (err < 0) + if (err < 0) { + phydev_err(phydev, "MACTYPE configuration invalid\n"); return err; + } /* Enable EDPD mode - saving 600mW */ return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); @@ -696,6 +719,9 @@ static void mv3310_update_interface(struct phy_device *phydev) { struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); + if (!phydev->link) + return; + /* In all of the "* with Rate Matching" modes the PHY interface is fixed * at 10Gb. The PHY adapts the rate to actual wire speed with help of * internal 16KB buffer. @@ -705,35 +731,34 @@ static void mv3310_update_interface(struct phy_device *phydev) return; } - if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || - phydev->interface == PHY_INTERFACE_MODE_2500BASEX || - phydev->interface == PHY_INTERFACE_MODE_5GBASER || - phydev->interface == PHY_INTERFACE_MODE_10GBASER) && - phydev->link) { - /* The PHY automatically switches its serdes interface (and - * active PHYXS instance) between Cisco SGMII, 10GBase-R and - * 2500BaseX modes according to the speed. Florian suggests - * setting phydev->interface to communicate this to the MAC. - * Only do this if we are already in one of the above modes. - */ - switch (phydev->speed) { - case SPEED_10000: - phydev->interface = PHY_INTERFACE_MODE_10GBASER; - break; - case SPEED_5000: - phydev->interface = PHY_INTERFACE_MODE_5GBASER; - break; - case SPEED_2500: - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; - break; - case SPEED_1000: - case SPEED_100: - case SPEED_10: - phydev->interface = PHY_INTERFACE_MODE_SGMII; - break; - default: - break; - } + if (priv->const_interface == PHY_INTERFACE_MODE_USXGMII) { + phydev->interface = PHY_INTERFACE_MODE_USXGMII; + return; + } + + /* The PHY automatically switches its serdes interface (and active PHYXS + * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / + * xaui / rxaui modes according to the speed. + * Florian suggests setting phydev->interface to communicate this to the + * MAC. Only do this if we are already in one of the above modes. + */ + switch (phydev->speed) { + case SPEED_10000: + phydev->interface = priv->const_interface; + break; + case SPEED_5000: + phydev->interface = PHY_INTERFACE_MODE_5GBASER; + break; + case SPEED_2500: + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; + break; + case SPEED_1000: + case SPEED_100: + case SPEED_10: + phydev->interface = PHY_INTERFACE_MODE_SGMII; + break; + default: + break; } } From patchwork Thu Mar 25 13:12:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 409324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C4E6C433E5 for ; Thu, 25 Mar 2021 13:14:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EC718619CB for ; Thu, 25 Mar 2021 13:14:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231183AbhCYNOP (ORCPT ); Thu, 25 Mar 2021 09:14:15 -0400 Received: from mail.kernel.org ([198.145.29.99]:52808 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230163AbhCYNNq (ORCPT ); Thu, 25 Mar 2021 09:13:46 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 9FBB1619A3; Thu, 25 Mar 2021 13:13:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1616678026; bh=pYFKKdkwNtpe0POAWCWJVc+BLLceRhX5L8OI7ja2qt0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z3OH+Mgyi10kNKPKjllRXPcxe6rGpoBSz5aO8J92XjenT/ifZjXcfa9HYJIOeblgo ATqpkYIOI833BSPBcEr6lHyTMBP1BRxOvo6HPpygcdY7DV/54bcxkNSbKo2BjP+vz5 LsYqO3g6qIgAANO7HvKNOP3JHlSc34wbg4LSTJdlRKxsJH8zeFay85sWz2FqYwYp/o DE92d2BEfbNYV2Qg8P+70H8m9l3z+ivloRqLXX4nyZ0qPbmpfhQ+KiQiCIEoT4QXIi SGPBjTOR3w+y0PckiPEPJ/YLzel1ZiBJ8yi7m2LuO8Sm34aLozP242HWHb57vkg4Vu ZpWSd8ke+Gisg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: netdev@vger.kernel.org, Andrew Lunn , "David S . Miller" , Florian Fainelli , Heiner Kallweit , Russell King , kuba@kernel.org Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH net-next v2 12/12] net: phy: marvell10g: better check for compatible interface Date: Thu, 25 Mar 2021 14:12:50 +0100 Message-Id: <20210325131250.15901-13-kabel@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210325131250.15901-1-kabel@kernel.org> References: <20210325131250.15901-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Do a model-specific check for compatible interface: - 88X3340 does not support XAUI - 88E21XX does not support XAUI and RXAUI - 88E21X1 does not support 5gbase-r Signed-off-by: Marek Behún --- drivers/net/phy/marvell10g.c | 38 ++++++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 84f24fcb832c..510e27c766e6 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -124,6 +124,7 @@ enum mv3310_model { struct mv3310_priv { enum mv3310_model model; + bool has_5g; u32 firmware_ver; phy_interface_t const_interface; @@ -399,7 +400,7 @@ static int mv3310_probe(struct phy_device *phydev) { struct mv3310_priv *priv; u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; - bool has_5g, has_macsec; + bool has_macsec; int ret, nports; if (!phydev->is_c45 || @@ -451,6 +452,7 @@ static int mv3310_probe(struct phy_device *phydev) return ret; has_macsec = !(ret & MV_PMA_XGSTAT_NO_MACSEC); + priv->has_5g = true; if (nports == 4) priv->model = MV_MODEL_88X3340; @@ -462,7 +464,7 @@ static int mv3310_probe(struct phy_device *phydev) if (ret < 0) return ret; - has_5g = ret & MDIO_PCS_SPEED_5G; + priv->has_5g = ret & MDIO_PCS_SPEED_5G; if (nports == 8) priv->model = MV_MODEL_88E218X; @@ -476,7 +478,7 @@ static int mv3310_probe(struct phy_device *phydev) switch (priv->model) { case MV_MODEL_88E211X: case MV_MODEL_88E218X: - phydev_info(phydev, "model 88E21%d%d\n", nports, !has_5g); + phydev_info(phydev, "model 88E21%d%d\n", nports, !priv->has_5g); break; case MV_MODEL_88X3310: case MV_MODEL_88X3340: @@ -543,6 +545,15 @@ static int mv2110_init_interface(struct phy_device *phydev) struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); int mactype; + /* Check that the PHY interface type is compatible */ + if (phydev->interface != PHY_INTERFACE_MODE_SGMII && + phydev->interface != PHY_INTERFACE_MODE_2500BASEX && + (phydev->interface != PHY_INTERFACE_MODE_5GBASER || + !priv->has_5g) && + phydev->interface != PHY_INTERFACE_MODE_10GBASER && + phydev->interface != PHY_INTERFACE_MODE_USXGMII) + return -ENODEV; + mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL); if (mactype < 0) return mactype; @@ -573,6 +584,17 @@ static int mv3310_init_interface(struct phy_device *phydev) struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); int mactype; + /* Check that the PHY interface type is compatible */ + if (phydev->interface != PHY_INTERFACE_MODE_SGMII && + phydev->interface != PHY_INTERFACE_MODE_2500BASEX && + phydev->interface != PHY_INTERFACE_MODE_5GBASER && + (phydev->interface != PHY_INTERFACE_MODE_XAUI || + priv->model == MV_MODEL_88X3340) && + phydev->interface != PHY_INTERFACE_MODE_RXAUI && + phydev->interface != PHY_INTERFACE_MODE_10GBASER && + phydev->interface != PHY_INTERFACE_MODE_USXGMII) + return -ENODEV; + mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); if (mactype < 0) return mactype; @@ -610,16 +632,6 @@ static int mv3310_config_init(struct phy_device *phydev) { int err; - /* Check that the PHY interface type is compatible */ - if (phydev->interface != PHY_INTERFACE_MODE_SGMII && - phydev->interface != PHY_INTERFACE_MODE_2500BASEX && - phydev->interface != PHY_INTERFACE_MODE_5GBASER && - phydev->interface != PHY_INTERFACE_MODE_XAUI && - phydev->interface != PHY_INTERFACE_MODE_RXAUI && - phydev->interface != PHY_INTERFACE_MODE_10GBASER && - phydev->interface != PHY_INTERFACE_MODE_USXGMII) - return -ENODEV; - phydev->mdix_ctrl = ETH_TP_MDI_AUTO; /* Power up so reset works */