From patchwork Thu Mar 25 06:19:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 409232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50472C433C1 for ; Thu, 25 Mar 2021 06:20:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 11DF161A0E for ; Thu, 25 Mar 2021 06:20:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229629AbhCYGTu (ORCPT ); Thu, 25 Mar 2021 02:19:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229493AbhCYGTh (ORCPT ); Thu, 25 Mar 2021 02:19:37 -0400 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63A8AC06174A; Wed, 24 Mar 2021 23:19:37 -0700 (PDT) Received: by mail-pj1-x102d.google.com with SMTP id kr3-20020a17090b4903b02900c096fc01deso482271pjb.4; Wed, 24 Mar 2021 23:19:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FoZkhqfpmRbVSsWSfogUf6yqaswcADGilysTVzy6KNo=; b=BoUNREw/iNHUAVyebP5ErSn9LjoHCABwNdhX/vDVJXJ+l/I6QcVSPytwhQS7JuJ0yp LDl82iCrvfSlrx85J90D3wkgCGPjjXpitTVkHmRfvD5XU+VcRrVEIr9TzOVTF6ggoric U5dLMz2zgGgItaJFFvJBpvAI2c6ymFjK87QeIdmr0e8wJRjkCbObFQ4WMI19sicb7iXD 5w5u9T4/JK5QPwe8wN2c9oWHMMrgAPDHSes6w1v9fjNCuIFmcuGEbnjOoVd8sTW/r5pF aXQ1CWPpWyif9HvSYLzJetzen10vRqX+FSl0p1409PGiB7EbX3ElCNTOQoAgu/fOdg9B dbMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FoZkhqfpmRbVSsWSfogUf6yqaswcADGilysTVzy6KNo=; b=Vao+h+uk8dFsRK7V0QoAqz3wu89Ou/QB7Kv+29A0SBuH/pV57ylD6KTAdCTK/ToXr8 48IeLq/YF5KKLrrqNcjDtG7aH8GwDl+LAn0eyW2QxBUMxeQd/xZLLzdvQ0Zj1scbxGqB reBsVAz9op3JFhghDsR6tXRz0tmk6hkxGdxHHVSWTD995PejmUYVT731t20WGAKzsukk L3jshqvU71qVNs5kinRT4qx188LdL1xGj4LJaqVXx83iQ1DA/Yxju+k/b/NEJdOSmZlQ l9KDto7a3uA4Qv8bFi6OiEGmA2kUFLUK8KgLQYMKa90tMhpZTpXU3oG3e8g2LiPagf/P C3TQ== X-Gm-Message-State: AOAM532a4jzwPD3zg8s02LcHa4DN9G0xgGucf8yXXbA8tT+AoinOmS/O k4Vmv7pI/MKVBdgVXONN/OU= X-Google-Smtp-Source: ABdhPJyZj5vBE7ex4Q7fFp4YugB2dszyYOGnnv0XOSXneqAmFDlZ/BbNXwve4sjpLlHK+x+qEUBNZA== X-Received: by 2002:a17:90a:db51:: with SMTP id u17mr7217623pjx.194.1616653176862; Wed, 24 Mar 2021 23:19:36 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id b19sm4393086pfo.7.2021.03.24.23.19.32 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Mar 2021 23:19:36 -0700 (PDT) From: dillon.minfei@gmail.com To: robh@kernel.org, valentin.caron@foss.st.com, Alexandre.torgue@foss.st.com, rong.a.chen@intel.com, a.fatoum@pengutronix.de, mcoquelin.stm32@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, vladimir.murzin@arm.com, afzal.mohd.ma@gmail.com, gregkh@linuxfoundation.org, erwan.leray@foss.st.com, erwan.leray@st.com, linux-serial@vger.kernel.org, lkp@intel.com Cc: dillon min Subject: [PATCH v5 4/9] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750 Date: Thu, 25 Mar 2021 14:19:17 +0800 Message-Id: <1616653162-19954-3-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616653162-19954-1-git-send-email-dillon.minfei@gmail.com> References: <1616653162-19954-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: dillon min This patch is intend to add support stm32h750 value line, just add stm32h7-pinctrl.dtsi for extending, with following changes: - rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi - move compatible string "st,stm32h743-pinctrl" from stm32h7-pinctrl.dtsi to stm32h743-pinctrl.dtsi - move 'pin-controller' from stm32h7-pinctrl.dtsi to stm32h743.dtsi, to fix make dtbs_check warrnings arch/arm/boot/dts/stm32h750i-art-pi.dt.yaml: soc: 'i2c@40005C00', 'i2c@58001C00' do not match any of the regexes: '@(0|[1-9a-f][0-9a-f]*)$', '^[^@]+$', 'pinctrl-[0-9]+' Signed-off-by: dillon min --- v5: no changes arch/arm/boot/dts/stm32h7-pinctrl.dtsi | 274 +++++++++++++++++++++++++++ arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 307 +------------------------------ 2 files changed, 280 insertions(+), 301 deletions(-) create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi new file mode 100644 index 000000000000..fbab41a01af5 --- /dev/null +++ b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi @@ -0,0 +1,274 @@ +/* + * Copyright 2017 - Alexandre Torgue + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +&pinctrl { + i2c1_pins_a: i2c1-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + ethernet_rmii: rmii-0 { + pins { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + + usart1_pins: usart1-0 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart2_pins: usart2-0 { + pins1 { + pinmux = ; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart3_pins: usart3-0 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + uart4_pins: uart4-0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + usbotg_hs_pins_a: usbotg-hs-0 { + pins { + pinmux = , /* ULPI_NXT */ + , /* ULPI_DIR> */ + , /* ULPI_STP> */ + , /* ULPI_CK> */ + , /* ULPI_D0> */ + , /* ULPI_D1> */ + , /* ULPI_D2> */ + , /* ULPI_D3> */ + , /* ULPI_D4> */ + , /* ULPI_D5> */ + , /* ULPI_D6> */ + ; /* ULPI_D7> */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + spi1_pins: spi1-0 { + pins1 { + pinmux = , + /* SPI1_CLK */ + ; + /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; + /* SPI1_MISO */ + bias-disable; + }; + }; +}; + diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi index fa5dcb6a5fdd..6b1e115307b9 100644 --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi @@ -1,306 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2017 - Alexandre Torgue - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. */ -#include +#include "stm32h7-pinctrl.dtsi" -/ { - soc { - pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32h743-pinctrl"; - ranges = <0 0x58020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@58020000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA_CK>; - st,bank-name = "GPIOA"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiob: gpio@58020400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc GPIOB_CK>; - st,bank-name = "GPIOB"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioc: gpio@58020800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc GPIOC_CK>; - st,bank-name = "GPIOC"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiod: gpio@58020c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc GPIOD_CK>; - st,bank-name = "GPIOD"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioe: gpio@58021000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOE_CK>; - st,bank-name = "GPIOE"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiof: gpio@58021400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc GPIOF_CK>; - st,bank-name = "GPIOF"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiog: gpio@58021800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc GPIOG_CK>; - st,bank-name = "GPIOG"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioh: gpio@58021c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc GPIOH_CK>; - st,bank-name = "GPIOH"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioi: gpio@58022000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOI_CK>; - st,bank-name = "GPIOI"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpioj: gpio@58022400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc GPIOJ_CK>; - st,bank-name = "GPIOJ"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpiok: gpio@58022800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc GPIOK_CK>; - st,bank-name = "GPIOK"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c1_pins_a: i2c1-0 { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - ethernet_rmii: rmii-0 { - pins { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - ; /* SDMMC1_CK */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - pins2{ - pinmux = ; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0 */ - , /* SDMMC1_D1 */ - , /* SDMMC1_D2 */ - , /* SDMMC1_D3 */ - , /* SDMMC1_CK */ - ; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_dir_pins_a: sdmmc1-dir-0 { - pins1 { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - ; /* SDMMC1_CDIR */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - pins2{ - pinmux = ; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { - pins { - pinmux = , /* SDMMC1_D0DIR */ - , /* SDMMC1_D123DIR */ - , /* SDMMC1_CDIR */ - ; /* SDMMC1_CKIN */ - }; - }; - - usart1_pins: usart1-0 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart2_pins: usart2-0 { - pins1 { - pinmux = ; /* USART2_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART2_RX */ - bias-disable; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = , /* ULPI_NXT */ - , /* ULPI_DIR> */ - , /* ULPI_STP> */ - , /* ULPI_CK> */ - , /* ULPI_D0> */ - , /* ULPI_D1> */ - , /* ULPI_D2> */ - , /* ULPI_D3> */ - , /* ULPI_D4> */ - , /* ULPI_D5> */ - , /* ULPI_D6> */ - ; /* ULPI_D7> */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - }; - }; +&pinctrl{ + compatible = "st,stm32h743-pinctrl"; }; From patchwork Thu Mar 25 06:19:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 409230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECF98C433E8 for ; Thu, 25 Mar 2021 06:20:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF09C61A0E for ; Thu, 25 Mar 2021 06:20:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229651AbhCYGTu (ORCPT ); Thu, 25 Mar 2021 02:19:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229533AbhCYGTl (ORCPT ); Thu, 25 Mar 2021 02:19:41 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A6F3C06174A; Wed, 24 Mar 2021 23:19:41 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id ha17so612279pjb.2; Wed, 24 Mar 2021 23:19:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hMTMgDP5KgynP82z79q6WdnAk8Vb5kqZCsaqfEY6s6w=; b=ZUzX3kSMQx0D3ecxwsVzDU7oykbu3A4V/Be9Rg3fxvHz4pXA16tVgS8F5LelhuaD+j DPeDeJF0q2Gk032lhqq0nvgfinR5X1NdwV8DYSwVLbcuP31ymHJHAY3RD57x+4RDoAxz gRpDt4+IQWCJCEBXWV82vZZSsUkfymnAt/NraHa9ScsG4tEhRFRbBki8p8CbUMfCKn7+ YdInz2MlbAssdqmUf1gtJMAOMdXbD7WJPxe4QSQnuEjW0IuOPG+Z+X0jd0gyJ++Rc5je YJyTh/rK02guSJOACfX7KFEnlUmf/zOHDutiA5+ljmM1ABd/P4aHXayx/zz1dMhlTGOl ib2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hMTMgDP5KgynP82z79q6WdnAk8Vb5kqZCsaqfEY6s6w=; b=ImJTJyf+DKJWeS9SkWEGuT+fy1tvEaLiIlLsT2g03jRT+RbV3eb2kzy7wgTJfPPu5w UoyL+16/OwnMv1U7CNXzzeunLO6qcd666UCOPossYQshlJcjWh/TjN8jyA4iM0Wsb2ia IX6c8otkr89ci7VseYndCBuXvu8KV2h3T+hwXrwU99OEGuydpjHfgUC7/Q84XwQ8uDFs HwKNWHf7g4aO9oj8qj/lhXtvwq2oyeXFJsaHDChkMOC74DynhNHtsZFwScvL1ln5Te6x 2yo90Ci1yndRJ5mqa4olZ+pjghhUzZ8j18OHt38KL1QD9FgI3Umvv+bRNlcMgK5id7G1 OOJA== X-Gm-Message-State: AOAM532X66AJKa8OIknfi5P0hyXoyxvQgNo7HsoZOrz62if1uPNCEhEc uA/WZsEUwWvNZqv+irNpe+c= X-Google-Smtp-Source: ABdhPJxsn1s7ZxAnDAyfj8LK68kGgP/q0iGXelo6xxh8qY6gTqMDj903e3alPP9rxHrNFtWFIbmfag== X-Received: by 2002:a17:90a:cb0a:: with SMTP id z10mr7385707pjt.170.1616653181218; Wed, 24 Mar 2021 23:19:41 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id b19sm4393086pfo.7.2021.03.24.23.19.37 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Mar 2021 23:19:40 -0700 (PDT) From: dillon.minfei@gmail.com To: robh@kernel.org, valentin.caron@foss.st.com, Alexandre.torgue@foss.st.com, rong.a.chen@intel.com, a.fatoum@pengutronix.de, mcoquelin.stm32@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, vladimir.murzin@arm.com, afzal.mohd.ma@gmail.com, gregkh@linuxfoundation.org, erwan.leray@foss.st.com, erwan.leray@st.com, linux-serial@vger.kernel.org, lkp@intel.com Cc: dillon min Subject: [PATCH v5 5/9] ARM: dts: stm32: add stm32h750-pinctrl.dtsi Date: Thu, 25 Mar 2021 14:19:18 +0800 Message-Id: <1616653162-19954-4-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616653162-19954-1-git-send-email-dillon.minfei@gmail.com> References: <1616653162-19954-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: dillon min This patch add stm32h750-pinctrl.dtsi which just reference stm32h7-pinctrl.dtsi Signed-off-by: dillon min --- v5: no changes arch/arm/boot/dts/stm32h750-pinctrl.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 arch/arm/boot/dts/stm32h750-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32h750-pinctrl.dtsi b/arch/arm/boot/dts/stm32h750-pinctrl.dtsi new file mode 100644 index 000000000000..ef8c4d881dba --- /dev/null +++ b/arch/arm/boot/dts/stm32h750-pinctrl.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Dillon Min for STMicroelectronics. + */ + +#include "stm32h7-pinctrl.dtsi" + +&pinctrl{ + compatible = "st,stm32h750-pinctrl"; +}; + From patchwork Thu Mar 25 06:19:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 409229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 538F5C433DB for ; Thu, 25 Mar 2021 06:21:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 24F8661A27 for ; Thu, 25 Mar 2021 06:21:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229592AbhCYGUh (ORCPT ); Thu, 25 Mar 2021 02:20:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229781AbhCYGTy (ORCPT ); Thu, 25 Mar 2021 02:19:54 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6470DC06174A; Wed, 24 Mar 2021 23:19:54 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id c204so978145pfc.4; Wed, 24 Mar 2021 23:19:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=31z6xcgVpgNt2rqQ4i917PEU8w/kVuNEF1a++fiq5dw=; b=nQ6TerCFDVxmOIgBYkQXfbaZtZgE4MkWwQ3DeGjNyiTbHdjhYHhK7j8av0reETN1yK 01VZiWl8qS5kxwekLzQAK2Dp2gQpoU+OYFYtwKv+mtQwKW7srdnVdLgKpUwxQBse4Dta RKA2WPFUCvMGhriQjsKI3LK6w1GYY4alUwEP8OgcBMc8blPbb+kUNiByY8KQ3rNFan18 Btyw0aMcpHJ+8bZSk61ZPhS4kVLz5aj272T47rUrKKGA6XxUOBCSgUA9bIDm/aqFTsHd ec3e/IpuZZ1XfWZLxVIOzjzq6lddK3j1nOzC2IiIX/BjSvZsJwUfp9DpUwaCcliUCDFU P+9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=31z6xcgVpgNt2rqQ4i917PEU8w/kVuNEF1a++fiq5dw=; b=gKy48PM1iNgE8QRPUIWdK0Yo2+R2UPxqQFCyqMxy+zkCi7j8h6OwGsv1+OIshHdu8U BU5KOM23w7zTL8WC9/HRWruuFaT326a2BdQ9GlcDNE9O93Vg4wCUI3tdIIwTpR1CLg/K hfSCYdAchdU5KcWvBeMZzy23c5NJk4usJpIt5U8wTLJnm57LxF5agsNO7MUw7QcHsVy/ Pv4nWZvlZL+rCA66RoZha+PKiVBdeuLjqu0tPhXaI+dpy+ivNVFIDMrMZUOebb9foTzu Rqjht30SEgXY1SDaOD4wZ9XzVu2DHbNQME4S+HAbdO1DHn9RJmW+3weyrEpJq/gz21ik ms/g== X-Gm-Message-State: AOAM530Dvgejuxuio6p33Y6+YHT2bMUWXwFeOnlWZk1Eg3nqO8TMxOwE cuuDCuK58xMMe4A7gT1U3kE= X-Google-Smtp-Source: ABdhPJxtsQ03IwysDluyYZpJWgXX97sGPpF47gdNS8CmZlpk8MrPym7e4+FukgzZIFGl0r0dsLH8FQ== X-Received: by 2002:aa7:91d1:0:b029:1fe:2a02:73b9 with SMTP id z17-20020aa791d10000b02901fe2a0273b9mr6683276pfa.2.1616653194038; Wed, 24 Mar 2021 23:19:54 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id b19sm4393086pfo.7.2021.03.24.23.19.50 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Mar 2021 23:19:53 -0700 (PDT) From: dillon.minfei@gmail.com To: robh@kernel.org, valentin.caron@foss.st.com, Alexandre.torgue@foss.st.com, rong.a.chen@intel.com, a.fatoum@pengutronix.de, mcoquelin.stm32@gmail.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, vladimir.murzin@arm.com, afzal.mohd.ma@gmail.com, gregkh@linuxfoundation.org, erwan.leray@foss.st.com, erwan.leray@st.com, linux-serial@vger.kernel.org, lkp@intel.com Cc: dillon min Subject: [PATCH v5 8/9] pinctrl: stm32: Add STM32H750 MCU pinctrl support Date: Thu, 25 Mar 2021 14:19:21 +0800 Message-Id: <1616653162-19954-7-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616653162-19954-1-git-send-email-dillon.minfei@gmail.com> References: <1616653162-19954-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: dillon min This patch adds STM32H750 pinctrl and GPIO support since stm32h750 has the same pin alternate functions with stm32h743, so just reuse the stm32h743's pinctrl driver Signed-off-by: dillon min --- v5: no changes drivers/pinctrl/stm32/Kconfig | 2 +- drivers/pinctrl/stm32/pinctrl-stm32h743.c | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index f36f29113370..fb1ffc94c57f 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -35,7 +35,7 @@ config PINCTRL_STM32F769 select PINCTRL_STM32 config PINCTRL_STM32H743 - bool "STMicroelectronics STM32H743 pin control" if COMPILE_TEST && !MACH_STM32H743 + bool "STMicroelectronics STM32H743/STM32H750 pin control" if COMPILE_TEST && !MACH_STM32H743 depends on OF && HAS_IOMEM default MACH_STM32H743 select PINCTRL_STM32 diff --git a/drivers/pinctrl/stm32/pinctrl-stm32h743.c b/drivers/pinctrl/stm32/pinctrl-stm32h743.c index ffe7b5271506..700206c7bc11 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32h743.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32h743.c @@ -1966,6 +1966,9 @@ static const struct of_device_id stm32h743_pctrl_match[] = { .compatible = "st,stm32h743-pinctrl", .data = &stm32h743_match_data, }, + { .compatible = "st,stm32h750-pinctrl", + .data = &stm32h743_match_data, + }, { } };