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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.52.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:52:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:16 -0700 Message-Id: <20180516155243.16937-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 01/28] fpu/softfloat: Fix conversion from uint64 to float128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-stable@nongnu.org, Petr Tesarik Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Petr Tesarik The significand is passed to normalizeRoundAndPackFloat128() as high first, low second. The current code passes the integer first, so the result is incorrectly shifted left by 64 bits. This bug affects the emulation of s390x instruction CXLGBR (convert from logical 64-bit binary-integer operand to extended BFP result). Cc: qemu-stable@nongnu.org Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Petr Tesarik Message-Id: <20180511071052.1443-1-ptesarik@suse.com> Signed-off-by: Richard Henderson --- fpu/softfloat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.0 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index bc0f52fa54..d07419324a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3147,7 +3147,7 @@ float128 uint64_to_float128(uint64_t a, float_status *status) if (a == 0) { return float128_zero; } - return normalizeRoundAndPackFloat128(0, 0x406E, a, 0, status); + return normalizeRoundAndPackFloat128(0, 0x406E, 0, a, status); } From patchwork Wed May 16 15:52:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136015 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1101059lji; Wed, 16 May 2018 08:56:03 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqmLt4Ac/TAyN1RTFKDuy/MtcyBSvELAPxsRS4OO3Mf8XKZFJMq/Sn9h39foLNN54DSCSh0 X-Received: by 2002:a0c:bd25:: with SMTP id m37-v6mr1450742qvg.209.1526486163272; Wed, 16 May 2018 08:56:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526486163; cv=none; d=google.com; s=arc-20160816; b=O2ZvUrcfeu/hDO3lttoCN+30BBgz02gbG1v20vwWRROIo7BDWaIJ7BiCfwe8xVumBU T6Hr/HH6+96D1kehuibJ1+RyoRvabU+EY1G1xFFUdYu82FxXHYPxna2a7CbBm7eJ1zYM o5RScq2DfVuGR9fbjSzdCU7s0iqR6q6VjIfB0zKlJ4D2IZ4PvhZxtw/6eJCr0A//Du/4 0s+KYPVGXqrPH7P0Y46hMryrTjTUbOgwV2z1uw5D+UWdi9W0HPEVzEGHi+pRGybuL12I peoldzPEEXQNWJff5zhhfYcXoStvuCYFoF08LKq8P4YhUfI6o2KuGaowKf1hYuehGOl3 o0tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=vUbiquEpPpv1Jwk4MPNGVRk9CWrHz238T8o7L7traPo=; b=yL6o4UyTSKQM27XKV/X77B/9O0BQZQ4Z1+ZEL9r5czHfgw7MempD8/WPnSukOkLZ1p EBYzETIEqGSpwgkUMT5wb4Kt8s+Xfdsg04xctnlBN/IgKV/ivjVIbWmpooklr2tFLUGo XQmHlXLd1M/op0WyHvPXHILdxsnWN38E02MadBkNV0EVhcdXZ+IJ7/T5VGZMOJDXDMUs iHfjmD16Rab+/3XRMrYAA4XepFNnbdxjKcCHqtP/kkGnO79mKqjbEIz3YzP3IfT2iz6J rRGdsjFKcrvUQSpXuMWWgVmis5IdSzw1A5gd2y1VatWOPCobKclIkm0rFVTcf+hRGJNO aNuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XBjyuNtw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.52.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:52:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:17 -0700 Message-Id: <20180516155243.16937-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 02/28] fpu/softfloat: Merge NO_SIGNALING_NANS definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the ifdef inside the relevant functions instead of duplicating the function declarations. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 100 +++++++++++++++---------------------- 1 file changed, 40 insertions(+), 60 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 27834af0de..58b05718c8 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -233,17 +233,6 @@ typedef struct { uint64_t high, low; } commonNaNT; -#ifdef NO_SIGNALING_NANS -int float16_is_quiet_nan(float16 a_, float_status *status) -{ - return float16_is_any_nan(a_); -} - -int float16_is_signaling_nan(float16 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the half-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -251,12 +240,16 @@ int float16_is_signaling_nan(float16 a_, float_status *status) int float16_is_quiet_nan(float16 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float16_is_any_nan(a_); +#else uint16_t a = float16_val(a_); if (status->snan_bit_is_one) { return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); } else { return ((a & ~0x8000) >= 0x7C80); } +#endif } /*---------------------------------------------------------------------------- @@ -266,14 +259,17 @@ int float16_is_quiet_nan(float16 a_, float_status *status) int float16_is_signaling_nan(float16 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint16_t a = float16_val(a_); if (status->snan_bit_is_one) { return ((a & ~0x8000) >= 0x7C80); } else { return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the half-precision floating point value `a' is a @@ -333,17 +329,6 @@ static float16 commonNaNToFloat16(commonNaNT a, float_status *status) } } -#ifdef NO_SIGNALING_NANS -int float32_is_quiet_nan(float32 a_, float_status *status) -{ - return float32_is_any_nan(a_); -} - -int float32_is_signaling_nan(float32 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -351,12 +336,16 @@ int float32_is_signaling_nan(float32 a_, float_status *status) int float32_is_quiet_nan(float32 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float32_is_any_nan(a_); +#else uint32_t a = float32_val(a_); if (status->snan_bit_is_one) { return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); } else { return ((uint32_t)(a << 1) >= 0xFF800000); } +#endif } /*---------------------------------------------------------------------------- @@ -366,14 +355,17 @@ int float32_is_quiet_nan(float32 a_, float_status *status) int float32_is_signaling_nan(float32 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint32_t a = float32_val(a_); if (status->snan_bit_is_one) { return ((uint32_t)(a << 1) >= 0xFF800000); } else { return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the single-precision floating point value `a' is a @@ -744,17 +736,6 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) } } -#ifdef NO_SIGNALING_NANS -int float64_is_quiet_nan(float64 a_, float_status *status) -{ - return float64_is_any_nan(a_); -} - -int float64_is_signaling_nan(float64 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -762,6 +743,9 @@ int float64_is_signaling_nan(float64 a_, float_status *status) int float64_is_quiet_nan(float64 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float64_is_any_nan(a_); +#else uint64_t a = float64_val(a_); if (status->snan_bit_is_one) { return (((a >> 51) & 0xFFF) == 0xFFE) @@ -769,6 +753,7 @@ int float64_is_quiet_nan(float64 a_, float_status *status) } else { return ((a << 1) >= 0xFFF0000000000000ULL); } +#endif } /*---------------------------------------------------------------------------- @@ -778,6 +763,9 @@ int float64_is_quiet_nan(float64 a_, float_status *status) int float64_is_signaling_nan(float64 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint64_t a = float64_val(a_); if (status->snan_bit_is_one) { return ((a << 1) >= 0xFFF0000000000000ULL); @@ -785,8 +773,8 @@ int float64_is_signaling_nan(float64 a_, float_status *status) return (((a >> 51) & 0xFFF) == 0xFFE) && (a & LIT64(0x0007FFFFFFFFFFFF)); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the double-precision floating point value `a' is a @@ -899,17 +887,6 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) } } -#ifdef NO_SIGNALING_NANS -int floatx80_is_quiet_nan(floatx80 a_, float_status *status) -{ - return floatx80_is_any_nan(a_); -} - -int floatx80_is_signaling_nan(floatx80 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the extended double-precision floating-point value `a' is a | quiet NaN; otherwise returns 0. This slightly differs from the same @@ -918,6 +895,9 @@ int floatx80_is_signaling_nan(floatx80 a_, float_status *status) int floatx80_is_quiet_nan(floatx80 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return floatx80_is_any_nan(a); +#else if (status->snan_bit_is_one) { uint64_t aLow; @@ -929,6 +909,7 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *status) return ((a.high & 0x7FFF) == 0x7FFF) && (LIT64(0x8000000000000000) <= ((uint64_t)(a.low << 1))); } +#endif } /*---------------------------------------------------------------------------- @@ -939,6 +920,9 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *status) int floatx80_is_signaling_nan(floatx80 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else if (status->snan_bit_is_one) { return ((a.high & 0x7FFF) == 0x7FFF) && ((a.low << 1) >= 0x8000000000000000ULL); @@ -950,8 +934,8 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) && (uint64_t)(aLow << 1) && (a.low == aLow); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the extended double-precision floating point value @@ -1060,17 +1044,6 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) } } -#ifdef NO_SIGNALING_NANS -int float128_is_quiet_nan(float128 a_, float_status *status) -{ - return float128_is_any_nan(a_); -} - -int float128_is_signaling_nan(float128 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -1078,6 +1051,9 @@ int float128_is_signaling_nan(float128 a_, float_status *status) int float128_is_quiet_nan(float128 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float128_is_any_nan(a); +#else if (status->snan_bit_is_one) { return (((a.high >> 47) & 0xFFFF) == 0xFFFE) && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); @@ -1085,6 +1061,7 @@ int float128_is_quiet_nan(float128 a, float_status *status) return ((a.high << 1) >= 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); } +#endif } /*---------------------------------------------------------------------------- @@ -1094,6 +1071,9 @@ int float128_is_quiet_nan(float128 a, float_status *status) int float128_is_signaling_nan(float128 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else if (status->snan_bit_is_one) { return ((a.high << 1) >= 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); @@ -1101,8 +1081,8 @@ int float128_is_signaling_nan(float128 a, float_status *status) return (((a.high >> 47) & 0xFFFF) == 0xFFFE) && (a.low || (a.high & LIT64(0x00007FFFFFFFFFFF))); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the quadruple-precision floating point value `a' is From patchwork Wed May 16 15:52:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136017 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1102893lji; Wed, 16 May 2018 08:57:47 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrjrbfTZcaKSlr03K8fL+RTTgmpWmTAfP0rgBMTBLMHYtvr68aSNT2u0NyYEGFbSr73XsHH X-Received: by 2002:a0c:d5f5:: with SMTP id h50-v6mr1490537qvi.218.1526486267747; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.52.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:52:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:18 -0700 Message-Id: <20180516155243.16937-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::230 Subject: [Qemu-devel] [PULL 03/28] fpu/softfloat: Split floatXX_silence_nan from floatXX_maybe_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The new function assumes that the input is an SNaN and does not double-check. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 174 +++++++++++++++++++++++++------------ include/fpu/softfloat.h | 5 ++ 2 files changed, 123 insertions(+), 56 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 58b05718c8..4fc9ea4ac0 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -271,22 +271,35 @@ int float16_is_signaling_nan(float16 a_, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the half-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float16 float16_silence_nan(float16 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return float16_default_nan(status); + } else { + return a | (1 << 9); + } +#endif +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN if the half-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *----------------------------------------------------------------------------*/ -float16 float16_maybe_silence_nan(float16 a_, float_status *status) + +float16 float16_maybe_silence_nan(float16 a, float_status *status) { - if (float16_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { - return float16_default_nan(status); - } else { - uint16_t a = float16_val(a_); - a |= (1 << 9); - return make_float16(a); - } + if (float16_is_signaling_nan(a, status)) { + return float16_silence_nan(a, status); } - return a_; + return a; } /*---------------------------------------------------------------------------- @@ -367,30 +380,40 @@ int float32_is_signaling_nan(float32 a_, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the single-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float32 float32_silence_nan(float32 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { +# ifdef TARGET_HPPA + a &= ~0x00400000; + a |= 0x00200000; + return a; +# else + return float32_default_nan(status); +# endif + } else { + return a | (1 << 22); + } +#endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the single-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *----------------------------------------------------------------------------*/ -float32 float32_maybe_silence_nan(float32 a_, float_status *status) +float32 float32_maybe_silence_nan(float32 a, float_status *status) { - if (float32_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { -#ifdef TARGET_HPPA - uint32_t a = float32_val(a_); - a &= ~0x00400000; - a |= 0x00200000; - return make_float32(a); -#else - return float32_default_nan(status); -#endif - } else { - uint32_t a = float32_val(a_); - a |= (1 << 22); - return make_float32(a); - } + if (float32_is_signaling_nan(a, status)) { + return float32_silence_nan(a, status); } - return a_; + return a; } /*---------------------------------------------------------------------------- @@ -776,30 +799,41 @@ int float64_is_signaling_nan(float64 a_, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the double-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float64 float64_silence_nan(float64 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { +# ifdef TARGET_HPPA + a &= ~0x0008000000000000ULL; + a |= 0x0004000000000000ULL; + return a; +# else + return float64_default_nan(status); +# endif + } else { + return a | LIT64(0x0008000000000000); + } +#endif +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN if the double-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *----------------------------------------------------------------------------*/ -float64 float64_maybe_silence_nan(float64 a_, float_status *status) +float64 float64_maybe_silence_nan(float64 a, float_status *status) { - if (float64_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { -#ifdef TARGET_HPPA - uint64_t a = float64_val(a_); - a &= ~0x0008000000000000ULL; - a |= 0x0004000000000000ULL; - return make_float64(a); -#else - return float64_default_nan(status); -#endif - } else { - uint64_t a = float64_val(a_); - a |= LIT64(0x0008000000000000); - return make_float64(a); - } + if (float64_is_signaling_nan(a, status)) { + return float64_silence_nan(a, status); } - return a_; + return a; } /*---------------------------------------------------------------------------- @@ -937,6 +971,25 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the extended double-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +floatx80 floatx80_silence_nan(floatx80 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return floatx80_default_nan(status); + } else { + a.low |= LIT64(0xC000000000000000); + return a; + } +#endif +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN if the extended double-precision floating point value | `a' is a signaling NaN; otherwise returns `a'. @@ -945,12 +998,7 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status) { if (floatx80_is_signaling_nan(a, status)) { - if (status->snan_bit_is_one) { - a = floatx80_default_nan(status); - } else { - a.low |= LIT64(0xC000000000000000); - return a; - } + return floatx80_silence_nan(a, status); } return a; } @@ -1084,6 +1132,25 @@ int float128_is_signaling_nan(float128 a, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the quadruple-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float128 float128_silence_nan(float128 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return float128_default_nan(status); + } else { + a.high |= LIT64(0x0000800000000000); + return a; + } +#endif +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN if the quadruple-precision floating point value `a' is | a signaling NaN; otherwise returns `a'. @@ -1092,12 +1159,7 @@ int float128_is_signaling_nan(float128 a, float_status *status) float128 float128_maybe_silence_nan(float128 a, float_status *status) { if (float128_is_signaling_nan(a, status)) { - if (status->snan_bit_is_one) { - a = float128_default_nan(status); - } else { - a.high |= LIT64(0x0000800000000000); - return a; - } + return float128_silence_nan(a, status); } return a; } diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 36626a501b..43962dc3f5 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -257,6 +257,7 @@ int float16_compare_quiet(float16, float16, float_status *status); int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); +float16 float16_silence_nan(float16, float_status *status); float16 float16_maybe_silence_nan(float16, float_status *status); static inline int float16_is_any_nan(float16 a) @@ -368,6 +369,7 @@ float32 float32_minnummag(float32, float32, float_status *status); float32 float32_maxnummag(float32, float32, float_status *status); int float32_is_quiet_nan(float32, float_status *status); int float32_is_signaling_nan(float32, float_status *status); +float32 float32_silence_nan(float32, float_status *status); float32 float32_maybe_silence_nan(float32, float_status *status); float32 float32_scalbn(float32, int, float_status *status); @@ -497,6 +499,7 @@ float64 float64_minnummag(float64, float64, float_status *status); float64 float64_maxnummag(float64, float64, float_status *status); int float64_is_quiet_nan(float64 a, float_status *status); int float64_is_signaling_nan(float64, float_status *status); +float64 float64_silence_nan(float64, float_status *status); float64 float64_maybe_silence_nan(float64, float_status *status); float64 float64_scalbn(float64, int, float_status *status); @@ -600,6 +603,7 @@ int floatx80_compare(floatx80, floatx80, float_status *status); int floatx80_compare_quiet(floatx80, floatx80, float_status *status); int floatx80_is_quiet_nan(floatx80, float_status *status); int floatx80_is_signaling_nan(floatx80, float_status *status); +floatx80 floatx80_silence_nan(floatx80, float_status *status); floatx80 floatx80_maybe_silence_nan(floatx80, float_status *status); floatx80 floatx80_scalbn(floatx80, int, float_status *status); @@ -811,6 +815,7 @@ int float128_compare(float128, float128, float_status *status); int float128_compare_quiet(float128, float128, float_status *status); int float128_is_quiet_nan(float128, float_status *status); int float128_is_signaling_nan(float128, float_status *status); +float128 float128_silence_nan(float128, float_status *status); float128 float128_maybe_silence_nan(float128, float_status *status); float128 float128_scalbn(float128, int, float_status *status); From patchwork Wed May 16 15:52:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136020 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1109634lji; Wed, 16 May 2018 09:02:33 -0700 (PDT) X-Google-Smtp-Source: AB8JxZr31Igyk1ji1kLtOas5Rcr3PGAp759XWYHFKuimrmx7tQ6bcVZsNCWWGz3ky4UH/DZWbpnu X-Received: by 2002:a37:b002:: with SMTP id z2-v6mr1396832qke.222.1526486553628; Wed, 16 May 2018 09:02:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526486553; cv=none; d=google.com; s=arc-20160816; b=bOMvj6hacNrT0ilNBto/P6jTwC7f9BlDhGXpA7DQNlMLUOcgRfeP5jfdKMYiEnKzVW IPm6Y1gy0noVw6BIrmgQfmtiPONKgX0ZDrGgH0Hn2v+AnBK2djWA4BTLjfawq4vFJZxA dQvH2/CKv0FeON7hYIW0jMG02dgvYlUAEJvhlsStCPFWOmhTSGlAXS2c6B1ZoqDG7QLB R5dbJCsmcfnGeVXehraMi/7P8mOhXvxzQPGwBcCIXbmPA5a97khTVod2OehSFSLRJAig c/gj8dCqU/8TYlw9RY6147HraA7BBOMoWh2LY7QUrd0+QuH5SieY4WchHYsJjwqVuhb8 QnRw== ARC-Message-Signature: i=1; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.52.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:52:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:19 -0700 Message-Id: <20180516155243.16937-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PULL 04/28] fpu/softfloat: Move softfloat-specialize.h below FloatParts definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We want to be able to specialize on the canonical representation. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index d07419324a..0d17027379 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -95,16 +95,6 @@ this code that are retained. *----------------------------------------------------------------------------*/ #include "fpu/softfloat-macros.h" -/*---------------------------------------------------------------------------- -| Functions and definitions to determine: (1) whether tininess for underflow -| is detected before or after rounding by default, (2) what (if anything) -| happens when exceptions are raised, (3) how signaling NaNs are distinguished -| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs -| are propagated from function inputs to output. These details are target- -| specific. -*----------------------------------------------------------------------------*/ -#include "softfloat-specialize.h" - /*---------------------------------------------------------------------------- | Returns the fraction bits of the half-precision floating-point value `a'. *----------------------------------------------------------------------------*/ @@ -322,6 +312,16 @@ static inline float64 float64_pack_raw(FloatParts p) return make_float64(pack_raw(float64_params, p)); } +/*---------------------------------------------------------------------------- +| Functions and definitions to determine: (1) whether tininess for underflow +| is detected before or after rounding by default, (2) what (if anything) +| happens when exceptions are raised, (3) how signaling NaNs are distinguished +| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs +| are propagated from function inputs to output. These details are target- +| specific. +*----------------------------------------------------------------------------*/ +#include "softfloat-specialize.h" + /* Canonicalize EXP and FRAC, setting CLS. */ static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, float_status *status) From patchwork Wed May 16 15:52:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136016 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1101618lji; Wed, 16 May 2018 08:56:34 -0700 (PDT) X-Google-Smtp-Source: AB8JxZq1d+KW2LVA7fX6TVs1m8x7L5HsRfhiy8VRP5691VvBMsXigMmUo3JEJvRPtNg0og6rTWS7 X-Received: by 2002:a37:80c7:: with SMTP id b190-v6mr1464061qkd.212.1526486194641; Wed, 16 May 2018 08:56:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526486194; cv=none; d=google.com; s=arc-20160816; b=o3almKBtn6hCY00CknOMY7H3D66udAIEc7EV6a3HWhgRpuA5JgJmYyw59YVWDxw3XE oPQIczziKIu0+CDrL/VWiLyJsnBlmySO9CADczJRlm6PysQrOhfruyC0fZPuox7wYKGj yqbpmRUl/I72l4kJcn07xEvOKdzwHtn2SeGkKn0RSWSOwxG4RKS1K77X1zmLTRsIWF8J cYH0SMPBDutAluiOd9Vq4ft8fc+RxQ6uFJLo+kFuF/vPrYR3bZnxx6e5muKLJ9tpZqpA hjPc//VwvJYRwjLU5xrD0dZ2Rc30DMbaMNC+nY6J0pSY3kVFaSyy+y0tf7xHAISQ36mv 3iYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=/xl8f2zQlEINP9lneuf7ucQwkBVVFUmq+tNHsXqCle4=; b=Jo+yVKI4BsE71pX4FeSeyyWr+lQECT/WpdGEl44R0pU3qmnqE+ugvt6lx4jJ8JKact CD2qmBFEonfhioCTeFyUnRd0drGJBg/kmpTxXmiGivzjp3QCFtI1ajKOn8ckcgJeHbcM NzttXP+SE/DMVg1X1HIvFaNBq7MuF+0ULHV/9DBIi4LPc0Wu4BOdomDJLUqS6iCRNOkS ZPyeXCDg4LYaGli7pPftJIystOOFIN2FbIv16QzcbWRO7kG93mN2Ow73Ok0IYUiXcu2y +r1KNlzFduTGkn/kfyYuJMILk2OnHkGpeuPE5flcfgJl69sU5A3cQX8NBjuWYlTY7BLU 372A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X5MWqfYR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.52.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:52:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:20 -0700 Message-Id: <20180516155243.16937-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PULL 05/28] fpu/softfloat: Canonicalize NaN fraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Shift the NaN fraction to a canonical position, much like we do for the fraction of normal numbers. This will facilitate manipulation of NaNs within the shared code paths. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.17.0 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 0d17027379..607c4a78d5 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -330,10 +330,11 @@ static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, if (part.frac == 0) { part.cls = float_class_inf; } else { + part.frac <<= parm->frac_shift; #ifdef NO_SIGNALING_NANS part.cls = float_class_qnan; #else - int64_t msb = part.frac << (parm->frac_shift + 2); + int64_t msb = part.frac << 2; if ((msb < 0) == status->snan_bit_is_one) { part.cls = float_class_snan; } else { @@ -480,6 +481,7 @@ static FloatParts round_canonical(FloatParts p, float_status *s, case float_class_qnan: case float_class_snan: exp = exp_max; + frac >>= parm->frac_shift; break; default: @@ -503,6 +505,7 @@ static float16 float16_round_pack_canonical(FloatParts p, float_status *s) case float_class_dnan: return float16_default_nan(s); case float_class_msnan: + p.frac >>= float16_params.frac_shift; return float16_maybe_silence_nan(float16_pack_raw(p), s); default: p = round_canonical(p, s, &float16_params); @@ -521,6 +524,7 @@ static float32 float32_round_pack_canonical(FloatParts p, float_status *s) case float_class_dnan: return float32_default_nan(s); case float_class_msnan: + p.frac >>= float32_params.frac_shift; return float32_maybe_silence_nan(float32_pack_raw(p), s); default: p = round_canonical(p, s, &float32_params); @@ -539,6 +543,7 @@ static float64 float64_round_pack_canonical(FloatParts p, float_status *s) case float_class_dnan: return float64_default_nan(s); case float_class_msnan: + p.frac >>= float64_params.frac_shift; return float64_maybe_silence_nan(float64_pack_raw(p), s); default: p = round_canonical(p, s, &float64_params); From patchwork Wed May 16 15:52:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136024 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1111986lji; Wed, 16 May 2018 09:04:10 -0700 (PDT) X-Google-Smtp-Source: AB8JxZo2EjHpAAdr91N3XYrFB/VHhb4yc8Zxygjtx60oQOfhk3q+fYAuiEIj8D5E3yqfvkIrC0GL X-Received: by 2002:a37:91c5:: with SMTP id t188-v6mr1360445qkd.159.1526486650080; Wed, 16 May 2018 09:04:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526486650; cv=none; d=google.com; s=arc-20160816; b=z7Sa/f0oV4nVtDl6ykS1PuEhskBn+1ekwBBSCse0DmnVFuljjw92eKum4D5r6q6ang 2GUqH9OrW9rwZrc3PayD66azwIUOGQZrlDfmaGTsUcqYvG+ZKpCADhdhFo9s67zS4aPZ rDr4GB+DBQQ1G+Rb63PFQy8YUgR2MwC7vvtNpSWuJCEPGYqTOaULZmRjEZ37OxUzR2GU fkWmMxAgu7jeRmYD7WE4VJLcu1D1mW1BgWMyYiCBtmU3Zb55w8Og969bRaDfszDuVmWc PZj+TUeEz8Sjx43hA/nD1cWSEkW/l09/zixo01+ghUZ0StKqlTjd7DP9MAzOhSH1B0gK PJXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=LQoF9e5L3ALMayOgvkerESyi2UVKdvRwamrm6aU1hPU=; b=s6cvHg09x7i3wjxrfV45nj1qPoNFjGxGdmO4i74nvgnaIfs9CJm8cYvgPy1MlWtrJ7 U2hwBc0e3rJZUFvZxqPCKkbZQ0LyxocJ+lT38CO1JefHPNJE8+NCp0omS72FhjRnnaPy RD3OxVembtGN4uLqluqQSJLm+WC7Qv+pkfY7GSOTVv9XyaQ5+kxX1gxc7vKWGTLsA6jn IV8DmIEyEJ1Y9tLSbL4UoiojowMBMITbnj4iPH8I3FX4wSxR7xA8XY3KHut7f6nz10Vb /KuIiS8euIvxLNEUyq2u20gwrsMvoTaJ2nUXXQUFrsVbGccMRhZSjSzGBpxGpJqpUAg0 JYOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QM4Qg8bX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.52.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:52:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:21 -0700 Message-Id: <20180516155243.16937-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22f Subject: [Qemu-devel] [PULL 06/28] fpu/softfloat: Introduce parts_is_snan_frac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 15 +++++++++++++++ fpu/softfloat.c | 12 ++---------- 2 files changed, 17 insertions(+), 10 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 4fc9ea4ac0..515cb12cfa 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -86,6 +86,21 @@ this code that are retained. #define NO_SIGNALING_NANS 1 #endif +/*---------------------------------------------------------------------------- +| For the deconstructed floating-point with fraction FRAC, return true +| if the fraction represents a signalling NaN; otherwise false. +*----------------------------------------------------------------------------*/ + +static bool parts_is_snan_frac(uint64_t frac, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return false; +#else + flag msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); + return msb == status->snan_bit_is_one; +#endif +} + /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 607c4a78d5..19f40d6932 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -331,16 +331,8 @@ static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, part.cls = float_class_inf; } else { part.frac <<= parm->frac_shift; -#ifdef NO_SIGNALING_NANS - part.cls = float_class_qnan; -#else - int64_t msb = part.frac << 2; - if ((msb < 0) == status->snan_bit_is_one) { - part.cls = float_class_snan; - } else { - part.cls = float_class_qnan; - } -#endif + part.cls = (parts_is_snan_frac(part.frac, status) + ? float_class_snan : float_class_qnan); } } else if (part.exp == 0) { if (likely(part.frac == 0)) { From patchwork Wed May 16 15:52:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136025 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1117054lji; Wed, 16 May 2018 09:07:40 -0700 (PDT) X-Google-Smtp-Source: AB8JxZp3abDP5Iuyz8KDfCSStn0mZsfrf37Ao3kD8bjRTR0V8cpmtImTgiYd+7W8e6LkXolhMi69 X-Received: by 2002:a37:4ed7:: with SMTP id c206-v6mr1375789qkb.207.1526486860391; Wed, 16 May 2018 09:07:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526486860; cv=none; d=google.com; s=arc-20160816; b=XzgG7f5IMg9ku6QyVvMJIvoVXJPV7dj8z/tx3qxN/PDJNlgg7E/Ii9VSYCoJ3wyJvo UM5Xtnjb2eWWOOfbwFtGXI2ThKUfmQeDsYv8W5o/HHgkYhGTYGEKH6EExiaKJ7c1u1yW GEQ+aySEU+NmHkL9fDuVxztfB1TrTO491jyN2kqrYZSOeSqJEPcih+2TnSzQN5zm9ZdK y+fcqkIMFv6iZyS0cdmoFxgLRIMzb7lloXo/gb+9hZKy8n9Ma1J4oTsjePzG6Kc1oYRz d3Dh0ggxzDvKEN3bfuatER11wLipUe3k19FbqSwwR4nm4ky4HO60PrIT4o8G84FmWbpU X2WA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=lJnCZDN0PRg9xnf5HrS6QJvF08nF0qG9pJRnCl2JME0=; b=JiTsp1RRRD2DVAcofeu81SKj9vge5NYVW1Xz77K6vnCweWSVINjWxWgydEH5TAP/E1 gfIzRixePqWAGkoZR2iNUtr64SajERkaN7P1WeLIBGMAkYJJnJyfHfiJH/6jsE0yJbGc tzXtwTA57Rg16wpPvPwgw1s+WwRvD1k4eVAZ971r89wieaWbBrVs0yIfA075nvHsCDm5 w9cRRpS3Dd+2++sSa5Y/nMZYo9/b8EQc8IzH35mnLP8hJOo6B5aBvEWIl5+UzJT6Rcz6 CzQerpOicH0C88ccYsfT3g0/oAR/cDpWvcZtHAy43cMX0iVD/wRu0PcRedFUqyuzTTVl CgAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=F3/x8SmQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.52.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:52:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:22 -0700 Message-Id: <20180516155243.16937-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 07/28] fpu/softfloat: Replace float_class_dnan with parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With a canonical representation of NaNs, we can return the default nan directly rather than delay the expansion until the final format is known. Note one case where we uselessly assigned to a.sign, which was overwritten/ignored later when expanding float_class_dnan. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 37 +++++++++++++++++++++++++++++++++++++ fpu/softfloat.c | 38 +++++++++++--------------------------- 2 files changed, 48 insertions(+), 27 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 515cb12cfa..0d3d81a52b 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -101,6 +101,43 @@ static bool parts_is_snan_frac(uint64_t frac, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| The pattern for a default generated deconstructed floating-point NaN. +*----------------------------------------------------------------------------*/ + +static FloatParts parts_default_nan(float_status *status) +{ + bool sign = 0; + uint64_t frac; + +#if defined(TARGET_SPARC) || defined(TARGET_M68K) + frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ + defined(TARGET_S390X) || defined(TARGET_RISCV) + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#elif defined(TARGET_HPPA) + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (status->snan_bit_is_one) { + frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; + } else { +#if defined(TARGET_MIPS) + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#else + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); + sign = 1; +#endif + } +#endif + + return (FloatParts) { + .cls = float_class_qnan, + .sign = sign, + .exp = INT_MAX, + .frac = frac + }; +} + /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 19f40d6932..51780b718f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -188,7 +188,6 @@ typedef enum __attribute__ ((__packed__)) { float_class_inf, float_class_qnan, /* all NaNs from here */ float_class_snan, - float_class_dnan, float_class_msnan, /* maybe silenced */ } FloatClass; @@ -494,8 +493,6 @@ static FloatParts float16_unpack_canonical(float16 f, float_status *s) static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float16_default_nan(s); case float_class_msnan: p.frac >>= float16_params.frac_shift; return float16_maybe_silence_nan(float16_pack_raw(p), s); @@ -513,8 +510,6 @@ static FloatParts float32_unpack_canonical(float32 f, float_status *s) static float32 float32_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float32_default_nan(s); case float_class_msnan: p.frac >>= float32_params.frac_shift; return float32_maybe_silence_nan(float32_pack_raw(p), s); @@ -532,8 +527,6 @@ static FloatParts float64_unpack_canonical(float64 f, float_status *s) static float64 float64_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float64_default_nan(s); case float_class_msnan: p.frac >>= float64_params.frac_shift; return float64_maybe_silence_nan(float64_pack_raw(p), s); @@ -566,7 +559,7 @@ static FloatParts return_nan(FloatParts a, float_status *s) /* fall through */ case float_class_qnan: if (s->default_nan_mode) { - a.cls = float_class_dnan; + return parts_default_nan(s); } break; @@ -583,7 +576,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) } if (s->default_nan_mode) { - a.cls = float_class_dnan; + return parts_default_nan(s); } else { if (pickNaN(is_qnan(a.cls), is_snan(a.cls), is_qnan(b.cls), is_snan(b.cls), @@ -614,8 +607,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, /* Note that this check is after pickNaNMulAdd so that function * has an opportunity to set the Invalid flag. */ - a.cls = float_class_dnan; - return a; + which = 3; } switch (which) { @@ -628,8 +620,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, a = c; break; case 3: - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); default: g_assert_not_reached(); } @@ -682,7 +673,7 @@ static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract, if (a.cls == float_class_inf) { if (b.cls == float_class_inf) { float_raise(float_flag_invalid, s); - a.cls = float_class_dnan; + return parts_default_nan(s); } return a; } @@ -828,9 +819,7 @@ static FloatParts mul_floats(FloatParts a, FloatParts b, float_status *s) if ((a.cls == float_class_inf && b.cls == float_class_zero) || (a.cls == float_class_zero && b.cls == float_class_inf)) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; - a.sign = sign; - return a; + return parts_default_nan(s); } /* Multiply by 0 or Inf */ if (a.cls == float_class_inf || a.cls == float_class_zero) { @@ -908,8 +897,7 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, if (inf_zero) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); } if (flags & float_muladd_negate_c) { @@ -933,12 +921,12 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, if (c.cls == float_class_inf) { if (p_class == float_class_inf && p_sign != c.sign) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; + return parts_default_nan(s); } else { a.cls = float_class_inf; a.sign = c.sign ^ sign_flip; + return a; } - return a; } if (p_class == float_class_inf) { @@ -1148,8 +1136,7 @@ static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s) && (a.cls == float_class_inf || a.cls == float_class_zero)) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); } /* Inf / x or 0 / x */ if (a.cls == float_class_inf || a.cls == float_class_zero) { @@ -1347,7 +1334,6 @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags = orig_flags | float_flag_invalid; return max; @@ -1439,7 +1425,6 @@ static uint64_t round_to_uint_and_pack(FloatParts in, int rmode, uint64_t max, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags = orig_flags | float_flag_invalid; return max; @@ -1940,8 +1925,7 @@ static FloatParts sqrt_float(FloatParts a, float_status *s, const FloatFmt *p) } if (a.sign) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); } if (a.cls == float_class_inf) { return a; /* sqrt(+inf) = +inf */ From patchwork Wed May 16 15:52:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136022 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1110650lji; Wed, 16 May 2018 09:03:11 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqAXZg8ws5zBo0BgVDcd6M7tyfR0goA++4nEkseUlb/kCyXOicTdq6sRYO74luMmLcviHyr X-Received: by 2002:a37:15ea:: with SMTP id 103-v6mr1425652qkv.349.1526486591725; Wed, 16 May 2018 09:03:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526486591; cv=none; d=google.com; s=arc-20160816; b=wr22rK+OuNp+QdjZTQE8Di8AvBT5qgLWrNwBsRebXbZHv6WgN4gyNoKwcubpoSrDJz DKSakjh6O+mp/0Q4DrMeTKVBtGJpVcL8e7ljCpJgKEFdyX42oJX2Dmj47B1qPDg4MgwN 318AUel83cJvLnIDQL4cZXP4Dfa7Na9e3N5gwAAZKL+821fZpFqVr8uCfgR3+dwhMccA 7RvOsaIH/20QUC2LJ68SbmIvuyh0IU9BupnHjCcPqKsbhf1X5M8kzq/zYy2bQVFPy34l ZONSuC/r8tmPG/0NxbK0Yv1DQSMcw/tL0RhiH98RClL34EGk5jWk6UnJ09KdA0HMh0/X LEPA== ARC-Message-Signature: i=1; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.52.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:52:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:23 -0700 Message-Id: <20180516155243.16937-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22e Subject: [Qemu-devel] [PULL 08/28] fpu/softfloat: Replace float_class_msnan with parts_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With a canonical representation of NaNs, we can silence an SNaN immediately rather than delay until the final format is known. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 23 ++++++++++++++++++++++ fpu/softfloat.c | 40 ++++++++++---------------------------- 2 files changed, 33 insertions(+), 30 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 0d3d81a52b..571d1df378 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -138,6 +138,29 @@ static FloatParts parts_default_nan(float_status *status) }; } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the deconstructed +| floating-point parts. +*----------------------------------------------------------------------------*/ + +static FloatParts parts_silence_nan(FloatParts a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#elif defined(TARGET_HPPA) + a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); + a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (status->snan_bit_is_one) { + return parts_default_nan(status); + } else { + a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); + } +#endif + a.cls = float_class_qnan; + return a; +} + /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 51780b718f..41253c6749 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -188,7 +188,6 @@ typedef enum __attribute__ ((__packed__)) { float_class_inf, float_class_qnan, /* all NaNs from here */ float_class_snan, - float_class_msnan, /* maybe silenced */ } FloatClass; /* @@ -492,14 +491,7 @@ static FloatParts float16_unpack_canonical(float16 f, float_status *s) static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - p.frac >>= float16_params.frac_shift; - return float16_maybe_silence_nan(float16_pack_raw(p), s); - default: - p = round_canonical(p, s, &float16_params); - return float16_pack_raw(p); - } + return float16_pack_raw(round_canonical(p, s, &float16_params)); } static FloatParts float32_unpack_canonical(float32 f, float_status *s) @@ -509,14 +501,7 @@ static FloatParts float32_unpack_canonical(float32 f, float_status *s) static float32 float32_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - p.frac >>= float32_params.frac_shift; - return float32_maybe_silence_nan(float32_pack_raw(p), s); - default: - p = round_canonical(p, s, &float32_params); - return float32_pack_raw(p); - } + return float32_pack_raw(round_canonical(p, s, &float32_params)); } static FloatParts float64_unpack_canonical(float64 f, float_status *s) @@ -526,14 +511,7 @@ static FloatParts float64_unpack_canonical(float64 f, float_status *s) static float64 float64_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - p.frac >>= float64_params.frac_shift; - return float64_maybe_silence_nan(float64_pack_raw(p), s); - default: - p = round_canonical(p, s, &float64_params); - return float64_pack_raw(p); - } + return float64_pack_raw(round_canonical(p, s, &float64_params)); } /* Simple helpers for checking if what NaN we have */ @@ -555,7 +533,7 @@ static FloatParts return_nan(FloatParts a, float_status *s) switch (a.cls) { case float_class_snan: s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_msnan; + a = parts_silence_nan(a, s); /* fall through */ case float_class_qnan: if (s->default_nan_mode) { @@ -584,7 +562,9 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) (a.frac == b.frac && a.sign < b.sign))) { a = b; } - a.cls = float_class_msnan; + if (is_snan(a.cls)) { + return parts_silence_nan(a, s); + } } return a; } @@ -624,8 +604,10 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, default: g_assert_not_reached(); } - a.cls = float_class_msnan; + if (is_snan(a.cls)) { + return parts_silence_nan(a, s); + } return a; } @@ -1334,7 +1316,6 @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_msnan: s->float_exception_flags = orig_flags | float_flag_invalid; return max; case float_class_inf: @@ -1425,7 +1406,6 @@ static uint64_t round_to_uint_and_pack(FloatParts in, int rmode, uint64_t max, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_msnan: s->float_exception_flags = orig_flags | float_flag_invalid; return max; case float_class_inf: From patchwork Wed May 16 15:52:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136027 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1119506lji; Wed, 16 May 2018 09:09:25 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpHkf1IRimtsid2Ic/SQW3rDSO3W2Vqbg9zB7eApRrCX/vAxq/vi0nN3eaRFo2YUSSuQgkQ X-Received: by 2002:aed:25f9:: with SMTP id y54-v6mr1594025qtc.62.1526486965387; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.52.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:52:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:24 -0700 Message-Id: <20180516155243.16937-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PULL 09/28] target/arm: convert conversion helpers to fpst/ahp_flag X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée Instead of passing env and leaving it up to the helper to get the right fpstatus we pass it explicitly. There was already a get_fpstatus helper for neon for the 32 bit code. We also add an get_ahp_flag() for passing the state of the alternative FP16 format flag. This leaves scope for later tracking the AHP state in translation flags. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.h | 10 +++--- target/arm/translate.h | 12 +++++++ target/arm/helper.c | 56 +++++------------------------ target/arm/translate-a64.c | 37 +++++++++++++++---- target/arm/translate.c | 74 +++++++++++++++++++++++++++++--------- 5 files changed, 112 insertions(+), 77 deletions(-) -- 2.17.0 diff --git a/target/arm/helper.h b/target/arm/helper.h index ce89968b2d..047f3bc1ca 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -187,12 +187,10 @@ DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr) DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) -DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env) -DEF_HELPER_2(vfp_fcvt_f32_to_f16, i32, f32, env) -DEF_HELPER_2(neon_fcvt_f16_to_f32, f32, i32, env) -DEF_HELPER_2(neon_fcvt_f32_to_f16, i32, f32, env) -DEF_HELPER_FLAGS_2(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, i32, env) -DEF_HELPER_FLAGS_2(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, i32, f64, env) +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, ptr, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, ptr, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i32) DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr) DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) diff --git a/target/arm/translate.h b/target/arm/translate.h index 37a1bba056..45f04244be 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -177,4 +177,16 @@ void arm_free_cc(DisasCompare *cmp); void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); +/* Return state of Alternate Half-precision flag, caller frees result */ +static inline TCGv_i32 get_ahp_flag(void) +{ + TCGv_i32 ret = tcg_temp_new_i32(); + + tcg_gen_ld_i32(ret, cpu_env, + offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR])); + tcg_gen_extract_i32(ret, ret, 26, 1); + + return ret; +} + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index c6fd7f9479..1762042fc7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11540,64 +11540,24 @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) } /* Half precision conversions. */ -static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) +float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode) { - int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; - float32 r = float16_to_float32(make_float16(a), ieee, s); - if (ieee) { - return float32_maybe_silence_nan(r, s); - } - return r; + return float16_to_float32(a, !ahp_mode, fpstp); } -static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) +float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) { - int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; - float16 r = float32_to_float16(a, ieee, s); - if (ieee) { - r = float16_maybe_silence_nan(r, s); - } - return float16_val(r); + return float32_to_float16(a, !ahp_mode, fpstp); } -float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) +float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode) { - return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); + return float16_to_float64(a, !ahp_mode, fpstp); } -uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) +float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) { - return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); -} - -float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) -{ - return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); -} - -uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) -{ - return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); -} - -float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) -{ - int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; - float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); - if (ieee) { - return float64_maybe_silence_nan(r, &env->vfp.fp_status); - } - return r; -} - -uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) -{ - int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; - float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); - if (ieee) { - r = float16_maybe_silence_nan(r, &env->vfp.fp_status); - } - return float16_val(r); + return float64_to_float16(a, !ahp_mode, fpstp); } #define float32_two make_float32(0x40000000) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a0b0c43d12..d8284678f7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5147,10 +5147,15 @@ static void handle_fp_fcvt(DisasContext *s, int opcode, } else { /* Single to half */ TCGv_i32 tcg_rd = tcg_temp_new_i32(); - gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, cpu_env); + TCGv_i32 ahp = get_ahp_flag(); + TCGv_ptr fpst = get_fpstatus_ptr(false); + + gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero */ write_fp_sreg(s, rd, tcg_rd); tcg_temp_free_i32(tcg_rd); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); } tcg_temp_free_i32(tcg_rn); break; @@ -5163,9 +5168,13 @@ static void handle_fp_fcvt(DisasContext *s, int opcode, /* Double to single */ gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); } else { + TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_i32 ahp = get_ahp_flag(); /* Double to half */ - gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero */ + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(ahp); } write_fp_sreg(s, rd, tcg_rd); tcg_temp_free_i32(tcg_rd); @@ -5175,17 +5184,21 @@ static void handle_fp_fcvt(DisasContext *s, int opcode, case 0x3: { TCGv_i32 tcg_rn = read_fp_sreg(s, rn); + TCGv_ptr tcg_fpst = get_fpstatus_ptr(false); + TCGv_i32 tcg_ahp = get_ahp_flag(); tcg_gen_ext16u_i32(tcg_rn, tcg_rn); if (dtype == 0) { /* Half to single */ TCGv_i32 tcg_rd = tcg_temp_new_i32(); - gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); write_fp_sreg(s, rd, tcg_rd); + tcg_temp_free_ptr(tcg_fpst); + tcg_temp_free_i32(tcg_ahp); tcg_temp_free_i32(tcg_rd); } else { /* Half to double */ TCGv_i64 tcg_rd = tcg_temp_new_i64(); - gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); write_fp_dreg(s, rd, tcg_rd); tcg_temp_free_i64(tcg_rd); } @@ -9053,12 +9066,17 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar, } else { TCGv_i32 tcg_lo = tcg_temp_new_i32(); TCGv_i32 tcg_hi = tcg_temp_new_i32(); + TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_i32 ahp = get_ahp_flag(); + tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op); - gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env); - gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp); + gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp); tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); tcg_temp_free_i32(tcg_lo); tcg_temp_free_i32(tcg_hi); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(ahp); } break; case 0x56: /* FCVTXN, FCVTXN2 */ @@ -11532,18 +11550,23 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, /* 16 -> 32 bit fp conversion */ int srcelt = is_q ? 4 : 0; TCGv_i32 tcg_res[4]; + TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_i32 ahp = get_ahp_flag(); for (pass = 0; pass < 4; pass++) { tcg_res[pass] = tcg_temp_new_i32(); read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16); gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass], - cpu_env); + fpst, ahp); } for (pass = 0; pass < 4; pass++) { write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); tcg_temp_free_i32(tcg_res[pass]); } + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(ahp); } } diff --git a/target/arm/translate.c b/target/arm/translate.c index 731cf327a1..613598d090 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3824,38 +3824,56 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) gen_vfp_sqrt(dp); break; case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */ + { + TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_i32 ahp_mode = get_ahp_flag(); tmp = gen_vfp_mrs(); tcg_gen_ext16u_i32(tmp, tmp); if (dp) { gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp, - cpu_env); + fpst, ahp_mode); } else { gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, - cpu_env); + fpst, ahp_mode); } + tcg_temp_free_i32(ahp_mode); + tcg_temp_free_ptr(fpst); tcg_temp_free_i32(tmp); break; + } case 5: /* vcvtt.f32.f16, vcvtt.f64.f16 */ + { + TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_i32 ahp = get_ahp_flag(); tmp = gen_vfp_mrs(); tcg_gen_shri_i32(tmp, tmp, 16); if (dp) { gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp, - cpu_env); + fpst, ahp); } else { gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, - cpu_env); + fpst, ahp); } tcg_temp_free_i32(tmp); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); break; + } case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */ + { + TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_i32 ahp = get_ahp_flag(); tmp = tcg_temp_new_i32(); + if (dp) { gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d, - cpu_env); + fpst, ahp); } else { gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, - cpu_env); + fpst, ahp); } + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); gen_mov_F0_vreg(0, rd); tmp2 = gen_vfp_mrs(); tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); @@ -3863,15 +3881,21 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tmp2); gen_vfp_msr(tmp); break; + } case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */ + { + TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_i32 ahp = get_ahp_flag(); tmp = tcg_temp_new_i32(); if (dp) { gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d, - cpu_env); + fpst, ahp); } else { gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, - cpu_env); + fpst, ahp); } + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); tcg_gen_shli_i32(tmp, tmp, 16); gen_mov_F0_vreg(0, rd); tmp2 = gen_vfp_mrs(); @@ -3880,6 +3904,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tmp2); gen_vfp_msr(tmp); break; + } case 8: /* cmp */ gen_vfp_cmp(dp); break; @@ -7222,53 +7247,70 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } break; case NEON_2RM_VCVT_F16_F32: + { + TCGv_ptr fpst; + TCGv_i32 ahp; + if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) || q || (rm & 1)) { return 1; } tmp = tcg_temp_new_i32(); tmp2 = tcg_temp_new_i32(); + fpst = get_fpstatus_ptr(false); + ahp = get_ahp_flag(); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0)); - gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, fpst, ahp); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1)); - gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, fpst, ahp); tcg_gen_shli_i32(tmp2, tmp2, 16); tcg_gen_or_i32(tmp2, tmp2, tmp); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2)); - gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, fpst, ahp); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3)); neon_store_reg(rd, 0, tmp2); tmp2 = tcg_temp_new_i32(); - gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, fpst, ahp); tcg_gen_shli_i32(tmp2, tmp2, 16); tcg_gen_or_i32(tmp2, tmp2, tmp); neon_store_reg(rd, 1, tmp2); tcg_temp_free_i32(tmp); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); break; + } case NEON_2RM_VCVT_F32_F16: + { + TCGv_ptr fpst; + TCGv_i32 ahp; if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) || q || (rd & 1)) { return 1; } + fpst = get_fpstatus_ptr(false); + ahp = get_ahp_flag(); tmp3 = tcg_temp_new_i32(); tmp = neon_load_reg(rm, 0); tmp2 = neon_load_reg(rm, 1); tcg_gen_ext16u_i32(tmp3, tmp); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0)); tcg_gen_shri_i32(tmp3, tmp, 16); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1)); tcg_temp_free_i32(tmp); tcg_gen_ext16u_i32(tmp3, tmp2); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2)); tcg_gen_shri_i32(tmp3, tmp2, 16); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3)); tcg_temp_free_i32(tmp2); tcg_temp_free_i32(tmp3); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); break; + } case NEON_2RM_AESE: case NEON_2RM_AESMC: if (!arm_dc_feature(s, ARM_FEATURE_V8_AES) || ((rm | rd) & 1)) { From patchwork Wed May 16 15:52:25 2018 Content-Type: text/plain; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.52.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:52:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:25 -0700 Message-Id: <20180516155243.16937-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::236 Subject: [Qemu-devel] [PULL 10/28] target/arm: squash FZ16 behaviour for conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée The ARM ARM specifies FZ16 is suppressed for conversions. Rather than pushing this logic into the softfloat code we can simply save the FZ state and temporarily disable it for the softfloat call. Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 40 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) -- 2.17.0 diff --git a/target/arm/helper.c b/target/arm/helper.c index 1762042fc7..238a3ceba8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11542,22 +11542,54 @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) /* Half precision conversions. */ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode) { - return float16_to_float32(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing input denormals. + */ + float_status *fpst = fpstp; + flag save = get_flush_inputs_to_zero(fpst); + set_flush_inputs_to_zero(false, fpst); + float32 r = float16_to_float32(a, !ahp_mode, fpst); + set_flush_inputs_to_zero(save, fpst); + return r; } float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) { - return float32_to_float16(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing output denormals. + */ + float_status *fpst = fpstp; + flag save = get_flush_to_zero(fpst); + set_flush_to_zero(false, fpst); + float16 r = float32_to_float16(a, !ahp_mode, fpst); + set_flush_to_zero(save, fpst); + return r; } float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode) { - return float16_to_float64(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing input denormals. + */ + float_status *fpst = fpstp; + flag save = get_flush_inputs_to_zero(fpst); + set_flush_inputs_to_zero(false, fpst); + float64 r = float16_to_float64(a, !ahp_mode, fpst); + set_flush_inputs_to_zero(save, fpst); + return r; } float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) { - return float64_to_float16(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing output denormals. + */ + float_status *fpst = fpstp; + flag save = get_flush_to_zero(fpst); + set_flush_to_zero(false, fpst); + float16 r = float64_to_float16(a, !ahp_mode, fpst); + set_flush_to_zero(save, fpst); + return r; } #define float32_two make_float32(0x40000000) From patchwork Wed May 16 15:52:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136029 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1120200lji; Wed, 16 May 2018 09:09:55 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqmP1phUXgWMzXUT92o58Qnl0bJPAZo638EyHzohr7d/u2ZCB3xJMxcAVpWxgkagDbwb2F7 X-Received: by 2002:ac8:1b8b:: with SMTP id z11-v6mr1579771qtj.294.1526486995459; Wed, 16 May 2018 09:09:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526486995; cv=none; d=google.com; s=arc-20160816; b=qlI149ZeW7nrr/8N+jdPNybgxvC5zR339dufYZnxx2kzWCodw5J2iZrvfYoK/+C5FE Az7aDjHZH/RZkUfQbs4GFVmYjatm1ObZmepe4GzBLSpht4QsC+yDNWcrNUppxEFyc4KS SUQjEmHA5uTakHzNaVIJ/b3jA1jsz5WgJ1OVvwLVUrpgKV/kvNaE5+xKwWNMALAlD69Z yOa7FF2izNC1kGEYDrQ/5unddJ3ZIXG30NkvndFOYUUuRQ1oRu2v1D+AwTPtetG4vBMb I0/BTjtm4X+QOhNFTWnleIeCbk2IBqvfjQcDPWNx8SZEbLsV86JxozwAQddoxtHeUDGf 2mOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=lRqGxJhzFUeyacxzleC4RhsXXY0zMiUoKTM/DfcJ4HY=; b=hOVxkrpw5FsxBpdErGjAORmpSOLVOIXrO4A6j2m8Vkc3swkF9/sS4exzdeSy76WNLj u8uweG3gy6O96xhpHYAYBVWe4qQrRenBrHTGu93MUuUWGghiQAwqqWrCdOZ0gWmd/qXr thlGED7O3NyKDSW1qCZrEiU77CbRWoZ136jKiuIvawiCHVbIEQmLEfhjlzfOFHnZfrS1 nZkrylJJtoCeG2U3Ci2P9SCnLT6jtLWIe2JDr6dqMjI5F25sptrdmPl0nLHmnwxOJing Q2O62MNLxFOIAUcBKoPeIhYQbi7tvb08mvrhAL4dsjwypRrgrpExXUTHoO8Rr/i3V4uU +jag== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=U0diJaEs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:26 -0700 Message-Id: <20180516155243.16937-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PULL 11/28] fpu/softfloat: Partial support for ARM Alternative half-precision X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée For float16 ARM supports an alternative half-precision format which sacrifices the ability to represent NaN/Inf in return for a higher dynamic range. The new FloatFmt flag, arm_althp, is then used to modify the behaviour of canonicalize and round_canonical with respect to representation and exception raising. Usage of this new flag waits until we re-factor float-to-float conversions. Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 41253c6749..64e1ad4f98 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -220,8 +220,10 @@ typedef struct { * frac_shift: shift to normalise the fraction with DECOMPOSED_BINARY_POINT * The following are computed based the size of fraction * frac_lsb: least significant bit of fraction - * fram_lsbm1: the bit bellow the least significant bit (for rounding) + * frac_lsbm1: the bit below the least significant bit (for rounding) * round_mask/roundeven_mask: masks used for rounding + * The following optional modifiers are available: + * arm_althp: handle ARM Alternative Half Precision */ typedef struct { int exp_size; @@ -233,6 +235,7 @@ typedef struct { uint64_t frac_lsbm1; uint64_t round_mask; uint64_t roundeven_mask; + bool arm_althp; } FloatFmt; /* Expand fields based on the size of exponent and fraction */ @@ -324,7 +327,7 @@ static inline float64 float64_pack_raw(FloatParts p) static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, float_status *status) { - if (part.exp == parm->exp_max) { + if (part.exp == parm->exp_max && !parm->arm_althp) { if (part.frac == 0) { part.cls = float_class_inf; } else { @@ -413,7 +416,15 @@ static FloatParts round_canonical(FloatParts p, float_status *s, } frac >>= frac_shift; - if (unlikely(exp >= exp_max)) { + if (parm->arm_althp) { + /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ + if (unlikely(exp > exp_max)) { + /* Overflow. Return the maximum normal. */ + flags = float_flag_invalid; + exp = exp_max; + frac = -1; + } + } else if (unlikely(exp >= exp_max)) { flags |= float_flag_overflow | float_flag_inexact; if (overflow_norm) { exp = exp_max - 1; @@ -464,12 +475,14 @@ static FloatParts round_canonical(FloatParts p, float_status *s, case float_class_inf: do_inf: + assert(!parm->arm_althp); exp = exp_max; frac = 0; break; case float_class_qnan: case float_class_snan: + assert(!parm->arm_althp); exp = exp_max; frac >>= parm->frac_shift; break; From patchwork Wed May 16 15:52:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136033 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1127390lji; Wed, 16 May 2018 09:15:24 -0700 (PDT) X-Google-Smtp-Source: AB8JxZo/3tbXZlaEgdWKYZPHOFfZhB82GVLVcuvqIeNpHZeMmGWPupKlBgYhCqjQ0J3pqTy/mBwu X-Received: by 2002:a37:a457:: with SMTP id n84-v6mr1530489qke.223.1526487324582; Wed, 16 May 2018 09:15:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526487324; cv=none; d=google.com; s=arc-20160816; b=q0a4hZe0m2EdEO2+BzZOox6q9Fhm5Dpd1JpM4KemgPwcNWWnh+pYyqB74B8NFlOtxQ 5/iRLzEf0q0lFDVC4yPD7zGeCK5zpSzWfe4VLwI+W8jnB2WMIFzVytKOMc2RtHuwZhu4 Ebw0Dw16LJTTQT3vV0ALbMijQ/s1TaFde56f4magg4MSPTUxPGuR2+HBv2hBIkf/oZZu SHGZfOnDgz/5cLCcXUiv3lry6FS5KRPSJEbWbizaXFUWOz2EQG1kQAmEPbWs8MqszVlV 6ay+fNewvQVptZdbwCO9XQ8N1lD+RWa2l7isVB3Kxofed2gW1Q9z83KQ+8GMcjEn4vnX 4lVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=NHK++rRcBK+nX1H3kfWQep2yH2z9rb0GTe6sEKFrKTM=; b=qHzmDe9MX1rQYPwgfxxdAJbl63v0ZVpxq98hy7fRP9Q9zox6UoaR+fYAjDQRWBoX02 Jxc03jXsGDuKS05L5pgt/Nam87OAsiEcUfCwwIe2iiI+bXSGGcliiFnPMyUqiIdstdQ4 +ldv76snv15n3A2O4z+WbDF2q8W/K63iWbpB0ftBZC8c8kqwmIgC9hi87NciNcFeXVL8 kNblom2S/m3+JOb7KcKzVvseUdtmh21sQKVRk2C2292GY5eICT1+WwQa8AOVUPFGKWT6 DiXRFJNcENYjrV+FHkKCg/fqYr5vvA5PxYANurx+1LRTidKVjogCNoR4nZplJ5fZMNu9 b18w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iOTaK3za; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:27 -0700 Message-Id: <20180516155243.16937-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 12/28] fpu/softfloat: re-factor float to float conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée This allows us to delete a lot of additional boilerplate code which is no longer needed. Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 40 --- include/fpu/softfloat.h | 8 +- fpu/softfloat.c | 488 +++++++++---------------------------- 3 files changed, 122 insertions(+), 414 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 571d1df378..995a0132c6 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -377,46 +377,6 @@ float16 float16_maybe_silence_nan(float16 a, float_status *status) return a; } -/*---------------------------------------------------------------------------- -| Returns the result of converting the half-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -static commonNaNT float16ToCommonNaN(float16 a, float_status *status) -{ - commonNaNT z; - - if (float16_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign = float16_val(a) >> 15; - z.low = 0; - z.high = ((uint64_t) float16_val(a)) << 54; - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the half- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -static float16 commonNaNToFloat16(commonNaNT a, float_status *status) -{ - uint16_t mantissa = a.high >> 54; - - if (status->default_nan_mode) { - return float16_default_nan(status); - } - - if (mantissa) { - return make_float16(((((uint16_t) a.sign) << 15) - | (0x1F << 10) | mantissa)); - } else { - return float16_default_nan(status); - } -} - /*---------------------------------------------------------------------------- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 43962dc3f5..a6860e858d 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -211,10 +211,10 @@ float128 uint64_to_float128(uint64_t, float_status *status); /*---------------------------------------------------------------------------- | Software half-precision conversion routines. *----------------------------------------------------------------------------*/ -float16 float32_to_float16(float32, flag, float_status *status); -float32 float16_to_float32(float16, flag, float_status *status); -float16 float64_to_float16(float64 a, flag ieee, float_status *status); -float64 float16_to_float64(float16 a, flag ieee, float_status *status); +float16 float32_to_float16(float32, bool ieee, float_status *status); +float32 float16_to_float32(float16, bool ieee, float_status *status); +float16 float64_to_float16(float64 a, bool ieee, float_status *status); +float64 float16_to_float64(float16 a, bool ieee, float_status *status); int16_t float16_to_int16(float16, float_status *status); uint16_t float16_to_uint16(float16 a, float_status *status); int16_t float16_to_int16_round_to_zero(float16, float_status *status); diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 64e1ad4f98..55e6701f26 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -113,15 +113,6 @@ static inline int extractFloat16Exp(float16 a) return (float16_val(a) >> 10) & 0x1f; } -/*---------------------------------------------------------------------------- -| Returns the sign bit of the single-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static inline flag extractFloat16Sign(float16 a) -{ - return float16_val(a)>>15; -} - /*---------------------------------------------------------------------------- | Returns the fraction bits of the single-precision floating-point value `a'. *----------------------------------------------------------------------------*/ @@ -254,6 +245,11 @@ static const FloatFmt float16_params = { FLOAT_PARAMS(5, 10) }; +static const FloatFmt float16_params_ahp = { + FLOAT_PARAMS(5, 10), + .arm_althp = true +}; + static const FloatFmt float32_params = { FLOAT_PARAMS(8, 23) }; @@ -497,14 +493,27 @@ static FloatParts round_canonical(FloatParts p, float_status *s, return p; } +/* Explicit FloatFmt version */ +static FloatParts float16a_unpack_canonical(float16 f, float_status *s, + const FloatFmt *params) +{ + return canonicalize(float16_unpack_raw(f), params, s); +} + static FloatParts float16_unpack_canonical(float16 f, float_status *s) { - return canonicalize(float16_unpack_raw(f), &float16_params, s); + return float16a_unpack_canonical(f, s, &float16_params); +} + +static float16 float16a_round_pack_canonical(FloatParts p, float_status *s, + const FloatFmt *params) +{ + return float16_pack_raw(round_canonical(p, s, params)); } static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { - return float16_pack_raw(round_canonical(p, s, &float16_params)); + return float16a_round_pack_canonical(p, s, &float16_params); } static FloatParts float32_unpack_canonical(float32 f, float_status *s) @@ -1181,6 +1190,104 @@ float64 float64_div(float64 a, float64 b, float_status *status) return float64_round_pack_canonical(pr, status); } +/* + * Float to Float conversions + * + * Returns the result of converting one float format to another. The + * conversion is performed according to the IEC/IEEE Standard for + * Binary Floating-Point Arithmetic. + * + * The float_to_float helper only needs to take care of raising + * invalid exceptions and handling the conversion on NaNs. + */ + +static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf, + float_status *s) +{ + if (dstf->arm_althp) { + switch (a.cls) { + case float_class_qnan: + case float_class_snan: + /* There is no NaN in the destination format. Raise Invalid + * and return a zero with the sign of the input NaN. + */ + s->float_exception_flags |= float_flag_invalid; + a.cls = float_class_zero; + a.frac = 0; + a.exp = 0; + break; + + case float_class_inf: + /* There is no Inf in the destination format. Raise Invalid + * and return the maximum normal with the correct sign. + */ + s->float_exception_flags |= float_flag_invalid; + a.cls = float_class_normal; + a.exp = dstf->exp_max; + a.frac = ((1ull << dstf->frac_size) - 1) << dstf->frac_shift; + break; + + default: + break; + } + } else if (is_nan(a.cls)) { + if (is_snan(a.cls)) { + s->float_exception_flags |= float_flag_invalid; + a = parts_silence_nan(a, s); + } + if (s->default_nan_mode) { + return parts_default_nan(s); + } + } + return a; +} + +float32 float16_to_float32(float16 a, bool ieee, float_status *s) +{ + const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; + FloatParts p = float16a_unpack_canonical(a, s, fmt16); + FloatParts pr = float_to_float(p, &float32_params, s); + return float32_round_pack_canonical(pr, s); +} + +float64 float16_to_float64(float16 a, bool ieee, float_status *s) +{ + const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; + FloatParts p = float16a_unpack_canonical(a, s, fmt16); + FloatParts pr = float_to_float(p, &float64_params, s); + return float64_round_pack_canonical(pr, s); +} + +float16 float32_to_float16(float32 a, bool ieee, float_status *s) +{ + const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; + FloatParts p = float32_unpack_canonical(a, s); + FloatParts pr = float_to_float(p, fmt16, s); + return float16a_round_pack_canonical(pr, s, fmt16); +} + +float64 float32_to_float64(float32 a, float_status *s) +{ + FloatParts p = float32_unpack_canonical(a, s); + FloatParts pr = float_to_float(p, &float64_params, s); + return float64_round_pack_canonical(pr, s); +} + +float16 float64_to_float16(float64 a, bool ieee, float_status *s) +{ + const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; + FloatParts p = float64_unpack_canonical(a, s); + FloatParts pr = float_to_float(p, fmt16, s); + return float16a_round_pack_canonical(pr, s, fmt16); +} + +float32 float64_to_float32(float64 a, float_status *s) +{ + FloatParts p = float64_unpack_canonical(a, s); + FloatParts pr = float_to_float(p, &float32_params, s); + return float32_round_pack_canonical(pr, s); +} + /* * Rounds the floating-point value `a' to an integer, and returns the * result as a floating-point value. The operation is performed @@ -3124,41 +3231,6 @@ float128 uint64_to_float128(uint64_t a, float_status *status) return normalizeRoundAndPackFloat128(0, 0x406E, 0, a, status); } - - - -/*---------------------------------------------------------------------------- -| Returns the result of converting the single-precision floating-point value -| `a' to the double-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float32_to_float64(float32 a, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - a = float32_squash_input_denormal(a, status); - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - if ( aExp == 0xFF ) { - if (aSig) { - return commonNaNToFloat64(float32ToCommonNaN(a, status), status); - } - return packFloat64( aSign, 0x7FF, 0 ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat64( aSign, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - --aExp; - } - return packFloat64( aSign, aExp + 0x380, ( (uint64_t) aSig )<<29 ); - -} - /*---------------------------------------------------------------------------- | Returns the result of converting the single-precision floating-point value | `a' to the extended double-precision floating-point format. The conversion @@ -3677,173 +3749,6 @@ int float32_unordered_quiet(float32 a, float32 b, float_status *status) return 0; } - -/*---------------------------------------------------------------------------- -| Returns the result of converting the double-precision floating-point value -| `a' to the single-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float64_to_float32(float64 a, float_status *status) -{ - flag aSign; - int aExp; - uint64_t aSig; - uint32_t zSig; - a = float64_squash_input_denormal(a, status); - - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - if ( aExp == 0x7FF ) { - if (aSig) { - return commonNaNToFloat32(float64ToCommonNaN(a, status), status); - } - return packFloat32( aSign, 0xFF, 0 ); - } - shift64RightJamming( aSig, 22, &aSig ); - zSig = aSig; - if ( aExp || zSig ) { - zSig |= 0x40000000; - aExp -= 0x381; - } - return roundAndPackFloat32(aSign, aExp, zSig, status); - -} - - -/*---------------------------------------------------------------------------- -| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a -| half-precision floating-point value, returning the result. After being -| shifted into the proper positions, the three fields are simply added -| together to form the result. This means that any integer portion of `zSig' -| will be added into the exponent. Since a properly normalized significand -| will have an integer portion equal to 1, the `zExp' input should be 1 less -| than the desired result exponent whenever `zSig' is a complete, normalized -| significand. -*----------------------------------------------------------------------------*/ -static float16 packFloat16(flag zSign, int zExp, uint16_t zSig) -{ - return make_float16( - (((uint32_t)zSign) << 15) + (((uint32_t)zExp) << 10) + zSig); -} - -/*---------------------------------------------------------------------------- -| Takes an abstract floating-point value having sign `zSign', exponent `zExp', -| and significand `zSig', and returns the proper half-precision floating- -| point value corresponding to the abstract input. Ordinarily, the abstract -| value is simply rounded and packed into the half-precision format, with -| the inexact exception raised if the abstract input cannot be represented -| exactly. However, if the abstract value is too large, the overflow and -| inexact exceptions are raised and an infinity or maximal finite value is -| returned. If the abstract value is too small, the input value is rounded to -| a subnormal number, and the underflow and inexact exceptions are raised if -| the abstract input cannot be represented exactly as a subnormal half- -| precision floating-point number. -| The `ieee' flag indicates whether to use IEEE standard half precision, or -| ARM-style "alternative representation", which omits the NaN and Inf -| encodings in order to raise the maximum representable exponent by one. -| The input significand `zSig' has its binary point between bits 22 -| and 23, which is 13 bits to the left of the usual location. This shifted -| significand must be normalized or smaller. If `zSig' is not normalized, -| `zExp' must be 0; in that case, the result returned is a subnormal number, -| and it must not require rounding. In the usual case that `zSig' is -| normalized, `zExp' must be 1 less than the ``true'' floating-point exponent. -| Note the slightly odd position of the binary point in zSig compared with the -| other roundAndPackFloat functions. This should probably be fixed if we -| need to implement more float16 routines than just conversion. -| The handling of underflow and overflow follows the IEC/IEEE Standard for -| Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -static float16 roundAndPackFloat16(flag zSign, int zExp, - uint32_t zSig, flag ieee, - float_status *status) -{ - int maxexp = ieee ? 29 : 30; - uint32_t mask; - uint32_t increment; - bool rounding_bumps_exp; - bool is_tiny = false; - - /* Calculate the mask of bits of the mantissa which are not - * representable in half-precision and will be lost. - */ - if (zExp < 1) { - /* Will be denormal in halfprec */ - mask = 0x00ffffff; - if (zExp >= -11) { - mask >>= 11 + zExp; - } - } else { - /* Normal number in halfprec */ - mask = 0x00001fff; - } - - switch (status->float_rounding_mode) { - case float_round_nearest_even: - increment = (mask + 1) >> 1; - if ((zSig & mask) == increment) { - increment = zSig & (increment << 1); - } - break; - case float_round_ties_away: - increment = (mask + 1) >> 1; - break; - case float_round_up: - increment = zSign ? 0 : mask; - break; - case float_round_down: - increment = zSign ? mask : 0; - break; - default: /* round_to_zero */ - increment = 0; - break; - } - - rounding_bumps_exp = (zSig + increment >= 0x01000000); - - if (zExp > maxexp || (zExp == maxexp && rounding_bumps_exp)) { - if (ieee) { - float_raise(float_flag_overflow | float_flag_inexact, status); - return packFloat16(zSign, 0x1f, 0); - } else { - float_raise(float_flag_invalid, status); - return packFloat16(zSign, 0x1f, 0x3ff); - } - } - - if (zExp < 0) { - /* Note that flush-to-zero does not affect half-precision results */ - is_tiny = - (status->float_detect_tininess == float_tininess_before_rounding) - || (zExp < -1) - || (!rounding_bumps_exp); - } - if (zSig & mask) { - float_raise(float_flag_inexact, status); - if (is_tiny) { - float_raise(float_flag_underflow, status); - } - } - - zSig += increment; - if (rounding_bumps_exp) { - zSig >>= 1; - zExp++; - } - - if (zExp < -10) { - return packFloat16(zSign, 0, 0); - } - if (zExp < 0) { - zSig >>= -zExp; - zExp = 0; - } - return packFloat16(zSign, zExp, zSig >> 13); -} - /*---------------------------------------------------------------------------- | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the value. @@ -3859,163 +3764,6 @@ float16 float16_squash_input_denormal(float16 a, float_status *status) return a; } -static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr, - uint32_t *zSigPtr) -{ - int8_t shiftCount = countLeadingZeros32(aSig) - 21; - *zSigPtr = aSig << shiftCount; - *zExpPtr = 1 - shiftCount; -} - -/* Half precision floats come in two formats: standard IEEE and "ARM" format. - The latter gains extra exponent range by omitting the NaN/Inf encodings. */ - -float32 float16_to_float32(float16 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - - aSign = extractFloat16Sign(a); - aExp = extractFloat16Exp(a); - aSig = extractFloat16Frac(a); - - if (aExp == 0x1f && ieee) { - if (aSig) { - return commonNaNToFloat32(float16ToCommonNaN(a, status), status); - } - return packFloat32(aSign, 0xff, 0); - } - if (aExp == 0) { - if (aSig == 0) { - return packFloat32(aSign, 0, 0); - } - - normalizeFloat16Subnormal(aSig, &aExp, &aSig); - aExp--; - } - return packFloat32( aSign, aExp + 0x70, aSig << 13); -} - -float16 float32_to_float16(float32 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - - a = float32_squash_input_denormal(a, status); - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - if ( aExp == 0xFF ) { - if (aSig) { - /* Input is a NaN */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0, 0); - } - return commonNaNToFloat16( - float32ToCommonNaN(a, status), status); - } - /* Infinity */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0x1f, 0x3ff); - } - return packFloat16(aSign, 0x1f, 0); - } - if (aExp == 0 && aSig == 0) { - return packFloat16(aSign, 0, 0); - } - /* Decimal point between bits 22 and 23. Note that we add the 1 bit - * even if the input is denormal; however this is harmless because - * the largest possible single-precision denormal is still smaller - * than the smallest representable half-precision denormal, and so we - * will end up ignoring aSig and returning via the "always return zero" - * codepath. - */ - aSig |= 0x00800000; - aExp -= 0x71; - - return roundAndPackFloat16(aSign, aExp, aSig, ieee, status); -} - -float64 float16_to_float64(float16 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - - aSign = extractFloat16Sign(a); - aExp = extractFloat16Exp(a); - aSig = extractFloat16Frac(a); - - if (aExp == 0x1f && ieee) { - if (aSig) { - return commonNaNToFloat64( - float16ToCommonNaN(a, status), status); - } - return packFloat64(aSign, 0x7ff, 0); - } - if (aExp == 0) { - if (aSig == 0) { - return packFloat64(aSign, 0, 0); - } - - normalizeFloat16Subnormal(aSig, &aExp, &aSig); - aExp--; - } - return packFloat64(aSign, aExp + 0x3f0, ((uint64_t)aSig) << 42); -} - -float16 float64_to_float16(float64 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint64_t aSig; - uint32_t zSig; - - a = float64_squash_input_denormal(a, status); - - aSig = extractFloat64Frac(a); - aExp = extractFloat64Exp(a); - aSign = extractFloat64Sign(a); - if (aExp == 0x7FF) { - if (aSig) { - /* Input is a NaN */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0, 0); - } - return commonNaNToFloat16( - float64ToCommonNaN(a, status), status); - } - /* Infinity */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0x1f, 0x3ff); - } - return packFloat16(aSign, 0x1f, 0); - } - shift64RightJamming(aSig, 29, &aSig); - zSig = aSig; - if (aExp == 0 && zSig == 0) { - return packFloat16(aSign, 0, 0); - } - /* Decimal point between bits 22 and 23. Note that we add the 1 bit - * even if the input is denormal; however this is harmless because - * the largest possible single-precision denormal is still smaller - * than the smallest representable half-precision denormal, and so we - * will end up ignoring aSig and returning via the "always return zero" - * codepath. - */ - zSig |= 0x00800000; - aExp -= 0x3F1; - - return roundAndPackFloat16(aSign, aExp, zSig, ieee, status); -} - /*---------------------------------------------------------------------------- | Returns the result of converting the double-precision floating-point value | `a' to the extended double-precision floating-point format. The conversion From patchwork Wed May 16 15:52:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136031 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1124886lji; Wed, 16 May 2018 09:13:36 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrYXBqSJ1GwJATBrvcxqmBbnxDGADSf8MFHg/FeDJ5oo0AzFuuIxik7B+YuQnIEp14hUgBv X-Received: by 2002:a0c:96f7:: with SMTP id b52-v6mr1553525qvd.170.1526487216380; Wed, 16 May 2018 09:13:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526487216; cv=none; d=google.com; s=arc-20160816; b=kHkWKeWd477exBICXiBJd5dmPubjPeeSC2tZaXay7sRGrUp+/H9U+UaTDgrbyJGJrD CtE2zmPYeKUY2oeVv1aMDKcA2k3lgKwt6ZcPC2wHUFEu+IV4RS/WzeZckdvpj4P14wnb UXp0cIcpSGL6cxBx4XpYWgW8Hw1MTc8Cksz6BibhGBw4Scc9Hs1lHnh/L/z6M3pVJdXD zGsi21wlu0T3/0pIJAaJpAWfgJ7vJEg/6lDrMwkbjfP8uJybXwxrHv94WeUPlqicS527 U60Gce0ddgbYLqjFJg+RK+LLb9vds7CRwrrDQp+53aoDyMa7z0NPeoluOllCVHRgNLtX eLWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=HCzhOWHu2+7g6xUjsUPmKAtx3rgdm8J3LWpkOAk/KmQ=; b=JRTLd/MEXG/YlXUScfN2P8/K5swWou2zspzs8fgrL+SfNbZhYCnAkEGgHWQPg9+Z+L yMrnkz47K12YPlcbGhkHdzd0kbSnfvoVe+uJOs6TUJ+C/u6QpxiMWAnP66dqnXT4YwrP fwG0YsFwgjTTOrKH0clOZHEPvu4FWNVCjma66PK8lDdOmSL+bQ7r4PYTkc7N9hZ5WC3O 5yP+qVoB87c5B+BK7XQhqy8EmQPrVGc+5aSkIF45wQpJ1QOspM6Fz+XaYEmduSjTMQiL tm/tXV+hw2J1M+n01xPPK1yZmCbEgdjlbfuFPTIqS9cE9yEAifCGNfh3XfxQWVV1DpSY kSNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NkVg6V9k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c01::229 Subject: [Qemu-devel] [PULL 13/28] target/arm: Use floatX_silence_nan when we have already checked for SNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 6 +++--- target/arm/helper.c | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) -- 2.17.0 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 4f8034c513..6f0eb83661 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -376,7 +376,7 @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp) float16 nan = a; if (float16_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float16_maybe_silence_nan(a, fpst); + nan = float16_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan = float16_default_nan(fpst); @@ -405,7 +405,7 @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp) float32 nan = a; if (float32_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float32_maybe_silence_nan(a, fpst); + nan = float32_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan = float32_default_nan(fpst); @@ -434,7 +434,7 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp) float64 nan = a; if (float64_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float64_maybe_silence_nan(a, fpst); + nan = float64_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan = float64_default_nan(fpst); diff --git a/target/arm/helper.c b/target/arm/helper.c index 238a3ceba8..e05c7230d4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11731,7 +11731,7 @@ float16 HELPER(recpe_f16)(float16 input, void *fpstp) float16 nan = f16; if (float16_is_signaling_nan(f16, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float16_maybe_silence_nan(f16, fpst); + nan = float16_silence_nan(f16, fpst); } if (fpst->default_nan_mode) { nan = float16_default_nan(fpst); @@ -11779,7 +11779,7 @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp) float32 nan = f32; if (float32_is_signaling_nan(f32, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float32_maybe_silence_nan(f32, fpst); + nan = float32_silence_nan(f32, fpst); } if (fpst->default_nan_mode) { nan = float32_default_nan(fpst); @@ -11827,7 +11827,7 @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp) float64 nan = f64; if (float64_is_signaling_nan(f64, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float64_maybe_silence_nan(f64, fpst); + nan = float64_silence_nan(f64, fpst); } if (fpst->default_nan_mode) { nan = float64_default_nan(fpst); @@ -11926,7 +11926,7 @@ float16 HELPER(rsqrte_f16)(float16 input, void *fpstp) float16 nan = f16; if (float16_is_signaling_nan(f16, s)) { float_raise(float_flag_invalid, s); - nan = float16_maybe_silence_nan(f16, s); + nan = float16_silence_nan(f16, s); } if (s->default_nan_mode) { nan = float16_default_nan(s); @@ -11970,7 +11970,7 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) float32 nan = f32; if (float32_is_signaling_nan(f32, s)) { float_raise(float_flag_invalid, s); - nan = float32_maybe_silence_nan(f32, s); + nan = float32_silence_nan(f32, s); } if (s->default_nan_mode) { nan = float32_default_nan(s); @@ -12013,7 +12013,7 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) float64 nan = f64; if (float64_is_signaling_nan(f64, s)) { float_raise(float_flag_invalid, s); - nan = float64_maybe_silence_nan(f64, s); + nan = float64_silence_nan(f64, s); } if (s->default_nan_mode) { nan = float64_default_nan(s); From patchwork Wed May 16 15:52:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136026 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1117937lji; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:29 -0700 Message-Id: <20180516155243.16937-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PULL 14/28] target/arm: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 1 - target/arm/helper.c | 12 ++---------- 2 files changed, 2 insertions(+), 11 deletions(-) -- 2.17.0 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 6f0eb83661..f92bdea732 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -466,7 +466,6 @@ float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env) set_float_rounding_mode(float_round_to_zero, &tstat); set_float_exception_flags(0, &tstat); r = float64_to_float32(a, &tstat); - r = float32_maybe_silence_nan(r, &tstat); exflags = get_float_exception_flags(&tstat); if (exflags & float_flag_inexact) { r = make_float32(float32_val(r) | 1); diff --git a/target/arm/helper.c b/target/arm/helper.c index e05c7230d4..db8bbe52a6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11348,20 +11348,12 @@ FLOAT_CONVS(ui, d, 64, u) /* floating point conversion */ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) { - float64 r = float32_to_float64(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float64_maybe_silence_nan(r, &env->vfp.fp_status); + return float32_to_float64(x, &env->vfp.fp_status); } float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) { - float32 r = float64_to_float32(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float32_maybe_silence_nan(r, &env->vfp.fp_status); + return float64_to_float32(x, &env->vfp.fp_status); } /* VFP3 fixed point conversion. */ From patchwork Wed May 16 15:52:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136034 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1127913lji; Wed, 16 May 2018 09:15:48 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqzsuXVBKKyeD/MDfqBif0fzn4skvYIyJmlPHLsTeMnbQa6Pm1T33bduBokoxCbbJGFgmLH X-Received: by 2002:a0c:a244:: with SMTP id f62-v6mr1522743qva.76.1526487348735; Wed, 16 May 2018 09:15:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526487348; cv=none; d=google.com; s=arc-20160816; b=ZufQukEUXfj+Cg99cpUcparnSRXRiwOZRA2jmZMmh5MiUh4fwUE5YMkbKMmBqwAJzi S1rfbkdDCdU3OFocu1Nw5C6JVWueflwxuieQFlky/FnNgFoG0vPYYKZKX4WDfUCpsuEp t2PwWZmjoXpIWSpli/Jr8gkNjwnEl36DGLBf0iV33d9DZzzOy/oouzAEH+AaL/Q6zJDa lHlnzTw2xGDNZhXMrlFuwJMv5uslX7+5eFSYtRYl8rBFL+/YmyAjUkYV0uzYYy+XsuFW 4Kb4/e6I6JNgnlFPxuVAJFASXsoGgmJEM9quPYyJMbKj6cXmbUrCbl5uf1z5SeZrgzcj xDRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=TD/lOXrmVofLedG4op9ymEqylnQt6zN7ClswSrkMaZc=; b=XTTfis34hWxI6Vh8BW01bKa15iAtT4+nGOCKfasKyHKyPxem84ex3k9xqLL1fxOlid rWaniHLswVAo7HfIC7e92jaG1n0cgcjSoYMYuTcLd9KqetrUuRfBqDd7Jypnw1fqOp41 Vb4TA3+Gj3BX76hSX0QfEZZF9WIaNMcrvGzmRRmRfIfE1UaSN7pbkZk/zIs/rHrSFF6G lCnbllrDXaz1fRUNrk3wCcdKJKFsdEJG8Dxr5kH7VUsJhNCi+0YfIdxnG+2boCE5dZ6U JVvylGt/HyTqUyDp9zyKDtIpFDLvLhaVIelUjJ+wVG+GucpnD9hbmTf8LT61zMqxV+jG FXYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PkVGOgVD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:30 -0700 Message-Id: <20180516155243.16937-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PULL 15/28] target/hppa: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/hppa/op_helper.c | 2 -- 1 file changed, 2 deletions(-) -- 2.17.0 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a3af62daf7..912e8d5be4 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -341,7 +341,6 @@ float64 HELPER(fdiv_d)(CPUHPPAState *env, float64 a, float64 b) float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg) { float64 ret = float32_to_float64(arg, &env->fp_status); - ret = float64_maybe_silence_nan(ret, &env->fp_status); update_fr0_op(env, GETPC()); return ret; } @@ -349,7 +348,6 @@ float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg) float32 HELPER(fcnv_d_s)(CPUHPPAState *env, float64 arg) { float32 ret = float64_to_float32(arg, &env->fp_status); - ret = float32_maybe_silence_nan(ret, &env->fp_status); update_fr0_op(env, GETPC()); return ret; } From patchwork Wed May 16 15:52:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136021 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1110632lji; Wed, 16 May 2018 09:03:10 -0700 (PDT) X-Google-Smtp-Source: AB8JxZogy0O+/bWHA5569JP5M4ziUDcvjhozm+kPjH+HTStIZ0+QDKETuaxOb90sEuZTumVeTG+Z X-Received: by 2002:a37:9682:: with SMTP id y124-v6mr1422893qkd.359.1526486590763; Wed, 16 May 2018 09:03:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526486590; cv=none; d=google.com; s=arc-20160816; b=RPj5hV1BumAu31yKnIq6zKcHfhDn+zvCLMpwmH35gnVlAE1a8haiJyFH0MoA3DNhns fIqzZwAiTC7MTL/Lfk4rzP9FwGj2CZlBVd+0C4g2UdUCkZhWKsLduFRb7CFpqNdXTQz2 LJDFtFyLD34Hns6c4WN77oSG8kMgaoYoNlF6jWgrHx+RUCvssL2Gmlp6Zk/UPdq9xh5V pu8V+MIiWQe3aMeGZ7inuqdW8Gi2pdM1S5pdnvaTRCuIlxOLKPdSAdPfyLEPjf5h2Wuk k2WYwAtlYZJgepMNc8ax46o37HdziR52BWfkZosxXxFDxtTONkc7gFeq8T0+PldWRMHQ eMCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=SPBg1TyIEk4O+QgkODhyiPa2jhkA37Z3ZFJ5t7jC9gU=; b=CuJ7RGoYmoa52RhEXNKTM0q1ID/aJCh/Iuvum171eMNrianKoWJeFTPQL7GUybPbTA /LzR6S6VcXqjnk7/TA8Y//qURPCAkAmct7R2r7VijzCr/jQw3bkynN6+oHxwXqH4FoaL ws7ZpOv5+vY10Q7c5T8WiyV4NlpjSTwCCL8AsI+ucu8JIih3GNb54NYZthR5FG64SNuu NOfVqUJTbbSPPSzH3K08mmrKtwsc1ario+JTDaTVz2BnWAktuQdjiqQaugJ5ZOmPLM4q /lcjT0vJUKLekmBX46OYH+GKUiloHtrp7pt+pOXKAg2Y4DuIvLlURecazbqhdh38RPXY bynA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kKMRlWGZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:31 -0700 Message-Id: <20180516155243.16937-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::232 Subject: [Qemu-devel] [PULL 16/28] target/m68k: Use floatX_silence_nan when we have already checked for SNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/softfloat.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.0 diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c index d093997219..b45a5e8690 100644 --- a/target/m68k/softfloat.c +++ b/target/m68k/softfloat.c @@ -31,13 +31,14 @@ static floatx80 propagateFloatx80NaNOneArg(floatx80 a, float_status *status) { if (floatx80_is_signaling_nan(a, status)) { float_raise(float_flag_invalid, status); + a = floatx80_silence_nan(a, status); } if (status->default_nan_mode) { return floatx80_default_nan(status); } - return floatx80_maybe_silence_nan(a, status); + return a; } /*---------------------------------------------------------------------------- From patchwork Wed May 16 15:52:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136037 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1135276lji; Wed, 16 May 2018 09:21:26 -0700 (PDT) X-Google-Smtp-Source: AB8JxZr8uHmTsc1os7WtTLzJAheO2IGzUXijMRwKSkjadh83Ev7RoT517Opfjut2QfCcnSgECmrC X-Received: by 2002:a37:50c4:: with SMTP id e187-v6mr1586743qkb.166.1526487685910; Wed, 16 May 2018 09:21:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526487685; cv=none; d=google.com; s=arc-20160816; b=BpqpEMF3Mw+967QD+q8+KBrnBTvXjI3jUdCfrcaIVodtK98ggWuep1oIVFd5hvvq9w zuT4PRv40nIN/hd+HaLVPrhg6QWf0s6tE7busPcu/gfKoqC0S+xUElqRrwGYNaVbTlm2 zPhCyHKLjs/rBHaxzSyo/bb8KwFbUbAFTcM9ywcuGe0ke52G2a+bipB6nHjY2WEC5TzA tfGddcPjLxSTkVxgPartPtClLoddBOLGsnxFqjz6H+kkl+Ht47Xyq2HWsTZYSxJXv49X 0yTOx1CBE5NhvC/BOxoLiXx1CQd8X1PKFLwWhqTeCYXkARwqJb5xjpcCsYcWiYIqmIh5 26gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=YG4WDuvg/nU14CtfIK1nI16sf1EHjyzdnNJh8QSrA1M=; b=NyJNI9yBVkM8+fIE9/Rru8CuJLHIxtHyjIFtbtAk+vbb9sN07GOL8+LMugGJjDJhfe IwiaegHy3IXIHPvcE0lWYUCxXSIA8M6F8uvfc0MrqcDaoDbJ0JMPrPy0guMCBrsKqh4n nFvT2jdhqA4mjluNoer86dupSdG7UxVsS+lNdpq4xqoNF8C10/Ozc2EIl3NmS6UQ1yYc oPt4SzJUSOGV4NcRdGQAtLgqHQjeyanqyKr4+S807jK+lN8Vmtib2nR1NZJoctOSZEnb fy8OZERqUIWylWOAPBOOALNZ5Mddoccbx/9mwDBvGU8hSkbM7YDKjy7Ha4N/HkEv1eig LIag== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZX/fcsS7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:32 -0700 Message-Id: <20180516155243.16937-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PULL 17/28] target/mips: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Yongbok Kim , Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Cc: Aurelien Jarno Cc: Yongbok Kim Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/mips/msa_helper.c | 4 ---- target/mips/op_helper.c | 2 -- 2 files changed, 6 deletions(-) -- 2.17.0 diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 8fb7a369ca..c74e3cdc65 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1615,7 +1615,6 @@ static inline float16 float16_from_float32(int32_t a, flag ieee, float16 f_val; f_val = float32_to_float16((float32)a, ieee, status); - f_val = float16_maybe_silence_nan(f_val, status); return a < 0 ? (f_val | (1 << 15)) : f_val; } @@ -1625,7 +1624,6 @@ static inline float32 float32_from_float64(int64_t a, float_status *status) float32 f_val; f_val = float64_to_float32((float64)a, status); - f_val = float32_maybe_silence_nan(f_val, status); return a < 0 ? (f_val | (1 << 31)) : f_val; } @@ -1636,7 +1634,6 @@ static inline float32 float32_from_float16(int16_t a, flag ieee, float32 f_val; f_val = float16_to_float32((float16)a, ieee, status); - f_val = float32_maybe_silence_nan(f_val, status); return a < 0 ? (f_val | (1 << 31)) : f_val; } @@ -1646,7 +1643,6 @@ static inline float64 float64_from_float32(int32_t a, float_status *status) float64 f_val; f_val = float32_to_float64((float64)a, status); - f_val = float64_maybe_silence_nan(f_val, status); return a < 0 ? (f_val | (1ULL << 63)) : f_val; } diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 798cdad030..9025f42366 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2700,7 +2700,6 @@ uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) uint64_t fdt2; fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); - fdt2 = float64_maybe_silence_nan(fdt2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return fdt2; } @@ -2790,7 +2789,6 @@ uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) uint32_t fst2; fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); - fst2 = float32_maybe_silence_nan(fst2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return fst2; } From patchwork Wed May 16 15:52:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136023 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1111559lji; Wed, 16 May 2018 09:03:49 -0700 (PDT) X-Google-Smtp-Source: AB8JxZo776Jbk3j8IQtmvwyJkLyVwLYLeYAzaijvMF+w/etj5drAMf/4PV6B+1sVf2PHDtvqb2+P X-Received: by 2002:ac8:431a:: with SMTP id z26-v6mr1585536qtm.377.1526486629468; Wed, 16 May 2018 09:03:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526486629; cv=none; d=google.com; s=arc-20160816; b=iudOkVMvOFTgxLjN87F4aApxrR4ODvcSEK7pTmOLCfXLBCyKiyG6y1EpDiqpFT9XxW elJVaFyN4obvyO3h6ocnbi6tcIojhkkwvreErmLE1OS3c6Ak30YvrNdtmJV+C5GqIgwn LtHprcjYwZappCkGT2HX5iv7QHktPzS/hEVK+RutAgjBakwazW65tSPFisT7Juf7hQLx ChghHoGdTR4SbRQcjltcrIPE9QLA8WiCoUOFT0JhZoFds1YlBddzDOzxHKTkRCChCfs/ lG1AurLMaXDwoV81zLwMCEK9pqVXkdYLZAP+7DVNssiEHZiv+xS9RXa/5JSKEUfk6DXb aMwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=lFbjHgIjVdntVwEG8TX8Zn/QYQH/a160DBSlPiGyBN4=; b=ZxkxuSgt/J7fI2iXTBRCMuc2nZrQ0fr5TK9KAJjbHbowyuaYROc0v2CCdIPpH1Ctcw FlgKYM7joUaZklTN10cfOEmBO/OAd6CdJuL1TgE+5sqosLJORzGnzMxcwhVKIpyU/J0H 4xbI9eol/eWkM+P0AirS8TobDVh073S+tWZ7fNG9WISrPFmfQJddsmWpz4KobUzhZWLL EVXV52RoLmJdW+BCip63xFykKeqh3SWRW6nav8QC4EvIHTh8lo3uVPwYLfsmmUCdi/zZ zjjAuJWiZ8necN9uQ+iJMWHjmXeG8lEY9Fpwe4MLHd70J+XYchv4WHnynRnniVyzfBZl bD+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DSLRegSy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:33 -0700 Message-Id: <20180516155243.16937-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::229 Subject: [Qemu-devel] [PULL 18/28] target/riscv: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Reviewed-by: Michael Clark Signed-off-by: Richard Henderson --- target/riscv/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.17.0 diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index abbadead5c..fdb87d8d82 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -279,14 +279,12 @@ uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) { - rs1 = float64_to_float32(rs1, &env->fp_status); - return float32_maybe_silence_nan(rs1, &env->fp_status); + return float64_to_float32(rs1, &env->fp_status); } uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) { - rs1 = float32_to_float64(rs1, &env->fp_status); - return float64_maybe_silence_nan(rs1, &env->fp_status); + return float32_to_float64(rs1, &env->fp_status); } uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) From patchwork Wed May 16 15:52:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136028 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1120010lji; Wed, 16 May 2018 09:09:48 -0700 (PDT) X-Google-Smtp-Source: AB8JxZp9RSywqi6feXukVDRncwQtuzoySp6TYMhoJx3AM7y+scdrr/Mfa77ecgAMDTomjoHyXwsk X-Received: by 2002:ae9:e105:: with SMTP id g5-v6mr1456439qkm.236.1526486988263; Wed, 16 May 2018 09:09:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526486988; cv=none; d=google.com; s=arc-20160816; b=daZenB0ts5IP8u0tINNwMwBN3/LKBEHxPN+i815xQN46P4o+hgdEunkeFTeQrR6x3x Yqs71Npnd4Iojy188yunQ54uw6oYVa1aNPCPZ68pdDLZGm7Dm9GuET33NbtfqI7+BiW8 21beD568ARWIDc+FA3MDwg+af3iLUfpp6EI12JmqrTwF/OMYbh4UO7cXHIyQ2TuHRPBM TjaOAxOTEIMaNv8qRZURbQHFb4MNkWNTi0RE+qlUzI6mQupqbOK+ir9olegWf91k/5zO ooZOJrj7fNjFwOKPaL5pZ1Hthd+6IZyhJQ9564DYKY5fCWrMalZ4swWQomNcUqOFKQ36 thtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=N/MQDXmC5P0rKEPWLGL6olcs6gD/4PAiety6G0UTpec=; b=cyUfeDISnbAg1A9pCdSKOdKYlJu09poXrQQM0l/S4mgTI9NcRH5TWtsnXHPpyA1XpE oIBdUwIzPysrJEu1lKhrjFp2G9NpIt+Wd9+/ZL0cJ4hIjnTq2t8Gw9RFonz+xFRiEOYI YqaKTvapctou48vz7BOWvEPomtrPJ2DLj+bUxTo/CCLrwYb1Fr6oSvEvgJzqQPdLjJCo BqMH8kdrYtevD6DN0KmuTSsNeXwp43CyZU2JcPY3ENhhMAurtBsygMgAqjVoWk8/oGSW ijdoPAPPnEUnIUWN6Ct0M32PVfAuWeGpdVt2DW4EACzt9Is7+TbvHrv8rO6lLlIN3jc6 UFBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X+Dv0iLk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:34 -0700 Message-Id: <20180516155243.16937-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PULL 19/28] target/s390x: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Alexander Graf Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Cc: Alexander Graf Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/fpu_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.17.0 diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c index 43f8bf1c94..5c5b451b3b 100644 --- a/target/s390x/fpu_helper.c +++ b/target/s390x/fpu_helper.c @@ -269,7 +269,7 @@ uint64_t HELPER(ldeb)(CPUS390XState *env, uint64_t f2) { float64 ret = float32_to_float64(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return float64_maybe_silence_nan(ret, &env->fpu_status); + return ret; } /* convert 128-bit float to 64-bit float */ @@ -277,7 +277,7 @@ uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, uint64_t al) { float64 ret = float128_to_float64(make_float128(ah, al), &env->fpu_status); handle_exceptions(env, GETPC()); - return float64_maybe_silence_nan(ret, &env->fpu_status); + return ret; } /* convert 64-bit float to 128-bit float */ @@ -285,7 +285,7 @@ uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) { float128 ret = float64_to_float128(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return RET128(float128_maybe_silence_nan(ret, &env->fpu_status)); + return RET128(ret); } /* convert 32-bit float to 128-bit float */ @@ -293,7 +293,7 @@ uint64_t HELPER(lxeb)(CPUS390XState *env, uint64_t f2) { float128 ret = float32_to_float128(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return RET128(float128_maybe_silence_nan(ret, &env->fpu_status)); + return RET128(ret); } /* convert 64-bit float to 32-bit float */ @@ -301,7 +301,7 @@ uint64_t HELPER(ledb)(CPUS390XState *env, uint64_t f2) { float32 ret = float64_to_float32(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return float32_maybe_silence_nan(ret, &env->fpu_status); + return ret; } /* convert 128-bit float to 32-bit float */ @@ -309,7 +309,7 @@ uint64_t HELPER(lexb)(CPUS390XState *env, uint64_t ah, uint64_t al) { float32 ret = float128_to_float32(make_float128(ah, al), &env->fpu_status); handle_exceptions(env, GETPC()); - return float32_maybe_silence_nan(ret, &env->fpu_status); + return ret; } /* 32-bit FP compare */ From patchwork Wed May 16 15:52:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136039 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1138720lji; Wed, 16 May 2018 09:24:03 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoCF0aAIPPEeKrszQ0GxjIW9BHxniFTG+sIzOwqHjfUFXsVbmWkaW7vepnKx2pUPTgTX5ad X-Received: by 2002:a37:9804:: with SMTP id a4-v6mr1514774qke.4.1526487843363; Wed, 16 May 2018 09:24:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526487843; cv=none; d=google.com; s=arc-20160816; b=BFQCqT9HG89RUwBjv953Fs/B0gHNvSKzhv5lyVmR//9Sn2yyvE0LKHQxAb0Dghqs0f 7Qcpim0NrlsrpfJpRFvIYcIV3Jtm0PU90rqJ8ott5R7IoOciIGnmO9EjyeqvTl7hOGfT v1HLrp7aUIEQRF+Phi0itAfNM3/hcGzAB/vY2ErE/SfdFHrtJWMqlGWhLShMsFyqD13z nM02cWs/Uj7wVtlNor0c+Ty4F0Aor7pfNoc5IelP9na1A7U2TRhEm6W51w2f/SepbGjE HoUAgk/bFBAxDdJQxxWWpIRa/o26aIjFYWoeuy4eINetbkTv3gms5G5xDhZlryYX/tQe mrIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=h62BzzH4LLhuXxYTEWEspmGWZCobGiYio26vYR2atOs=; b=dk9Y60cpoCKLH9TVw/wT9ytTVq5rRfxglSM5/5qsy5u4a6PiAZTikjluyBvT7onMit C9cWL3xhfprXDy3zuFLos4Bop0fDeF3EAPbRxOtPOZvKnqZBrBNVBpjEGf6Acg9Fo0L6 3kMELV8YFWagIPeE0CJMzv7xvetVF33j5icXLOVTfaVBYu1hmXXBGUOLmwAALFUAqcXE DlI7ufs9VMWFSap8dKAyDg6W5ihkKemAqQEypQRtQibC1kBd+UKbp3JYCyHuRrpSTRjz 74/DRI/+Uu3P1d0oO1tZztbSDoQeam3KiZBKQeQxAVgJC12TWE/LNkAexT4u2r4F1dBw DqjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BQTWQtja; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:35 -0700 Message-Id: <20180516155243.16937-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PULL 20/28] fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have already checked the arguments for SNaN; we don't need to do it again. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 44 +++++++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 10 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 995a0132c6..4fa068a5dc 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -498,7 +498,7 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status) | The routine is passed various bits of information about the | two NaNs and should return 0 to select NaN a and 1 for NaN b. | Note that signalling NaNs are always squashed to quiet NaNs -| by the caller, by calling floatXX_maybe_silence_nan() before +| by the caller, by calling floatXX_silence_nan() before | returning them. | | aIsLargerSignificand is only valid if both a and b are NaNs @@ -536,7 +536,7 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, { /* According to MIPS specifications, if one of the two operands is * a sNaN, a new qNaN has to be generated. This is done in - * floatXX_maybe_silence_nan(). For qNaN inputs the specifications + * floatXX_silence_nan(). For qNaN inputs the specifications * says: "When possible, this QNaN result is one of the operand QNaN * values." In practice it seems that most implementations choose * the first operand if both operands are qNaN. In short this gives @@ -788,9 +788,15 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float32_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float32_silence_nan(b, status); + } + return b; } else { - return float32_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float32_silence_nan(a, status); + } + return a; } } @@ -950,9 +956,15 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float64_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float64_silence_nan(b, status); + } + return b; } else { - return float64_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float64_silence_nan(a, status); + } + return a; } } @@ -1121,9 +1133,15 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return floatx80_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return floatx80_silence_nan(b, status); + } + return b; } else { - return floatx80_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return floatx80_silence_nan(a, status); + } + return a; } } @@ -1270,8 +1288,14 @@ static float128 propagateFloat128NaN(float128 a, float128 b, if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float128_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float128_silence_nan(b, status); + } + return b; } else { - return float128_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float128_silence_nan(a, status); + } + return a; } } From patchwork Wed May 16 15:52:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136041 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1142079lji; Wed, 16 May 2018 09:26:34 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrKxBtACD8WDFsisK7AGwQ1uEmdzMLxW2ymkFSaPKXkkRnTrOuSTK/h1bpwmIcvp7Vt1Eal X-Received: by 2002:aed:2b03:: with SMTP id p3-v6mr1661996qtd.44.1526487994771; Wed, 16 May 2018 09:26:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526487994; cv=none; d=google.com; s=arc-20160816; b=IESPxWXeAeOMGn9EHicSj6jg3LEepQWU+z9WqFD0mVfk50CEVBf5rPrh2F8b0/WXfY 8MjHWiL/FvtOCAbzjEsAoBCAR/WWdYoIDgRysbPYJNp7ZGJ18jYK7uMMwsKb5W9iOYM/ 0i0oVom0erUm6DSfmrIsdKxdFda8nbA80GM9Lzaq4wS6r0G6ZfQJOCQgNjd08SQHuMXr aHTcDeIb224YFjG43PsFP9F1UgKNnPI7beWXQIzzmxJ7bQ8cBSnuaMamQJqBpWuyOFyq 1BUDLrPg/MclJ7HB7jAL+pqm4VHW25Cz7GKj3CChd1uM1Kr97BQ5bNp7xtBPf1q9wCwn DOPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=RsqR6JXjuFwzF6uI5jtDfE8pIEemv36hmgqjkM16TQs=; b=V8I8fgEH7zHek8RdWAWs+zO6+HSrLC9B5uTa06cHhVw0TnwR8Z2RctsVD5ySXzGeQU k5fhah5agaB+e2UHmGTxf5t7cA78Hu7mZovPVCGGyeQeVxlvgT7oCwMIvZpf/qWcySx3 NHCYT9nZlRcfP4PzoqI1+ms1hQDgdeUlmXxgv5dwGZXEHFm0flrbt3i2JbHfH+TbBS3y Jr9bHBQ8ZxkItOYD9kkQQZYp4pqn+8wDdp9DxbaqdlB3ZzDL2yur0LilHuQUes2L1Q6f ME1epodhlgivzj7+j+yYt6b/c+7xpAaQRui68jrofCfyZ06Moa5qFtnqzfVenrIABL5h nyJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CELl1lEo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:36 -0700 Message-Id: <20180516155243.16937-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::234 Subject: [Qemu-devel] [PULL 21/28] fpu/softfloat: Remove floatX_maybe_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These functions are now unused. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 63 -------------------------------------- include/fpu/softfloat.h | 5 --- 2 files changed, 68 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 4fa068a5dc..d7033b7757 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -364,19 +364,6 @@ float16 float16_silence_nan(float16 a, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the half-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -float16 float16_maybe_silence_nan(float16 a, float_status *status) -{ - if (float16_is_signaling_nan(a, status)) { - return float16_silence_nan(a, status); - } - return a; -} - /*---------------------------------------------------------------------------- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -438,18 +425,6 @@ float32 float32_silence_nan(float32 a, float_status *status) } #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the single-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -float32 float32_maybe_silence_nan(float32 a, float_status *status) -{ - if (float32_is_signaling_nan(a, status)) { - return float32_silence_nan(a, status); - } - return a; -} /*---------------------------------------------------------------------------- | Returns the result of converting the single-precision floating-point NaN @@ -864,18 +839,6 @@ float64 float64_silence_nan(float64 a, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the double-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -float64 float64_maybe_silence_nan(float64 a, float_status *status) -{ - if (float64_is_signaling_nan(a, status)) { - return float64_silence_nan(a, status); - } - return a; -} /*---------------------------------------------------------------------------- | Returns the result of converting the double-precision floating-point NaN @@ -1037,19 +1000,6 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the extended double-precision floating point value -| `a' is a signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status) -{ - if (floatx80_is_signaling_nan(a, status)) { - return floatx80_silence_nan(a, status); - } - return a; -} - /*---------------------------------------------------------------------------- | Returns the result of converting the extended double-precision floating- | point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the @@ -1204,19 +1154,6 @@ float128 float128_silence_nan(float128 a, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the quadruple-precision floating point value `a' is -| a signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -float128 float128_maybe_silence_nan(float128 a, float_status *status) -{ - if (float128_is_signaling_nan(a, status)) { - return float128_silence_nan(a, status); - } - return a; -} - /*---------------------------------------------------------------------------- | Returns the result of converting the quadruple-precision floating-point NaN | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index a6860e858d..69f4dbc4db 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -258,7 +258,6 @@ int float16_compare_quiet(float16, float16, float_status *status); int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); float16 float16_silence_nan(float16, float_status *status); -float16 float16_maybe_silence_nan(float16, float_status *status); static inline int float16_is_any_nan(float16 a) { @@ -370,7 +369,6 @@ float32 float32_maxnummag(float32, float32, float_status *status); int float32_is_quiet_nan(float32, float_status *status); int float32_is_signaling_nan(float32, float_status *status); float32 float32_silence_nan(float32, float_status *status); -float32 float32_maybe_silence_nan(float32, float_status *status); float32 float32_scalbn(float32, int, float_status *status); static inline float32 float32_abs(float32 a) @@ -500,7 +498,6 @@ float64 float64_maxnummag(float64, float64, float_status *status); int float64_is_quiet_nan(float64 a, float_status *status); int float64_is_signaling_nan(float64, float_status *status); float64 float64_silence_nan(float64, float_status *status); -float64 float64_maybe_silence_nan(float64, float_status *status); float64 float64_scalbn(float64, int, float_status *status); static inline float64 float64_abs(float64 a) @@ -604,7 +601,6 @@ int floatx80_compare_quiet(floatx80, floatx80, float_status *status); int floatx80_is_quiet_nan(floatx80, float_status *status); int floatx80_is_signaling_nan(floatx80, float_status *status); floatx80 floatx80_silence_nan(floatx80, float_status *status); -floatx80 floatx80_maybe_silence_nan(floatx80, float_status *status); floatx80 floatx80_scalbn(floatx80, int, float_status *status); static inline floatx80 floatx80_abs(floatx80 a) @@ -816,7 +812,6 @@ int float128_compare_quiet(float128, float128, float_status *status); int float128_is_quiet_nan(float128, float_status *status); int float128_is_signaling_nan(float128, float_status *status); float128 float128_silence_nan(float128, float_status *status); -float128 float128_maybe_silence_nan(float128, float_status *status); float128 float128_scalbn(float128, int, float_status *status); static inline float128 float128_abs(float128 a) From patchwork Wed May 16 15:52:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136038 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1138089lji; Wed, 16 May 2018 09:23:35 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoIJ5LfHOU5mFa/yfSiN4WUdn3m/235aD/sLfk8m57W7f8lo1f5ngoIEJlZso97C/UozxX4 X-Received: by 2002:a0c:83e5:: with SMTP id k92-v6mr1603769qva.85.1526487815020; Wed, 16 May 2018 09:23:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526487815; cv=none; d=google.com; s=arc-20160816; b=OmeD+f+z0W1rLAhzf1WQFBTmlXeeLG7LhE34QYu5dYG9q5DiGV7DWPWvZRHFKdmPLh rFJXF5zJnKIbcGtmHpObxA126PcHwYdZFf5itCZ3e0vIAp2O0qeWsA3TGhVrygekGTYJ KFKrsRtsnAuiqp47EUK5lsJJljqzzOk9JZT2r+VhllVw+74ZoeTiY6JJi0+TKhapo72A SOuZS1wP8S+EIfm5UcdkLdea3BeQsIB7EQp4+A8kaoRzqiyLrECj0xRUbOE201brciuk N9TvqZGrymuA8S6x4ns4Vluu+Gjq+2h9ySCCFbvl7dTFI0MuQB1gu0sM5ZkjkM+Svpfr 2r5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=qT+dcRle1BZEnASBKOdKNp0UGnIwNg5lHSBhmnCFOZ0=; b=IbxlhhrAMBGm+mPMte1PwAbP+NoX7dyxFVfP3sfeFq1fKkWpVr2zTUZvxNVfyIWU6S g/VB5JxYukPQ/1VVC3YcoRL4mMDLe7IB3HvuWNaWSc/BIywk55ujzac1twx7dQiJdOZO O8Vug1y55QL/w9xqTJsa7xdQe7C+ZilK3dWNfEGGYq+ly0onhUDMsCit04WCi9EYn5eq 2bZL4jVqHWNtUSl53Xn5bqbxODXlILyRE31foC6Jn2L9RBqmcyNQbBFkZE+UchPexyDL +PVZGh70vrLpKYDlk1KFqNI57qgKzWhFyNd1Gp1e6XCdDTDszwZTdMECm/oJKSvP2+HI kNEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WMtcwxjv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:37 -0700 Message-Id: <20180516155243.16937-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PULL 22/28] fpu/softfloat: Specialize on snan_bit_is_one X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Alexander Graf , Guan Xuetao , Yongbok Kim , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Only MIPS requires snan_bit_is_one to be variable. While we are specializing softfloat behaviour, allow other targets to eliminate this runtime check. Cc: Aurelien Jarno Cc: Yongbok Kim Cc: David Gibson Cc: Alexander Graf Cc: Guan Xuetao Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 68 ++++++++++++++++++++++------------- include/fpu/softfloat-types.h | 1 + target/hppa/cpu.c | 1 - target/ppc/fpu_helper.c | 1 - target/sh4/cpu.c | 1 - target/unicore32/cpu.c | 2 -- 6 files changed, 44 insertions(+), 30 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index d7033b7757..d1e06da75b 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -79,13 +79,31 @@ this code that are retained. * version 2 or later. See the COPYING file in the top-level directory. */ -#if defined(TARGET_XTENSA) /* Define for architectures which deviate from IEEE in not supporting * signaling NaNs (so all NaNs are treated as quiet). */ +#if defined(TARGET_XTENSA) #define NO_SIGNALING_NANS 1 #endif +/* Define how the architecture discriminates signaling NaNs. + * This done with the most significant bit of the fraction. + * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 + * the msb must be zero. MIPS is (so far) unique in supporting both the + * 2008 revision and backward compatibility with their original choice. + * Thus for MIPS we must make the choice at runtime. + */ +static inline flag snan_bit_is_one(float_status *status) +{ +#if defined(TARGET_MIPS) + return status->snan_bit_is_one; +#elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4) + return 1; +#else + return 0; +#endif +} + /*---------------------------------------------------------------------------- | For the deconstructed floating-point with fraction FRAC, return true | if the fraction represents a signalling NaN; otherwise false. @@ -97,7 +115,7 @@ static bool parts_is_snan_frac(uint64_t frac, float_status *status) return false; #else flag msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); - return msb == status->snan_bit_is_one; + return msb == snan_bit_is_one(status); #endif } @@ -118,7 +136,7 @@ static FloatParts parts_default_nan(float_status *status) #elif defined(TARGET_HPPA) frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; } else { #if defined(TARGET_MIPS) @@ -151,7 +169,7 @@ static FloatParts parts_silence_nan(FloatParts a, float_status *status) a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return parts_default_nan(status); } else { a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); @@ -169,7 +187,7 @@ float16 float16_default_nan(float_status *status) #if defined(TARGET_ARM) return const_float16(0x7E00); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return const_float16(0x7DFF); } else { #if defined(TARGET_MIPS) @@ -195,7 +213,7 @@ float32 float32_default_nan(float_status *status) #elif defined(TARGET_HPPA) return const_float32(0x7FA00000); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return const_float32(0x7FBFFFFF); } else { #if defined(TARGET_MIPS) @@ -220,7 +238,7 @@ float64 float64_default_nan(float_status *status) #elif defined(TARGET_HPPA) return const_float64(LIT64(0x7FF4000000000000)); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return const_float64(LIT64(0x7FF7FFFFFFFFFFFF)); } else { #if defined(TARGET_MIPS) @@ -242,7 +260,7 @@ floatx80 floatx80_default_nan(float_status *status) r.low = LIT64(0xFFFFFFFFFFFFFFFF); r.high = 0x7FFF; #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { r.low = LIT64(0xBFFFFFFFFFFFFFFF); r.high = 0x7FFF; } else { @@ -274,7 +292,7 @@ float128 float128_default_nan(float_status *status) { float128 r; - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { r.low = LIT64(0xFFFFFFFFFFFFFFFF); r.high = LIT64(0x7FFF7FFFFFFFFFFF); } else { @@ -319,7 +337,7 @@ int float16_is_quiet_nan(float16 a_, float_status *status) return float16_is_any_nan(a_); #else uint16_t a = float16_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); } else { return ((a & ~0x8000) >= 0x7C80); @@ -338,7 +356,7 @@ int float16_is_signaling_nan(float16 a_, float_status *status) return 0; #else uint16_t a = float16_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a & ~0x8000) >= 0x7C80); } else { return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); @@ -356,7 +374,7 @@ float16 float16_silence_nan(float16 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return float16_default_nan(status); } else { return a | (1 << 9); @@ -375,7 +393,7 @@ int float32_is_quiet_nan(float32 a_, float_status *status) return float32_is_any_nan(a_); #else uint32_t a = float32_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); } else { return ((uint32_t)(a << 1) >= 0xFF800000); @@ -394,7 +412,7 @@ int float32_is_signaling_nan(float32 a_, float_status *status) return 0; #else uint32_t a = float32_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((uint32_t)(a << 1) >= 0xFF800000); } else { return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); @@ -412,7 +430,7 @@ float32 float32_silence_nan(float32 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { # ifdef TARGET_HPPA a &= ~0x00400000; a |= 0x00200000; @@ -651,7 +669,7 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, return 3; } - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { /* Prefer sNaN over qNaN, in the a, b, c order. */ if (aIsSNaN) { return 0; @@ -786,7 +804,7 @@ int float64_is_quiet_nan(float64 a_, float_status *status) return float64_is_any_nan(a_); #else uint64_t a = float64_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a >> 51) & 0xFFF) == 0xFFE) && (a & 0x0007FFFFFFFFFFFFULL); } else { @@ -806,7 +824,7 @@ int float64_is_signaling_nan(float64 a_, float_status *status) return 0; #else uint64_t a = float64_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a << 1) >= 0xFFF0000000000000ULL); } else { return (((a >> 51) & 0xFFF) == 0xFFE) @@ -825,7 +843,7 @@ float64 float64_silence_nan(float64 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { # ifdef TARGET_HPPA a &= ~0x0008000000000000ULL; a |= 0x0004000000000000ULL; @@ -942,7 +960,7 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *status) #ifdef NO_SIGNALING_NANS return floatx80_is_any_nan(a); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { uint64_t aLow; aLow = a.low & ~0x4000000000000000ULL; @@ -967,7 +985,7 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) #ifdef NO_SIGNALING_NANS return 0; #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a.high & 0x7FFF) == 0x7FFF) && ((a.low << 1) >= 0x8000000000000000ULL); } else { @@ -991,7 +1009,7 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return floatx80_default_nan(status); } else { a.low |= LIT64(0xC000000000000000); @@ -1105,7 +1123,7 @@ int float128_is_quiet_nan(float128 a, float_status *status) #ifdef NO_SIGNALING_NANS return float128_is_any_nan(a); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a.high >> 47) & 0xFFFF) == 0xFFFE) && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); } else { @@ -1125,7 +1143,7 @@ int float128_is_signaling_nan(float128 a, float_status *status) #ifdef NO_SIGNALING_NANS return 0; #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a.high << 1) >= 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); } else { @@ -1145,7 +1163,7 @@ float128 float128_silence_nan(float128 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return float128_default_nan(status); } else { a.high |= LIT64(0x0000800000000000); diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 4e378cb612..2aae6a89b1 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -173,6 +173,7 @@ typedef struct float_status { /* should denormalised inputs go to zero and set the input_denormal flag? */ flag flush_inputs_to_zero; flag default_nan_mode; + /* not always used -- see snan_bit_is_one() in softfloat-specialize.h */ flag snan_bit_is_one; } float_status; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c261b6b090..00bf444620 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -141,7 +141,6 @@ static void hppa_cpu_initfn(Object *obj) cs->env_ptr = env; cs->exception_index = -1; cpu_hppa_loaded_fr0(env); - set_snan_bit_is_one(true, &env->fp_status); cpu_hppa_put_psw(env, PSW_W); } diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 9ae418a577..d31a933cbb 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3382,7 +3382,6 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode) xt.f128 = xb.f128; } else if (float128_is_neg(xb.f128) && !float128_is_zero(xb.f128)) { float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); - set_snan_bit_is_one(0, &env->fp_status); xt.f128 = float128_default_nan(&env->fp_status); } } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 541ffc2d97..b9f393b7c7 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -71,7 +71,6 @@ static void superh_cpu_reset(CPUState *s) set_flush_to_zero(1, &env->fp_status); #endif set_default_nan_mode(1, &env->fp_status); - set_snan_bit_is_one(1, &env->fp_status); } static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 29d160a88d..68f978d80b 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -70,7 +70,6 @@ static void unicore_ii_cpu_initfn(Object *obj) set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); - set_snan_bit_is_one(1, &env->ucf64.fp_status); } static void uc32_any_cpu_initfn(Object *obj) @@ -83,7 +82,6 @@ static void uc32_any_cpu_initfn(Object *obj) set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); - set_snan_bit_is_one(1, &env->ucf64.fp_status); } static void uc32_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Wed May 16 15:52:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136030 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1120648lji; Wed, 16 May 2018 09:10:18 -0700 (PDT) X-Google-Smtp-Source: AB8JxZr45de2tq/ANzd9MEm4IeVk8vQREGd8ns512Av5Ms9VNLLMalNuyTPxvhIvrih0CpK0/e0J X-Received: by 2002:a37:49d8:: with SMTP id w207-v6mr1430761qka.139.1526487017926; Wed, 16 May 2018 09:10:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526487017; cv=none; d=google.com; s=arc-20160816; b=DLPjsG9/m19CJIxK/z8KyC/rQbPA5+j5psVY/adtywqxnBbOf5uzNlMiaSndf8YhYf udT5n2IgQxIuCnt4PmItZ0Bo5LOtg/230Newch+mBO83uND26SBIqlKRoE4dEZGcsXAZ aFRuCZknHdCIC+F1lrU5ahAA1mfPJEdb5GtJerqhGuLnA7L2DoBfo5CZzvvroVwRSi7u ALwuT5S76o5pefBhrrpT91TTZedxWXayhQYZoNH9WWgZ/ReUA+tvmC0BBCP4mbKtqmQ5 Op8Ja9bLCwHKh0EiuXTCh4zLbrpxVyeJw7ryldr+W8RvnFzcdqsDmlHjVQHzOCvPGyx+ AkeA== ARC-Message-Signature: i=1; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:38 -0700 Message-Id: <20180516155243.16937-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 23/28] fpu/softfloat: Make is_nan et al available to softfloat-specialize.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will need these helpers within softfloat-specialize.h, so move the definitions above the include. After specialization, they will not always be used so mark them to avoid the Werror. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 55e6701f26..ea252e0c84 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -181,6 +181,22 @@ typedef enum __attribute__ ((__packed__)) { float_class_snan, } FloatClass; +/* Simple helpers for checking if, or what kind of, NaN we have */ +static inline __attribute__((unused)) bool is_nan(FloatClass c) +{ + return unlikely(c >= float_class_qnan); +} + +static inline __attribute__((unused)) bool is_snan(FloatClass c) +{ + return c == float_class_snan; +} + +static inline __attribute__((unused)) bool is_qnan(FloatClass c) +{ + return c == float_class_qnan; +} + /* * Structure holding all of the decomposed parts of a float. The * exponent is unbiased and the fraction is normalized. All @@ -536,20 +552,6 @@ static float64 float64_round_pack_canonical(FloatParts p, float_status *s) return float64_pack_raw(round_canonical(p, s, &float64_params)); } -/* Simple helpers for checking if what NaN we have */ -static bool is_nan(FloatClass c) -{ - return unlikely(c >= float_class_qnan); -} -static bool is_snan(FloatClass c) -{ - return c == float_class_snan; -} -static bool is_qnan(FloatClass c) -{ - return c == float_class_qnan; -} - static FloatParts return_nan(FloatParts a, float_status *s) { switch (a.cls) { From patchwork Wed May 16 15:52:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136036 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1131555lji; Wed, 16 May 2018 09:18:28 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqZPRxfY/8Prdau9K5MiDEqjLgzHeKu0jN6U1YVUiBFJfIyiXqIFCarhBHetmpghMCWb7JB X-Received: by 2002:a0c:bc91:: with SMTP id l17-v6mr1575371qvg.228.1526487508408; Wed, 16 May 2018 09:18:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526487508; cv=none; d=google.com; s=arc-20160816; b=XRZjrYqlX+kmROQVhSyA/FFZYjzVm07qBlbeNcs9RKO77Gozy9OMnsYSmtTRmmCnr1 aXkPgMWIoW4pBOV16Z7SdeWCz6gVcar4xL67MNbsYzjFh7BOJ8101X/D8wCTzNUfBNeS 0xFaFpoeTlMWUhqcEiCFiUPokiT1gHTBtBbIrX9297t6LB7cCjPHQxGB3M5kGbYGVHGH TTz6OFh/+Kgs2ZxFxsbJsydKQwZH6WcCcaC6qK13zSzdNQj7sGJMf4D1kEsf4O17HqGR wzYWV0Q0gkW0uI2huWtTB/9JYtSK9wi8zMy8WUYqTdIi4DuA7dZfbYjIlCykrQYOCF+y bcaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ZlRhHgLQ4KpeMhtq0dx6G/jOtWDQQYOnoKzkDphqGgs=; b=jXTpHaLLmhbsLRhoYWACvNKAYyyhz93GP2vKxBfIdUtZmhYtYTHSu9GBA+5TeGi1Z1 2E9/0fRS3c0EdNV4YXzrjekK/OKGBx8HKaeHv9ly5n3kFJkq25aiQbS2c2AgUr9XJV96 RqHRx/h53tfUww7EqqlNiLMSJ2NnqOQql5n8MTl28/gqDtcs76rqaWLXohILCke9z18p BLLAm1fJBRga1PT3zzli6Ns4P1RPDvJ8vSbGZlzyArFUFyOimKr+hToyaDSgHz+MaHN2 WUmF5TXy9Mu9RLwp7fkmSJdPC9P42hBzzAx4cT8IHq7crYieE+OjDOnlXekV3cN/m9M+ n+6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WZnWON4p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:39 -0700 Message-Id: <20180516155243.16937-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL 24/28] fpu/softfloat: Pass FloatClass to pickNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For each operand, pass a single enumeration instead of a pair of booleans. The commit also merges multiple different ifdef-selected implementations of pickNaN into a single function whose body is ifdef-selected. Tested-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 168 ++++++++++++++++++------------------- fpu/softfloat.c | 3 +- 2 files changed, 82 insertions(+), 89 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index d1e06da75b..2695183188 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -501,10 +501,10 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status) | tie-break rule. *----------------------------------------------------------------------------*/ -#if defined(TARGET_ARM) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, +static int pickNaN(FloatClass a_cls, FloatClass b_cls, flag aIsLargerSignificand) { +#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take * the first of: * 1. A if it is signaling @@ -513,20 +513,6 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, * 4. B (quiet) * A signaling NaN is always quietened before returning it. */ - if (aIsSNaN) { - return 0; - } else if (bIsSNaN) { - return 1; - } else if (aIsQNaN) { - return 0; - } else { - return 1; - } -} -#elif defined(TARGET_MIPS) || defined(TARGET_HPPA) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* According to MIPS specifications, if one of the two operands is * a sNaN, a new qNaN has to be generated. This is done in * floatXX_silence_nan(). For qNaN inputs the specifications @@ -540,35 +526,21 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, * 4. B (quiet) * A signaling NaN is always silenced before returning it. */ - if (aIsSNaN) { + if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } -} -#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ +#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K) /* PowerPC propagation rules: * 1. A if it sNaN or qNaN * 2. B if it sNaN or qNaN * A signaling NaN is always silenced before returning it. */ - if (aIsSNaN || aIsQNaN) { - return 0; - } else { - return 1; - } -} -#elif defined(TARGET_M68K) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL * 3.4 FLOATING-POINT INSTRUCTION DETAILS * If either operand, but not both operands, of an operation is a @@ -583,16 +555,12 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, * a nonsignaling NaN. The operation then continues as described in the * preceding paragraph for nonsignaling NaNs. */ - if (aIsQNaN || aIsSNaN) { /* a is the destination operand */ - return 0; /* return the destination operand */ + if (is_nan(a_cls)) { + return 0; } else { - return 1; /* return b */ + return 1; } -} #else -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* This implements x87 NaN propagation rules: * SNaN + QNaN => return the QNaN * two SNaNs => return the one with the larger significand, silenced @@ -603,13 +571,13 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, * If we get down to comparing significands and they are the same, * return the NaN with the positive sign bit (if any). */ - if (aIsSNaN) { - if (bIsSNaN) { + if (is_snan(a_cls)) { + if (is_snan(b_cls)) { return aIsLargerSignificand ? 0 : 1; } - return bIsQNaN ? 1 : 0; - } else if (aIsQNaN) { - if (bIsSNaN || !bIsQNaN) { + return is_qnan(b_cls) ? 1 : 0; + } else if (is_qnan(a_cls)) { + if (is_snan(b_cls) || !is_qnan(b_cls)) { return 0; } else { return aIsLargerSignificand ? 0 : 1; @@ -617,8 +585,8 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, } else { return 1; } -} #endif +} /*---------------------------------------------------------------------------- | Select which NaN to propagate for a three-input operation. @@ -752,18 +720,26 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; uint32_t av, bv; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!float32_is_any_nan(a) + ? float_class_normal + : float32_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!float32_is_any_nan(b) + ? float_class_normal + : float32_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); - aIsQuietNaN = float32_is_quiet_nan(a, status); - aIsSignalingNaN = float32_is_signaling_nan(a, status); - bIsQuietNaN = float32_is_quiet_nan(b, status); - bIsSignalingNaN = float32_is_signaling_nan(b, status); av = float32_val(a); bv = float32_val(b); - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } @@ -779,14 +755,13 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) aIsLargerSignificand = (av < bv) ? 1 : 0; } - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float32_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float32_silence_nan(a, status); } return a; @@ -908,18 +883,26 @@ static float64 commonNaNToFloat64(commonNaNT a, float_status *status) static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; uint64_t av, bv; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!float64_is_any_nan(a) + ? float_class_normal + : float64_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!float64_is_any_nan(b) + ? float_class_normal + : float64_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); - aIsQuietNaN = float64_is_quiet_nan(a, status); - aIsSignalingNaN = float64_is_signaling_nan(a, status); - bIsQuietNaN = float64_is_quiet_nan(b, status); - bIsSignalingNaN = float64_is_signaling_nan(b, status); av = float64_val(a); bv = float64_val(b); - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } @@ -935,14 +918,13 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) aIsLargerSignificand = (av < bv) ? 1 : 0; } - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float64_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float64_silence_nan(a, status); } return a; @@ -1075,15 +1057,22 @@ static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status) floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; + FloatClass a_cls, b_cls; - aIsQuietNaN = floatx80_is_quiet_nan(a, status); - aIsSignalingNaN = floatx80_is_signaling_nan(a, status); - bIsQuietNaN = floatx80_is_quiet_nan(b, status); - bIsSignalingNaN = floatx80_is_signaling_nan(b, status); + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!floatx80_is_any_nan(a) + ? float_class_normal + : floatx80_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!floatx80_is_any_nan(b) + ? float_class_normal + : floatx80_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } @@ -1099,14 +1088,13 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) aIsLargerSignificand = (a.high < b.high) ? 1 : 0; } - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return floatx80_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return floatx80_silence_nan(a, status); } return a; @@ -1217,15 +1205,22 @@ static float128 commonNaNToFloat128(commonNaNT a, float_status *status) static float128 propagateFloat128NaN(float128 a, float128 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; + FloatClass a_cls, b_cls; - aIsQuietNaN = float128_is_quiet_nan(a, status); - aIsSignalingNaN = float128_is_signaling_nan(a, status); - bIsQuietNaN = float128_is_quiet_nan(b, status); - bIsSignalingNaN = float128_is_signaling_nan(b, status); + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!float128_is_any_nan(a) + ? float_class_normal + : float128_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!float128_is_any_nan(b) + ? float_class_normal + : float128_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } @@ -1241,14 +1236,13 @@ static float128 propagateFloat128NaN(float128 a, float128 b, aIsLargerSignificand = (a.high < b.high) ? 1 : 0; } - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float128_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float128_silence_nan(a, status); } return a; diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ea252e0c84..55954385ff 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -580,8 +580,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) if (s->default_nan_mode) { return parts_default_nan(s); } else { - if (pickNaN(is_qnan(a.cls), is_snan(a.cls), - is_qnan(b.cls), is_snan(b.cls), + if (pickNaN(a.cls, b.cls, a.frac > b.frac || (a.frac == b.frac && a.sign < b.sign))) { a = b; From patchwork Wed May 16 15:52:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136035 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1130662lji; Wed, 16 May 2018 09:17:49 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpCYRxAkdrM2FYcIoJHiAOENz3FwDV2Ws7k4tfxNqOfRMEt/+gNCNl1D+M9xeYh9NQBexi5 X-Received: by 2002:a37:ddd6:: with SMTP id u83-v6mr1484765qku.234.1526487469789; Wed, 16 May 2018 09:17:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526487469; cv=none; d=google.com; s=arc-20160816; b=q/wcEvkRC3ZUUsOvyadJyp8aPE650CL87cwbbHNnDpaEds99fvub4w8WuJRPXu00D0 r4HarZyt2QxA7Kfjoxk9tV121Ikhl30gmkxR7rbvpUGnym0xB0V4aKcAGP/B+PhpO49c wUmJZecRyT2tnwD/BS2U3ATIvAD/8edXSnEvMltgKWFdYCz702uMaSb+eCuSUAbdeatI MvCIVfcMm5lvYrgS+XchaeB+BXPi+5r264MFEkk+GcKYVKR0Lfhg/sF2wKLXZaSTI2gn DiNb0UGIldqdie9laRsIRLzKUcy2h9sPfndnW88nj8w05INtbCCFxQhodS7OljHGZUYb sBFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=l7WMGMq5FTzJZw/8Ol7jK0ePReknNRBHJTqi+3dsjxg=; b=B3XGNOa/H0FUawEntsLvkppikAHgsX5DtV2ahL+xLCJGgcE4eswb/fJ0jygHp+2BXg PytyPeIOFEXOpHPlfPecTUUBG1hg9aOeVQ8p0syYzZEZlCaFwYLj+UKAjPMMrRaSylZC lTq/awqmL7TejxNZ7+cg9YLwky/9g/0BvM8jf2f6AngopA3m8vnHyk6ZC/3R3VdZk03f y7721XJEgiHMmutA2JX0I1KXmkwM5ONxNNxC0/CQbsg0O5miJfHdzKr8BzbrxtX2uX47 LpScbQYfSKIOk4pwD2p9MqEGKU1D6TjdHD1wqvtiYj9DXD/Faqw5IP1d6DN+PyXt0sA2 92mQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fWt0snpH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:40 -0700 Message-Id: <20180516155243.16937-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 25/28] fpu/softfloat: Pass FloatClass to pickNaNMulAdd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For each operand, pass a single enumeration instead of a pair of booleans. The commit also merges multiple different ifdef-selected implementations of pickNaNMulAdd into a single function whose body is ifdef-selected. Tested-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 70 +++++++++++++++----------------------- fpu/softfloat.c | 5 +-- 2 files changed, 28 insertions(+), 47 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 2695183188..0399dfe011 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -594,15 +594,14 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | information. | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN *----------------------------------------------------------------------------*/ -#if defined(TARGET_ARM) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) +static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, + bool infzero, float_status *status) { +#if defined(TARGET_ARM) /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN */ - if (infzero && cIsQNaN) { + if (infzero && is_qnan(c_cls)) { float_raise(float_flag_invalid, status); return 3; } @@ -610,25 +609,20 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, /* This looks different from the ARM ARM pseudocode, because the ARM ARM * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. */ - if (cIsSNaN) { + if (is_snan(c_cls)) { return 2; - } else if (aIsSNaN) { + } else if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsQNaN) { + } else if (is_qnan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } -} #elif defined(TARGET_MIPS) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN */ @@ -639,41 +633,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, if (snan_bit_is_one(status)) { /* Prefer sNaN over qNaN, in the a, b, c order. */ - if (aIsSNaN) { + if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsSNaN) { + } else if (is_snan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; - } else if (bIsQNaN) { + } else if (is_qnan(b_cls)) { return 1; } else { return 2; } } else { /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (cIsSNaN) { + if (is_snan(c_cls)) { return 2; - } else if (aIsSNaN) { + } else if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsQNaN) { + } else if (is_qnan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } } -} #elif defined(TARGET_PPC) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer * to return an input NaN if we have one (ie c) rather than generating * a default NaN @@ -686,31 +675,26 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB */ - if (aIsSNaN || aIsQNaN) { + if (is_nan(a_cls)) { return 0; - } else if (cIsSNaN || cIsQNaN) { + } else if (is_nan(c_cls)) { return 2; } else { return 1; } -} #else -/* A default implementation: prefer a to b to c. - * This is unlikely to actually match any real implementation. - */ -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ - if (aIsSNaN || aIsQNaN) { + /* A default implementation: prefer a to b to c. + * This is unlikely to actually match any real implementation. + */ + if (is_nan(a_cls)) { return 0; - } else if (bIsSNaN || bIsQNaN) { + } else if (is_nan(b_cls)) { return 1; } else { return 2; } -} #endif +} /*---------------------------------------------------------------------------- | Takes two single-precision floating-point values `a' and `b', one of which diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 55954385ff..8e97602ace 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -601,10 +601,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, s->float_exception_flags |= float_flag_invalid; } - which = pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls), - is_qnan(b.cls), is_snan(b.cls), - is_qnan(c.cls), is_snan(c.cls), - inf_zero, s); + which = pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s); if (s->default_nan_mode) { /* Note that this check is after pickNaNMulAdd so that function From patchwork Wed May 16 15:52:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136040 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1141550lji; Wed, 16 May 2018 09:26:11 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpkhGn2JUWbZ4rghZyhsgIb5iEvSt7Sx6aXF709O6Io3VlODRYLUF99qHDc62TfxhuLTPqn X-Received: by 2002:a37:ad04:: with SMTP id f4-v6mr1598779qkm.101.1526487970979; Wed, 16 May 2018 09:26:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526487970; cv=none; d=google.com; s=arc-20160816; b=Mlr1ALu1777OWJRSSTet/MnxE/yhvdfp2x8kaoJTKzwWnnJNXDCLOzEIyFiVYO/TbI EsXnSeuH+zy7Rr7i85nmGTqLdo69FXVuUHuyY7Xpr9vM40IdzaX8Knh49tqXhbQxYyjf YGrprKZ+oAPE/jq4i/xmJF+68PW0cJj7To/mso0Za2BlMYTgeovFKoOUcdSyv43/50um AhC6vrKqFpzMUulePyJX7ShgcD9PXJL2pEeacu+I+S6z+EvGDWnxy46sIcqQfIdhffxv udG8OZD7jsYyVN0xT+73bktGhl0JrqL3jOFYGpr37redFKWpLNdqGRaqspDZJx3AW0Y+ hvvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Rz3IqVdJzcvtjJ/dJ47cdMMS5avvv1bCkZtCabOjQ9w=; b=aMwemWqK2Ng730Te8zlwwC5RT+Rt7LjlEX53xkyfiX7Wmys+n3CABqz566ft7mAwpu xWdw5ZRUW/5WhS66CcQAp46S6mlMf4/Y2J8w2evR6ARKLKGEelwUUfN/oT2uTtrg4KYB O+6jwxP1mjYNYBZuC6YyNb0Uzrdko3jPB9uiCR1iwUNwwYsu1DNhV/is7axBJvat9KNK XwOF+EilGsRtB7zVY1WLRnRIE9AfHNncYRZK6TRIQKt9oxo/eqrTk2+k6ogKX80Z78Jb O74tZvNic4cIM/pMGjvIHoIXTCNyVhtrs7EZ4FLJRQfZmz1tqORi1XtxSVNfSeVL8ioo 7WCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Pkhytwaz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:41 -0700 Message-Id: <20180516155243.16937-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22a Subject: [Qemu-devel] [PULL 26/28] fpu/softfloat: Define floatN_default_nan in terms of parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Isolate the target-specific choice to 2 functions instead of 6. The code in float16_default_nan was only correct for ARM, MIPS, and X86. Though float16 support is rare among our targets. The code in float128_default_nan was arguably wrong for Sparc. While QEMU supports the Sparc 128-bit insns, no real cpu enables it. The code in floatx80_default_nan tried to be over-general. There are only two targets that support this format: x86 and m68k. Thus there is no point in inventing a value for snan_bit_is_one. Move routines that no longer have ifdefs out of softfloat-specialize.h. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 105 +++---------------------------------- fpu/softfloat.c | 41 +++++++++++++++ 2 files changed, 47 insertions(+), 99 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 0399dfe011..9d562ed504 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -179,94 +179,22 @@ static FloatParts parts_silence_nan(FloatParts a, float_status *status) return a; } -/*---------------------------------------------------------------------------- -| The pattern for a default generated half-precision NaN. -*----------------------------------------------------------------------------*/ -float16 float16_default_nan(float_status *status) -{ -#if defined(TARGET_ARM) - return const_float16(0x7E00); -#else - if (snan_bit_is_one(status)) { - return const_float16(0x7DFF); - } else { -#if defined(TARGET_MIPS) - return const_float16(0x7E00); -#else - return const_float16(0xFE00); -#endif - } -#endif -} - -/*---------------------------------------------------------------------------- -| The pattern for a default generated single-precision NaN. -*----------------------------------------------------------------------------*/ -float32 float32_default_nan(float_status *status) -{ -#if defined(TARGET_SPARC) || defined(TARGET_M68K) - return const_float32(0x7FFFFFFF); -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ - defined(TARGET_XTENSA) || defined(TARGET_S390X) || \ - defined(TARGET_TRICORE) || defined(TARGET_RISCV) - return const_float32(0x7FC00000); -#elif defined(TARGET_HPPA) - return const_float32(0x7FA00000); -#else - if (snan_bit_is_one(status)) { - return const_float32(0x7FBFFFFF); - } else { -#if defined(TARGET_MIPS) - return const_float32(0x7FC00000); -#else - return const_float32(0xFFC00000); -#endif - } -#endif -} - -/*---------------------------------------------------------------------------- -| The pattern for a default generated double-precision NaN. -*----------------------------------------------------------------------------*/ -float64 float64_default_nan(float_status *status) -{ -#if defined(TARGET_SPARC) || defined(TARGET_M68K) - return const_float64(LIT64(0x7FFFFFFFFFFFFFFF)); -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ - defined(TARGET_S390X) || defined(TARGET_RISCV) - return const_float64(LIT64(0x7FF8000000000000)); -#elif defined(TARGET_HPPA) - return const_float64(LIT64(0x7FF4000000000000)); -#else - if (snan_bit_is_one(status)) { - return const_float64(LIT64(0x7FF7FFFFFFFFFFFF)); - } else { -#if defined(TARGET_MIPS) - return const_float64(LIT64(0x7FF8000000000000)); -#else - return const_float64(LIT64(0xFFF8000000000000)); -#endif - } -#endif -} - /*---------------------------------------------------------------------------- | The pattern for a default generated extended double-precision NaN. *----------------------------------------------------------------------------*/ floatx80 floatx80_default_nan(float_status *status) { floatx80 r; + + /* None of the targets that have snan_bit_is_one use floatx80. */ + assert(!snan_bit_is_one(status)); #if defined(TARGET_M68K) r.low = LIT64(0xFFFFFFFFFFFFFFFF); r.high = 0x7FFF; #else - if (snan_bit_is_one(status)) { - r.low = LIT64(0xBFFFFFFFFFFFFFFF); - r.high = 0x7FFF; - } else { - r.low = LIT64(0xC000000000000000); - r.high = 0xFFFF; - } + /* X86 */ + r.low = LIT64(0xC000000000000000); + r.high = 0xFFFF; #endif return r; } @@ -285,27 +213,6 @@ floatx80 floatx80_default_nan(float_status *status) const floatx80 floatx80_infinity = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); -/*---------------------------------------------------------------------------- -| The pattern for a default generated quadruple-precision NaN. -*----------------------------------------------------------------------------*/ -float128 float128_default_nan(float_status *status) -{ - float128 r; - - if (snan_bit_is_one(status)) { - r.low = LIT64(0xFFFFFFFFFFFFFFFF); - r.high = LIT64(0x7FFF7FFFFFFFFFFF); - } else { - r.low = LIT64(0x0000000000000000); -#if defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_RISCV) - r.high = LIT64(0x7FFF800000000000); -#else - r.high = LIT64(0xFFFF800000000000); -#endif - } - return r; -} - /*---------------------------------------------------------------------------- | Raises the exceptions specified by `flags'. Floating-point traps can be | defined here if desired. It is currently not possible for such a trap diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8e97602ace..c8b33e35f4 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2092,6 +2092,47 @@ float64 __attribute__((flatten)) float64_sqrt(float64 a, float_status *status) return float64_round_pack_canonical(pr, status); } +/*---------------------------------------------------------------------------- +| The pattern for a default generated NaN. +*----------------------------------------------------------------------------*/ + +float16 float16_default_nan(float_status *status) +{ + FloatParts p = parts_default_nan(status); + p.frac >>= float16_params.frac_shift; + return float16_pack_raw(p); +} + +float32 float32_default_nan(float_status *status) +{ + FloatParts p = parts_default_nan(status); + p.frac >>= float32_params.frac_shift; + return float32_pack_raw(p); +} + +float64 float64_default_nan(float_status *status) +{ + FloatParts p = parts_default_nan(status); + p.frac >>= float64_params.frac_shift; + return float64_pack_raw(p); +} + +float128 float128_default_nan(float_status *status) +{ + FloatParts p = parts_default_nan(status); + float128 r; + + /* Extrapolate from the choices made by parts_default_nan to fill + * in the quad-floating format. If the low bit is set, assume we + * want to set all non-snan bits. + */ + r.low = -(p.frac & 1); + r.high = p.frac >> (DECOMPOSED_BINARY_POINT - 48); + r.high |= LIT64(0x7FFF000000000000); + r.high |= (uint64_t)p.sign << 63; + + return r; +} /*---------------------------------------------------------------------------- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 From patchwork Wed May 16 15:52:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136043 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1145438lji; Wed, 16 May 2018 09:29:13 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoCNZP99jBDaei+eHjoSZq3TVWVUTihdvOAkwikKC0Wv7lnBnu5TDsqhE2xkf8OKx9NMpLP X-Received: by 2002:ac8:2237:: with SMTP id o52-v6mr1673329qto.355.1526488152949; Wed, 16 May 2018 09:29:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526488152; cv=none; d=google.com; s=arc-20160816; b=EIoaow3r2kasEdJSsUy5Lge2tSv70HnnMgO2sFP6qlsqKOT9Lst6qT59XuXTsIV+M8 9QQlW8zQSMiDfYcLs87XfCFmuXdPTJ84OuX7n6vBJSWNlbgrqC9q/Oww9U2GJC+E3Cbb HsS9J+P2G4LL/qVzuSgEygyZ5BHck4UptXjLr7TRgrl2LNf7nWvLROrx1laBxQqGbw0G FpBohHWkYM54KjY0mRqjsed9TVu1gmq1e/9XoGxy/VKVAEwBR4EVwLsAFjZJm/BOvgxV hU3PGPrqyF6SfTlRSfKASipLQAIs3nF9VpzLPQHuwFcg1pWsUUsCTmEt1NKZmEbbYxba rrXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=FoXwUVq86zr0ueZIYvuCk2E7EmzERIvaAi2zhHeG+WQ=; b=YxCS8PbVOnMlpjLZwdbjAY+8Qp357qQIub+cVtWu/RQtZp3EL/j54TUGu5HwttV/eV TnUw+4Qk8jv0OTkA8L4I41hWePL2j8N0u2WovUWjIsRe8cvkaJD/Ozu1Oym1tR8wlovm QJV6o+gv/yr2vPvZKOWnWstR36i+f1sJw9SR+7LkmleMzqe3YGkqzy6Uq3IrHSXP0cEB rFedt/cjRg6Hz2AmJ5jLLk4jdC1n4nLUMa1cd54LCfW1MQGrbw1sT1Z+tmgJW8q8rxDl T69O+qjIfgH1cVvq0cI1gFeLaZ+E7gMzX16tY41GQtAJcp+rMYBwWH7NBr2PZPwWh7N3 aqDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XnpDxK4d; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:42 -0700 Message-Id: <20180516155243.16937-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PULL 27/28] fpu/softfloat: Clean up parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reduce the number of ifdefs. Correct the result for OpenRISC and TriCore (although TriCore fixed in target-specific code). Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 9d562ed504..ec4fb6ba8b 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -129,22 +129,29 @@ static FloatParts parts_default_nan(float_status *status) uint64_t frac; #if defined(TARGET_SPARC) || defined(TARGET_M68K) + /* !snan_bit_is_one, set all bits */ frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ - defined(TARGET_S390X) || defined(TARGET_RISCV) +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ + || defined(TARGET_MICROBLAZE) + /* !snan_bit_is_one, set sign and msb */ frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); + sign = 1; #elif defined(TARGET_HPPA) + /* snan_bit_is_one, set msb-1. */ frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else + /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, + * S390, SH4, TriCore, and Xtensa. I cannot find documentation + * for Unicore32; the choice from the original commit is unchanged. + * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile, + * do not have floating-point. + */ if (snan_bit_is_one(status)) { + /* set all bits other than msb */ frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; } else { -#if defined(TARGET_MIPS) + /* set msb */ frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); -#else - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); - sign = 1; -#endif } #endif From patchwork Wed May 16 15:52:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 136042 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1142088lji; Wed, 16 May 2018 09:26:35 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrmIyNcCHLXti+AMa50eS8/7+HdlcZTZ9aRrkSoYQi6Htq5mcTdqd2PMFFueC6rjb13EZrz X-Received: by 2002:a0c:bfb4:: with SMTP id s49-v6mr1664464qvj.168.1526487995063; Wed, 16 May 2018 09:26:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526487995; cv=none; d=google.com; s=arc-20160816; b=x0XDBJg+x3CF8vXHHknRtMNo8akembos3PY6S5cqus3/YNPWYSInRU380XDht5sFtW +pnWmr1Eq7E5d+8kmpLZZUw0jwjeX5L6obexKEP1Q6mRWc/3BHdv5SeEl1Y4/g8/n2eA NfNFW+7QsFBl6gY0NCVzo8l8qu1OAJlA2VqhRwVkxMGrQRROVPj9N8kr0PhVJmKj8xgW vrW/rZGw0ugperQZ9ud3MjKsKcTrmHq0yHPI1C6M8qcpgfCSlYpElp8uR1wJ9UOHSsPk nyRVZAVl90xsCzCowba+o7iwaTzppGEsY6fdwWeRiICQLXvwh+MXslQ9drrlgjQtzX8n xShA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ZC9TUm1Wa76g6xZsbJV8AL4lnK1ydFZXG6NTJq37V0g=; b=Nei8kCl1jLfpQWD/oAyARQrJlj3HOfQo3WcbrdzQxo9NzYD3IPP6AkwwXHl1hwfqDt /BZXPio56sG08RrLcHb3GWmwqRnCAIU8SiDhvzoCln3f30gd0NuQswHcMFch0N4zRFBb 7tZf3+HL3G6gTW5BrOq80txfw62TxIK+GKMSFFhtLaXAxKW/U+vN5zyjr4h/rrgyGJbw dYQw23Pe7vCl86GGfsQoeYwCcRabNoFQOs6/tuTg7f+mnVUNifGElQeGdqYgqFzhaMBY smcaeEW/D1unk2BPHBwvTqJG2jHscp+MSQhstraOm4xh37dHf42lovfYz8nZlSq19Ssb B9Fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=G4scEjNN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id l184-v6si1181421qkd.287.2018.05.16.09.26.34 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 16 May 2018 09:26:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=G4scEjNN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53980 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIzG6-0006Ez-F7 for patch@linaro.org; Wed, 16 May 2018 12:26:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42164) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fIyk4-0004kl-H9 for qemu-devel@nongnu.org; Wed, 16 May 2018 11:53:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fIyk3-0005CL-En for qemu-devel@nongnu.org; Wed, 16 May 2018 11:53:28 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:33617) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fIyk3-0005Bu-76 for qemu-devel@nongnu.org; Wed, 16 May 2018 11:53:27 -0400 Received: by mail-pl0-x244.google.com with SMTP id n10-v6so673974plp.0 for ; Wed, 16 May 2018 08:53:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZC9TUm1Wa76g6xZsbJV8AL4lnK1ydFZXG6NTJq37V0g=; b=G4scEjNNLVwVVHmNVtkh38YUbMIp9VMG8kMu35hGspt8uP/EvPNxbLtHojF+6UQJUr NkW+9qZGHu5Rz9/3GQw+1M0Sn09GdX9/G5jHRBxcqz81zf7pBuYLcutEX67GPEQzsnW9 MuZsc24Bj2a249b4INwFYHojgnkE4osPfwcW4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZC9TUm1Wa76g6xZsbJV8AL4lnK1ydFZXG6NTJq37V0g=; b=sGN0JvUgwQTy76P96owO4vS8DJwusgx8TCE8bztmpdyiG0iNUyuDDQyJFNkd+FF7iF JpcPNnD1LOi9ylTph9x1WVDriPvlpsCI20zRApWAkR47LWr8m8G548BoenNQV3fyIe64 z5VteZNRRp6Z/OZpe0L1lx2L4liF/tJ17NEQAWCgfXen4czhx93iGRhsGPmxUIV1IAdC rgpEjeMb1C3fuRKPjTf228hw5einox8pxihkMukc8HmMHL3PZKTGmfvT4kqgbfAv0X1o h2v7TRku0g18AfxFM51CB8AOPiEsCwOqCQRDKW/YZ+6WaFb74ACe8xgU/oUIIxPv4CtL eg8A== X-Gm-Message-State: ALKqPwcHyRBS4phkdhy6d1eTzm4uIrOKTv1YwnYcBUbtwZT6grK+nIyD 6xMpX+o9GQARU7XqH+6Fv+nlXLIoyCE= X-Received: by 2002:a17:902:8f97:: with SMTP id z23-v6mr1459157plo.329.1526486005786; Wed, 16 May 2018 08:53:25 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id c3-v6sm4966632pfn.62.2018.05.16.08.53.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 08:53:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 08:52:43 -0700 Message-Id: <20180516155243.16937-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516155243.16937-1-richard.henderson@linaro.org> References: <20180516155243.16937-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PULL 28/28] fpu/softfloat: Define floatN_silence_nan in terms of parts_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Isolate the target-specific choice to 3 functions instead of 6. The code in floatx80_default_nan tried to be over-general. There are only two targets that support this format: x86 and m68k. Thus there is no point in inventing a mechanism for snan_bit_is_one. Move routines that no longer have ifdefs out of softfloat-specialize.h. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 81 ++------------------------------------ fpu/softfloat.c | 31 +++++++++++++++ 2 files changed, 35 insertions(+), 77 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index ec4fb6ba8b..16c0bcb6fa 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -278,24 +278,6 @@ int float16_is_signaling_nan(float16 a_, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN from a signalling NaN for the half-precision -| floating point value `a'. -*----------------------------------------------------------------------------*/ - -float16 float16_silence_nan(float16 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { - return float16_default_nan(status); - } else { - return a | (1 << 9); - } -#endif -} - /*---------------------------------------------------------------------------- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -334,30 +316,6 @@ int float32_is_signaling_nan(float32 a_, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN from a signalling NaN for the single-precision -| floating point value `a'. -*----------------------------------------------------------------------------*/ - -float32 float32_silence_nan(float32 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { -# ifdef TARGET_HPPA - a &= ~0x00400000; - a |= 0x00200000; - return a; -# else - return float32_default_nan(status); -# endif - } else { - return a | (1 << 22); - } -#endif -} - /*---------------------------------------------------------------------------- | Returns the result of converting the single-precision floating-point NaN | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid @@ -706,31 +664,6 @@ int float64_is_signaling_nan(float64 a_, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN from a signalling NaN for the double-precision -| floating point value `a'. -*----------------------------------------------------------------------------*/ - -float64 float64_silence_nan(float64 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { -# ifdef TARGET_HPPA - a &= ~0x0008000000000000ULL; - a |= 0x0004000000000000ULL; - return a; -# else - return float64_default_nan(status); -# endif - } else { - return a | LIT64(0x0008000000000000); - } -#endif -} - - /*---------------------------------------------------------------------------- | Returns the result of converting the double-precision floating-point NaN | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid @@ -886,16 +819,10 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) floatx80 floatx80_silence_nan(floatx80 a, float_status *status) { -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { - return floatx80_default_nan(status); - } else { - a.low |= LIT64(0xC000000000000000); - return a; - } -#endif + /* None of the targets that have snan_bit_is_one use floatx80. */ + assert(!snan_bit_is_one(status)); + a.low |= LIT64(0xC000000000000000); + return a; } /*---------------------------------------------------------------------------- diff --git a/fpu/softfloat.c b/fpu/softfloat.c index c8b33e35f4..8cd2400081 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2134,6 +2134,37 @@ float128 float128_default_nan(float_status *status) return r; } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the floating point value `a'. +*----------------------------------------------------------------------------*/ + +float16 float16_silence_nan(float16 a, float_status *status) +{ + FloatParts p = float16_unpack_raw(a); + p.frac <<= float16_params.frac_shift; + p = parts_silence_nan(p, status); + p.frac >>= float16_params.frac_shift; + return float16_pack_raw(p); +} + +float32 float32_silence_nan(float32 a, float_status *status) +{ + FloatParts p = float32_unpack_raw(a); + p.frac <<= float32_params.frac_shift; + p = parts_silence_nan(p, status); + p.frac >>= float32_params.frac_shift; + return float32_pack_raw(p); +} + +float64 float64_silence_nan(float64 a, float_status *status) +{ + FloatParts p = float64_unpack_raw(a); + p.frac <<= float64_params.frac_shift; + p = parts_silence_nan(p, status); + p.frac >>= float64_params.frac_shift; + return float64_pack_raw(p); +} + /*---------------------------------------------------------------------------- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to the