From patchwork Tue Apr 18 01:17:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 97515 Delivered-To: patch@linaro.org Received: by 10.140.109.52 with SMTP id k49csp1580014qgf; Mon, 17 Apr 2017 18:17:51 -0700 (PDT) X-Received: by 10.99.119.4 with SMTP id s4mr13904616pgc.71.1492478271726; Mon, 17 Apr 2017 18:17:51 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Mon, 17 Apr 2017 18:17:48 -0700 (PDT) Received: from localhost.localdomain ([104.237.91.92]) by smtp.gmail.com with ESMTPSA id t5sm20163049pgb.58.2017.04.17.18.17.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Apr 2017 18:17:47 -0700 (PDT) From: Zhangfei Gao To: Stephen Boyd , Rob Herring , guodong Xu , xuwei5@hisilicon.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Zhangfei Gao , Li Pengcheng Subject: [PATCH 1/2] clk: hi6220: add acpu clock Date: Tue, 18 Apr 2017 09:17:21 +0800 Message-Id: <1492478242-16146-1-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add acpu clock, including sft clock controlling hi6220 coresight module Signed-off-by: Zhangfei Gao Signed-off-by: Li Pengcheng --- .../devicetree/bindings/clock/hi6220-clock.txt | 1 + drivers/clk/hisilicon/clk-hi6220.c | 23 ++++++++++++++++++++++ include/dt-bindings/clock/hi6220-clock.h | 4 ++++ 3 files changed, 28 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt b/Documentation/devicetree/bindings/clock/hi6220-clock.txt index e4d5fea..ef3deb7 100644 --- a/Documentation/devicetree/bindings/clock/hi6220-clock.txt +++ b/Documentation/devicetree/bindings/clock/hi6220-clock.txt @@ -11,6 +11,7 @@ Required Properties: - compatible: the compatible should be one of the following strings to indicate the clock controller functionality. + - "hisilicon,hi6220-acpu-sctrl" - "hisilicon,hi6220-aoctrl" - "hisilicon,hi6220-sysctrl" - "hisilicon,hi6220-mediactrl" diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index 2ae151c..fc8813f 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -285,3 +285,26 @@ static void __init hi6220_clk_power_init(struct device_node *np) ARRAY_SIZE(hi6220_div_clks_power), clk_data); } CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init); + + +/* clocks in acpu */ +static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = { + { HI6220_ACPU_SFT_AT_S, "sft_at_s", "cs_atb", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0xc, 11, 0, }, +}; + +static void __init hi6220_clk_acpu_init(struct device_node *np) +{ + struct hisi_clock_data *clk_data; + int nr = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks); + + clk_data = hisi_clk_init(np, nr); + if (!clk_data) + return; + + hisi_clk_register_gate_sep(hi6220_acpu_sc_gate_sep_clks, + ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks), + clk_data); +} + +CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_acpu_init); diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h index b8ba665..409cc02 100644 --- a/include/dt-bindings/clock/hi6220-clock.h +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -174,4 +174,8 @@ #define HI6220_DDRC_AXI1 7 #define HI6220_POWER_NR_CLKS 8 + +/* clk in Hi6220 acpu sctrl */ +#define HI6220_ACPU_SFT_AT_S 0 + #endif From patchwork Tue Apr 18 01:17:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 97516 Delivered-To: patch@linaro.org Received: by 10.140.109.52 with SMTP id k49csp1580072qgf; Mon, 17 Apr 2017 18:18:06 -0700 (PDT) X-Received: by 10.98.106.199 with SMTP id f190mr15499642pfc.142.1492478286328; Mon, 17 Apr 2017 18:18:06 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j90si3238229pfk.240.2017.04.17.18.18.06; Mon, 17 Apr 2017 18:18:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755929AbdDRBSE (ORCPT + 7 others); Mon, 17 Apr 2017 21:18:04 -0400 Received: from mail-pg0-f45.google.com ([74.125.83.45]:33937 "EHLO mail-pg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755050AbdDRBR4 (ORCPT ); Mon, 17 Apr 2017 21:17:56 -0400 Received: by mail-pg0-f45.google.com with SMTP id z127so15882645pgb.1 for ; Mon, 17 Apr 2017 18:17:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Gp4mPj1OZ99eykQA0vkoB9krKS+SKfMauWZky9wNO0A=; b=I2hWv9/pJxAnTROJYKusK4EKKk7XVNiNR76YgH2vZ52Etue+YZiSJE8idZ5DNExZiI eCP4p5SBH8/9gtVPrCwyvtegnWmM7Vn+fCoolK7vawhAtAg30edSG13xNo7lL0898WQd TT/Gp4cuQnjvwUHYXRE5/z+PX2QSW2GsMH8bU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Gp4mPj1OZ99eykQA0vkoB9krKS+SKfMauWZky9wNO0A=; b=og/GXsFL9Nd7MTS2tZFKgRTHz231FgxbaWE/EZGeoN5pyZfmntpUaEW4eFgTGrKpco 2yi4gOc4ZNlLXWlL42dG6fNcUn0NOmr+j5C+B4XxgORJDEStuPfF0vftE9SC3mkoyx5n mym9AIASgDlD2bB1ZGVwDIPGmLgKntxV5hiUWYOMqidwYNrVb4QSc78atoW0jNrhLFn/ PtqjgG93nXJYxylLzbM4M1uy2bSVFzvTFqMJlYQFhs5GNJOM0n/l3zk0Nf0b3Nh6zllB jLjKdqG0Pi5IZqpK1uLhSeL+f2pgmmccU+aRy0ZtfQuZJbc7O5jFE49xaQacg7mwptRm rl/A== X-Gm-Message-State: AN3rC/7Y4ndKxesj1MSM+AQVfDu4JYFampHhxl0qjlmYVWqeooM6jQHt 1fcPBjpa7adqO1qw X-Received: by 10.98.16.208 with SMTP id 77mr14702377pfq.105.1492478276296; Mon, 17 Apr 2017 18:17:56 -0700 (PDT) Received: from localhost.localdomain ([104.237.91.92]) by smtp.gmail.com with ESMTPSA id t5sm20163049pgb.58.2017.04.17.18.17.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Apr 2017 18:17:55 -0700 (PDT) From: Zhangfei Gao To: Stephen Boyd , Rob Herring , guodong Xu , xuwei5@hisilicon.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Zhangfei Gao , Li Pengcheng Subject: [PATCH 2/2] arm64: dts: hi6220: add acpu_sctrl Date: Tue, 18 Apr 2017 09:17:22 +0800 Message-Id: <1492478242-16146-2-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492478242-16146-1-git-send-email-zhangfei.gao@linaro.org> References: <1492478242-16146-1-git-send-email-zhangfei.gao@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add acpu_sctrl clock node Signed-off-by: Zhangfei Gao Signed-off-by: Li Pengcheng --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Wei Xu diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 470461d..710cc34 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -262,6 +262,12 @@ #clock-cells = <1>; }; + acpu_sctrl: acpu_sctrl@f7032000 { + compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; + reg = <0x0 0xf6504000 0x0 0x1000>; + #clock-cells = <1>; + }; + medianoc_ade: medianoc_ade@f4520000 { compatible = "syscon"; reg = <0x0 0xf4520000 0x0 0x4000>;