From patchwork Tue Mar 23 18:43:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 406943 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4701553jai; Tue, 23 Mar 2021 11:46:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy2lNifL0B0WucoIFsq3nnDNUmNW5c+vuKbjdokfQNI+ZjNO3W9ubCa8PLZYn6KfNDy476g X-Received: by 2002:a9d:6a0d:: with SMTP id g13mr5600851otn.102.1616525206590; Tue, 23 Mar 2021 11:46:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616525206; cv=none; d=google.com; s=arc-20160816; b=HTvc3glLvJyQue6SrGkSfcOyZK6a6IWEAP4Nd18ducoqFGaqbnGzGrnf7NpPsII40m +K9wiUvTQV0+0BbBKsALpQSLIZ1orBWXY/WeaYNe1NRbi9zOV4QRhWvCfH/8b3fSB/TD dt/8hFC0u5j/UQK1XK5GpXNgpQlE8eW1FZFPaiLWWmQtf1ZCCihzx35plutJi1bQfmgy XkWqYhjN8w8h5KLbPB8QcSzS5+CnlQvV5Q55YsxTUT7MGoI2UkLq5SHA5RNqzVQuKQpJ fYlwQ7DMXPbpYTOskAxisRbZk4e8PZNCfXUxxX88sORyJ3jg3+2HeVHnUARWgiC2HVwj oLGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZZn5IlT2BapleTJTqEZmRXFES9KCoo4eQgHLgV0kshE=; b=ozJUZrSZ7mAI+PffNMPf1sZaVE23MaA0C6wUN/W7n1/tyj/S0Tqj8MGkgp1cbHNcAs QSuBFEO9nKnKWe1scWV5lUXLY5erMBv+cRnxjwazUVLOYOOT9c1b4W8B55ex7DwB9LVZ kdSANmvW5TaNx2rRBtUnKlQe72pv976MUhJNsJFzldf0OC6R820Wcaybo/RBUoPhcixg 2GWILJWbITghXt5iXHnTL8jJX9ddlaugKk4KJXJgB76GgbwQS0TJWhdmbXgJXGoh5ZuV WRYz+6FPJkCU3dneknrNsTO7ulXi/JcupBrg6pXcedXq6TzNrDRpbBDQlbyejGJa0tee 9Exg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KFLJe20O; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n9si9501060oij.74.2021.03.23.11.46.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Mar 2021 11:46:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KFLJe20O; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lOm3B-0008I3-U1 for patch@linaro.org; Tue, 23 Mar 2021 14:46:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36486) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lOm0l-0008Fb-04 for qemu-devel@nongnu.org; Tue, 23 Mar 2021 14:44:16 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]:46015) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lOm0L-0003fG-CL for qemu-devel@nongnu.org; Tue, 23 Mar 2021 14:44:11 -0400 Received: by mail-oi1-x22e.google.com with SMTP id d12so18099751oiw.12 for ; Tue, 23 Mar 2021 11:43:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZZn5IlT2BapleTJTqEZmRXFES9KCoo4eQgHLgV0kshE=; b=KFLJe20OoyGU7DeNegRcCDinW+fVHZ2S6bCuEfl6Pd8uqm54RBK4MIRF76Vof4ckIN CZYnjs2zrJ2b332cxhKzclrLdiI6Wsd0VPXpHwvXeH/c2lyVYVihCMpFNMdZZmfGEKx7 yzigmPa2FKljB6Rhu1V0mp7+uhDzeJroYtmsgyh8HzuwBqQjy953MrROBpt2DW3ZVyzZ A06uaG0qfBGMX2+AjRtFR6Y5cREtDfJKuBnPr7UcfqnI0sTMJyKuyCq3bjCIvYleMhiG bIkxRVsnrkyEtt9JQazbFEMA1TbyLIAv5OVqdpxLse2wde4vBqnVsuumfUNsLD2YGY2/ HQ5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZZn5IlT2BapleTJTqEZmRXFES9KCoo4eQgHLgV0kshE=; b=AL5ZqEOyWni/Ul1dN5jR5av38yYp9C6ied86LE+XmFi7RxNVx1sBqUV/67fr54FEHb IWrBoEVY3mT5mMIqCYzqry/Pb9m9NplH9c1SAKpHTTPIgrG2Zu5iI+LZ8Uti0bvvfUG1 nkDdjRZQqGATtja7PUExBd/SUD4ywou4QHQNrV+cyjpDddDae6/0kSvp3uUz1DHy4siv iuRBeQFZ/ETBM35wkp6JDgE0tA+Js6wVXY2YB7T7nILpaFAeAmkSGGAGwhaOvPQQahN4 wk7Xt+D7BeVbNrT8vHfhGNN0mHMomk/lXDLkk/UpTkpSdDE7V4wlnDXzrZ4gsalf77ks g37g== X-Gm-Message-State: AOAM533HCX/KT93rr1FFpYa8RZ/22IDtATRo316KHGjjluZvqVB/HZwM mhusuPRPC0uim5RkGsuY7DFd63sQYJq43zeL X-Received: by 2002:a05:6808:13d0:: with SMTP id d16mr4451655oiw.169.1616525024541; Tue, 23 Mar 2021 11:43:44 -0700 (PDT) Received: from localhost.localdomain (171.189-204-159.bestelclientes.com.mx. [189.204.159.171]) by smtp.gmail.com with ESMTPSA id x23sm3902825ood.28.2021.03.23.11.43.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 11:43:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 01/10] target/ppc: Extract post_load_update_msr Date: Tue, 23 Mar 2021 12:43:31 -0600 Message-Id: <20210323184340.619757-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210323184340.619757-1-richard.henderson@linaro.org> References: <20210323184340.619757-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Extract post_load_update_msr to share between cpu_load_old and cpu_post_load in updating the msr. Suggested-by: Cédric Le Goater Signed-off-by: Richard Henderson --- target/ppc/machine.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 1f7a353c78..09c5765a87 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -10,6 +10,18 @@ #include "kvm_ppc.h" #include "exec/helper-proto.h" +static void post_load_update_msr(CPUPPCState *env) +{ + target_ulong msr = env->msr; + + /* + * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB + * before restoring. Note that this recomputes hflags and mem_idx. + */ + env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); + ppc_store_msr(env, msr); +} + static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) { PowerPCCPU *cpu = opaque; @@ -21,7 +33,6 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) int32_t slb_nr; #endif target_ulong xer; - target_ulong msr; for (i = 0; i < 32; i++) { qemu_get_betls(f, &env->gpr[i]); @@ -117,13 +128,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) qemu_get_sbe32(f); /* Discard unused mmu_idx */ qemu_get_sbe32(f); /* Discard unused power_mode */ - /* - * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB - * before restoring. Note that this recomputes hflags and mem_idx. - */ - msr = env->msr; - env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); - ppc_store_msr(env, msr); + post_load_update_msr(env); return 0; } @@ -343,7 +348,6 @@ static int cpu_post_load(void *opaque, int version_id) PowerPCCPU *cpu = opaque; CPUPPCState *env = &cpu->env; int i; - target_ulong msr; /* * If we're operating in compat mode, we should be ok as long as @@ -417,13 +421,7 @@ static int cpu_post_load(void *opaque, int version_id) ppc_store_sdr1(env, env->spr[SPR_SDR1]); } - /* - * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB - * before restoring. Note that this recomputes hflags and mem_idx. - */ - msr = env->msr; - env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); - ppc_store_msr(env, msr); + post_load_update_msr(env); return 0; } From patchwork Tue Mar 23 18:43:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 406947 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4724241jai; Tue, 23 Mar 2021 12:19:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxZFiaEqSyqk8wrup3J2Dsb5htEg9P9LY0zXYOSUa8za0p7D0oiJ6kX9FM4ociVjUQZzS+t X-Received: by 2002:a02:942d:: with SMTP id a42mr6006046jai.71.1616527174940; Tue, 23 Mar 2021 12:19:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616527174; cv=none; d=google.com; s=arc-20160816; b=EO5q+Ltg/M506FX8jDhsXZkACtGNOC6KW254tfhno5Kzdpskv6HtM9XlViBfHDwSJk /GcN14uXoV1Q84urr5cxZHUn+9jEWOCafEEFNIRkNi4SNb8A+F81Gz2Fe4jLjZOBIhVa thTzcsgwZCq+IzMLxedXp4VHQ+tDNHWrjl9uJha/Yk8A6oFhtNuQtC+rYNZZPwrnpPIy DuXstN+oIuWKmRIunSWM5cqakTLPFv0mJcUtEAkq6cM6MYDCureh7sE5AUWtBQt7AWEe hlBVCtxL3c/uZj608oicY7SzWsjPJx3QMRFg5TI4gNHx5Vt35KcuGRop8aFQg3GznglJ A3dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PwM2bOqU7aXMNaHDMLaVbRDxjZE33v838lGFsqK/S70=; b=YJfiC7LAFrqCLjxmoNAABIVNUNSn2HArd2riD8egMAxMZmdNLWTZ0eIneseTnq2co0 0Iab+ogQnChbLq9DyWLHQhdKI0MwXhTv91/zlvcAzYqo/wVeBzQEUQ7MpkWVC7POty3S nMzedA8ridufoSAg79TfVLovWsBXlA8MfxDGS3qoSv8MDkZkjlZb39rNoUaGDm9RlWg/ haoqlu4JEjXcxG/GqBjmzq/iC+k4eiAVCvRRaZ33E0LQbtiOdR/oQi1j1HuSqkWlf2VH Xq/VSuSBIR33WvIcKUL7pYqIT0iHzA09SQLkELbP8yTWieaZsPaTwPsN2647GbxZ6PJx OY9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="w/YHdJbg"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[189.204.159.171]) by smtp.gmail.com with ESMTPSA id x23sm3902825ood.28.2021.03.23.11.43.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 11:43:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 02/10] target/ppc: Disconnect hflags from MSR Date: Tue, 23 Mar 2021 12:43:32 -0600 Message-Id: <20210323184340.619757-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210323184340.619757-1-richard.henderson@linaro.org> References: <20210323184340.619757-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ivan Warren , qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Copying flags directly from msr has drawbacks: (1) msr bits mean different things per cpu, (2) msr has 64 bits on 64 cpus while tb->flags has only 32 bits. Create a enum to define these bits. Document the origin of each bit and validate those bits that must match MSR. This fixes the truncation of env->hflags to tb->flags, because we no longer have hflags bits set above bit 31. Most of the code in ppc_tr_init_disas_context is moved over to hreg_compute_hflags. Some of it is simple extractions from msr, some requires examining other cpu flags. Anything that is moved becomes a simple extract from hflags in ppc_tr_init_disas_context. Several existing bugs are left in ppc_tr_init_disas_context, where additional changes are required -- to be addressed in future patches. Remove a broken #if 0 block. Reported-by: Ivan Warren Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 25 ++++++++++++++++ target/ppc/helper_regs.c | 65 +++++++++++++++++++++++++++++++++------- target/ppc/translate.c | 55 ++++++++++------------------------ 3 files changed, 95 insertions(+), 50 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index fd13489dce..fe6c3f815d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -585,6 +585,31 @@ enum { POWERPC_FLAG_HID0_LE = 0x00400000, }; +/* + * Bits for env->hflags. + * + * Most of these bits overlap with corresponding bits in MSR, + * but some come from other sources. Those that do come from + * the MSR are validated in hreg_compute_hflags. + */ +enum { + HFLAGS_LE = 0, /* MSR_LE -- comes from elsewhere on 601 */ + HFLAGS_HV = 1, /* computed from MSR_HV and other state */ + HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ + HFLAGS_DR = 4, /* MSR_DR */ + HFLAGS_IR = 5, /* MSR_IR */ + HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ + HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */ + HFLAGS_TM = 8, /* computed from MSR_TM */ + HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ + HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */ + HFLAGS_FP = 13, /* MSR_FP */ + HFLAGS_PR = 14, /* MSR_PR */ + HFLAGS_SA = 22, /* MSR_SA */ + HFLAGS_AP = 23, /* MSR_AP */ + HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ +}; + /*****************************************************************************/ /* Floating point status and control register */ #define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index a87e354ca2..df9673b90f 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "cpu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" @@ -87,24 +88,66 @@ void hreg_compute_mem_idx(CPUPPCState *env) void hreg_compute_hflags(CPUPPCState *env) { - target_ulong hflags_mask; + target_ulong msr = env->msr; + uint32_t ppc_flags = env->flags; + uint32_t hflags = 0; + uint32_t msr_mask; - /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ - hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | - (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | - (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); - hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; - hreg_compute_mem_idx(env); - env->hflags = env->msr & hflags_mask; + /* Some bits come straight across from MSR. */ + QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE); + QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR); + QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR); + QEMU_BUILD_BUG_ON(MSR_IR != HFLAGS_IR); + QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP); + QEMU_BUILD_BUG_ON(MSR_SA != HFLAGS_SA); + QEMU_BUILD_BUG_ON(MSR_AP != HFLAGS_AP); + msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | + (1 << MSR_DR) | (1 << MSR_IR) | + (1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP)); - if (env->flags & POWERPC_FLAG_HID0_LE) { + if (ppc_flags & POWERPC_FLAG_HID0_LE) { /* * Note that MSR_LE is not set in env->msr_mask for this cpu, - * and so will never be set in msr or hflags at this point. + * and so will never be set in msr. */ uint32_t le = extract32(env->spr[SPR_HID0], 3, 1); - env->hflags |= le << MSR_LE; + hflags |= le << MSR_LE; } + + if (ppc_flags & POWERPC_FLAG_BE) { + QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE); + msr_mask |= 1 << MSR_BE; + } + if (ppc_flags & POWERPC_FLAG_SE) { + QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE); + msr_mask |= 1 << MSR_SE; + } + + if (msr_is_64bit(env, msr)) { + hflags |= 1 << HFLAGS_64; + } + if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) { + hflags |= 1 << HFLAGS_SPE; + } + if (ppc_flags & POWERPC_FLAG_VRE) { + QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR); + msr_mask |= 1 << MSR_VR; + } + if ((ppc_flags & POWERPC_FLAG_VSX) && (msr & (1 << MSR_VSX))) { + hflags |= 1 << HFLAGS_VSX; + } + if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { + hflags |= 1 << HFLAGS_TM; + } + +#ifndef CONFIG_USER_ONLY + if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { + hflags |= 1 << HFLAGS_HV; + } +#endif + + env->hflags = hflags | (msr & msr_mask); + hreg_compute_mem_idx(env); } void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0984ce637b..a9325a12e5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7879,67 +7879,48 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPUPPCState *env = cs->env_ptr; + uint32_t hflags = ctx->base.tb->flags; int bound; ctx->exception = POWERPC_EXCP_NONE; ctx->spr_cb = env->spr_cb; - ctx->pr = msr_pr; + ctx->pr = (hflags >> HFLAGS_PR) & 1; ctx->mem_idx = env->dmmu_idx; - ctx->dr = msr_dr; -#if !defined(CONFIG_USER_ONLY) - ctx->hv = msr_hv || !env->has_hv_mode; -#endif + ctx->dr = (hflags >> HFLAGS_DR) & 1; + ctx->hv = (hflags >> HFLAGS_HV) & 1; ctx->insns_flags = env->insns_flags; ctx->insns_flags2 = env->insns_flags2; ctx->access_type = -1; ctx->need_access_type = !mmu_is_64bit(env->mmu_model); - ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); + ctx->le_mode = (hflags >> HFLAGS_LE) & 1; ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; ctx->flags = env->flags; #if defined(TARGET_PPC64) - ctx->sf_mode = msr_is_64bit(env, env->msr); + ctx->sf_mode = (hflags >> HFLAGS_64) & 1; ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); #endif ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B || env->mmu_model == POWERPC_MMU_601 || env->mmu_model & POWERPC_MMU_64; - ctx->fpu_enabled = !!msr_fp; - if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) { - ctx->spe_enabled = !!msr_spe; - } else { - ctx->spe_enabled = false; - } - if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) { - ctx->altivec_enabled = !!msr_vr; - } else { - ctx->altivec_enabled = false; - } - if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { - ctx->vsx_enabled = !!msr_vsx; - } else { - ctx->vsx_enabled = false; - } + ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; + ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; + ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; + ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; if ((env->flags & POWERPC_FLAG_SCV) && (env->spr[SPR_FSCR] & (1ull << FSCR_SCV))) { ctx->scv_enabled = true; } else { ctx->scv_enabled = false; } -#if defined(TARGET_PPC64) - if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { - ctx->tm_enabled = !!msr_tm; - } else { - ctx->tm_enabled = false; - } -#endif + ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); - if ((env->flags & POWERPC_FLAG_SE) && msr_se) { - ctx->singlestep_enabled = CPU_SINGLE_STEP; - } else { - ctx->singlestep_enabled = 0; + + ctx->singlestep_enabled = 0; + if ((hflags >> HFLAGS_SE) & 1) { + ctx->singlestep_enabled |= CPU_SINGLE_STEP; } - if ((env->flags & POWERPC_FLAG_BE) && msr_be) { + if ((hflags >> HFLAGS_BE) & 1) { ctx->singlestep_enabled |= CPU_BRANCH_STEP; } if ((env->flags & POWERPC_FLAG_DE) && msr_de) { @@ -7956,10 +7937,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if (unlikely(ctx->base.singlestep_enabled)) { ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; } -#if defined(DO_SINGLE_STEP) && 0 - /* Single step trace mode */ - msr_se = 1; -#endif bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns = MIN(ctx->base.max_insns, bound); From patchwork Tue Mar 23 18:43:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 406944 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4704753jai; Tue, 23 Mar 2021 11:52:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzRVt1Poi9xL2BVXorI9TvmBTUqn+Pnu7ubFnEM9VaqineOqKc8Z6tUAP6iI7bfPoBzMPxV X-Received: by 2002:a5e:d907:: with SMTP id n7mr5797898iop.177.1616525537662; Tue, 23 Mar 2021 11:52:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616525537; cv=none; d=google.com; s=arc-20160816; b=fMEh/hxUpBgKoaBCuzg+fpityySm8sF0B2wIZSiMfVtIga0BBTRqu6dEy0jVPEcLes Ktrlt613aFmN5o33yfgaCggUg6RiK3rSU7msB9CeXEaA30VnGseJHBSvIa7eyyyAhNl1 zr90qOoWRWaTI/u5oRFMF6OwDkWayiH6HYj4OfKtVD+aO8NuXzuhSvBhrhmDtGJVZmrU +jwiEVDYSEMEKpExObc5TpmKh1p8wPLvwhr6jlWGxCMjkvCzpg0EDfNA7AyNKx7dN131 0jynPovVlug0DTpw7skj7v01DiqXOJi5HDAl13uflKI5GOP/RHO8ba8S/1sfGePuWLkb pOHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=u6cU8I9ufF4e1/CeycrI3fKqm/ECMUPYXSwRs2bukw0=; b=bGnepD/uh+eE8pfF7yYgw2oUEtQryohXlAiSjOFEfmr6//1HymMocDqSuisc+i9IKS 0GTBfBWlX0lQt5R14YX3KmuLzQHEpiihYBI2EL4CJqjwm3d/MtiLQI530ropu4rwh3pZ JawqzQZIGEfT+2Qlp2sHBcfDYWzaU2TTGLw8xrL+nZwhgpMek87BpzzeiSWFSLV41Nl9 EU/agQ7BHFJhSi8050lP3E6gJQMZ5F6dH79n7D9Mx4B4at5j9KEB1OAHtWMk23nQeK3s ZbOrc873yXqagtOVvrFq+IU/sNUAJTIiWHK6NqNKdGb+mdtypsBue2YF3gAzrbJXCa1M UWZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SeJQ9DiJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[189.204.159.171]) by smtp.gmail.com with ESMTPSA id x23sm3902825ood.28.2021.03.23.11.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 11:43:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 03/10] target/ppc: Reduce env->hflags to uint32_t Date: Tue, 23 Mar 2021 12:43:33 -0600 Message-Id: <20210323184340.619757-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210323184340.619757-1-richard.henderson@linaro.org> References: <20210323184340.619757-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It will be stored in tb->flags, which is also uint32_t, so let's use the correct size. Reviewed-by: Cédric Le Goater Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 4 ++-- target/ppc/misc_helper.c | 2 +- target/ppc/translate.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index fe6c3f815d..d5f362506a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1129,8 +1129,8 @@ struct CPUPPCState { bool resume_as_sreset; #endif - /* These resources are used only in QEMU core */ - target_ulong hflags; + /* These resources are used only in TCG */ + uint32_t hflags; target_ulong hflags_compat_nmsr; /* for migration compatibility */ int immu_idx; /* precomputed MMU index to speed up insn accesses */ int dmmu_idx; /* precomputed MMU index to speed up data accesses */ diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 63e3147eb4..b04b4d7c6e 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -199,7 +199,7 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val) if ((val ^ hid0) & 0x00000008) { /* Change current endianness */ hreg_compute_hflags(env); - qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__, + qemu_log("%s: set endianness to %c => %08x\n", __func__, val & 0x8 ? 'l' : 'b', env->hflags); } } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a9325a12e5..a85b890bb0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7657,7 +7657,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) env->nip, env->lr, env->ctr, cpu_read_xer(env), cs->cpu_index); qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " - TARGET_FMT_lx " iidx %d didx %d\n", + "%08x iidx %d didx %d\n", env->msr, env->spr[SPR_HID0], env->hflags, env->immu_idx, env->dmmu_idx); #if !defined(NO_TIMER_DUMP) From patchwork Tue Mar 23 18:43:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 406952 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4733487jai; Tue, 23 Mar 2021 12:34:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMz0wJDnoVd9N3IDMd20eaPcPPBLmKL9NS/cTB+zH/8zrieP59W5a1vM1OJwseqmATlo/3 X-Received: by 2002:a05:6e02:92f:: with SMTP id o15mr6183019ilt.111.1616528050156; Tue, 23 Mar 2021 12:34:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616528050; cv=none; d=google.com; s=arc-20160816; b=t31/9bOKDTPSoazyxoAbH5F4tJKAEqrwWtfFzxZ2S2kNvF3Y0xanPl3ec4U6SaQSYs 7tyJCNwAYhsgMhFsRAanGinD0Ld7ChF+g21XHM18SXrPRQVy6Liu1nLNPqXsKJJnQmEw 8VOBkIH1q3TzV+l1nAEX0cMEfvqo+ClDVAJuhN6H918DAwddWwQVGrR6v1RDnjXEhvO6 ZtvpIFhyrDIa5yihxey2+B8D/sKa1i8vLiP5iWdcM0lkVHU26y/4Kzf1QkeEGYoWyEeq JOxmEySZmZfEps6e+1uzngpOSb/CdIbwaXO5vuKeEHT7FAWNIMTmVGCia1InGpMh2QBQ mKsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7hjRKYvKwPhnZczNplHlGNdiwX+bsNrNu6SiB/+LyZA=; b=D60i8KsfsaXFtHNXuYtmLs5DE3fiBgiOJh5xVLFn8Z80ubLpmhP2CrF1MqjbqydAN0 P5wptcT6wgdqWoEohDDAYcYDZQIpdsZT10vi0GcpFZg3wqRKIvIaLcJVbwTOyHXzwgAe RrUMlDAr2qqachm/TccW6GTk5hBN4lv2qZMpTBvGCp5bFutoCIYA193cqmPRyZTP9dmw vwPoKZ0MFMBaHsA9PvZtteK+JnbXiwzxPntZO6JCP/4qNh4CTUo/LILD+J1xN+94u75p lQskxweCpF1tbDosFEBgNUhSyDQXBV4fy1h5ELkfdunji9r09jQto8yDGmIhjyEGJVQR dfbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SQ+27xqY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[189.204.159.171]) by smtp.gmail.com with ESMTPSA id x23sm3902825ood.28.2021.03.23.11.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 11:43:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 04/10] target/ppc: Put dbcr0 single-step bits into hflags Date: Tue, 23 Mar 2021 12:43:34 -0600 Message-Id: <20210323184340.619757-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210323184340.619757-1-richard.henderson@linaro.org> References: <20210323184340.619757-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because these bits were not in hflags, the code generated for single-stepping on BookE was essentially random. Recompute hflags when storing to dbcr0. Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- target/ppc/helper_regs.c | 24 +++++++++++++++++------- target/ppc/misc_helper.c | 3 +++ target/ppc/translate.c | 11 ----------- 3 files changed, 20 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index df9673b90f..e345966b6b 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -114,13 +114,23 @@ void hreg_compute_hflags(CPUPPCState *env) hflags |= le << MSR_LE; } - if (ppc_flags & POWERPC_FLAG_BE) { - QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE); - msr_mask |= 1 << MSR_BE; - } - if (ppc_flags & POWERPC_FLAG_SE) { - QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE); - msr_mask |= 1 << MSR_SE; + if (ppc_flags & POWERPC_FLAG_DE) { + target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; + if (dbcr0 & DBCR0_ICMP) { + hflags |= 1 << HFLAGS_SE; + } + if (dbcr0 & DBCR0_BRT) { + hflags |= 1 << HFLAGS_BE; + } + } else { + if (ppc_flags & POWERPC_FLAG_BE) { + QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE); + msr_mask |= 1 << MSR_BE; + } + if (ppc_flags & POWERPC_FLAG_SE) { + QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE); + msr_mask |= 1 << MSR_SE; + } } if (msr_is_64bit(env, msr)) { diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index b04b4d7c6e..002958be26 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -215,6 +215,9 @@ void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val) { + /* Bits 26 & 27 affect single-stepping. */ + hreg_compute_hflags(env); + /* Bits 28 & 29 affect reset or shutdown. */ store_40x_dbcr0(env, val); } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a85b890bb0..7912495f28 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7923,17 +7923,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if ((hflags >> HFLAGS_BE) & 1) { ctx->singlestep_enabled |= CPU_BRANCH_STEP; } - if ((env->flags & POWERPC_FLAG_DE) && msr_de) { - ctx->singlestep_enabled = 0; - target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; - if (dbcr0 & DBCR0_ICMP) { - ctx->singlestep_enabled |= CPU_SINGLE_STEP; - } - if (dbcr0 & DBCR0_BRT) { - ctx->singlestep_enabled |= CPU_BRANCH_STEP; - } - - } if (unlikely(ctx->base.singlestep_enabled)) { ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; } From patchwork Tue Mar 23 18:43:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 406948 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4726968jai; Tue, 23 Mar 2021 12:23:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwqbOlERIaDC2zkRAc/6tistZMcQ/Ei9grJmQVGXyJt1x9dewBZe1ZXtG2dZvLhoG3c3q+B X-Received: by 2002:a05:6638:2a3:: with SMTP id d3mr6224032jaq.42.1616527418225; Tue, 23 Mar 2021 12:23:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616527418; cv=none; d=google.com; s=arc-20160816; b=txeu9zhuq7DlyN9MkY24p5g+YJ8KpY8VYWc6VjjeNFjw5z4wEZtXsn7kJ3tbeg3BVf MDtGAyTKM1bjxSjaYjO4EnjFY7n7OjqkIkCDHPAhZU1g73BxSKzS3Xa8oTTp2TB25eTZ 0sxzgXy4S5Z3h9EHgY2XHB1m5CMoR992YXOsAo2daX4LEzN7Xzf5/yC5vW3KZHZ5uRDa UmkmNTAb16wvIZ9s0Y08Dy15eE0TQkkleafX+1h4UUFWhimhMXVvUidV1kitj/Cna1rP wobNdl1H6PqUGLcZTwCpJ61WAaC4lvkybN2gA9pTcBRsyny90wra83xl2f18eOBmY1Mh xTUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nDEzeJHZqdUXe/dXYq7qR5PEy35VBqTIPDXHrdEdgcc=; b=Wu2elSxcYHIqFcJiZvMgfiOWzDmbsI42uR+qpGJjnU5b6GkeFvIGjpoh1ssm6r0E+h I5U/qMEeUp61D9C/nbRuTUTspeEy/uIbcKzDBijSFEIGWi5WM1sug0dAHyBEdQPMhFAW CrU5NuUydWlOz1BiI0f/EO8/q7hEV5oLW3yFv6bRgQEFAMD3ORZNK8R/s3dJL5j9oq9v +9OjBSwXHdwcAXBKO65NWsAVuQ4wPSilNkSZX/q0VMx+hjbioRILZHQ0CUA73U0Eip63 oXa7wVRH1LQ6qG9sBrSmSxZlk8i//cWaSHkz0RVrWwPjLOheDtggrVpkrnGOobmqLI/b 9YQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="s/lmuF8T"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[189.204.159.171]) by smtp.gmail.com with ESMTPSA id x23sm3902825ood.28.2021.03.23.11.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 11:43:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 05/10] target/ppc: Create helper_scv Date: Tue, 23 Mar 2021 12:43:35 -0600 Message-Id: <20210323184340.619757-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210323184340.619757-1-richard.henderson@linaro.org> References: <20210323184340.619757-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Perform the test against FSCR_SCV at runtime, in the helper. This means we can remove the incorrect set against SCV in ppc_tr_init_disas_context and do not need to add an HFLAGS bit. Signed-off-by: Richard Henderson --- target/ppc/helper.h | 1 + target/ppc/excp_helper.c | 9 +++++++++ target/ppc/translate.c | 20 +++++++------------- 3 files changed, 17 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6a4dccf70c..513066d54d 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -13,6 +13,7 @@ DEF_HELPER_1(rfci, void, env) DEF_HELPER_1(rfdi, void, env) DEF_HELPER_1(rfmci, void, env) #if defined(TARGET_PPC64) +DEF_HELPER_2(scv, noreturn, env, i32) DEF_HELPER_2(pminsn, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 85de7e6c90..5c95e0c103 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1130,6 +1130,15 @@ void helper_store_msr(CPUPPCState *env, target_ulong val) } #if defined(TARGET_PPC64) +void helper_scv(CPUPPCState *env, uint32_t lev) +{ + if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) { + raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev); + } else { + raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV); + } +} + void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn) { CPUState *cs; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7912495f28..d48c554290 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -173,7 +173,6 @@ struct DisasContext { bool vsx_enabled; bool spe_enabled; bool tm_enabled; - bool scv_enabled; bool gtse; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; @@ -4081,15 +4080,16 @@ static void gen_sc(DisasContext *ctx) #if !defined(CONFIG_USER_ONLY) static void gen_scv(DisasContext *ctx) { - uint32_t lev; + uint32_t lev = (ctx->opcode >> 5) & 0x7F; - if (unlikely(!ctx->scv_enabled)) { - gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_SCV); - return; + /* Set the PC back to the faulting instruction. */ + if (ctx->exception == POWERPC_EXCP_NONE) { + gen_update_nip(ctx, ctx->base.pc_next - 4); } + gen_helper_scv(cpu_env, tcg_constant_i32(lev)); - lev = (ctx->opcode >> 5) & 0x7F; - gen_exception_err(ctx, POWERPC_SYSCALL_VECTORED, lev); + /* This need not be exact, just not POWERPC_EXCP_NONE */ + ctx->exception = POWERPC_SYSCALL_VECTORED; } #endif #endif @@ -7907,12 +7907,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; - if ((env->flags & POWERPC_FLAG_SCV) - && (env->spr[SPR_FSCR] & (1ull << FSCR_SCV))) { - ctx->scv_enabled = true; - } else { - ctx->scv_enabled = false; - } ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); From patchwork Tue Mar 23 18:43:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 406945 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4706081jai; Tue, 23 Mar 2021 11:54:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxeSV2TFBGLtzrn0pLUGTk1tFn0y/K1IoZUrfdnS64qg3Udv01QB5zUYQy3d2l5vOQgGoGh X-Received: by 2002:a92:d686:: with SMTP id p6mr5960966iln.268.1616525665792; Tue, 23 Mar 2021 11:54:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616525665; cv=none; d=google.com; s=arc-20160816; b=k4lFUkb9RDeCer3+mKJyxDDuLVtR8gizlBf/2s5tDKj4FLbGk8tG46VwY3QdsP8DZb eWIbOx+Dw8TngcY3mQuKmv4IdhivD8bCViWxhmId9T8U0+6v539U2lOb2Ut70S/ff89h MrPEQ4Cy4jGTFXAzhQiEMIADcGkERIPancK15IdgEf+oZ65TLVOPG3Kw6SxwMrMNf7hO jyBhha+Lg/BSqx4WfgXUsNvlcAxBG44qXzQontT9JzX+CdS5iXsf12fFi9o8hHk3u+sK nETLcS/d3cgyEVOO7fw6SJ5louqkDTw1OfLrTVUZFOJ3HLujq+vsL1GynrDseUZOFW81 Au3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0y0jim2Psup2n6cJG/ney9BoSyKMVklHs3Io6+sGx/4=; b=mZ+vjoRtnOYgOAXnuX+dSjMZVORXefzalrznjwjzgh0v0Xy+ixyv4EV4FH7qbLNye0 KV6DRJdUnFN+UghzpHnrrXV0M/QHpqN31IeWWXtHc53PzFeuSMYZrdIMC3o82hKku90p FIzLtp2hHUpDIoOgelNGqTScJAobvUOMzbQ0hp33FL8SGMBRYVRHzuPivwAAJXxyQ+ld 4P06nZy88HS6oqKvyZbIwwNujvcMDVPFBCiDLnFdZWCB87h6cJ1Ox07m5Gr9fNXWp3e0 LRlgoP8J+UgxjQjCFKrctN+6Aj3RfGc+f2JzaNXPDtmvm1jhJxVsQaH/2gPNNNdbhnny xTEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="sAfD/7jS"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[189.204.159.171]) by smtp.gmail.com with ESMTPSA id x23sm3902825ood.28.2021.03.23.11.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 11:43:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 06/10] target/ppc: Put LPCR[GTSE] in hflags Date: Tue, 23 Mar 2021 12:43:36 -0600 Message-Id: <20210323184340.619757-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210323184340.619757-1-richard.henderson@linaro.org> References: <20210323184340.619757-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c34; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because this bit was not in hflags, the privilege check for tlb instructions was essentially random. Recompute hflags when storing to LPCR. Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 1 + target/ppc/helper_regs.c | 3 +++ target/ppc/mmu-hash64.c | 3 +++ target/ppc/translate.c | 2 +- 4 files changed, 8 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d5f362506a..3c28ddb331 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -596,6 +596,7 @@ enum { HFLAGS_LE = 0, /* MSR_LE -- comes from elsewhere on 601 */ HFLAGS_HV = 1, /* computed from MSR_HV and other state */ HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ + HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */ HFLAGS_DR = 4, /* MSR_DR */ HFLAGS_IR = 5, /* MSR_IR */ HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index e345966b6b..f85bb14d1d 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -149,6 +149,9 @@ void hreg_compute_hflags(CPUPPCState *env) if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { hflags |= 1 << HFLAGS_TM; } + if (env->spr[SPR_LPCR] & LPCR_GTSE) { + hflags |= 1 << HFLAGS_GTSE; + } #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 0fabc10302..d517a99832 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -30,6 +30,7 @@ #include "exec/log.h" #include "hw/hw.h" #include "mmu-book3s-v3.h" +#include "helper_regs.h" /* #define DEBUG_SLB */ @@ -1125,6 +1126,8 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) CPUPPCState *env = &cpu->env; env->spr[SPR_LPCR] = val & pcc->lpcr_mask; + /* The gtse bit affects hflags */ + hreg_compute_hflags(env); } void helper_store_lpcr(CPUPPCState *env, target_ulong val) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d48c554290..5e629291d3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7908,7 +7908,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; - ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); + ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; ctx->singlestep_enabled = 0; if ((hflags >> HFLAGS_SE) & 1) { From patchwork Tue Mar 23 18:43:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 406953 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4735486jai; Tue, 23 Mar 2021 12:37:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz0rDV8uhtbBAYNbzxgO/lB40caCLaiM8JyhI9POYzPNLZQMViXUi/adnwfB5rWKiT7/DGr X-Received: by 2002:a92:c6d0:: with SMTP id v16mr5880144ilm.289.1616528260594; Tue, 23 Mar 2021 12:37:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616528260; cv=none; d=google.com; s=arc-20160816; b=pP9kBU8rjM0qCUcYU+OM0ya+b/nzGNOtK8L/11DqTtgw2rUcOCF8V5SGMar20i7pky BgW0dfWtcJdHy2t9MdU1rbtREMNzQY+LwhhZYV3hEdVttghTgOD+b6COH8lzRyOSItUu bfgc6lpNHSNbiQSaiWdp0lv1XB8ww6n8CgKEaHvjA/E1YeZnHexmCJYBPKPRTDuQjO/m 5I/HZoruhlP/VuSlRe/utO5V9q15ESJRC30/S5+eZAQX5XczS9efcEUMNr0AJAj/GqkC e1YBWq3BF5kqyzJcedIlvnRYP6iBjcLdTFfGyRPkgcTpJSUb/R0JzkcsoYS3ToiDg2HJ S8RA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3FXi8snd//6e3eo194okSdd2MkYemigNkupkO7nrNNk=; b=DjLbtciWqpLqNQ2aTnj75AFesKYjP4ZplT2t1JGBihsXOf4THw0EnhoCO+aHF12/fi MVoK6c5ZqDIVmRpGwQPFxupKJJHrs6DBIY93Ir/sfvywDAzH91IrmiYtglQZm49AK5Wx hh8gc+OJjjVXxkrslbOW6prrYMaBLVOGAnFXMGxH5CFOreNPs4guSGxFCDat1tFOVjbk TUWshTM/k2NRajlxRpXXf3VkTuooRR1lBpH5TJ+KykNiHnfL2QMBENX2ys9c8Y1/dUdU eERvOZMmlrAnvZcF/ALB0Evmo+6j3kvM48mDtGIJuOAciCwZQADXahUiOVw5ss3cCuA7 7qSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yCF3E+0D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[189.204.159.171]) by smtp.gmail.com with ESMTPSA id x23sm3902825ood.28.2021.03.23.11.43.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 11:43:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 07/10] target/ppc: Remove MSR_SA and MSR_AP from hflags Date: Tue, 23 Mar 2021 12:43:37 -0600 Message-Id: <20210323184340.619757-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210323184340.619757-1-richard.henderson@linaro.org> References: <20210323184340.619757-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Nothing within the translator -- or anywhere else for that matter -- checks MSR_SA or MSR_AP on the 602. This may be a mistake. However, for the moment, we need not record these bits in hflags. This allows us to simplify HFLAGS_VSX computation by moving it to overlap with MSR_VSX. Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 4 +--- target/ppc/helper_regs.c | 10 ++++------ 2 files changed, 5 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 3c28ddb331..2f72f83ee3 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -600,14 +600,12 @@ enum { HFLAGS_DR = 4, /* MSR_DR */ HFLAGS_IR = 5, /* MSR_IR */ HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ - HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */ HFLAGS_TM = 8, /* computed from MSR_TM */ HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */ HFLAGS_FP = 13, /* MSR_FP */ HFLAGS_PR = 14, /* MSR_PR */ - HFLAGS_SA = 22, /* MSR_SA */ - HFLAGS_AP = 23, /* MSR_AP */ + HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ }; diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index f85bb14d1d..dd3cd770a3 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -99,11 +99,8 @@ void hreg_compute_hflags(CPUPPCState *env) QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR); QEMU_BUILD_BUG_ON(MSR_IR != HFLAGS_IR); QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP); - QEMU_BUILD_BUG_ON(MSR_SA != HFLAGS_SA); - QEMU_BUILD_BUG_ON(MSR_AP != HFLAGS_AP); msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | - (1 << MSR_DR) | (1 << MSR_IR) | - (1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP)); + (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP)); if (ppc_flags & POWERPC_FLAG_HID0_LE) { /* @@ -143,8 +140,9 @@ void hreg_compute_hflags(CPUPPCState *env) QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR); msr_mask |= 1 << MSR_VR; } - if ((ppc_flags & POWERPC_FLAG_VSX) && (msr & (1 << MSR_VSX))) { - hflags |= 1 << HFLAGS_VSX; + if (ppc_flags & POWERPC_FLAG_VSX) { + QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX); + msr_mask |= 1 << MSR_VSX; } if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { hflags |= 1 << HFLAGS_TM; From patchwork Tue Mar 23 18:43:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 406949 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4729992jai; Tue, 23 Mar 2021 12:28:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFFtchyMVnTV8sslQygylqabBAhOTiayOItYNb9OGgszNphsQxCeFN8Vy9J+4fVzerMdv9 X-Received: by 2002:a05:6e02:188f:: with SMTP id o15mr6410861ilu.178.1616527698555; Tue, 23 Mar 2021 12:28:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616527698; cv=none; d=google.com; s=arc-20160816; b=CYqTgsyE2iK+Ks0dwYHye8IcwqksnHEHvLqpoUoZG/k1UWKtZbs85tKmmQVc0uSBHv oqlvuspQckbYaodEp34OAUvAMNmmBaKyKGn0Sg/9a3At5qRa/iIxV2Ihj1V37QZXeoGZ iSCqDZXvAoCwZ/7KcgI4Z8OhAitohBAzo6DQAxGBDAmk3ntD/HB6Lj40YsR4uFxXeblo tRbAPwZqL6W6YCVyZ31FNIXBVCkorbU9a2oukMWcfO+Ch45lDOhUssyWjh0NscD5Uoow 9G+OD+wizn8xsBAIEDff3vVoGrX/lINqWVglfzOeQ7Is2Q8OGqg5mq8qWtBvacjpg6UN amOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yR6a5C+RN4aXpJjTSKMGXA72kDkxG0ld+xL4kg1fU/Y=; b=xQxxT0sUNRRzrpqOPdoduOJ8vNBgzojpM7Je8KNqJtya9UrrmbRAejB1TlnS5Ddban ppcY3zC/IofyvppuGeg+/CrlFVgAt23lKXfqOKS868xtDE6Z7Q1idSdt6eTfVDaq0fIa bSv9dz2NWPxZUFnQfM3A+sho/LLqt927UOZXq1ySdmJEH3RwIUdwJwJnkKqhekh9WIay gp7aYlzECAmme91V1rwKoRc0xMkV2aGXPBVPxtD3+Pm3tND3qyPps1+4SL/zWZAwXs5T r/6X9a4Tr6mMxoFwsYHlPAlQ/rqEygjTVeWv79aj2OJZ+C+aWd8KpOu2a3cHOdgPSksN seTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PZDcHwkR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[189.204.159.171]) by smtp.gmail.com with ESMTPSA id x23sm3902825ood.28.2021.03.23.11.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 11:43:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 08/10] target/ppc: Remove env->immu_idx and env->dmmu_idx Date: Tue, 23 Mar 2021 12:43:38 -0600 Message-Id: <20210323184340.619757-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210323184340.619757-1-richard.henderson@linaro.org> References: <20210323184340.619757-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We weren't recording MSR_GS in hflags, which means that BookE memory accesses were essentially random vs Guest State. Instead of adding this bit directly, record the completed mmu indexes instead. This makes it obvious that we are recording exactly the information that we need. This also means that we can stop directly recording MSR_IR. Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 12 ++++-- target/ppc/helper_regs.h | 1 - target/ppc/helper_regs.c | 89 +++++++++++++++++++--------------------- target/ppc/machine.c | 2 +- target/ppc/mem_helper.c | 2 +- target/ppc/translate.c | 6 +-- 6 files changed, 56 insertions(+), 56 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2f72f83ee3..3d021f61f3 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -598,7 +598,6 @@ enum { HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */ HFLAGS_DR = 4, /* MSR_DR */ - HFLAGS_IR = 5, /* MSR_IR */ HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ HFLAGS_TM = 8, /* computed from MSR_TM */ HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ @@ -607,6 +606,9 @@ enum { HFLAGS_PR = 14, /* MSR_PR */ HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ + + HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */ + HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */ }; /*****************************************************************************/ @@ -1131,8 +1133,6 @@ struct CPUPPCState { /* These resources are used only in TCG */ uint32_t hflags; target_ulong hflags_compat_nmsr; /* for migration compatibility */ - int immu_idx; /* precomputed MMU index to speed up insn accesses */ - int dmmu_idx; /* precomputed MMU index to speed up data accesses */ /* Power management */ int (*check_pow)(CPUPPCState *env); @@ -1368,7 +1368,11 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); #define MMU_USER_IDX 0 static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) { - return ifetch ? env->immu_idx : env->dmmu_idx; +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7; +#endif } /* Compatibility modes */ diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index 4148a442b3..42f26870b9 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -21,7 +21,6 @@ #define HELPER_REGS_H void hreg_swap_gpr_tgpr(CPUPPCState *env); -void hreg_compute_mem_idx(CPUPPCState *env); void hreg_compute_hflags(CPUPPCState *env); void cpu_interrupt_exittb(CPUState *cs); int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv); diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index dd3cd770a3..5411a67e9a 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -43,49 +43,6 @@ void hreg_swap_gpr_tgpr(CPUPPCState *env) env->tgpr[3] = tmp; } -void hreg_compute_mem_idx(CPUPPCState *env) -{ - /* - * This is our encoding for server processors. The architecture - * specifies that there is no such thing as userspace with - * translation off, however it appears that MacOS does it and some - * 32-bit CPUs support it. Weird... - * - * 0 = Guest User space virtual mode - * 1 = Guest Kernel space virtual mode - * 2 = Guest User space real mode - * 3 = Guest Kernel space real mode - * 4 = HV User space virtual mode - * 5 = HV Kernel space virtual mode - * 6 = HV User space real mode - * 7 = HV Kernel space real mode - * - * For BookE, we need 8 MMU modes as follow: - * - * 0 = AS 0 HV User space - * 1 = AS 0 HV Kernel space - * 2 = AS 1 HV User space - * 3 = AS 1 HV Kernel space - * 4 = AS 0 Guest User space - * 5 = AS 0 Guest Kernel space - * 6 = AS 1 Guest User space - * 7 = AS 1 Guest Kernel space - */ - if (env->mmu_model & POWERPC_MMU_BOOKE) { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_is ? 2 : 0; - env->dmmu_idx += msr_ds ? 2 : 0; - env->immu_idx += msr_gs ? 4 : 0; - env->dmmu_idx += msr_gs ? 4 : 0; - } else { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_ir ? 0 : 2; - env->dmmu_idx += msr_dr ? 0 : 2; - env->immu_idx += msr_hv ? 4 : 0; - env->dmmu_idx += msr_hv ? 4 : 0; - } -} - void hreg_compute_hflags(CPUPPCState *env) { target_ulong msr = env->msr; @@ -97,10 +54,9 @@ void hreg_compute_hflags(CPUPPCState *env) QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE); QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR); QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR); - QEMU_BUILD_BUG_ON(MSR_IR != HFLAGS_IR); QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP); msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | - (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP)); + (1 << MSR_DR) | (1 << MSR_FP)); if (ppc_flags & POWERPC_FLAG_HID0_LE) { /* @@ -155,10 +111,51 @@ void hreg_compute_hflags(CPUPPCState *env) if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { hflags |= 1 << HFLAGS_HV; } + + /* + * This is our encoding for server processors. The architecture + * specifies that there is no such thing as userspace with + * translation off, however it appears that MacOS does it and some + * 32-bit CPUs support it. Weird... + * + * 0 = Guest User space virtual mode + * 1 = Guest Kernel space virtual mode + * 2 = Guest User space real mode + * 3 = Guest Kernel space real mode + * 4 = HV User space virtual mode + * 5 = HV Kernel space virtual mode + * 6 = HV User space real mode + * 7 = HV Kernel space real mode + * + * For BookE, we need 8 MMU modes as follow: + * + * 0 = AS 0 HV User space + * 1 = AS 0 HV Kernel space + * 2 = AS 1 HV User space + * 3 = AS 1 HV Kernel space + * 4 = AS 0 Guest User space + * 5 = AS 0 Guest Kernel space + * 6 = AS 1 Guest User space + * 7 = AS 1 Guest Kernel space + */ + unsigned immu_idx, dmmu_idx; + dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1; + if (env->mmu_model & POWERPC_MMU_BOOKE) { + dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0; + immu_idx = dmmu_idx; + immu_idx |= msr & (1 << MSR_IS) ? 2 : 0; + dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0; + } else { + dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0; + immu_idx = dmmu_idx; + immu_idx |= msr & (1 << MSR_IR) ? 0 : 2; + dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2; + } + hflags |= immu_idx << HFLAGS_IMMU_IDX; + hflags |= dmmu_idx << HFLAGS_DMMU_IDX; #endif env->hflags = hflags | (msr & msr_mask); - hreg_compute_mem_idx(env); } void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 09c5765a87..e5bffbe365 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -16,7 +16,7 @@ static void post_load_update_msr(CPUPPCState *env) /* * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB - * before restoring. Note that this recomputes hflags and mem_idx. + * before restoring. Note that this recomputes hflags. */ env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index f4f7e730de..444b2a30ef 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -278,7 +278,7 @@ static void dcbz_common(CPUPPCState *env, target_ulong addr, target_ulong mask, dcbz_size = env->dcache_line_size; uint32_t i; void *haddr; - int mmu_idx = epid ? PPC_TLB_EPID_STORE : env->dmmu_idx; + int mmu_idx = epid ? PPC_TLB_EPID_STORE : cpu_mmu_index(env, false); #if defined(TARGET_PPC64) /* Check for dcbz vs dcbzl on 970 */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5e629291d3..a53463b9b8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7658,8 +7658,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) cs->cpu_index); qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " "%08x iidx %d didx %d\n", - env->msr, env->spr[SPR_HID0], - env->hflags, env->immu_idx, env->dmmu_idx); + env->msr, env->spr[SPR_HID0], env->hflags, + cpu_mmu_index(env, true), cpu_mmu_index(env, false)); #if !defined(NO_TIMER_DUMP) qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 #if !defined(CONFIG_USER_ONLY) @@ -7885,7 +7885,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->exception = POWERPC_EXCP_NONE; ctx->spr_cb = env->spr_cb; ctx->pr = (hflags >> HFLAGS_PR) & 1; - ctx->mem_idx = env->dmmu_idx; + ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; ctx->dr = (hflags >> HFLAGS_DR) & 1; ctx->hv = (hflags >> HFLAGS_HV) & 1; ctx->insns_flags = env->insns_flags; From patchwork Tue Mar 23 18:43:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 406950 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4731268jai; Tue, 23 Mar 2021 12:30:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz3Hu8jTyJFEXrSQWWI7RlH8QIkwgXt2QfzvWtsaKuKMsgIrQixkYZEQi1eF7dADktPgfv1 X-Received: by 2002:a92:540d:: with SMTP id i13mr6220417ilb.8.1616527822809; Tue, 23 Mar 2021 12:30:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616527822; cv=none; d=google.com; s=arc-20160816; b=JAx/oqDsUN8Az3F1YfIKSICfAqf6KZM9yPIE9+a9B4tEJJPi6hqZ9S5By86lJDrJat Ohc+uxpoyxVJ5gRsyfvxsIHRvVV+LuwZN1Uo9KNaIbGEVZ/n9zBBlLg4RvMYSGcaqouI OKHeUCSFHnotNK8V0EznhRE+vPJoxCcQF+zPnzNJJc7yAvO8uTQyxzi26CbEn4w+Zy4D SraaUqOo8ep/wYqRLH28bwm/cH19tsSWJT+nwsqedfpM0u8i21MbUWSFDBliP1q9qt5p Wpqz6vu/YV9TTOS/VWibA4rx/LRsAOwXAB+UrAZubOa86C5nsTRws11jn7T9Gyd3vDGw eQjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GP7KN1O/N4US4bdn1IcXHif9taZ0y5n50rRX2Q2HUDY=; b=QkUZ7yGLCaxcZdFYIvs4ENo6Tif3MhedAnSnoqkEPNlcdxLyuGO5qGwvh3pDmZFP55 5wWTvx8773x9wF4+OwkrVb3tF04j1Ihj3fOy71UMeSrhykE3J0Q3kBJyDMSquTIA/WEF LyTidyvyX14mp+LmMG5EeeT/dFMY74a7A00Xmtp7779cDVjKQn9+xvFDBa7WvfWIbs1M f+9hgBSv9ZOd33KP0HvQTUFcAyhnQwLxjRBfV+rgD4NipdjdHXGpIa9wzyR511p3fkfc oqmLKPjEH03+2o4igr/bIPgLIOWah/SQltg0BJgONGgxjoyYNRhH5ww07ZjwReYlkvLB utyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Jc0b5pnP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[189.204.159.171]) by smtp.gmail.com with ESMTPSA id x23sm3902825ood.28.2021.03.23.11.43.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 11:43:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 09/10] linux-user/ppc: Fix msr updates for signal handling Date: Tue, 23 Mar 2021 12:43:39 -0600 Message-Id: <20210323184340.619757-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210323184340.619757-1-richard.henderson@linaro.org> References: <20210323184340.619757-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In save_user_regs, there are two bugs where we OR in a bit number instead of the bit, clobbering the low bits of MSR. However: The MSR_VR and MSR_SPE bits control the availability of the insns. If the bits were not already set in MSR, then any attempt to access those registers would result in SIGILL. For linux-user, we always initialize MSR to the capabilities of the cpu. We *could* add checks vs MSR where we currently check insn_flags and insn_flags2, but we know they match. Also, there's a stray cut-and-paste comment in restore. Then, do not force little-endian binaries into big-endian mode. Finally, use ppc_store_msr for the update to affect hflags. Which is the reason none of these bugs were previously noticed. Signed-off-by: Richard Henderson --- linux-user/ppc/cpu_loop.c | 5 +++-- linux-user/ppc/signal.c | 23 +++++++++++------------ 2 files changed, 14 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index df71e15a25..4a0f6c8dc2 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -492,11 +492,12 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) #if defined(TARGET_PPC64) int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF; #if defined(TARGET_ABI32) - env->msr &= ~((target_ulong)1 << flag); + ppc_store_msr(env, env->msr & ~((target_ulong)1 << flag)); #else - env->msr |= (target_ulong)1 << flag; + ppc_store_msr(env, env->msr | (target_ulong)1 << flag); #endif #endif + env->nip = regs->nip; for(i = 0; i < 32; i++) { env->gpr[i] = regs->gpr[i]; diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index b78613f7c8..bad38f8ed9 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -261,9 +261,6 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) __put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); __put_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); } - /* Set MSR_VR in the saved MSR value to indicate that - frame->mc_vregs contains valid data. */ - msr |= MSR_VR; #if defined(TARGET_PPC64) vrsave = (uint32_t *)&frame->mc_vregs.altivec[33]; /* 64-bit needs to put a pointer to the vectors in the frame */ @@ -300,9 +297,6 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) for (i = 0; i < ARRAY_SIZE(env->gprh); i++) { __put_user(env->gprh[i], &frame->mc_vregs.spe[i]); } - /* Set MSR_SPE in the saved MSR value to indicate that - frame->mc_vregs contains valid data. */ - msr |= MSR_SPE; __put_user(env->spe_fscr, &frame->mc_vregs.spe[32]); } #endif @@ -354,8 +348,10 @@ static void restore_user_regs(CPUPPCState *env, __get_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); /* If doing signal return, restore the previous little-endian mode. */ - if (sig) - env->msr = (env->msr & ~(1ull << MSR_LE)) | (msr & (1ull << MSR_LE)); + if (sig) { + ppc_store_msr(env, ((env->msr & ~(1ull << MSR_LE)) | + (msr & (1ull << MSR_LE)))); + } /* Restore Altivec registers if necessary. */ if (env->insns_flags & PPC_ALTIVEC) { @@ -376,8 +372,6 @@ static void restore_user_regs(CPUPPCState *env, __get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); __get_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); } - /* Set MSR_VEC in the saved MSR value to indicate that - frame->mc_vregs contains valid data. */ #if defined(TARGET_PPC64) vrsave = (uint32_t *)&v_regs[33]; #else @@ -468,7 +462,7 @@ void setup_frame(int sig, struct target_sigaction *ka, env->nip = (target_ulong) ka->_sa_handler; /* Signal handlers are entered in big-endian mode. */ - env->msr &= ~(1ull << MSR_LE); + ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); unlock_user_struct(frame, frame_addr, 1); return; @@ -563,8 +557,13 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, env->nip = (target_ulong) ka->_sa_handler; #endif +#ifdef TARGET_WORDS_BIGENDIAN /* Signal handlers are entered in big-endian mode. */ - env->msr &= ~(1ull << MSR_LE); + ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); +#else + /* Signal handlers are entered in little-endian mode. */ + ppc_store_msr(env, env->msr | (1ull << MSR_LE)); +#endif unlock_user_struct(rt_sf, rt_sf_addr, 1); return; From patchwork Tue Mar 23 18:43:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 406946 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4718815jai; 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[189.204.159.171]) by smtp.gmail.com with ESMTPSA id x23sm3902825ood.28.2021.03.23.11.43.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 11:43:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 10/10] target/ppc: Validate hflags with CONFIG_DEBUG_TCG Date: Tue, 23 Mar 2021 12:43:40 -0600 Message-Id: <20210323184340.619757-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210323184340.619757-1-richard.henderson@linaro.org> References: <20210323184340.619757-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Verify that hflags was updated correctly whenever we change cpu state that is used by hflags. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 5 +++++ target/ppc/helper_regs.c | 29 +++++++++++++++++++++++++++-- 2 files changed, 32 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 3d021f61f3..69fc9a2831 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2425,6 +2425,10 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xer); */ #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) +#ifdef CONFIG_DEBUG_TCG +void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags); +#else static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { @@ -2432,6 +2436,7 @@ static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, *cs_base = 0; *flags = env->hflags; } +#endif void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception); void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 5411a67e9a..3723872aa6 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -43,7 +43,7 @@ void hreg_swap_gpr_tgpr(CPUPPCState *env) env->tgpr[3] = tmp; } -void hreg_compute_hflags(CPUPPCState *env) +static uint32_t hreg_compute_hflags_value(CPUPPCState *env) { target_ulong msr = env->msr; uint32_t ppc_flags = env->flags; @@ -155,9 +155,34 @@ void hreg_compute_hflags(CPUPPCState *env) hflags |= dmmu_idx << HFLAGS_DMMU_IDX; #endif - env->hflags = hflags | (msr & msr_mask); + return hflags | (msr & msr_mask); } +void hreg_compute_hflags(CPUPPCState *env) +{ + env->hflags = hreg_compute_hflags_value(env); +} + +#ifdef CONFIG_DEBUG_TCG +void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags) +{ + uint32_t hflags_current = env->hflags; + uint32_t hflags_rebuilt; + + *pc = env->nip; + *cs_base = 0; + *flags = hflags_current; + + hflags_rebuilt = hreg_compute_hflags_value(env); + if (unlikely(hflags_current != hflags_rebuilt)) { + cpu_abort(env_cpu(env), + "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", + hflags_current, hflags_rebuilt); + } +} +#endif + void cpu_interrupt_exittb(CPUState *cs) { if (!kvm_enabled()) {