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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id o13sm8961147iob.17.2021.03.23.07.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 07:51:38 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: bjorn.andersson@linaro.org, evgreen@chromium.org, cpratapa@codeaurora.org, subashab@codeaurora.org, elder@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/6] net: ipa: reduce IPA version assumptions Date: Tue, 23 Mar 2021 09:51:27 -0500 Message-Id: <20210323145132.2291316-2-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210323145132.2291316-1-elder@linaro.org> References: <20210323145132.2291316-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Modify conditional tests throughout the IPA code so they do not assume that IPA v3.5.1 is the oldest version supported. Also remove assumptions that IPA v4.5 is the newest version of IPA supported. Augment versions in comments with "+", to be clearer that the comment applies to a version and subsequent versions. (E.g., "present for IPA v4.2+" instead of just "present for v4.2".) Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 8 ++++---- drivers/net/ipa/ipa_cmd.c | 26 +++++++++++++++----------- drivers/net/ipa/ipa_endpoint.c | 25 ++++++++++++++----------- drivers/net/ipa/ipa_main.c | 6 +++--- drivers/net/ipa/ipa_qmi.c | 2 +- 5 files changed, 37 insertions(+), 30 deletions(-) -- 2.27.0 diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 7f3e338ca7a72..cf54c6f4c34ca 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -827,14 +827,14 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell) /* Max prefetch is 1 segment (do not set MAX_PREFETCH_FMASK) */ - /* We enable the doorbell engine for IPA v3.5.1 */ - if (gsi->version == IPA_VERSION_3_5_1 && doorbell) + /* No need to use the doorbell engine starting at IPA v4.0 */ + if (gsi->version < IPA_VERSION_4_0 && doorbell) val |= USE_DB_ENG_FMASK; /* v4.0 introduces an escape buffer for prefetch. We use it * on all but the AP command channel. */ - if (gsi->version != IPA_VERSION_3_5_1 && !channel->command) { + if (gsi->version >= IPA_VERSION_4_0 && !channel->command) { /* If not otherwise set, prefetch buffers are used */ if (gsi->version < IPA_VERSION_4_5) val |= USE_ESCAPE_BUF_ONLY_FMASK; @@ -973,7 +973,7 @@ void gsi_channel_reset(struct gsi *gsi, u32 channel_id, bool doorbell) gsi_channel_reset_command(channel); /* Due to a hardware quirk we may need to reset RX channels twice. */ - if (gsi->version == IPA_VERSION_3_5_1 && !channel->toward_ipa) + if (gsi->version < IPA_VERSION_4_0 && !channel->toward_ipa) gsi_channel_reset_command(channel); gsi_channel_program(channel, doorbell); diff --git a/drivers/net/ipa/ipa_cmd.c b/drivers/net/ipa/ipa_cmd.c index 35e35852c25c5..a0be25f1f4427 100644 --- a/drivers/net/ipa/ipa_cmd.c +++ b/drivers/net/ipa/ipa_cmd.c @@ -71,13 +71,12 @@ struct ipa_cmd_hw_hdr_init_local { /* IPA_CMD_REGISTER_WRITE */ -/* For IPA v4.0+, this opcode gets modified with pipeline clear options */ - +/* For IPA v4.0+, the pipeline clear options are encoded in the opcode */ #define REGISTER_WRITE_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8) #define REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9) struct ipa_cmd_register_write { - __le16 flags; /* Unused/reserved for IPA v3.5.1 */ + __le16 flags; /* Unused/reserved prior to IPA v4.0 */ __le16 offset; __le32 value; __le32 value_mask; @@ -85,12 +84,12 @@ struct ipa_cmd_register_write { }; /* Field masks for ipa_cmd_register_write structure fields */ -/* The next field is present for IPA v4.0 and above */ +/* The next field is present for IPA v4.0+ */ #define REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK GENMASK(14, 11) -/* The next field is present for IPA v3.5.1 only */ +/* The next field is not present for IPA v4.0+ */ #define REGISTER_WRITE_FLAGS_SKIP_CLEAR_FMASK GENMASK(15, 15) -/* The next field and its values are present for IPA v3.5.1 only */ +/* The next field and its values are not present for IPA v4.0+ */ #define REGISTER_WRITE_CLEAR_OPTIONS_FMASK GENMASK(1, 0) /* IPA_CMD_IP_PACKET_INIT */ @@ -123,7 +122,7 @@ struct ipa_cmd_hw_dma_mem_mem { /* Field masks for ipa_cmd_hw_dma_mem_mem structure fields */ #define DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK GENMASK(0, 0) -/* The next two fields are present for IPA v3.5.1 only. */ +/* The next two fields are not present for IPA v4.0+ */ #define DMA_SHARED_MEM_FLAGS_SKIP_CLEAR_FMASK GENMASK(1, 1) #define DMA_SHARED_MEM_FLAGS_CLEAR_OPTIONS_FMASK GENMASK(3, 2) @@ -237,11 +236,12 @@ static bool ipa_cmd_register_write_offset_valid(struct ipa *ipa, u32 bit_count; /* The maximum offset in a register_write immediate command depends - * on the version of IPA. IPA v3.5.1 supports a 16 bit offset, but - * newer versions allow some additional high-order bits. + * on the version of IPA. A 16 bit offset is always supported, + * but starting with IPA v4.0 some additional high-order bits are + * allowed. */ bit_count = BITS_PER_BYTE * sizeof(payload->offset); - if (ipa->version != IPA_VERSION_3_5_1) + if (ipa->version >= IPA_VERSION_4_0) bit_count += hweight32(REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK); BUILD_BUG_ON(bit_count > 32); offset_max = ~0U >> (32 - bit_count); @@ -440,7 +440,11 @@ void ipa_cmd_register_write_add(struct gsi_trans *trans, u32 offset, u32 value, /* pipeline_clear_src_grp is not used */ clear_option = clear_full ? pipeline_clear_full : pipeline_clear_hps; - if (ipa->version != IPA_VERSION_3_5_1) { + /* IPA v4.0+ represents the pipeline clear options in the opcode. It + * also supports a larger offset by encoding additional high-order + * bits in the payload flags field. + */ + if (ipa->version >= IPA_VERSION_4_0) { u16 offset_high; u32 val; diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 88310d3585574..5f93bd60c7586 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -266,7 +266,7 @@ ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay) * if (endpoint->toward_ipa) * assert(ipa->version != IPA_VERSION_4.2); * else - * assert(ipa->version == IPA_VERSION_3_5_1); + * assert(ipa->version < IPA_VERSION_4_0); */ mask = endpoint->toward_ipa ? ENDP_DELAY_FMASK : ENDP_SUSPEND_FMASK; @@ -347,7 +347,7 @@ ipa_endpoint_program_suspend(struct ipa_endpoint *endpoint, bool enable) { bool suspended; - if (endpoint->ipa->version != IPA_VERSION_3_5_1) + if (endpoint->ipa->version >= IPA_VERSION_4_0) return enable; /* For IPA v4.0+, no change made */ /* assert(!endpoint->toward_ipa); */ @@ -515,7 +515,7 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint) /* Where IPA will write the length */ offset = offsetof(struct rmnet_map_header, pkt_len); /* Upper bits are stored in HDR_EXT with IPA v4.5 */ - if (version == IPA_VERSION_4_5) + if (version >= IPA_VERSION_4_5) offset &= field_mask(HDR_OFST_PKT_SIZE_FMASK); val |= HDR_OFST_PKT_SIZE_VALID_FMASK; @@ -562,7 +562,7 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint) /* IPA v4.5 adds some most-significant bits to a few fields, * two of which are defined in the HDR (not HDR_EXT) register. */ - if (ipa->version == IPA_VERSION_4_5) { + if (ipa->version >= IPA_VERSION_4_5) { /* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0, so MSB is 0 */ if (endpoint->data->qmap && !endpoint->toward_ipa) { u32 offset; @@ -776,7 +776,7 @@ static u32 hol_block_timer_val(struct ipa *ipa, u32 microseconds) if (!microseconds) return 0; /* Nothing to compute if timer period is 0 */ - if (ipa->version == IPA_VERSION_4_5) + if (ipa->version >= IPA_VERSION_4_5) return hol_block_timer_qtime_val(ipa, microseconds); /* Use 64 bit arithmetic to avoid overflow... */ @@ -1468,8 +1468,7 @@ static void ipa_endpoint_reset(struct ipa_endpoint *endpoint) * is active, we need to handle things specially to recover. * All other cases just need to reset the underlying GSI channel. */ - special = ipa->version == IPA_VERSION_3_5_1 && - !endpoint->toward_ipa && + special = ipa->version < IPA_VERSION_4_0 && !endpoint->toward_ipa && endpoint->data->aggregation; if (special && ipa_endpoint_aggr_active(endpoint)) ret = ipa_endpoint_reset_rx_aggr(endpoint); @@ -1567,8 +1566,10 @@ void ipa_endpoint_suspend_one(struct ipa_endpoint *endpoint) (void)ipa_endpoint_program_suspend(endpoint, true); } - /* IPA v3.5.1 doesn't use channel stop for suspend */ - stop_channel = endpoint->ipa->version != IPA_VERSION_3_5_1; + /* Starting with IPA v4.0, endpoints are suspended by stopping the + * underlying GSI channel rather than using endpoint suspend mode. + */ + stop_channel = endpoint->ipa->version >= IPA_VERSION_4_0; ret = gsi_channel_suspend(gsi, endpoint->channel_id, stop_channel); if (ret) dev_err(dev, "error %d suspending channel %u\n", ret, @@ -1588,8 +1589,10 @@ void ipa_endpoint_resume_one(struct ipa_endpoint *endpoint) if (!endpoint->toward_ipa) (void)ipa_endpoint_program_suspend(endpoint, false); - /* IPA v3.5.1 doesn't use channel start for resume */ - start_channel = endpoint->ipa->version != IPA_VERSION_3_5_1; + /* Starting with IPA v4.0, the underlying GSI channel must be + * restarted for resume. + */ + start_channel = endpoint->ipa->version >= IPA_VERSION_4_0; ret = gsi_channel_resume(gsi, endpoint->channel_id, start_channel); if (ret) dev_err(dev, "error %d resuming channel %u\n", ret, diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index 64b92dfdd3f5c..62d82d48aed69 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -227,8 +227,8 @@ static void ipa_hardware_config_comp(struct ipa *ipa) { u32 val; - /* Nothing to configure for IPA v3.5.1 */ - if (ipa->version == IPA_VERSION_3_5_1) + /* Nothing to configure prior to IPA v4.0 */ + if (ipa->version < IPA_VERSION_4_0) return; val = ioread32(ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET); @@ -388,7 +388,7 @@ static void ipa_hardware_config(struct ipa *ipa, const struct ipa_data *data) } /* Implement some hardware workarounds */ - if (version != IPA_VERSION_3_5_1 && version < IPA_VERSION_4_5) { + if (version >= IPA_VERSION_4_0 && version < IPA_VERSION_4_5) { /* Enable open global clocks (not needed for IPA v4.5) */ val = GLOBAL_FMASK; val |= GLOBAL_2X_CLK_FMASK; diff --git a/drivers/net/ipa/ipa_qmi.c b/drivers/net/ipa/ipa_qmi.c index af8666b89b375..7b833e92a0ac7 100644 --- a/drivers/net/ipa/ipa_qmi.c +++ b/drivers/net/ipa/ipa_qmi.c @@ -377,7 +377,7 @@ init_modem_driver_req(struct ipa_qmi *ipa_qmi) /* None of the stats fields are valid (IPA v4.0 and above) */ - if (ipa->version != IPA_VERSION_3_5_1) { + if (ipa->version >= IPA_VERSION_4_0) { mem = &ipa->mem[IPA_MEM_STATS_QUOTA_MODEM]; if (mem->size) { req.hw_stats_quota_base_addr_valid = 1; From patchwork Tue Mar 23 14:51:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 406902 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4523626jai; Tue, 23 Mar 2021 07:52:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyRUALo7Zvh4YYg/4PzcT9Ly/FDdyEmmjFUAZnt7HYpOUIKitche0hE+lyFNSZAj5qNGPX2 X-Received: by 2002:a17:906:4e57:: with SMTP id g23mr5284365ejw.47.1616511176181; Tue, 23 Mar 2021 07:52:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616511176; cv=none; d=google.com; s=arc-20160816; b=D1kGhzQeUsxo6iPDn6eA3hIyEsLMyanw4IDX7k8T5DJgosB/Lqe0iJ38/y+HyTCCKZ kGG9Fc7l36eLC7jFia+g82WOWo/GRruX+uhXX8xokNerp7k/XBHkF4W5yLJ40AFu7doe lx/HSCG7W4hVfqWpA9wAZMZM2WvBLgxRwuPb2NIbVe638Z9YLRvXy5LHmMyGMIViDkY0 OC2b/glRPRmDE9SFHqyc/R7Anl/11koy/zsPRdZv0TDNqF1sAV9XXAUv+GUzl5KDlKoj HUXwh3Ehi+CVATUxEnObSWzuQ6hF7Z1SRSBUIoCQiufZgNulQA4O3SrE0WEPunfTWiYc yLTA== ARC-Message-Signature: i=1; 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id o13sm8961147iob.17.2021.03.23.07.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 07:51:39 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: bjorn.andersson@linaro.org, evgreen@chromium.org, cpratapa@codeaurora.org, subashab@codeaurora.org, elder@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/6] net: ipa: update version definitions Date: Tue, 23 Mar 2021 09:51:28 -0500 Message-Id: <20210323145132.2291316-3-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210323145132.2291316-1-elder@linaro.org> References: <20210323145132.2291316-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add IPA version definitions for all IPA v3.x and v4.x. Fix the GSI version associated with IPA version 4.1. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_version.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.27.0 diff --git a/drivers/net/ipa/ipa_version.h b/drivers/net/ipa/ipa_version.h index 2944e2a890231..ec87b0824c307 100644 --- a/drivers/net/ipa/ipa_version.h +++ b/drivers/net/ipa/ipa_version.h @@ -14,11 +14,17 @@ * it where it's needed. */ enum ipa_version { - IPA_VERSION_3_5_1, /* GSI version 1.3.0 */ + IPA_VERSION_3_0, /* GSI version 1.0 */ + IPA_VERSION_3_1, /* GSI version 1.1 */ + IPA_VERSION_3_5, /* GSI version 1.2 */ + IPA_VERSION_3_5_1, /* GSI version 1.3 */ IPA_VERSION_4_0, /* GSI version 2.0 */ - IPA_VERSION_4_1, /* GSI version 2.1 */ + IPA_VERSION_4_1, /* GSI version 2.0 */ IPA_VERSION_4_2, /* GSI version 2.2 */ IPA_VERSION_4_5, /* GSI version 2.5 */ + IPA_VERSION_4_7, /* GSI version 2.7 */ + IPA_VERSION_4_9, /* GSI version 2.9 */ + IPA_VERSION_4_11, /* GSI version 2.11 (2.1.1) */ }; #endif /* _IPA_VERSION_H_ */ From patchwork Tue Mar 23 14:51:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 406903 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4523908jai; Tue, 23 Mar 2021 07:53:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzll/86rbaqYqyxm3utdAmVxveZO85RSsXb7YJd4BJEywKYLVttA/ms0PT9sXdjW2kAUJci X-Received: by 2002:a17:906:8308:: with SMTP id j8mr5118759ejx.339.1616511203304; Tue, 23 Mar 2021 07:53:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616511203; cv=none; d=google.com; s=arc-20160816; b=UWYR29bgpepU6P2ykiw0LkMFXlBh3ZEGHMnW+mtfTI0B11WzqHNz7/Nwl7hbW5tS2+ nMIDtE/x77FjGjSxIVoRuqXJdSsFdr7NuwJ4hO/u3NNtpRks9KhEs/4WPURYHQVyKdBg NvatpNk+qfOZHFgXgC5DZWkogJGzTkp+xP0H4ZRA/rBgKn+WD+sn4kvZdmlFfAmi7UX3 xuPgzAouZn7WVUv3P3DLLL4DgQwQU6wKl4bIKKu4+vvzC8EvW30lkBq7VNynriYM/lW8 3nbeFXj2JvcZwtRNt3Igd7I7CC4Ziv6JLMbNaRLDAH9igysskWuV7+KXxb+0fXfxRYiE OmgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qKrY3MtVV0SjI4PDoOYPSEatpvEs6DJpVc9j1EaE/t0=; b=sSfUYzRKjd+ZBSUn8NNF6mh2/PN9LnGMiOTPWxo+5Y2WxiSEZTTO5GlQcEobKX0yxC 1uDdC/0I+bY2TY4fd74CIruTs02ux0cIlzPL7DDIbChfcRyF36GTaV4KCy126j/WhSkf jQmCpu120jeqwuP338pd0F1wYanR689gPmgKtShXlJwP1bGfbMA8dI8UxVnAz1WQZh+M 4FEb5Z6kdbJWPOJsirzg2vGTmW4wyy/+LYfGFS8J1cHhHlvwU5piF07k/3tmgM/NWNw6 kBL6vtGMcGErcV8wPCvyCSbh6o4Ys5Pt7xxVzObPkBv6jdCdOJaYyza9W+JToKS/ftpe QCYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xr5F6b0j; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id o13sm8961147iob.17.2021.03.23.07.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 07:51:40 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: bjorn.andersson@linaro.org, evgreen@chromium.org, cpratapa@codeaurora.org, subashab@codeaurora.org, elder@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 3/6] net: ipa: define the ENDP_INIT_NAT register Date: Tue, 23 Mar 2021 09:51:29 -0500 Message-Id: <20210323145132.2291316-4-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210323145132.2291316-1-elder@linaro.org> References: <20210323145132.2291316-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Define the ENDP_INIT_NAT register for setting up the NAT configuration for an endpoint. We aren't using NAT at this time, so explicitly set the type to BYPASS for all endpoints. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_endpoint.c | 17 ++++++++++++++++- drivers/net/ipa/ipa_reg.h | 14 +++++++++++++- 2 files changed, 29 insertions(+), 2 deletions(-) -- 2.27.0 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 5f93bd60c7586..38e83cd467b52 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019-2020 Linaro Ltd. + * Copyright (C) 2019-2021 Linaro Ltd. */ #include @@ -468,6 +468,20 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint) iowrite32(val, endpoint->ipa->reg_virt + offset); } +static void ipa_endpoint_init_nat(struct ipa_endpoint *endpoint) +{ + u32 offset; + u32 val; + + if (!endpoint->toward_ipa) + return; + + offset = IPA_REG_ENDP_INIT_NAT_N_OFFSET(endpoint->endpoint_id); + val = u32_encode_bits(IPA_NAT_BYPASS, NAT_EN_FMASK); + + iowrite32(val, endpoint->ipa->reg_virt + offset); +} + /** * ipa_endpoint_init_hdr() - Initialize HDR endpoint configuration register * @endpoint: Endpoint pointer @@ -1488,6 +1502,7 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint) else (void)ipa_endpoint_program_suspend(endpoint, false); ipa_endpoint_init_cfg(endpoint); + ipa_endpoint_init_nat(endpoint); ipa_endpoint_init_hdr(endpoint); ipa_endpoint_init_hdr_ext(endpoint); ipa_endpoint_init_hdr_metadata_mask(endpoint); diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 36fe746575f6b..bba088e80cd1e 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2018-2020 Linaro Ltd. + * Copyright (C) 2018-2021 Linaro Ltd. */ #ifndef _IPA_REG_H_ #define _IPA_REG_H_ @@ -388,6 +388,18 @@ enum ipa_cs_offload_en { IPA_CS_OFFLOAD_DL = 0x2, }; +/* Valid only for TX (IPA consumer) endpoints */ +#define IPA_REG_ENDP_INIT_NAT_N_OFFSET(ep) \ + (0x0000080c + 0x0070 * (ep)) +#define NAT_EN_FMASK GENMASK(1, 0) + +/** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */ +enum ipa_nat_en { + IPA_NAT_BYPASS = 0x0, + IPA_NAT_SRC = 0x1, + IPA_NAT_DST = 0x2, +}; + #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ (0x00000810 + 0x0070 * (ep)) #define HDR_LEN_FMASK GENMASK(5, 0) From patchwork Tue Mar 23 14:51:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 406904 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4523925jai; Tue, 23 Mar 2021 07:53:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwz/Tpbjr6pqooDKC77D57DaslTiNJaKFKXol5Rz+26WfgYWCstxxWGz4qTFh026vdZVTVQ X-Received: by 2002:a17:906:82c5:: with SMTP id a5mr5447163ejy.232.1616511204301; Tue, 23 Mar 2021 07:53:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616511204; cv=none; d=google.com; s=arc-20160816; b=PChWglqrOQfxfJ/gi88P34fHsjuom5VaLucMo1hkIR+kzTiSUaWCWHysz0On4gUopl V/kkhBhwAJM7BRD2BlmgFoLMmDDu69N0ZTB2E+E6FWHibq7c82PIxu6dGy5r5PQEOR9s AP0M6nky7zQ//efIqLL8MiG9EbVY7jVf1YnyHfYJt+jmyEjRuIxdVUAYjINe1QMOkosN lhDfoZ7YzpW1N4Y7znmobBQXd3Vo23v6+8JnuurCWJv68+kXiJStfpi9YYq64dxwOCPQ ix9n2xQOUIAHTd6GIYXALOEkJisqPeKE/m7q4AUMNuAgQgQCIEt6x5IWHQqU3x1aNwvi pm9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=urnf0slLMOPXg7nga5dabZHaUvtoQMaa3zOQvFLPfpg=; b=wmJGrmZ77zJ09Y5CCvxg4af0N2wlcuh+Zou8/bkHT0fyiyGE1nSyzXvOIEsbIoJ0fX gm3b5cPv+cohLkgXj/bl7vxG8Uk5fUFpLAhhtIvlvLBSK8nD3h3jtS6edcSk+6ydNC1U mJyQh5oP9erJV3YtrJ1NXH6G0Bw9R3JnqS4wK+uGUcRZAa54BrPIkzTiwdv3wjj0Xncs sHMJUMfH5Xta2/tXZTUF+/O/7qUZINNFwv5hXOpTly5mA/sZ1TZygOtKssR1YanrAROS b6UxbQ0MGgxFa6MDhLHcSoKZmOVzxlsI0872XBRwBUopHEetwhp+XmGWpfgUDT4fRWDd 2qbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pfdUAefH; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id o13sm8961147iob.17.2021.03.23.07.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 07:51:41 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: bjorn.andersson@linaro.org, evgreen@chromium.org, cpratapa@codeaurora.org, subashab@codeaurora.org, elder@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/6] net: ipa: limit local processing context address Date: Tue, 23 Mar 2021 09:51:30 -0500 Message-Id: <20210323145132.2291316-5-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210323145132.2291316-1-elder@linaro.org> References: <20210323145132.2291316-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Not all of the bits of the LOCAL_PKT_PROC_CNTXT register are valid. Until IPA v4.5, there are 17 valid bits (though the bottom three must be zero). Starting with IPA v4.5, 18 bits are valid. Introduce proc_cntxt_base_addr_encoded() to encode the base address for use in the register using only the valid bits. Shorten the name of the register (omit "_BASE") to avoid the need to wrap the line in the one place it's used. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_mem.c | 6 ++++-- drivers/net/ipa/ipa_reg.h | 14 ++++++++++++-- 2 files changed, 16 insertions(+), 4 deletions(-) -- 2.27.0 diff --git a/drivers/net/ipa/ipa_mem.c b/drivers/net/ipa/ipa_mem.c index f25029b9ec857..32907dde5dc6a 100644 --- a/drivers/net/ipa/ipa_mem.c +++ b/drivers/net/ipa/ipa_mem.c @@ -61,6 +61,7 @@ int ipa_mem_setup(struct ipa *ipa) struct gsi_trans *trans; u32 offset; u16 size; + u32 val; /* Get a transaction to define the header memory region and to zero * the processing context and modem memory regions. @@ -89,8 +90,9 @@ int ipa_mem_setup(struct ipa *ipa) gsi_trans_commit_wait(trans); /* Tell the hardware where the processing context area is located */ - iowrite32(ipa->mem_offset + ipa->mem[IPA_MEM_MODEM_PROC_CTX].offset, - ipa->reg_virt + IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET); + offset = ipa->mem_offset + ipa->mem[IPA_MEM_MODEM_PROC_CTX].offset; + val = proc_cntxt_base_addr_encoded(ipa->version, offset); + iowrite32(val, ipa->reg_virt + IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET); return 0; } diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index bba088e80cd1e..cbfef27bbcf2c 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -217,8 +217,18 @@ static inline u32 ipa_reg_bcr_val(enum ipa_version version) return 0x00000000; } -/* The value of the next register must be a multiple of 8 */ -#define IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET 0x000001e8 +/* The value of the next register must be a multiple of 8 (bottom 3 bits 0) */ +#define IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET 0x000001e8 + +/* Encoded value for LOCAL_PKT_PROC_CNTXT register BASE_ADDR field */ +static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version, + u32 addr) +{ + if (version < IPA_VERSION_4_5) + return u32_encode_bits(addr, GENMASK(16, 0)); + + return u32_encode_bits(addr, GENMASK(17, 0)); +} /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec From patchwork Tue Mar 23 14:51:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 406905 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4524246jai; Tue, 23 Mar 2021 07:53:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyv+DCCwwM07YrVHC5yrBTDGGZxzlzzBgIKY16vQ5BDbElhbvNZBW/y7XczSRWpu8VozGax X-Received: by 2002:a17:907:33cd:: with SMTP id zk13mr5274739ejb.224.1616511230115; Tue, 23 Mar 2021 07:53:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616511230; cv=none; d=google.com; s=arc-20160816; b=E+XR5UOLA4e8o++O6mG7Nv2MlBxu4ETjp15QvfiK1aKrFyjlzm8enwzheUMTQ534uQ aS+mzIYnZVAfOfhYCg1frpWUGg1VOQgsPQbXWZLQukvPuvP83WF0PC0s5Ua4knMU65hj Gz6NZhmRvqLL5SNsB9zMS/8/J37VpC4H7AoS5ptj1JkBDneO+TPhdxSTzMAlXTlkAyiA zd9xNY9TfjVrrTLYk8MCNQ3P30eiDNdqS7ufawiZJrP43OMjJlARCpr5zIiRYqB/1xNk H3dxN5vs1ccovurI8FiKd6ODwm7/w+gIBtJ3A8hDTFEybpfaCJMkxdgdAA1c1z0mKjB2 57Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mz7860lZzk6VZ253Yqzghlj/rfYbeBGQaKOgyWdMwc4=; b=z+FD4yUIhh5AaYDMcfRwaA9xhKCIm5j+e0Ph9MagMIgBtMnoLCf4P47DAa9zt5zF7Z jcTF5KTP5j52QPJptLSmHL+Ym4Y9olqqhLQ2xPOiIWqI+matcpNwzirkB5JYJPs3aueM uj3qkGiLsfhg3D6o67PNjB/Nst1OFwK4lf8jwVoyc4uGonKkhCpW/V4QpMj1Y+KhLdI8 PzAytxnMrpIRW7fSyqNjZBPsQe4n3iLfrUHEv7IWI1tnyyDNFowDxsfeXH6+hK4pBRlM 0ndzrIfwWaiwmTHUsi1iFHurPx/FMvMWyEdjIn4TTwaIRGp8sTa5IxeqnPQj1hGTMIlc IwCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pCVav1dz; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id o13sm8961147iob.17.2021.03.23.07.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 07:51:42 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: bjorn.andersson@linaro.org, evgreen@chromium.org, cpratapa@codeaurora.org, subashab@codeaurora.org, elder@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 5/6] net: ipa: move ipa_aggr_granularity_val() Date: Tue, 23 Mar 2021 09:51:31 -0500 Message-Id: <20210323145132.2291316-6-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210323145132.2291316-1-elder@linaro.org> References: <20210323145132.2291316-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org We only use ipa_aggr_granularity_val() inside "ipa_main.c", so it doesn't really need to be defined in a header file. It makes some sense to be grouped with the register definitions, but it is unlike the other inline functions now defined in "ipa_reg.h". So move it into "ipa_main.c" where it's used. TIMER_FREQUENCY is used only by that function, so move that definition as well. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_main.c | 15 +++++++++++++++ drivers/net/ipa/ipa_reg.h | 12 ------------ 2 files changed, 15 insertions(+), 12 deletions(-) -- 2.27.0 diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index 62d82d48aed69..ba1bfc30210a3 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -287,6 +287,21 @@ ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data) iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_READS_OFFSET); } +/* The internal inactivity timer clock is used for the aggregation timer */ +#define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ + +/* Compute the value to use in the COUNTER_CFG register AGGR_GRANULARITY + * field to represent the given number of microseconds. The value is one + * less than the number of timer ticks in the requested period. 0 is not + * a valid granularity value. + */ +static u32 ipa_aggr_granularity_val(u32 usec) +{ + /* assert(usec != 0); */ + + return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1; +} + /* IPA uses unified Qtime starting at IPA v4.5, implementing various * timestamps and timers independent of the IPA core clock rate. The * Qtimer is based on a 56-bit timestamp incremented at each tick of diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index cbfef27bbcf2c..86fe2978e8102 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -237,18 +237,6 @@ static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version, #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) -/* The internal inactivity timer clock is used for the aggregation timer */ -#define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ - -/* Compute the value to use in the AGGR_GRANULARITY field representing the - * given number of microseconds. The value is one less than the number of - * timer ticks in the requested period. 0 not a valid granularity value. - */ -static inline u32 ipa_aggr_granularity_val(u32 usec) -{ - return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1; -} - /* The next register is not present for IPA v4.5 */ #define IPA_REG_TX_CFG_OFFSET 0x000001fc /* The first three fields are present for IPA v3.5.1 only */ From patchwork Tue Mar 23 14:51:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 406906 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4524282jai; Tue, 23 Mar 2021 07:53:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzJ5x9k7SAnBG9dJk5FMiKNYksrq672LdQSxX0XOWhjQ+Dyux929NrvJz5utKZpqeFpNnFI X-Received: by 2002:a17:906:358c:: with SMTP id o12mr5449001ejb.156.1616511233376; Tue, 23 Mar 2021 07:53:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616511233; cv=none; d=google.com; s=arc-20160816; b=RF9R5LVGWzgYbmi/U8jJ7hNaM5+fb6sZa8/KNyWqFmt88qiMGaPjYRXmivptP9YazE wjHS9qOu7VgZAFQasc1XRULwNDPmyipep/E2WTl54G7iAjb3egBsA8CApdW7BDRkZT5d 6adz1HtVvYji5QgUOL7CyDaJTmrThnW/dXDu9E+rtScmG7Uh8UTy0sExyIk3eq6Rtq0g qmtHzphUAcUQU0WfRYDXEvfFc46jgRweadMZr6ILZRwzsiuqoGat+Q0NmL/cGPdxq1Qm ijRB7YwFjROa2TcFlDdZQ2tB2NvsX2K1lajC+F7hclaoyLZbregxxMYku5WVXwtZq/mm N3hA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FQFA2QStDKmo1XhVZ4KOEMpN+hi3li+F67WfkjwPMWs=; b=XZQ1a4aukgJDuSIFVDWGVxPXvopTFM191Y82p68kuC/KxsYrQFaC3eaVNV7RsZICxb h/C8mE0lei7kVmwqrFgCWlxGhPuAMQwH4CdpOqFJBcAs3ONNoTyZ571i3ofi8xjicJnD XZc5S37y5sWENzwk+27mrPLBDGOQ6G4G5iUPvRYVq5cZY54nFUM2kg+6k5IorhXNtFtb Yt7sFPzvvO3nmz6CxUiNpUeE9ecrj/qnJNTS+kh6NBY6siuMR+Ssz8qA81py34DqIQXW 5pmeWN83kye9mdgv5NX03cwAZC9A1rHg6c7xa6c38WFlZvV/PYir3DWmF3aCNeX5BbOa 03wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zOGbG6kW; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id o13sm8961147iob.17.2021.03.23.07.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 07:51:43 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: bjorn.andersson@linaro.org, evgreen@chromium.org, cpratapa@codeaurora.org, subashab@codeaurora.org, elder@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 6/6] net: ipa: increase channels and events Date: Tue, 23 Mar 2021 09:51:32 -0500 Message-Id: <20210323145132.2291316-7-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210323145132.2291316-1-elder@linaro.org> References: <20210323145132.2291316-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Increase the maximum number of channels and event rings supported by the driver, to allow the maximum available on the SDX55. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.27.0 diff --git a/drivers/net/ipa/gsi.h b/drivers/net/ipa/gsi.h index efc980f96109e..d5996bdb20ef5 100644 --- a/drivers/net/ipa/gsi.h +++ b/drivers/net/ipa/gsi.h @@ -16,8 +16,8 @@ #include "ipa_version.h" /* Maximum number of channels and event rings supported by the driver */ -#define GSI_CHANNEL_COUNT_MAX 17 -#define GSI_EVT_RING_COUNT_MAX 13 +#define GSI_CHANNEL_COUNT_MAX 23 +#define GSI_EVT_RING_COUNT_MAX 20 /* Maximum TLV FIFO size for a channel; 64 here is arbitrary (and high) */ #define GSI_TLV_MAX 64