From patchwork Sat May 12 00:42:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135586 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1563639lji; Fri, 11 May 2018 17:43:48 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqASAEi09IrhkojFyb6gqQApxWzmsL/ljUWlk6NPfwQ8NTznMEORHKWQ2fZlKNCxC3ISgDN X-Received: by 2002:a37:6d4:: with SMTP id 203-v6mr216104qkg.325.1526085828405; Fri, 11 May 2018 17:43:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526085828; cv=none; d=google.com; s=arc-20160816; b=XXbTCd7/Qyw3+SeLUr7n/JwPH27AwtFlzXGr0F76pWDzUtLy+YCTPrff3G1E7Cmz5Z RdMWvleudz8/syPKbE61kiztbwX3Vbbxg6a8Vbg2T2zSnfoVeMR9FyVkIOnfrrVgSXrJ T1OQeqU3u2DGiQzWcfe5CWyYZjANMXKnlc2h8pvINMs0Jrqj0M0VZ3Zt2OudJBvaP0aZ dow0K4mjrf5uUZfpZEtTUMpbCRyH7hfg+LQW0IoV7rGkT1fYH4jC3DQiVpRbQDmj6Dwb kbrvgukyV1ctMbVrS/EpkbrSRgv/nJMYi35BD4CXXg6ftLgiSgSUdLODUjOLjQr2d/13 kY5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=gTm+bwNj3Vmeeh+y4VTHeITGzCj9TBpSwD1rhJ16Jh8=; b=dLfNZeskNySZ3eAeQkbcrmtzlNSgorKBEAozHilZgiIm4bKd/tgu5mRvTQdOK9OE9o XeVC+aICGgzO5WxxbFOZoohYQ/kyiXlIT1MYcETSHLpc2ci30P7UIczQG5B6zvQFcCZ9 5Wf0XRUtwsNBUh4WqunVqLHnTRRypfIk4hb6SAunZO7np1/VBqrUiwoH9FRaOVm2IYtb /9hfHIPO9OT2yJskmxLPSLUK+kCiZhaYm7sUWYp7wXgNCbN7YwrtM/DerkZOBbz9EoEz FWhsP4PKSq+B5P7vQsCL5hKFoLzrt+CFuTMPkBHJ1h5hjs8WGnGhUvRI7+2YxmZRnJ1e h2jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ig/YOY99; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:45 -0700 Message-Id: <20180512004311.9299-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v2 01/27] fpu/softfloat: int_to_float ensure r fully initialised X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée Reported by Coverity (CID1390635). We ensure this for uint_to_float later on so we might as well mirror that. Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8401b37bd4..b39c0c6fbb 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1525,7 +1525,7 @@ FLOAT_TO_UINT(64, 64) static FloatParts int_to_float(int64_t a, float_status *status) { - FloatParts r; + FloatParts r = {}; if (a == 0) { r.cls = float_class_zero; r.sign = false; From patchwork Sat May 12 00:42:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135589 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1566054lji; Fri, 11 May 2018 17:46:43 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrDqp1PYZUHYL1ZKWeW5vcWNZFFcvat6AtCj0CXKxbBf+mcBlCQRSU3wnn0fjd31av0OAvm X-Received: by 2002:ac8:2c49:: with SMTP id e9-v6mr272477qta.24.1526086003764; Fri, 11 May 2018 17:46:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086003; cv=none; d=google.com; s=arc-20160816; b=VJmU+eeKRLxnwANm/SuroL9r3OtGSGQYEl3aHzr2voSvYk4QOL8IB8OMLUcjEOZGcY r6MEJhMfDTn1BzrWJ7vUDhqrVF5odMjA1bUyGdWRijFJELp4KWzFnjzVz5WhNe7ZR0kU T0MOzlYoguzXM585QN8FzertoroA0M2Rsf+qzvDp6Rh+scfAAtxQio/4lQDFnepW/GFF LkCJpxYcwzvVYvUdbArRgdIP8B4KnsJHxGz/z/e1Uggbe1P+sVFEB2yC5sBc8drbV89S +O0bmlXyqB0KMnPAXuNGJNSuUmao9iNuMyEDSDKky5C7oqo7z266TTHCz4NiolQDD7OH io3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=KKM5+1s0S4RtYoVM9p3qzJTyULZIllGWLcjzz7/+Vb8=; b=pzB84gU25LpAXrFD94qbkuVHwa0ayIT07qaWSGxaj4El8ViBMY4qvCy9AqPlXIN/S9 tCXjUp1sidTE6i/+AdcFA7yJaEaf29gnn8IifU57F/ufi7iMdk07ERLukfB2/6k89Xdz w2mvEyarUS5TdwDPGaQF+s9i4jdJ+s4McPaUBqj9Rkju83QfMq4zYLPCNaADt8/J/N/3 CFm4ADuiOuog5nIv2faWzuFld2bgFPfREWsFWdfohlZNVKBLRTw07ERx1qhhXzjAlTDw yOPDx3cKvtwI2Hi560S5sZflKF40GxjSjHuDWpKu6Y7wyof+jyGhJctv5sEHijZPv7nB Q9Ww== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZzMWcyDJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:46 -0700 Message-Id: <20180512004311.9299-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v2 02/27] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell In float-to-integer conversion, if the floating point input converts exactly to the largest or smallest integer that fits in to the result type, this is not an overflow. In this situation we were producing the correct result value, but were incorrectly setting the Invalid flag. For example for Arm A64, "FCVTAS w0, d0" on an input of 0x41dfffffffc00000 should produce 0x7fffffff and set no flags. Fix the boundary case to take the right half of the if() statements. This fixes a regression from 2.11 introduced by the softfloat refactoring. Cc: qemu-stable@nongnu.org Fixes: ab52f973a50 Signed-off-by: Peter Maydell --- fpu/softfloat.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.0 Reviewed-by: Richard Henderson diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b39c0c6fbb..bc0f52fa54 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1368,14 +1368,14 @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode, r = UINT64_MAX; } if (p.sign) { - if (r < -(uint64_t) min) { + if (r <= -(uint64_t) min) { return -r; } else { s->float_exception_flags = orig_flags | float_flag_invalid; return min; } } else { - if (r < max) { + if (r <= max) { return r; } else { s->float_exception_flags = orig_flags | float_flag_invalid; From patchwork Sat May 12 00:42:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135588 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1563973lji; Fri, 11 May 2018 17:44:13 -0700 (PDT) X-Google-Smtp-Source: AB8JxZokyj13vWRXuMSs8qyAoSZ2k7Udb9hofrYuqghw4qTR7KMwcqUJ3/+t+r3dzjn+DNUAXtdt X-Received: by 2002:a37:b187:: with SMTP id a129-v6mr203364qkf.377.1526085853044; Fri, 11 May 2018 17:44:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526085853; cv=none; d=google.com; s=arc-20160816; b=LkttPTUOWfuEdLEuS3tIy67eNYFPkVA3c0p9D0QWOypgJ+1GshqHZPqgXtO1Ny83hx /GYPSOlQ3OqTW4Q/qHko6VmXP4YTTU6OwuzSX7gWRPT1hwsNe6dc+TQQIr0sUkZxeIGb sI9MMEMGa4hF5Lo/JiypvnGB5sorSkCvGQnIO5Ni2eAntRiGPRxwKV1/GkMWwQo9SvE4 fPq4bg+5u8w+VuaFFKzHUr/IqwZ8jVNMxZyzfxvqw1ll518FyWv3rkY230bn5yN7VJ/D GUl4hG0HBGoBKrGf70sjZy8DCmXmRaEHRecC6k4KKzAHR6u5Y9VJno27z43dgyMzSWx+ jFFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=olimn3ekHRDV+cAwPhqm4nCUN2El89E2UfOyxJwGVa8=; b=MvwkBpqnNIsP4ydmpchgoa84lPOEGp4LVPyacj4kIdIMMgIka3J2UyGBGsXnT5gXtG qDk70S59pBjyumB+G1i/PdP0X5xJd7DqrohHrH8o8dWEyv3jNofBo4rC/jE1qCHR4erZ WF5s2mWBxYe/r49p8h4hmgVNKn97OOCdwZ+iLz3YqYd6It7U6W7+Qqkr61ccoFWxRAZk 36lMe3hIfEe4sXayPddGucYF+t+IssVxLQ+oDJrlv2BOJe1kx3FYJf10gKaUcWMInZIQ 9Z6JgvwPN6AXen+0GhsB9Y+azzT9NmrP3BdEhfnKKh/Rpff4ZqGuIl+GPJgY1j22m0A+ IR7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FWApbiTJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:47 -0700 Message-Id: <20180512004311.9299-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v2 03/27] fpu/softfloat: Merge NO_SIGNALING_NANS definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the ifdef inside the relevant functions instead of duplicating the function declarations. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 100 +++++++++++++++---------------------- 1 file changed, 40 insertions(+), 60 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 27834af0de..58b05718c8 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -233,17 +233,6 @@ typedef struct { uint64_t high, low; } commonNaNT; -#ifdef NO_SIGNALING_NANS -int float16_is_quiet_nan(float16 a_, float_status *status) -{ - return float16_is_any_nan(a_); -} - -int float16_is_signaling_nan(float16 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the half-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -251,12 +240,16 @@ int float16_is_signaling_nan(float16 a_, float_status *status) int float16_is_quiet_nan(float16 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float16_is_any_nan(a_); +#else uint16_t a = float16_val(a_); if (status->snan_bit_is_one) { return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); } else { return ((a & ~0x8000) >= 0x7C80); } +#endif } /*---------------------------------------------------------------------------- @@ -266,14 +259,17 @@ int float16_is_quiet_nan(float16 a_, float_status *status) int float16_is_signaling_nan(float16 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint16_t a = float16_val(a_); if (status->snan_bit_is_one) { return ((a & ~0x8000) >= 0x7C80); } else { return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the half-precision floating point value `a' is a @@ -333,17 +329,6 @@ static float16 commonNaNToFloat16(commonNaNT a, float_status *status) } } -#ifdef NO_SIGNALING_NANS -int float32_is_quiet_nan(float32 a_, float_status *status) -{ - return float32_is_any_nan(a_); -} - -int float32_is_signaling_nan(float32 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -351,12 +336,16 @@ int float32_is_signaling_nan(float32 a_, float_status *status) int float32_is_quiet_nan(float32 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float32_is_any_nan(a_); +#else uint32_t a = float32_val(a_); if (status->snan_bit_is_one) { return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); } else { return ((uint32_t)(a << 1) >= 0xFF800000); } +#endif } /*---------------------------------------------------------------------------- @@ -366,14 +355,17 @@ int float32_is_quiet_nan(float32 a_, float_status *status) int float32_is_signaling_nan(float32 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint32_t a = float32_val(a_); if (status->snan_bit_is_one) { return ((uint32_t)(a << 1) >= 0xFF800000); } else { return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the single-precision floating point value `a' is a @@ -744,17 +736,6 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) } } -#ifdef NO_SIGNALING_NANS -int float64_is_quiet_nan(float64 a_, float_status *status) -{ - return float64_is_any_nan(a_); -} - -int float64_is_signaling_nan(float64 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -762,6 +743,9 @@ int float64_is_signaling_nan(float64 a_, float_status *status) int float64_is_quiet_nan(float64 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float64_is_any_nan(a_); +#else uint64_t a = float64_val(a_); if (status->snan_bit_is_one) { return (((a >> 51) & 0xFFF) == 0xFFE) @@ -769,6 +753,7 @@ int float64_is_quiet_nan(float64 a_, float_status *status) } else { return ((a << 1) >= 0xFFF0000000000000ULL); } +#endif } /*---------------------------------------------------------------------------- @@ -778,6 +763,9 @@ int float64_is_quiet_nan(float64 a_, float_status *status) int float64_is_signaling_nan(float64 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint64_t a = float64_val(a_); if (status->snan_bit_is_one) { return ((a << 1) >= 0xFFF0000000000000ULL); @@ -785,8 +773,8 @@ int float64_is_signaling_nan(float64 a_, float_status *status) return (((a >> 51) & 0xFFF) == 0xFFE) && (a & LIT64(0x0007FFFFFFFFFFFF)); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the double-precision floating point value `a' is a @@ -899,17 +887,6 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) } } -#ifdef NO_SIGNALING_NANS -int floatx80_is_quiet_nan(floatx80 a_, float_status *status) -{ - return floatx80_is_any_nan(a_); -} - -int floatx80_is_signaling_nan(floatx80 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the extended double-precision floating-point value `a' is a | quiet NaN; otherwise returns 0. This slightly differs from the same @@ -918,6 +895,9 @@ int floatx80_is_signaling_nan(floatx80 a_, float_status *status) int floatx80_is_quiet_nan(floatx80 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return floatx80_is_any_nan(a); +#else if (status->snan_bit_is_one) { uint64_t aLow; @@ -929,6 +909,7 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *status) return ((a.high & 0x7FFF) == 0x7FFF) && (LIT64(0x8000000000000000) <= ((uint64_t)(a.low << 1))); } +#endif } /*---------------------------------------------------------------------------- @@ -939,6 +920,9 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *status) int floatx80_is_signaling_nan(floatx80 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else if (status->snan_bit_is_one) { return ((a.high & 0x7FFF) == 0x7FFF) && ((a.low << 1) >= 0x8000000000000000ULL); @@ -950,8 +934,8 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) && (uint64_t)(aLow << 1) && (a.low == aLow); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the extended double-precision floating point value @@ -1060,17 +1044,6 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) } } -#ifdef NO_SIGNALING_NANS -int float128_is_quiet_nan(float128 a_, float_status *status) -{ - return float128_is_any_nan(a_); -} - -int float128_is_signaling_nan(float128 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -1078,6 +1051,9 @@ int float128_is_signaling_nan(float128 a_, float_status *status) int float128_is_quiet_nan(float128 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float128_is_any_nan(a); +#else if (status->snan_bit_is_one) { return (((a.high >> 47) & 0xFFFF) == 0xFFFE) && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); @@ -1085,6 +1061,7 @@ int float128_is_quiet_nan(float128 a, float_status *status) return ((a.high << 1) >= 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); } +#endif } /*---------------------------------------------------------------------------- @@ -1094,6 +1071,9 @@ int float128_is_quiet_nan(float128 a, float_status *status) int float128_is_signaling_nan(float128 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else if (status->snan_bit_is_one) { return ((a.high << 1) >= 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); @@ -1101,8 +1081,8 @@ int float128_is_signaling_nan(float128 a, float_status *status) return (((a.high >> 47) & 0xFFFF) == 0xFFFE) && (a.low || (a.high & LIT64(0x00007FFFFFFFFFFF))); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the quadruple-precision floating point value `a' is From patchwork Sat May 12 00:42:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135593 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1568833lji; Fri, 11 May 2018 17:50:25 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpGPPwBAbWrAuEa4f8gIvfrtvbEJN8uPiWyoAel6AEht5xMR9Td+C+zquOLop1GpLswnPV+ X-Received: by 2002:aed:3ac3:: with SMTP id o61-v6mr250945qte.335.1526086225559; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:48 -0700 Message-Id: <20180512004311.9299-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v2 04/27] fpu/softfloat: Split floatXX_silence_nan from floatXX_maybe_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The new function assumes that the input is an SNaN and does not double-check. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 174 +++++++++++++++++++++++++------------ include/fpu/softfloat.h | 5 ++ 2 files changed, 123 insertions(+), 56 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 58b05718c8..4fc9ea4ac0 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -271,22 +271,35 @@ int float16_is_signaling_nan(float16 a_, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the half-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float16 float16_silence_nan(float16 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return float16_default_nan(status); + } else { + return a | (1 << 9); + } +#endif +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN if the half-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *----------------------------------------------------------------------------*/ -float16 float16_maybe_silence_nan(float16 a_, float_status *status) + +float16 float16_maybe_silence_nan(float16 a, float_status *status) { - if (float16_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { - return float16_default_nan(status); - } else { - uint16_t a = float16_val(a_); - a |= (1 << 9); - return make_float16(a); - } + if (float16_is_signaling_nan(a, status)) { + return float16_silence_nan(a, status); } - return a_; + return a; } /*---------------------------------------------------------------------------- @@ -367,30 +380,40 @@ int float32_is_signaling_nan(float32 a_, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the single-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float32 float32_silence_nan(float32 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { +# ifdef TARGET_HPPA + a &= ~0x00400000; + a |= 0x00200000; + return a; +# else + return float32_default_nan(status); +# endif + } else { + return a | (1 << 22); + } +#endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the single-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *----------------------------------------------------------------------------*/ -float32 float32_maybe_silence_nan(float32 a_, float_status *status) +float32 float32_maybe_silence_nan(float32 a, float_status *status) { - if (float32_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { -#ifdef TARGET_HPPA - uint32_t a = float32_val(a_); - a &= ~0x00400000; - a |= 0x00200000; - return make_float32(a); -#else - return float32_default_nan(status); -#endif - } else { - uint32_t a = float32_val(a_); - a |= (1 << 22); - return make_float32(a); - } + if (float32_is_signaling_nan(a, status)) { + return float32_silence_nan(a, status); } - return a_; + return a; } /*---------------------------------------------------------------------------- @@ -776,30 +799,41 @@ int float64_is_signaling_nan(float64 a_, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the double-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float64 float64_silence_nan(float64 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { +# ifdef TARGET_HPPA + a &= ~0x0008000000000000ULL; + a |= 0x0004000000000000ULL; + return a; +# else + return float64_default_nan(status); +# endif + } else { + return a | LIT64(0x0008000000000000); + } +#endif +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN if the double-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *----------------------------------------------------------------------------*/ -float64 float64_maybe_silence_nan(float64 a_, float_status *status) +float64 float64_maybe_silence_nan(float64 a, float_status *status) { - if (float64_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { -#ifdef TARGET_HPPA - uint64_t a = float64_val(a_); - a &= ~0x0008000000000000ULL; - a |= 0x0004000000000000ULL; - return make_float64(a); -#else - return float64_default_nan(status); -#endif - } else { - uint64_t a = float64_val(a_); - a |= LIT64(0x0008000000000000); - return make_float64(a); - } + if (float64_is_signaling_nan(a, status)) { + return float64_silence_nan(a, status); } - return a_; + return a; } /*---------------------------------------------------------------------------- @@ -937,6 +971,25 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the extended double-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +floatx80 floatx80_silence_nan(floatx80 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return floatx80_default_nan(status); + } else { + a.low |= LIT64(0xC000000000000000); + return a; + } +#endif +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN if the extended double-precision floating point value | `a' is a signaling NaN; otherwise returns `a'. @@ -945,12 +998,7 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status) { if (floatx80_is_signaling_nan(a, status)) { - if (status->snan_bit_is_one) { - a = floatx80_default_nan(status); - } else { - a.low |= LIT64(0xC000000000000000); - return a; - } + return floatx80_silence_nan(a, status); } return a; } @@ -1084,6 +1132,25 @@ int float128_is_signaling_nan(float128 a, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the quadruple-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float128 float128_silence_nan(float128 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return float128_default_nan(status); + } else { + a.high |= LIT64(0x0000800000000000); + return a; + } +#endif +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN if the quadruple-precision floating point value `a' is | a signaling NaN; otherwise returns `a'. @@ -1092,12 +1159,7 @@ int float128_is_signaling_nan(float128 a, float_status *status) float128 float128_maybe_silence_nan(float128 a, float_status *status) { if (float128_is_signaling_nan(a, status)) { - if (status->snan_bit_is_one) { - a = float128_default_nan(status); - } else { - a.high |= LIT64(0x0000800000000000); - return a; - } + return float128_silence_nan(a, status); } return a; } diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 36626a501b..43962dc3f5 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -257,6 +257,7 @@ int float16_compare_quiet(float16, float16, float_status *status); int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); +float16 float16_silence_nan(float16, float_status *status); float16 float16_maybe_silence_nan(float16, float_status *status); static inline int float16_is_any_nan(float16 a) @@ -368,6 +369,7 @@ float32 float32_minnummag(float32, float32, float_status *status); float32 float32_maxnummag(float32, float32, float_status *status); int float32_is_quiet_nan(float32, float_status *status); int float32_is_signaling_nan(float32, float_status *status); +float32 float32_silence_nan(float32, float_status *status); float32 float32_maybe_silence_nan(float32, float_status *status); float32 float32_scalbn(float32, int, float_status *status); @@ -497,6 +499,7 @@ float64 float64_minnummag(float64, float64, float_status *status); float64 float64_maxnummag(float64, float64, float_status *status); int float64_is_quiet_nan(float64 a, float_status *status); int float64_is_signaling_nan(float64, float_status *status); +float64 float64_silence_nan(float64, float_status *status); float64 float64_maybe_silence_nan(float64, float_status *status); float64 float64_scalbn(float64, int, float_status *status); @@ -600,6 +603,7 @@ int floatx80_compare(floatx80, floatx80, float_status *status); int floatx80_compare_quiet(floatx80, floatx80, float_status *status); int floatx80_is_quiet_nan(floatx80, float_status *status); int floatx80_is_signaling_nan(floatx80, float_status *status); +floatx80 floatx80_silence_nan(floatx80, float_status *status); floatx80 floatx80_maybe_silence_nan(floatx80, float_status *status); floatx80 floatx80_scalbn(floatx80, int, float_status *status); @@ -811,6 +815,7 @@ int float128_compare(float128, float128, float_status *status); int float128_compare_quiet(float128, float128, float_status *status); int float128_is_quiet_nan(float128, float_status *status); int float128_is_signaling_nan(float128, float_status *status); +float128 float128_silence_nan(float128, float_status *status); float128 float128_maybe_silence_nan(float128, float_status *status); float128 float128_scalbn(float128, int, float_status *status); From patchwork Sat May 12 00:42:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135594 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1570296lji; Fri, 11 May 2018 17:52:27 -0700 (PDT) X-Google-Smtp-Source: AB8JxZo8bhRgqEnOPrgNnOhThOdAhXlB+us4XK0qSlp6RzvmGc5HiE9RWcPSMJ1BDu0bZrVRyaCi X-Received: by 2002:a37:6dc7:: with SMTP id i190-v6mr253685qkc.114.1526086347044; Fri, 11 May 2018 17:52:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086347; cv=none; d=google.com; s=arc-20160816; b=AAX4otjms+uYOgoyvNZd4WjSe6h00CT8lqZoj23CRZMjflq0Sljz1lZP7b3951M3qA hr7tSt1EZJCy3h2Rp9iXUbRAiKFhyOIIu1eCJfmcHQ6rYp/7UYEzx1eq36AFzixc61n6 /viFI2TzHHtFD3SMxoUsjfvbb1mq0ImpXEebtfwKFnWLfIpSNPQwg8GJqFto7NOHkP5N HYwKSnG6lZZU8zLOciHg+zNXQ7UeDdaIKciE8M/PJ9Yg8YRpI2mzqlyWJMdwhD8YcjSt pOVacEe13f67Fuv9fiAsnQsiloWXJf5CSU3uLAQP+wW3ZljnU/bDzhdqH+apsA7u+Tbm HbHA== ARC-Message-Signature: i=1; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:49 -0700 Message-Id: <20180512004311.9299-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 05/27] fpu/softfloat: Move softfloat-specialize.h below FloatParts definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We want to be able to specialize on the canonical representation. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat.c b/fpu/softfloat.c index bc0f52fa54..353893aaea 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -95,16 +95,6 @@ this code that are retained. *----------------------------------------------------------------------------*/ #include "fpu/softfloat-macros.h" -/*---------------------------------------------------------------------------- -| Functions and definitions to determine: (1) whether tininess for underflow -| is detected before or after rounding by default, (2) what (if anything) -| happens when exceptions are raised, (3) how signaling NaNs are distinguished -| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs -| are propagated from function inputs to output. These details are target- -| specific. -*----------------------------------------------------------------------------*/ -#include "softfloat-specialize.h" - /*---------------------------------------------------------------------------- | Returns the fraction bits of the half-precision floating-point value `a'. *----------------------------------------------------------------------------*/ @@ -247,6 +237,16 @@ typedef struct { uint64_t roundeven_mask; } FloatFmt; +/*---------------------------------------------------------------------------- +| Functions and definitions to determine: (1) whether tininess for underflow +| is detected before or after rounding by default, (2) what (if anything) +| happens when exceptions are raised, (3) how signaling NaNs are distinguished +| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs +| are propagated from function inputs to output. These details are target- +| specific. +*----------------------------------------------------------------------------*/ +#include "softfloat-specialize.h" + /* Expand fields based on the size of exponent and fraction */ #define FLOAT_PARAMS(E, F) \ .exp_size = E, \ From patchwork Sat May 12 00:42:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135591 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1566438lji; Fri, 11 May 2018 17:47:16 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrHdSfrvPg+hLeop/gfavmWrtbC9SEZnGUCR48p1CiEWFC0iRcW3eCawYatVbzFaC8EHJvi X-Received: by 2002:a37:7f46:: with SMTP id a67-v6mr250047qkd.328.1526086036739; Fri, 11 May 2018 17:47:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086036; cv=none; d=google.com; s=arc-20160816; b=hFqZAFQyu1BBzGTkx1GqCB/73TlmAJjG/ZEs4UkBeaP05Oz5ePMiJWuHTi8DprQLmz IHjn0DHFZPtqAD/wdwAI22vrAk2YesyrA14j3eGZnkr5pnr0gnXGzKG+0OyRidiHIgYG 4VWVTwTHewB5bvmWkDficZR9B3QuxAQi92ceG9/452esOrdK9B5gnzhoGuQKGZJSIx8u W6v80W8l2Niyk5Wa4az35FxO8hUEiGepSS+ycEDrIYruGtOZqBU4GRKvmkXBXztZvOQY CYWQQhNQ6SfPrqiu+iEtN58LQGyuJy3lhnmtGBa2smBkFeAj/Y/lF775iR+9R3u/rtu8 6guQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=YDzpf8JdwZ0xAB5562vl+r2U0ux0aekXDL/EfP74jnQ=; b=KqRf1rINJrNoeF6fle+o4jfesJlHWHtVaP/Y97ZfYQmdMLuYa8ndmPy3fN8FrZqnbd dfeNzf58Mx3pe0fKd5U3yxbNlaA45dlzhaJLiV4qSUfQ3OeIIFNlH/dDRH9E01uPShbB AfM67L2/liG9rFSi00F3b0I1VqXMNFJU8saqD25DIgKF3uW2WalQq7Q7y3qlL4S/XHdc O0ao27hNz/kcD3UDMsqAe321+LFCLGNiQY6Bzy7hJFLK2SbNyumG2j3p5ijFgprC34H8 jlbluqIIP98DJix1D50TB4dciaKpfsHm+npTKvWDO2+Ko8x0958mAzJw734PeQOdwvlq dsNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BN4wHySX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:50 -0700 Message-Id: <20180512004311.9299-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v2 06/27] fpu/softfloat: Canonicalize NaN fraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Shift the NaN fraction to a canonical position, much like we do for the fraction of normal numbers. Immediately, this simplifies the float-to-float conversion. Later, this will facilitate manipulation of NaNs within the shared code paths. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.17.0 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 353893aaea..a56d3d975b 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -330,10 +330,11 @@ static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, if (part.frac == 0) { part.cls = float_class_inf; } else { + part.frac <<= parm->frac_shift; #ifdef NO_SIGNALING_NANS part.cls = float_class_qnan; #else - int64_t msb = part.frac << (parm->frac_shift + 2); + int64_t msb = part.frac << 2; if ((msb < 0) == status->snan_bit_is_one) { part.cls = float_class_snan; } else { @@ -480,6 +481,7 @@ static FloatParts round_canonical(FloatParts p, float_status *s, case float_class_qnan: case float_class_snan: exp = exp_max; + frac >>= parm->frac_shift; break; default: @@ -503,6 +505,7 @@ static float16 float16_round_pack_canonical(FloatParts p, float_status *s) case float_class_dnan: return float16_default_nan(s); case float_class_msnan: + p.frac >>= float16_params.frac_shift; return float16_maybe_silence_nan(float16_pack_raw(p), s); default: p = round_canonical(p, s, &float16_params); @@ -521,6 +524,7 @@ static float32 float32_round_pack_canonical(FloatParts p, float_status *s) case float_class_dnan: return float32_default_nan(s); case float_class_msnan: + p.frac >>= float32_params.frac_shift; return float32_maybe_silence_nan(float32_pack_raw(p), s); default: p = round_canonical(p, s, &float32_params); @@ -539,6 +543,7 @@ static float64 float64_round_pack_canonical(FloatParts p, float_status *s) case float_class_dnan: return float64_default_nan(s); case float_class_msnan: + p.frac >>= float64_params.frac_shift; return float64_maybe_silence_nan(float64_pack_raw(p), s); default: p = round_canonical(p, s, &float64_params); From patchwork Sat May 12 00:42:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135597 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1571017lji; Fri, 11 May 2018 17:53:27 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpU8+/icMoxKCpLDJE2XWWfYOqbLXVNYcPx19aySSuVPlvmu29BaPH47MWd2MChFHyTyc+d X-Received: by 2002:a37:d15c:: with SMTP id s89-v6mr270977qki.132.1526086407421; Fri, 11 May 2018 17:53:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086407; cv=none; d=google.com; s=arc-20160816; b=B0uWO1PN4mIauKpuWA1D0AT/ztgLUGuHf2nEYCmg+JkFQgEm4Inzrd7uZkjaTjT/fh NA+9yBSPYAr8pSKR7uQU/L9Zj3+haCHEu5HQNP/qi7LPQH3NjrDYN61MjVo0i9Ja85TZ oCnL9UO9r/I9DmMqlONhEBwivvPCburjBaSksck9JST2Zlvtwl+IiTWzAULgmAczhi/X BgoigmdABt5Qy7pGYNC6bonxJUoDJJegi+Ly+mlxmssr5Okwf9R0knmXg1j+m7nCs0wp YuaWcgJWaTvw54uPimrwsmJACDVCMoIPF2Av8idkZ2nCWggbCawbIbChbl1jVWVp9mYT +bkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=rvlR+Ql7MEYt3TgPxBAN9LiqLt4J1geWtV6fjJYwD6Q=; b=KABHGXhJwZp2aZJwUpFBqOW3FdSs7p0ThjnW82uEpwJoSoT+IwNhnLwvWQwDyTZYVs KHje+moTB1/2be4wpsa8YPUyUx51je1usd5HJ/BBg88uxAnQ12u0/o3cRUrirlck1vPJ 1rtWUNHbG09ctGf6AR47d5AmK7bsZ31n6sL8dVqO6ICTuqmLc89XHU9KDZgf7+vdXBE4 x4FrrQVT5Vo8N9h9taEH5Hbk/9KbIqpz4SyjrrRChJX4NUdvu3nwa4xb32TjekBbKtDx S/Ao6bX0QSIKtZBoN/4SoETBI50L0xBTYsAVYirJ3y6pKaZi1pMCSrFolkxtNt77zk6m lNqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KNOHSlTo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:51 -0700 Message-Id: <20180512004311.9299-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v2 07/27] fpu/softfloat: Introduce parts_is_snan_frac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 15 +++++++++++++++ fpu/softfloat.c | 12 ++---------- 2 files changed, 17 insertions(+), 10 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 4fc9ea4ac0..515cb12cfa 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -86,6 +86,21 @@ this code that are retained. #define NO_SIGNALING_NANS 1 #endif +/*---------------------------------------------------------------------------- +| For the deconstructed floating-point with fraction FRAC, return true +| if the fraction represents a signalling NaN; otherwise false. +*----------------------------------------------------------------------------*/ + +static bool parts_is_snan_frac(uint64_t frac, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return false; +#else + flag msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); + return msb == status->snan_bit_is_one; +#endif +} + /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index a56d3d975b..cb68f2eb20 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -331,16 +331,8 @@ static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, part.cls = float_class_inf; } else { part.frac <<= parm->frac_shift; -#ifdef NO_SIGNALING_NANS - part.cls = float_class_qnan; -#else - int64_t msb = part.frac << 2; - if ((msb < 0) == status->snan_bit_is_one) { - part.cls = float_class_snan; - } else { - part.cls = float_class_qnan; - } -#endif + part.cls = (parts_is_snan_frac(part.frac, status) + ? float_class_snan : float_class_qnan); } } else if (part.exp == 0) { if (likely(part.frac == 0)) { From patchwork Sat May 12 00:42:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135590 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1566376lji; Fri, 11 May 2018 17:47:11 -0700 (PDT) X-Google-Smtp-Source: AB8JxZruiGK4oSZ9a+qeDbV/T7KLodSyE5YTRnaDFqZ3cGwufpuX6TsaMsKmoJCzmQkhUQ5YK4aV X-Received: by 2002:a37:c081:: with SMTP id v1-v6mr246174qkv.176.1526086031746; Fri, 11 May 2018 17:47:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086031; cv=none; d=google.com; s=arc-20160816; b=hv0H/hs/oa8sm4DecEddNh18Wzw0ed12HoAD6T4nITjVZqVDbLIZs+DscCv2eADvIn XeN+kBpzFNjHltYTeqPFZgjkMN86NasdwXXV7g37M4D2l7VDml7T98SFMAw2d+Pn/vx4 7bPO1MfKdorGwz9GwLx7XzBOhmrnA4ofpwd3XLt82L79lA/luF5ua+ptGwCHvWtjZmL5 Q4QebX66poVRBOi20cioM48xLxC4XhbdgKC36PzmNKs7i/ZPZOjlbH/gtwxx4UDgzSdW ZrvF1/jpMiZfe8G2s4So04Vg8XEkyXMaG2u88DMjBqG8KbL96XndBEcMYlxMN2LIHHaW G00A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=/V/ku6SmT7UDnjk0P7hS1ShPNhtIhUSO+Jw3IebMoWQ=; b=XEO3AgQYLRykgiVK/phXTwhYibW7ksszHeIBHqeImc64owtP9dMCUsedTg2lrggc+g IZs5l4m5ScGaLpMwrtDf7MCeAHbj/j6bE1RQxG0XKyFobAt1fVcaj+8KifhtCHOK0q8F aVGZ+f9AiV4YPes+vJc8HxkYv10CeCmja3kimZuXXXxIMzlwo623r1go2D+iUS3zX4F+ uZEJRRw8R9sTkFUTDlf0zKxXUnNUzrzNuCoa5eApgPVKrPM+1EqaJGFPjbtY/1BG/zbx peTb1vzuUVmk0SXvMizDXW+LN8eM3zJEA0rksnmDsPe8CWbZvZY4VIM4yHFB19bYyzV0 aUwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LHyOv8UY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o15-v6si3782332qta.339.2018.05.11.17.47.11 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 11 May 2018 17:47:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LHyOv8UY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59107 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fHIgp-0008E5-6O for patch@linaro.org; Fri, 11 May 2018 20:47:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33353) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fHIdE-0004O6-II for qemu-devel@nongnu.org; Fri, 11 May 2018 20:43:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fHIdD-0002rp-Bi for qemu-devel@nongnu.org; Fri, 11 May 2018 20:43:28 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:44967) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fHIdD-0002rY-3v for qemu-devel@nongnu.org; Fri, 11 May 2018 20:43:27 -0400 Received: by mail-pf0-x244.google.com with SMTP id q22-v6so3430880pff.11 for ; Fri, 11 May 2018 17:43:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/V/ku6SmT7UDnjk0P7hS1ShPNhtIhUSO+Jw3IebMoWQ=; b=LHyOv8UYJ57cIkCqC1PjTjZREz5YE75rTOkL0aGC/FSsiaax7CBFPd9tyk62x+3zwL TmlLVq7YmGqStqXkSbA2fHE5W5pLATOLKqdHx+4PNPs2OjF2kfgJtMKS06Pf1nAM+n9D +reVcQG8unJ3zuayd3uvEna1xNPL5zXLbOU9A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/V/ku6SmT7UDnjk0P7hS1ShPNhtIhUSO+Jw3IebMoWQ=; b=pPQQ2d9DNRVWu8AsWIKWOVGoJqQ2b1AIrRxBta6pkj6nGngKbEw6LpvL21du2kwp3H KVE/foMZPCgTeEM8AE1LBXRIJUT1NFvtvq7KC4mvavXr2u7Ajtx17/jxcIpN/9PMJ4t6 slSzG01UEj6clMLfWMflm0fxBHZulVd+qfNgc31vHAvAft1Pe4ILqZ0hzY+FdG3DvrVY u4kb2UibmBo5tDQyFqQFIFFOnlMivAV8EUUWz8RnJd1Fq42oivm6E5sA/w7V+Edg7wWk 6MKjQI+YFRvPzJ2xtg2QLmi09W1C4ziyvKrFJdQnIrsw7D2sE8rnb+r8IHCU4ePHz3oY eSOQ== X-Gm-Message-State: ALKqPwcNuKodCtxXqVgxcM6ft7caHkDQA+c1Vep2BXrH14trUF70gJiD 1dNGIY08Mdvcr6QMCMx1t8iToA0Uk30= X-Received: by 2002:a62:d905:: with SMTP id s5-v6mr1015028pfg.20.1526085805795; Fri, 11 May 2018 17:43:25 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:52 -0700 Message-Id: <20180512004311.9299-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v2 08/27] fpu/softfloat: Replace float_class_dnan with parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With a canonical representation of NaNs, we can return the default nan directly rather than delay the expansion until the final format is known. Note one case where we uselessly assigned to a.sign, which was overwritten/ignored later when expanding float_class_dnan. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 37 +++++++++++++++++++++++++++++++++++++ fpu/softfloat.c | 38 +++++++++++--------------------------- 2 files changed, 48 insertions(+), 27 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 515cb12cfa..0d3d81a52b 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -101,6 +101,43 @@ static bool parts_is_snan_frac(uint64_t frac, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| The pattern for a default generated deconstructed floating-point NaN. +*----------------------------------------------------------------------------*/ + +static FloatParts parts_default_nan(float_status *status) +{ + bool sign = 0; + uint64_t frac; + +#if defined(TARGET_SPARC) || defined(TARGET_M68K) + frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ + defined(TARGET_S390X) || defined(TARGET_RISCV) + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#elif defined(TARGET_HPPA) + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (status->snan_bit_is_one) { + frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; + } else { +#if defined(TARGET_MIPS) + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#else + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); + sign = 1; +#endif + } +#endif + + return (FloatParts) { + .cls = float_class_qnan, + .sign = sign, + .exp = INT_MAX, + .frac = frac + }; +} + /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index cb68f2eb20..d16b11a85b 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -188,7 +188,6 @@ typedef enum __attribute__ ((__packed__)) { float_class_inf, float_class_qnan, /* all NaNs from here */ float_class_snan, - float_class_dnan, float_class_msnan, /* maybe silenced */ } FloatClass; @@ -494,8 +493,6 @@ static FloatParts float16_unpack_canonical(float16 f, float_status *s) static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float16_default_nan(s); case float_class_msnan: p.frac >>= float16_params.frac_shift; return float16_maybe_silence_nan(float16_pack_raw(p), s); @@ -513,8 +510,6 @@ static FloatParts float32_unpack_canonical(float32 f, float_status *s) static float32 float32_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float32_default_nan(s); case float_class_msnan: p.frac >>= float32_params.frac_shift; return float32_maybe_silence_nan(float32_pack_raw(p), s); @@ -532,8 +527,6 @@ static FloatParts float64_unpack_canonical(float64 f, float_status *s) static float64 float64_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float64_default_nan(s); case float_class_msnan: p.frac >>= float64_params.frac_shift; return float64_maybe_silence_nan(float64_pack_raw(p), s); @@ -566,7 +559,7 @@ static FloatParts return_nan(FloatParts a, float_status *s) /* fall through */ case float_class_qnan: if (s->default_nan_mode) { - a.cls = float_class_dnan; + return parts_default_nan(s); } break; @@ -583,7 +576,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) } if (s->default_nan_mode) { - a.cls = float_class_dnan; + return parts_default_nan(s); } else { if (pickNaN(is_qnan(a.cls), is_snan(a.cls), is_qnan(b.cls), is_snan(b.cls), @@ -614,8 +607,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, /* Note that this check is after pickNaNMulAdd so that function * has an opportunity to set the Invalid flag. */ - a.cls = float_class_dnan; - return a; + which = 3; } switch (which) { @@ -628,8 +620,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, a = c; break; case 3: - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); default: g_assert_not_reached(); } @@ -682,7 +673,7 @@ static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract, if (a.cls == float_class_inf) { if (b.cls == float_class_inf) { float_raise(float_flag_invalid, s); - a.cls = float_class_dnan; + return parts_default_nan(s); } return a; } @@ -828,9 +819,7 @@ static FloatParts mul_floats(FloatParts a, FloatParts b, float_status *s) if ((a.cls == float_class_inf && b.cls == float_class_zero) || (a.cls == float_class_zero && b.cls == float_class_inf)) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; - a.sign = sign; - return a; + return parts_default_nan(s); } /* Multiply by 0 or Inf */ if (a.cls == float_class_inf || a.cls == float_class_zero) { @@ -908,8 +897,7 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, if (inf_zero) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); } if (flags & float_muladd_negate_c) { @@ -933,12 +921,12 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, if (c.cls == float_class_inf) { if (p_class == float_class_inf && p_sign != c.sign) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; + return parts_default_nan(s); } else { a.cls = float_class_inf; a.sign = c.sign ^ sign_flip; + return a; } - return a; } if (p_class == float_class_inf) { @@ -1148,8 +1136,7 @@ static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s) && (a.cls == float_class_inf || a.cls == float_class_zero)) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); } /* Inf / x or 0 / x */ if (a.cls == float_class_inf || a.cls == float_class_zero) { @@ -1347,7 +1334,6 @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags = orig_flags | float_flag_invalid; return max; @@ -1439,7 +1425,6 @@ static uint64_t round_to_uint_and_pack(FloatParts in, int rmode, uint64_t max, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags = orig_flags | float_flag_invalid; return max; @@ -1940,8 +1925,7 @@ static FloatParts sqrt_float(FloatParts a, float_status *s, const FloatFmt *p) } if (a.sign) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); } if (a.cls == float_class_inf) { return a; /* sqrt(+inf) = +inf */ From patchwork Sat May 12 00:42:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135602 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1573874lji; Fri, 11 May 2018 17:57:48 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqvdPCMAGFu+6FKq2AgOm2v87J5AvESPiJKGd68GFl6+gGQ3++l7LpfF3ev69jL2GNbWyZb X-Received: by 2002:ac8:2f3b:: with SMTP id j56-v6mr288419qta.224.1526086668724; Fri, 11 May 2018 17:57:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086668; cv=none; d=google.com; s=arc-20160816; b=WErVmiXvDTSLLUm38JQrlvRGE401vNmbjSHQE0mXQoEY4cK3i9zrTHypKNmlzGzN2T 2g+HcXEHPO3X/hGJpuUlccgWJ34r5xB6R6cq8R+FQFLtA3wcxKHoSdxX3g8anTH9Q/RF +5CQk3L+T3FDcFlwDnWO9RSca1BYHPUAY1LepSXGQfoe4pgTeYffYIiJsShy+KPIFTW4 9ypS2+Z8zwMCiBUGu6cXQKIOU5x9vs3OCK6KUJOLY3UWmMwg/b5r6gsN1F1wBRKXB0UR EL46F1toqfm1+FGTPhNg1jT1Bjj+Sqz7j+FcApKloJbvjU2kHn762TXPGk9YapGyZzcE GWZw== ARC-Message-Signature: i=1; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:53 -0700 Message-Id: <20180512004311.9299-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2 09/27] fpu/softfloat: Replace float_class_msnan with parts_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With a canonical representation of NaNs, we can silence an SNaN immediately rather than delay until the final format is known. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 23 ++++++++++++++++++++++ fpu/softfloat.c | 40 ++++++++++---------------------------- 2 files changed, 33 insertions(+), 30 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 0d3d81a52b..571d1df378 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -138,6 +138,29 @@ static FloatParts parts_default_nan(float_status *status) }; } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the deconstructed +| floating-point parts. +*----------------------------------------------------------------------------*/ + +static FloatParts parts_silence_nan(FloatParts a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#elif defined(TARGET_HPPA) + a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); + a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (status->snan_bit_is_one) { + return parts_default_nan(status); + } else { + a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); + } +#endif + a.cls = float_class_qnan; + return a; +} + /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index d16b11a85b..c8f683963f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -188,7 +188,6 @@ typedef enum __attribute__ ((__packed__)) { float_class_inf, float_class_qnan, /* all NaNs from here */ float_class_snan, - float_class_msnan, /* maybe silenced */ } FloatClass; /* @@ -492,14 +491,7 @@ static FloatParts float16_unpack_canonical(float16 f, float_status *s) static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - p.frac >>= float16_params.frac_shift; - return float16_maybe_silence_nan(float16_pack_raw(p), s); - default: - p = round_canonical(p, s, &float16_params); - return float16_pack_raw(p); - } + return float16_pack_raw(round_canonical(p, s, &float16_params)); } static FloatParts float32_unpack_canonical(float32 f, float_status *s) @@ -509,14 +501,7 @@ static FloatParts float32_unpack_canonical(float32 f, float_status *s) static float32 float32_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - p.frac >>= float32_params.frac_shift; - return float32_maybe_silence_nan(float32_pack_raw(p), s); - default: - p = round_canonical(p, s, &float32_params); - return float32_pack_raw(p); - } + return float32_pack_raw(round_canonical(p, s, &float32_params)); } static FloatParts float64_unpack_canonical(float64 f, float_status *s) @@ -526,14 +511,7 @@ static FloatParts float64_unpack_canonical(float64 f, float_status *s) static float64 float64_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - p.frac >>= float64_params.frac_shift; - return float64_maybe_silence_nan(float64_pack_raw(p), s); - default: - p = round_canonical(p, s, &float64_params); - return float64_pack_raw(p); - } + return float64_pack_raw(round_canonical(p, s, &float64_params)); } /* Simple helpers for checking if what NaN we have */ @@ -555,7 +533,7 @@ static FloatParts return_nan(FloatParts a, float_status *s) switch (a.cls) { case float_class_snan: s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_msnan; + a = parts_silence_nan(a, s); /* fall through */ case float_class_qnan: if (s->default_nan_mode) { @@ -584,7 +562,9 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) (a.frac == b.frac && a.sign < b.sign))) { a = b; } - a.cls = float_class_msnan; + if (is_snan(a.cls)) { + return parts_silence_nan(a, s); + } } return a; } @@ -624,8 +604,10 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, default: g_assert_not_reached(); } - a.cls = float_class_msnan; + if (is_snan(a.cls)) { + return parts_silence_nan(a, s); + } return a; } @@ -1334,7 +1316,6 @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_msnan: s->float_exception_flags = orig_flags | float_flag_invalid; return max; case float_class_inf: @@ -1425,7 +1406,6 @@ static uint64_t round_to_uint_and_pack(FloatParts in, int rmode, uint64_t max, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_msnan: s->float_exception_flags = orig_flags | float_flag_invalid; return max; case float_class_inf: From patchwork Sat May 12 00:42:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135603 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1574080lji; Fri, 11 May 2018 17:58:12 -0700 (PDT) X-Google-Smtp-Source: AB8JxZryrkrw+7845QixNLpQVY9zAWsDA6eCDVFdWem5QmKRtNIuTB6QE9r03f+Hzc5gyqD5CcTK X-Received: by 2002:a37:5ac5:: with SMTP id o188-v6mr237645qkb.295.1526086692436; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:54 -0700 Message-Id: <20180512004311.9299-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH v2 10/27] fpu/softfloat: re-factor float to float conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée This allows us to delete a lot of additional boilerplate code which is no longer needed. Currently the ieee flag is ignored (everything is assumed to be ieee). Handling for ARM AHP will be in the next patch. Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- v2 - pass FloatFmt to float_to_float instead of sizes - split AHP handling to another patch - use rth's suggested re-packing (+ setting .exp) v3 - also rm extractFloat16Sign v4 - update for canonical nan handling --- fpu/softfloat-specialize.h | 40 ---- include/fpu/softfloat.h | 8 +- fpu/softfloat.c | 437 ++++++------------------------------- 3 files changed, 73 insertions(+), 412 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 571d1df378..995a0132c6 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -377,46 +377,6 @@ float16 float16_maybe_silence_nan(float16 a, float_status *status) return a; } -/*---------------------------------------------------------------------------- -| Returns the result of converting the half-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -static commonNaNT float16ToCommonNaN(float16 a, float_status *status) -{ - commonNaNT z; - - if (float16_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign = float16_val(a) >> 15; - z.low = 0; - z.high = ((uint64_t) float16_val(a)) << 54; - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the half- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -static float16 commonNaNToFloat16(commonNaNT a, float_status *status) -{ - uint16_t mantissa = a.high >> 54; - - if (status->default_nan_mode) { - return float16_default_nan(status); - } - - if (mantissa) { - return make_float16(((((uint16_t) a.sign) << 15) - | (0x1F << 10) | mantissa)); - } else { - return float16_default_nan(status); - } -} - /*---------------------------------------------------------------------------- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 43962dc3f5..a6860e858d 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -211,10 +211,10 @@ float128 uint64_to_float128(uint64_t, float_status *status); /*---------------------------------------------------------------------------- | Software half-precision conversion routines. *----------------------------------------------------------------------------*/ -float16 float32_to_float16(float32, flag, float_status *status); -float32 float16_to_float32(float16, flag, float_status *status); -float16 float64_to_float16(float64 a, flag ieee, float_status *status); -float64 float16_to_float64(float16 a, flag ieee, float_status *status); +float16 float32_to_float16(float32, bool ieee, float_status *status); +float32 float16_to_float32(float16, bool ieee, float_status *status); +float16 float64_to_float16(float64 a, bool ieee, float_status *status); +float64 float16_to_float64(float16 a, bool ieee, float_status *status); int16_t float16_to_int16(float16, float_status *status); uint16_t float16_to_uint16(float16 a, float_status *status); int16_t float16_to_int16_round_to_zero(float16, float_status *status); diff --git a/fpu/softfloat.c b/fpu/softfloat.c index c8f683963f..aa219223ff 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -113,15 +113,6 @@ static inline int extractFloat16Exp(float16 a) return (float16_val(a) >> 10) & 0x1f; } -/*---------------------------------------------------------------------------- -| Returns the sign bit of the single-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static inline flag extractFloat16Sign(float16 a) -{ - return float16_val(a)>>15; -} - /*---------------------------------------------------------------------------- | Returns the fraction bits of the single-precision floating-point value `a'. *----------------------------------------------------------------------------*/ @@ -1168,6 +1159,75 @@ float64 float64_div(float64 a, float64 b, float_status *status) return float64_round_pack_canonical(pr, status); } +/* + * Float to Float conversions + * + * Returns the result of converting one float format to another. The + * conversion is performed according to the IEC/IEEE Standard for + * Binary Floating-Point Arithmetic. + * + * The float_to_float helper only needs to take care of raising + * invalid exceptions and handling the conversion on NaNs. + */ + +static FloatParts float_to_float(FloatParts a, + const FloatFmt *srcf, const FloatFmt *dstf, + float_status *s) +{ + if (is_nan(a.cls)) { + if (is_snan(a.cls)) { + s->float_exception_flags |= float_flag_invalid; + a = parts_silence_nan(a, s); + } + if (s->default_nan_mode) { + return parts_default_nan(s); + } + } + return a; +} + +float32 float16_to_float32(float16 a, bool ieee, float_status *s) +{ + FloatParts p = float16_unpack_canonical(a, s); + FloatParts pr = float_to_float(p, &float16_params, &float32_params, s); + return float32_round_pack_canonical(pr, s); +} + +float64 float16_to_float64(float16 a, bool ieee, float_status *s) +{ + FloatParts p = float16_unpack_canonical(a, s); + FloatParts pr = float_to_float(p, &float16_params, &float64_params, s); + return float64_round_pack_canonical(pr, s); +} + +float16 float32_to_float16(float32 a, bool ieee, float_status *s) +{ + FloatParts p = float32_unpack_canonical(a, s); + FloatParts pr = float_to_float(p, &float32_params, &float16_params, s); + return float16_round_pack_canonical(pr, s); +} + +float64 float32_to_float64(float32 a, float_status *s) +{ + FloatParts p = float32_unpack_canonical(a, s); + FloatParts pr = float_to_float(p, &float32_params, &float64_params, s); + return float64_round_pack_canonical(pr, s); +} + +float16 float64_to_float16(float64 a, bool ieee, float_status *s) +{ + FloatParts p = float64_unpack_canonical(a, s); + FloatParts pr = float_to_float(p, &float64_params, &float16_params, s); + return float16_round_pack_canonical(pr, s); +} + +float32 float64_to_float32(float64 a, float_status *s) +{ + FloatParts p = float64_unpack_canonical(a, s); + FloatParts pr = float_to_float(p, &float64_params, &float32_params, s); + return float32_round_pack_canonical(pr, s); +} + /* * Rounds the floating-point value `a' to an integer, and returns the * result as a floating-point value. The operation is performed @@ -3111,41 +3171,6 @@ float128 uint64_to_float128(uint64_t a, float_status *status) return normalizeRoundAndPackFloat128(0, 0x406E, a, 0, status); } - - - -/*---------------------------------------------------------------------------- -| Returns the result of converting the single-precision floating-point value -| `a' to the double-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float32_to_float64(float32 a, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - a = float32_squash_input_denormal(a, status); - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - if ( aExp == 0xFF ) { - if (aSig) { - return commonNaNToFloat64(float32ToCommonNaN(a, status), status); - } - return packFloat64( aSign, 0x7FF, 0 ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat64( aSign, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - --aExp; - } - return packFloat64( aSign, aExp + 0x380, ( (uint64_t) aSig )<<29 ); - -} - /*---------------------------------------------------------------------------- | Returns the result of converting the single-precision floating-point value | `a' to the extended double-precision floating-point format. The conversion @@ -3664,173 +3689,6 @@ int float32_unordered_quiet(float32 a, float32 b, float_status *status) return 0; } - -/*---------------------------------------------------------------------------- -| Returns the result of converting the double-precision floating-point value -| `a' to the single-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float64_to_float32(float64 a, float_status *status) -{ - flag aSign; - int aExp; - uint64_t aSig; - uint32_t zSig; - a = float64_squash_input_denormal(a, status); - - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - if ( aExp == 0x7FF ) { - if (aSig) { - return commonNaNToFloat32(float64ToCommonNaN(a, status), status); - } - return packFloat32( aSign, 0xFF, 0 ); - } - shift64RightJamming( aSig, 22, &aSig ); - zSig = aSig; - if ( aExp || zSig ) { - zSig |= 0x40000000; - aExp -= 0x381; - } - return roundAndPackFloat32(aSign, aExp, zSig, status); - -} - - -/*---------------------------------------------------------------------------- -| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a -| half-precision floating-point value, returning the result. After being -| shifted into the proper positions, the three fields are simply added -| together to form the result. This means that any integer portion of `zSig' -| will be added into the exponent. Since a properly normalized significand -| will have an integer portion equal to 1, the `zExp' input should be 1 less -| than the desired result exponent whenever `zSig' is a complete, normalized -| significand. -*----------------------------------------------------------------------------*/ -static float16 packFloat16(flag zSign, int zExp, uint16_t zSig) -{ - return make_float16( - (((uint32_t)zSign) << 15) + (((uint32_t)zExp) << 10) + zSig); -} - -/*---------------------------------------------------------------------------- -| Takes an abstract floating-point value having sign `zSign', exponent `zExp', -| and significand `zSig', and returns the proper half-precision floating- -| point value corresponding to the abstract input. Ordinarily, the abstract -| value is simply rounded and packed into the half-precision format, with -| the inexact exception raised if the abstract input cannot be represented -| exactly. However, if the abstract value is too large, the overflow and -| inexact exceptions are raised and an infinity or maximal finite value is -| returned. If the abstract value is too small, the input value is rounded to -| a subnormal number, and the underflow and inexact exceptions are raised if -| the abstract input cannot be represented exactly as a subnormal half- -| precision floating-point number. -| The `ieee' flag indicates whether to use IEEE standard half precision, or -| ARM-style "alternative representation", which omits the NaN and Inf -| encodings in order to raise the maximum representable exponent by one. -| The input significand `zSig' has its binary point between bits 22 -| and 23, which is 13 bits to the left of the usual location. This shifted -| significand must be normalized or smaller. If `zSig' is not normalized, -| `zExp' must be 0; in that case, the result returned is a subnormal number, -| and it must not require rounding. In the usual case that `zSig' is -| normalized, `zExp' must be 1 less than the ``true'' floating-point exponent. -| Note the slightly odd position of the binary point in zSig compared with the -| other roundAndPackFloat functions. This should probably be fixed if we -| need to implement more float16 routines than just conversion. -| The handling of underflow and overflow follows the IEC/IEEE Standard for -| Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -static float16 roundAndPackFloat16(flag zSign, int zExp, - uint32_t zSig, flag ieee, - float_status *status) -{ - int maxexp = ieee ? 29 : 30; - uint32_t mask; - uint32_t increment; - bool rounding_bumps_exp; - bool is_tiny = false; - - /* Calculate the mask of bits of the mantissa which are not - * representable in half-precision and will be lost. - */ - if (zExp < 1) { - /* Will be denormal in halfprec */ - mask = 0x00ffffff; - if (zExp >= -11) { - mask >>= 11 + zExp; - } - } else { - /* Normal number in halfprec */ - mask = 0x00001fff; - } - - switch (status->float_rounding_mode) { - case float_round_nearest_even: - increment = (mask + 1) >> 1; - if ((zSig & mask) == increment) { - increment = zSig & (increment << 1); - } - break; - case float_round_ties_away: - increment = (mask + 1) >> 1; - break; - case float_round_up: - increment = zSign ? 0 : mask; - break; - case float_round_down: - increment = zSign ? mask : 0; - break; - default: /* round_to_zero */ - increment = 0; - break; - } - - rounding_bumps_exp = (zSig + increment >= 0x01000000); - - if (zExp > maxexp || (zExp == maxexp && rounding_bumps_exp)) { - if (ieee) { - float_raise(float_flag_overflow | float_flag_inexact, status); - return packFloat16(zSign, 0x1f, 0); - } else { - float_raise(float_flag_invalid, status); - return packFloat16(zSign, 0x1f, 0x3ff); - } - } - - if (zExp < 0) { - /* Note that flush-to-zero does not affect half-precision results */ - is_tiny = - (status->float_detect_tininess == float_tininess_before_rounding) - || (zExp < -1) - || (!rounding_bumps_exp); - } - if (zSig & mask) { - float_raise(float_flag_inexact, status); - if (is_tiny) { - float_raise(float_flag_underflow, status); - } - } - - zSig += increment; - if (rounding_bumps_exp) { - zSig >>= 1; - zExp++; - } - - if (zExp < -10) { - return packFloat16(zSign, 0, 0); - } - if (zExp < 0) { - zSig >>= -zExp; - zExp = 0; - } - return packFloat16(zSign, zExp, zSig >> 13); -} - /*---------------------------------------------------------------------------- | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the value. @@ -3846,163 +3704,6 @@ float16 float16_squash_input_denormal(float16 a, float_status *status) return a; } -static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr, - uint32_t *zSigPtr) -{ - int8_t shiftCount = countLeadingZeros32(aSig) - 21; - *zSigPtr = aSig << shiftCount; - *zExpPtr = 1 - shiftCount; -} - -/* Half precision floats come in two formats: standard IEEE and "ARM" format. - The latter gains extra exponent range by omitting the NaN/Inf encodings. */ - -float32 float16_to_float32(float16 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - - aSign = extractFloat16Sign(a); - aExp = extractFloat16Exp(a); - aSig = extractFloat16Frac(a); - - if (aExp == 0x1f && ieee) { - if (aSig) { - return commonNaNToFloat32(float16ToCommonNaN(a, status), status); - } - return packFloat32(aSign, 0xff, 0); - } - if (aExp == 0) { - if (aSig == 0) { - return packFloat32(aSign, 0, 0); - } - - normalizeFloat16Subnormal(aSig, &aExp, &aSig); - aExp--; - } - return packFloat32( aSign, aExp + 0x70, aSig << 13); -} - -float16 float32_to_float16(float32 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - - a = float32_squash_input_denormal(a, status); - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - if ( aExp == 0xFF ) { - if (aSig) { - /* Input is a NaN */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0, 0); - } - return commonNaNToFloat16( - float32ToCommonNaN(a, status), status); - } - /* Infinity */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0x1f, 0x3ff); - } - return packFloat16(aSign, 0x1f, 0); - } - if (aExp == 0 && aSig == 0) { - return packFloat16(aSign, 0, 0); - } - /* Decimal point between bits 22 and 23. Note that we add the 1 bit - * even if the input is denormal; however this is harmless because - * the largest possible single-precision denormal is still smaller - * than the smallest representable half-precision denormal, and so we - * will end up ignoring aSig and returning via the "always return zero" - * codepath. - */ - aSig |= 0x00800000; - aExp -= 0x71; - - return roundAndPackFloat16(aSign, aExp, aSig, ieee, status); -} - -float64 float16_to_float64(float16 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint32_t aSig; - - aSign = extractFloat16Sign(a); - aExp = extractFloat16Exp(a); - aSig = extractFloat16Frac(a); - - if (aExp == 0x1f && ieee) { - if (aSig) { - return commonNaNToFloat64( - float16ToCommonNaN(a, status), status); - } - return packFloat64(aSign, 0x7ff, 0); - } - if (aExp == 0) { - if (aSig == 0) { - return packFloat64(aSign, 0, 0); - } - - normalizeFloat16Subnormal(aSig, &aExp, &aSig); - aExp--; - } - return packFloat64(aSign, aExp + 0x3f0, ((uint64_t)aSig) << 42); -} - -float16 float64_to_float16(float64 a, flag ieee, float_status *status) -{ - flag aSign; - int aExp; - uint64_t aSig; - uint32_t zSig; - - a = float64_squash_input_denormal(a, status); - - aSig = extractFloat64Frac(a); - aExp = extractFloat64Exp(a); - aSign = extractFloat64Sign(a); - if (aExp == 0x7FF) { - if (aSig) { - /* Input is a NaN */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0, 0); - } - return commonNaNToFloat16( - float64ToCommonNaN(a, status), status); - } - /* Infinity */ - if (!ieee) { - float_raise(float_flag_invalid, status); - return packFloat16(aSign, 0x1f, 0x3ff); - } - return packFloat16(aSign, 0x1f, 0); - } - shift64RightJamming(aSig, 29, &aSig); - zSig = aSig; - if (aExp == 0 && zSig == 0) { - return packFloat16(aSign, 0, 0); - } - /* Decimal point between bits 22 and 23. Note that we add the 1 bit - * even if the input is denormal; however this is harmless because - * the largest possible single-precision denormal is still smaller - * than the smallest representable half-precision denormal, and so we - * will end up ignoring aSig and returning via the "always return zero" - * codepath. - */ - zSig |= 0x00800000; - aExp -= 0x3F1; - - return roundAndPackFloat16(aSign, aExp, zSig, ieee, status); -} - /*---------------------------------------------------------------------------- | Returns the result of converting the double-precision floating-point value | `a' to the extended double-precision floating-point format. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:55 -0700 Message-Id: <20180512004311.9299-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v2 11/27] fpu/softfloat: support ARM Alternative half-precision X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée For float16 ARM supports an alternative half-precision format which sacrifices the ability to represent NaN/Inf in return for a higher dynamic range. To support this I've added an additional FloatFmt (float16_params_ahp). The new FloatFmt flag (arm_althp) is then used to modify the behaviour of canonicalize and round_canonical with respect to representation and exception raising. Finally the float16_to_floatN and floatN_to_float16 conversion routines select the new alternative FloatFmt when !ieee. Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- v3 - squash NaN to 0 if destination is AHP F16 v4 - handle inf -> ahp max in float_to_float not round_canonical - assert no nan and inf for ahp in round_canonical - check ahp before snan in float_to_float --- fpu/softfloat.c | 95 +++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 81 insertions(+), 14 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index aa219223ff..15a272759d 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -211,8 +211,10 @@ typedef struct { * frac_shift: shift to normalise the fraction with DECOMPOSED_BINARY_POINT * The following are computed based the size of fraction * frac_lsb: least significant bit of fraction - * fram_lsbm1: the bit bellow the least significant bit (for rounding) + * frac_lsbm1: the bit bellow the least significant bit (for rounding) * round_mask/roundeven_mask: masks used for rounding + * The following optional modifiers are available: + * arm_althp: handle ARM Alternative Half Precision */ typedef struct { int exp_size; @@ -224,6 +226,7 @@ typedef struct { uint64_t frac_lsbm1; uint64_t round_mask; uint64_t roundeven_mask; + bool arm_althp; } FloatFmt; /*---------------------------------------------------------------------------- @@ -252,6 +255,11 @@ static const FloatFmt float16_params = { FLOAT_PARAMS(5, 10) }; +static const FloatFmt float16_params_ahp = { + FLOAT_PARAMS(5, 10), + .arm_althp = true +}; + static const FloatFmt float32_params = { FLOAT_PARAMS(8, 23) }; @@ -315,7 +323,7 @@ static inline float64 float64_pack_raw(FloatParts p) static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, float_status *status) { - if (part.exp == parm->exp_max) { + if (part.exp == parm->exp_max && !parm->arm_althp) { if (part.frac == 0) { part.cls = float_class_inf; } else { @@ -404,7 +412,15 @@ static FloatParts round_canonical(FloatParts p, float_status *s, } frac >>= frac_shift; - if (unlikely(exp >= exp_max)) { + if (parm->arm_althp) { + /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ + if (unlikely(exp > exp_max)) { + /* Overflow. Return the maximum normal. */ + flags = float_flag_invalid; + exp = exp_max; + frac = -1; + } + } else if (unlikely(exp >= exp_max)) { flags |= float_flag_overflow | float_flag_inexact; if (overflow_norm) { exp = exp_max - 1; @@ -455,12 +471,14 @@ static FloatParts round_canonical(FloatParts p, float_status *s, case float_class_inf: do_inf: + assert(!parm->arm_althp); exp = exp_max; frac = 0; break; case float_class_qnan: case float_class_snan: + assert(!parm->arm_althp); exp = exp_max; frac >>= parm->frac_shift; break; @@ -475,14 +493,27 @@ static FloatParts round_canonical(FloatParts p, float_status *s, return p; } +/* Explicit FloatFmt version */ +static FloatParts float16a_unpack_canonical(float16 f, float_status *s, + const FloatFmt *params) +{ + return canonicalize(float16_unpack_raw(f), params, s); +} + static FloatParts float16_unpack_canonical(float16 f, float_status *s) { - return canonicalize(float16_unpack_raw(f), &float16_params, s); + return float16a_unpack_canonical(f, s, &float16_params); +} + +static float16 float16a_round_pack_canonical(FloatParts p, float_status *s, + const FloatFmt *params) +{ + return float16_pack_raw(round_canonical(p, s, params)); } static float16 float16_round_pack_canonical(FloatParts p, float_status *s) { - return float16_pack_raw(round_canonical(p, s, &float16_params)); + return float16a_round_pack_canonical(p, s, &float16_params); } static FloatParts float32_unpack_canonical(float32 f, float_status *s) @@ -1174,7 +1205,33 @@ static FloatParts float_to_float(FloatParts a, const FloatFmt *srcf, const FloatFmt *dstf, float_status *s) { - if (is_nan(a.cls)) { + if (dstf->arm_althp) { + switch (a.cls) { + case float_class_qnan: + case float_class_snan: + /* There is no NaN in the destination format. Raise Invalid + * and return a zero with the sign of the input NaN. + */ + s->float_exception_flags |= float_flag_invalid; + a.cls = float_class_zero; + a.frac = 0; + a.exp = 0; + break; + + case float_class_inf: + /* There is no Inf in the destination format. Raise Invalid + * and return the maximum normal with the correct sign. + */ + s->float_exception_flags |= float_flag_invalid; + a.cls = float_class_normal; + a.exp = dstf->exp_max; + a.frac = ((1ull << dstf->frac_size) - 1) << dstf->frac_shift; + break; + + default: + break; + } + } else if (is_nan(a.cls)) { if (is_snan(a.cls)) { s->float_exception_flags |= float_flag_invalid; a = parts_silence_nan(a, s); @@ -1186,25 +1243,34 @@ static FloatParts float_to_float(FloatParts a, return a; } +/* + * Currently non-ieee implies ARM Alternative Half Precision handling + * for float16 values. If more are needed we'll need to expand the API + * into softfloat. + */ + float32 float16_to_float32(float16 a, bool ieee, float_status *s) { - FloatParts p = float16_unpack_canonical(a, s); - FloatParts pr = float_to_float(p, &float16_params, &float32_params, s); + const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; + FloatParts p = float16a_unpack_canonical(a, s, fmt16); + FloatParts pr = float_to_float(p, fmt16, &float32_params, s); return float32_round_pack_canonical(pr, s); } float64 float16_to_float64(float16 a, bool ieee, float_status *s) { - FloatParts p = float16_unpack_canonical(a, s); - FloatParts pr = float_to_float(p, &float16_params, &float64_params, s); + const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; + FloatParts p = float16a_unpack_canonical(a, s, fmt16); + FloatParts pr = float_to_float(p, fmt16, &float64_params, s); return float64_round_pack_canonical(pr, s); } float16 float32_to_float16(float32 a, bool ieee, float_status *s) { + const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; FloatParts p = float32_unpack_canonical(a, s); - FloatParts pr = float_to_float(p, &float32_params, &float16_params, s); - return float16_round_pack_canonical(pr, s); + FloatParts pr = float_to_float(p, &float32_params, fmt16, s); + return float16a_round_pack_canonical(pr, s, fmt16); } float64 float32_to_float64(float32 a, float_status *s) @@ -1216,9 +1282,10 @@ float64 float32_to_float64(float32 a, float_status *s) float16 float64_to_float16(float64 a, bool ieee, float_status *s) { + const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; FloatParts p = float64_unpack_canonical(a, s); - FloatParts pr = float_to_float(p, &float64_params, &float16_params, s); - return float16_round_pack_canonical(pr, s); + FloatParts pr = float_to_float(p, &float64_params, fmt16, s); + return float16a_round_pack_canonical(pr, s, fmt16); } float32 float64_to_float32(float64 a, float_status *s) From patchwork Sat May 12 00:42:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135592 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1568824lji; Fri, 11 May 2018 17:50:24 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrwbk9A5ISxgo4act86x8+ST39uxsw3vSssoDp68pfwFvebQy+J2ceejThHT9PA2fycI4fP X-Received: by 2002:ac8:316e:: with SMTP id h43-v6mr247357qtb.299.1526086224436; Fri, 11 May 2018 17:50:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086224; cv=none; d=google.com; s=arc-20160816; b=ftp5KDTuxKfPZRFYpuHPrdb5vEZlUG0KOUDf0Gd9jEpcq5DsFOi6WA5fjEWCdrWX8q uvSH6++IuTX7KBotYPxzaFTOu4T/nTjcPW89qUHPMZf/tkhYWZjQ08kkBGUnzdOWF5lU SghwGpzW7oNkIs7OS0KALfwOwKweTIHzyoSD8M5qg2s2+k1Pk5jLxvdKcfK/B9Tg/p9p Emqxbm/vnTPhfq+28+TJpCenoxRBLWkC5FhCrzv3PhUWe4pxBSTCXeCCcBVkyjFQtrNG fYyZj0LKZB5AjfMU17zoCWz2Yl158FabTNl5AkW7cBqdaR/4TDNYw7kZ2H8OKrVdc9Be 5ouA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=wHdlJfexyPx1KMaIXVXWmvRZE1xD2xfRVvH9LtyDBZQ=; b=MCjfeCefnB1n00/OS84FUVDeB5Vk1OSu6Dyh7IIMhHB7SlKigGjCW8s+9hl26feAyG a1HgMN+l6OQ5t6HrRZaEVuolzUF0CFdOWqg+Nfsj/Xv0M9/+l2j69gD+5Hd5wrO1f6eY KRUJjjoJrX8HsP3QRO/3Xa7cqcu4ewbNGd6zbVGI0cbfF6cnT0JRmanM+FsE0chDcAHW XiboM6egXpdl3JZBVXc8vS8okdtjL/9UvME8c+Fo3GMGvDcOfNkgO9PXvg8V86BPOJoC JNQdR0KmbHvq/hjKZQ/So4271Qre1auPu3WqbXSUrRET23/3qICC9rNbnYHRWP7NgT39 dFtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cj6tnqhh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:56 -0700 Message-Id: <20180512004311.9299-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v2 12/27] target/arm: Use floatX_silence_nan when we have already checked for SNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 6 +++--- target/arm/helper.c | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 4f8034c513..6f0eb83661 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -376,7 +376,7 @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp) float16 nan = a; if (float16_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float16_maybe_silence_nan(a, fpst); + nan = float16_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan = float16_default_nan(fpst); @@ -405,7 +405,7 @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp) float32 nan = a; if (float32_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float32_maybe_silence_nan(a, fpst); + nan = float32_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan = float32_default_nan(fpst); @@ -434,7 +434,7 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp) float64 nan = a; if (float64_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float64_maybe_silence_nan(a, fpst); + nan = float64_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan = float64_default_nan(fpst); diff --git a/target/arm/helper.c b/target/arm/helper.c index c6fd7f9479..3df5cf30e4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11739,7 +11739,7 @@ float16 HELPER(recpe_f16)(float16 input, void *fpstp) float16 nan = f16; if (float16_is_signaling_nan(f16, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float16_maybe_silence_nan(f16, fpst); + nan = float16_silence_nan(f16, fpst); } if (fpst->default_nan_mode) { nan = float16_default_nan(fpst); @@ -11787,7 +11787,7 @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp) float32 nan = f32; if (float32_is_signaling_nan(f32, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float32_maybe_silence_nan(f32, fpst); + nan = float32_silence_nan(f32, fpst); } if (fpst->default_nan_mode) { nan = float32_default_nan(fpst); @@ -11835,7 +11835,7 @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp) float64 nan = f64; if (float64_is_signaling_nan(f64, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float64_maybe_silence_nan(f64, fpst); + nan = float64_silence_nan(f64, fpst); } if (fpst->default_nan_mode) { nan = float64_default_nan(fpst); @@ -11934,7 +11934,7 @@ float16 HELPER(rsqrte_f16)(float16 input, void *fpstp) float16 nan = f16; if (float16_is_signaling_nan(f16, s)) { float_raise(float_flag_invalid, s); - nan = float16_maybe_silence_nan(f16, s); + nan = float16_silence_nan(f16, s); } if (s->default_nan_mode) { nan = float16_default_nan(s); @@ -11978,7 +11978,7 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) float32 nan = f32; if (float32_is_signaling_nan(f32, s)) { float_raise(float_flag_invalid, s); - nan = float32_maybe_silence_nan(f32, s); + nan = float32_silence_nan(f32, s); } if (s->default_nan_mode) { nan = float32_default_nan(s); @@ -12021,7 +12021,7 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) float64 nan = f64; if (float64_is_signaling_nan(f64, s)) { float_raise(float_flag_invalid, s); - nan = float64_maybe_silence_nan(f64, s); + nan = float64_silence_nan(f64, s); } if (s->default_nan_mode) { nan = float64_default_nan(s); From patchwork Sat May 12 00:42:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135610 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1579803lji; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:57 -0700 Message-Id: <20180512004311.9299-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v2 13/27] target/arm: convert conversion helpers to fpst/ahp_flag X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée Instead of passing env and leaving it up to the helper to get the right fpstatus we pass it explicitly. There was already a get_fpstatus helper for neon for the 32 bit code. We also add an get_ahp_flag() for passing the state of the alternative FP16 format flag. This leaves scope for later tracking the AHP state in translation flags. Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- v4 - remove neon_fcvt_*; they are now identical to vfp_fcvt_*. - add flags to vfp_fcvt_* helper decls. - add some missing tcg_temp_free_*. --- target/arm/helper.h | 10 +++--- target/arm/translate.h | 12 +++++++ target/arm/helper.c | 56 +++++------------------------ target/arm/translate-a64.c | 38 ++++++++++++++++---- target/arm/translate.c | 74 +++++++++++++++++++++++++++++--------- 5 files changed, 113 insertions(+), 77 deletions(-) -- 2.17.0 diff --git a/target/arm/helper.h b/target/arm/helper.h index ce89968b2d..047f3bc1ca 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -187,12 +187,10 @@ DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr) DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) -DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env) -DEF_HELPER_2(vfp_fcvt_f32_to_f16, i32, f32, env) -DEF_HELPER_2(neon_fcvt_f16_to_f32, f32, i32, env) -DEF_HELPER_2(neon_fcvt_f32_to_f16, i32, f32, env) -DEF_HELPER_FLAGS_2(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, i32, env) -DEF_HELPER_FLAGS_2(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, i32, f64, env) +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, ptr, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, ptr, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i32) DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr) DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) diff --git a/target/arm/translate.h b/target/arm/translate.h index 37a1bba056..45f04244be 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -177,4 +177,16 @@ void arm_free_cc(DisasCompare *cmp); void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); +/* Return state of Alternate Half-precision flag, caller frees result */ +static inline TCGv_i32 get_ahp_flag(void) +{ + TCGv_i32 ret = tcg_temp_new_i32(); + + tcg_gen_ld_i32(ret, cpu_env, + offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR])); + tcg_gen_extract_i32(ret, ret, 26, 1); + + return ret; +} + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 3df5cf30e4..a1c1dc5bbe 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11540,64 +11540,24 @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) } /* Half precision conversions. */ -static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) +float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode) { - int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; - float32 r = float16_to_float32(make_float16(a), ieee, s); - if (ieee) { - return float32_maybe_silence_nan(r, s); - } - return r; + return float16_to_float32(a, !ahp_mode, fpstp); } -static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) +float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) { - int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; - float16 r = float32_to_float16(a, ieee, s); - if (ieee) { - r = float16_maybe_silence_nan(r, s); - } - return float16_val(r); + return float32_to_float16(a, !ahp_mode, fpstp); } -float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) +float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode) { - return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); + return float16_to_float64(a, !ahp_mode, fpstp); } -uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) +float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) { - return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); -} - -float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) -{ - return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); -} - -uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) -{ - return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); -} - -float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) -{ - int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; - float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); - if (ieee) { - return float64_maybe_silence_nan(r, &env->vfp.fp_status); - } - return r; -} - -uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) -{ - int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; - float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); - if (ieee) { - r = float16_maybe_silence_nan(r, &env->vfp.fp_status); - } - return float16_val(r); + return float64_to_float16(a, !ahp_mode, fpstp); } #define float32_two make_float32(0x40000000) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a0b0c43d12..570791e7b5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5147,10 +5147,15 @@ static void handle_fp_fcvt(DisasContext *s, int opcode, } else { /* Single to half */ TCGv_i32 tcg_rd = tcg_temp_new_i32(); - gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, cpu_env); + TCGv_i32 ahp = get_ahp_flag(); + TCGv_ptr fpst = get_fpstatus_ptr(true); + + gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero */ write_fp_sreg(s, rd, tcg_rd); tcg_temp_free_i32(tcg_rd); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); } tcg_temp_free_i32(tcg_rn); break; @@ -5163,9 +5168,13 @@ static void handle_fp_fcvt(DisasContext *s, int opcode, /* Double to single */ gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); } else { + TCGv_ptr fpst = get_fpstatus_ptr(true); + TCGv_i32 ahp = get_ahp_flag(); /* Double to half */ - gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero */ + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(ahp); } write_fp_sreg(s, rd, tcg_rd); tcg_temp_free_i32(tcg_rd); @@ -5175,17 +5184,21 @@ static void handle_fp_fcvt(DisasContext *s, int opcode, case 0x3: { TCGv_i32 tcg_rn = read_fp_sreg(s, rn); + TCGv_ptr tcg_fpst = get_fpstatus_ptr(true); + TCGv_i32 tcg_ahp = get_ahp_flag(); tcg_gen_ext16u_i32(tcg_rn, tcg_rn); if (dtype == 0) { /* Half to single */ TCGv_i32 tcg_rd = tcg_temp_new_i32(); - gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); write_fp_sreg(s, rd, tcg_rd); + tcg_temp_free_ptr(tcg_fpst); + tcg_temp_free_i32(tcg_ahp); tcg_temp_free_i32(tcg_rd); } else { /* Half to double */ TCGv_i64 tcg_rd = tcg_temp_new_i64(); - gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); write_fp_dreg(s, rd, tcg_rd); tcg_temp_free_i64(tcg_rd); } @@ -9053,12 +9066,17 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar, } else { TCGv_i32 tcg_lo = tcg_temp_new_i32(); TCGv_i32 tcg_hi = tcg_temp_new_i32(); + TCGv_ptr fpst = get_fpstatus_ptr(true); + TCGv_i32 ahp = get_ahp_flag(); + tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op); - gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env); - gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp); + gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp); tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); tcg_temp_free_i32(tcg_lo); tcg_temp_free_i32(tcg_hi); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(ahp); } break; case 0x56: /* FCVTXN, FCVTXN2 */ @@ -11532,18 +11550,24 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, /* 16 -> 32 bit fp conversion */ int srcelt = is_q ? 4 : 0; TCGv_i32 tcg_res[4]; + TCGv_ptr fpst = get_fpstatus_ptr(true); + TCGv_i32 ahp = get_ahp_flag(); + for (pass = 0; pass < 4; pass++) { tcg_res[pass] = tcg_temp_new_i32(); read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16); gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass], - cpu_env); + fpst, ahp); } for (pass = 0; pass < 4; pass++) { write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); tcg_temp_free_i32(tcg_res[pass]); } + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(ahp); } } diff --git a/target/arm/translate.c b/target/arm/translate.c index 731cf327a1..5ba59e0188 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3824,38 +3824,56 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) gen_vfp_sqrt(dp); break; case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */ + { + TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_i32 ahp_mode = get_ahp_flag(); tmp = gen_vfp_mrs(); tcg_gen_ext16u_i32(tmp, tmp); if (dp) { gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp, - cpu_env); + fpst, ahp_mode); } else { gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, - cpu_env); + fpst, ahp_mode); } + tcg_temp_free_i32(ahp_mode); + tcg_temp_free_ptr(fpst); tcg_temp_free_i32(tmp); break; + } case 5: /* vcvtt.f32.f16, vcvtt.f64.f16 */ + { + TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_i32 ahp = get_ahp_flag(); tmp = gen_vfp_mrs(); tcg_gen_shri_i32(tmp, tmp, 16); if (dp) { gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp, - cpu_env); + fpst, ahp); } else { gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, - cpu_env); + fpst, ahp); } tcg_temp_free_i32(tmp); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); break; + } case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */ + { + TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_i32 ahp = get_ahp_flag(); tmp = tcg_temp_new_i32(); + if (dp) { gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d, - cpu_env); + fpst, ahp); } else { gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, - cpu_env); + fpst, ahp); } + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); gen_mov_F0_vreg(0, rd); tmp2 = gen_vfp_mrs(); tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); @@ -3863,15 +3881,21 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tmp2); gen_vfp_msr(tmp); break; + } case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */ + { + TCGv_ptr fpst = get_fpstatus_ptr(true); + TCGv_i32 ahp = get_ahp_flag(); tmp = tcg_temp_new_i32(); if (dp) { gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d, - cpu_env); + fpst, ahp); } else { gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, - cpu_env); + fpst, ahp); } + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); tcg_gen_shli_i32(tmp, tmp, 16); gen_mov_F0_vreg(0, rd); tmp2 = gen_vfp_mrs(); @@ -3880,6 +3904,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tmp2); gen_vfp_msr(tmp); break; + } case 8: /* cmp */ gen_vfp_cmp(dp); break; @@ -7222,53 +7247,70 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } break; case NEON_2RM_VCVT_F16_F32: + { + TCGv_ptr fpst; + TCGv_i32 ahp; + if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) || q || (rm & 1)) { return 1; } tmp = tcg_temp_new_i32(); tmp2 = tcg_temp_new_i32(); + fpst = get_fpstatus_ptr(true); + ahp = get_ahp_flag(); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0)); - gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, fpst, ahp); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1)); - gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, fpst, ahp); tcg_gen_shli_i32(tmp2, tmp2, 16); tcg_gen_or_i32(tmp2, tmp2, tmp); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2)); - gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, fpst, ahp); tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3)); neon_store_reg(rd, 0, tmp2); tmp2 = tcg_temp_new_i32(); - gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env); + gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, fpst, ahp); tcg_gen_shli_i32(tmp2, tmp2, 16); tcg_gen_or_i32(tmp2, tmp2, tmp); neon_store_reg(rd, 1, tmp2); tcg_temp_free_i32(tmp); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); break; + } case NEON_2RM_VCVT_F32_F16: + { + TCGv_ptr fpst; + TCGv_i32 ahp; if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) || q || (rd & 1)) { return 1; } + fpst = get_fpstatus_ptr(true); + ahp = get_ahp_flag(); tmp3 = tcg_temp_new_i32(); tmp = neon_load_reg(rm, 0); tmp2 = neon_load_reg(rm, 1); tcg_gen_ext16u_i32(tmp3, tmp); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0)); tcg_gen_shri_i32(tmp3, tmp, 16); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1)); tcg_temp_free_i32(tmp); tcg_gen_ext16u_i32(tmp3, tmp2); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2)); tcg_gen_shri_i32(tmp3, tmp2, 16); - gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env); + gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp); tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3)); tcg_temp_free_i32(tmp2); tcg_temp_free_i32(tmp3); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); break; + } case NEON_2RM_AESE: case NEON_2RM_AESMC: if (!arm_dc_feature(s, ARM_FEATURE_V8_AES) || ((rm | rd) & 1)) { From patchwork Sat May 12 00:42:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135609 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1577897lji; Fri, 11 May 2018 18:03:21 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrEvorqagEjAg/LL2hTLTosMv0Hs+Qea1fWYIwuHEBypiMm80BHwnu4hSqNuZii10VLpCVy X-Received: by 2002:a37:8c82:: with SMTP id o124-v6mr272766qkd.209.1526087001324; Fri, 11 May 2018 18:03:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526087001; cv=none; d=google.com; s=arc-20160816; b=zr+Pej/NyAmi6rvIz+PN+jFBFS89GoAdLpRXHWqML10RVUZVEpLW/zpqetTlSH/nXp sASishR7b76AqjQL7HpvB8bPG3Tl4h7EcTRK9U63ASjARDDhl2HdJFn3Q24kCYDEFfoc obKXXcDeRkOv/SIw7bR70ecBP//uPNarxRukMHNSzgUpVW4rlhwqihjSCggOIxVZefYp 2AuqN/lV9eMhUSuok9AQqvMVDT5Fk8XLdwIZoWI6pZK6TTEtYjIBTMgzjO95EsAmNJT1 pW4IjX990ZgvzvCk0kjWuDDUokbR80nbuo/EtfPF/Jej5WKRA2SBMD7gJOGftfo10FqS 7cVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:58 -0700 Message-Id: <20180512004311.9299-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v2 14/27] target/arm: squash FZ16 behaviour for conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée The ARM ARM specifies FZ16 is suppressed for conversions. Rather than pushing this logic into the softfloat code we can simply save the FZ state and temporarily disable it for the softfloat call. Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- v4 - float16_to_floatX squished the wrong softfloat bit for FZ16; need to adjust input denormals in this case. --- target/arm/helper.c | 40 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.c b/target/arm/helper.c index a1c1dc5bbe..e05c7230d4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11542,22 +11542,54 @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) /* Half precision conversions. */ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode) { - return float16_to_float32(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing input denormals. + */ + float_status *fpst = fpstp; + flag save = get_flush_inputs_to_zero(fpst); + set_flush_inputs_to_zero(false, fpst); + float32 r = float16_to_float32(a, !ahp_mode, fpst); + set_flush_inputs_to_zero(save, fpst); + return r; } float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) { - return float32_to_float16(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing output denormals. + */ + float_status *fpst = fpstp; + flag save = get_flush_to_zero(fpst); + set_flush_to_zero(false, fpst); + float16 r = float32_to_float16(a, !ahp_mode, fpst); + set_flush_to_zero(save, fpst); + return r; } float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode) { - return float16_to_float64(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing input denormals. + */ + float_status *fpst = fpstp; + flag save = get_flush_inputs_to_zero(fpst); + set_flush_inputs_to_zero(false, fpst); + float64 r = float16_to_float64(a, !ahp_mode, fpst); + set_flush_inputs_to_zero(save, fpst); + return r; } float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) { - return float64_to_float16(a, !ahp_mode, fpstp); + /* Squash FZ16 to 0 for the duration of conversion. In this case, + * it would affect flushing output denormals. + */ + float_status *fpst = fpstp; + flag save = get_flush_to_zero(fpst); + set_flush_to_zero(false, fpst); + float16 r = float64_to_float16(a, !ahp_mode, fpst); + set_flush_to_zero(save, fpst); + return r; } #define float32_two make_float32(0x40000000) From patchwork Sat May 12 00:42:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135598 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1571706lji; Fri, 11 May 2018 17:54:25 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoZZ6X4Kfh+BjMjHI8VfHRN1L4gqTe5WHrJf9svWfaScBrvY9xzwqfslm3yd2XqpxNlEOvP X-Received: by 2002:a0c:f381:: with SMTP id i1-v6mr631974qvk.214.1526086465027; Fri, 11 May 2018 17:54:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086465; cv=none; d=google.com; s=arc-20160816; b=gg3Ty0Vyg6VFuxYRxKvEkY/3aAqqUvKK+WWkhQ74odSOtEswX16oZyCMTObgF/OURJ bJueYQ16CsBlTwx+kMFgaM5iqVDPjz5hG6jFNxOA24Toc6y8JBAwiS+tZgGamgpSm7t1 jKZ7lXMxUDBjAOEc2MOmGbXpKePsrTBAIaoUn7v2FfCLeKvAv+Bj7NzR+iTDP/CXfOdY 8CbUQ7AmDJbNsvsMKNVExbQ8aJEbcF4KXW0uMkAPzMuUdM74urf7xXFWQF9KeYoWDUW9 re2OcdBlnXN1qhMm10KC7C7MBPAn2ky8QxdmvNO3tZ+bvNX3BuvsTTx7hW7WHx5h9hwH Xo0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=jnB8tA4c5Y4Msd2PfhBNR5wBe9pwdTmI4+OOGSATPKw=; b=f15/hEjEsh1B4Br6M/mZAj39lyJywPGgY3Xgb7BQFSEArSpSeAU9yst2+cbj2UUfm9 Nw2M3wy3yXRpp6yYgRaEfng5ZwVk2SGRhRZkswZJA/Dkg85Hq537RXBGoaGBwRz2Ha8m PmxY2LB5gZk4RPPS5m6pf3/a9+KfEblDggoZVMmyNqiwR8zderDoZp8upL7PliQveMZk Nsp6J39MiHy4xz/XwWje8PoD+M4P1qu3jzwyKWFvzEDl8WGlL8cG7hH30iQQzHQqgTOD PUe+S2p4qx0vUYssdP8zFJr7JJ3U46pJKqtXEx9BqKyc8dy5IkMRHtiZ84QOVjMaWKnP 9IYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fE4Ji2Bh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:59 -0700 Message-Id: <20180512004311.9299-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v2 15/27] target/arm: Fix fp_status_f16 tininess before rounding X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell In commit d81ce0ef2c4f105 we added an extra float_status field fp_status_fp16 for Arm, but forgot to initialize it correctly by setting it to float_tininess_before_rounding. This currently will only cause problems for the new V8_FP16 feature, since the float-to-float conversion code doesn't use it yet. The effect would be that we failed to set the Underflow IEEE exception flag in all the cases where we should. Add the missing initialization. Fixes: d81ce0ef2c4f105 Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.0 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d175c5e94f..7939c6b8ae 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -324,6 +324,8 @@ static void arm_cpu_reset(CPUState *s) &env->vfp.fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->vfp.standard_fp_status); + set_float_detect_tininess(float_tininess_before_rounding, + &env->vfp.fp_status_f16); #ifndef CONFIG_USER_ONLY if (kvm_enabled()) { kvm_arm_reset_vcpu(cpu); From patchwork Sat May 12 00:43:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135596 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1570976lji; Fri, 11 May 2018 17:53:23 -0700 (PDT) X-Google-Smtp-Source: AB8JxZp38GLec0YGABXt2UlBDKkXCOBZv+BPeRWYqwmWadnbjRHV9fJ2CoSSSiyI4z72mDaAw4Tz X-Received: by 2002:a37:129b:: with SMTP id 27-v6mr264622qks.96.1526086403626; Fri, 11 May 2018 17:53:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086403; cv=none; d=google.com; s=arc-20160816; b=sxTxd/ZqPdtCvHIVxpIzLlyRVA2JAZxuWgM4MBUrnzTWuV8M7UdzpyXsiTf9EXyQAx kev6j9rqZt8vCZSJR+lHWjUQ+GgplYC92IW8joj3fs3+7sZwS5HyyX2pUz8ySpDx3NzI 6r+HhwCFKNMTDeBDvHOM0+of4wdl/niT16ZIiZ2dmXj9DNm1WT0vZ3LbnRRYb5qhPzUn BQQvUcXbVT/EdqHelgvwKPcNEJxSXc9eOaSdfiaYEUNIpFQGpYXRa5pswNnsUgwzF+Dy o3LqpgMtwZDdzSAFvufts37VjvxBAmhME1F/Ow2OBTO5P9GkPndFuIG+HvtM9MmUIcQw VzNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=azT2szVJWo3w0aiYlJcxf2GCjh0Q/WRHs+y2Wc2Yg20=; b=DiclSb+hk1IjEUyXiz4e5COLWRp01JferWq/+KzYR1RemQAFsq6PlPWjp3UiM0hPRD KFmcvbswG8+l81CwUXZgFGu/chCO+z8I/Om/6NXZgZ6R6nd3oHHUxJZeWXz+TSyS6NVR 4X8sC8jF9/6P5W5KuD3zWQWY09VOM2btGZxe0H1t7v4HHf40V+9uJGWMTRBN9ru9TDCV fCzyVhnKb0b0vOQIogk8OVNQEYpRY8b24EjpvPVdGL1r4Ip7wEF6tNx4sD64NXRI+sxA kE1GcUdS1WVgEzmunLduCq+/BxLGubfqdlFJ3V66pZi8wGyRsLsVG6c8Mp55hhOyrdON cJ5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=REB0Nzmd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a187-v6si4432033qkf.205.2018.05.11.17.53.23 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 11 May 2018 17:53:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=REB0Nzmd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59303 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fHImp-0008MF-27 for patch@linaro.org; Fri, 11 May 2018 20:53:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33518) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fHIdP-0004kj-Bn for qemu-devel@nongnu.org; Fri, 11 May 2018 20:43:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fHIdO-0002xg-Ci for qemu-devel@nongnu.org; Fri, 11 May 2018 20:43:39 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:35291) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fHIdO-0002xN-6x for qemu-devel@nongnu.org; Fri, 11 May 2018 20:43:38 -0400 Received: by mail-pf0-x242.google.com with SMTP id x9-v6so3436894pfm.2 for ; Fri, 11 May 2018 17:43:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=azT2szVJWo3w0aiYlJcxf2GCjh0Q/WRHs+y2Wc2Yg20=; b=REB0Nzmd20pfDxij/AOfM6jbnTz0WpZLt3AGp2aX7iQTpEc6d9QoQwIeWtVfzDsZOK AcPrbT3MllPJnlCASijcDMTgl+DWQGiS5iV68DDX98w+ZXXNUtqfMD/1N/EvXQgPVmX9 pw2xAdiQ0vk7TfrogwcGViOAh0T1qZyIG4Gkc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=azT2szVJWo3w0aiYlJcxf2GCjh0Q/WRHs+y2Wc2Yg20=; b=CTUR8FdYXTx0GamEXnrx7VSBEuaPVej6Wdwfxv7XTZeR/QmxmfWlLkghVcDO36Mxcp 7RWI+DaAi+vU4207q09bcJv3CT1Xw/uGzyzrswnvGMp6uqrPBaf/r0IZRd1l/GhDLe2V kTEcncuUTCRNOolOWfA7WmrjA7ecMJ75XY84KjSnUSMk4cW1cMLPOdSNRwTlu+ZhxZSp 5rPgCsx/VCswc0D09EPdbyG2vBzHALC6vpRhV9Vin05w1uJ5AcMulcPZW7HuPwodLxZS RzwaTK2c1lrWTqqYHetvHwiyMPibMGY0Yrq3MybtFa/iQJstG05A3p+3rlCUSodRtn6V NMUQ== X-Gm-Message-State: ALKqPwfnPv2gQUox3onqbc1Y7Xi4pVkTcQccgSd2TiQgWDyWGULjrs1N EGkke8LTMvFtkkd8xkEU6lMBay/9Sa0= X-Received: by 2002:a65:6496:: with SMTP id e22-v6mr1002687pgv.386.1526085816803; Fri, 11 May 2018 17:43:36 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:43:00 -0700 Message-Id: <20180512004311.9299-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v2 16/27] target/arm: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 1 - target/arm/helper.c | 12 ++---------- 2 files changed, 2 insertions(+), 11 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 6f0eb83661..f92bdea732 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -466,7 +466,6 @@ float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env) set_float_rounding_mode(float_round_to_zero, &tstat); set_float_exception_flags(0, &tstat); r = float64_to_float32(a, &tstat); - r = float32_maybe_silence_nan(r, &tstat); exflags = get_float_exception_flags(&tstat); if (exflags & float_flag_inexact) { r = make_float32(float32_val(r) | 1); diff --git a/target/arm/helper.c b/target/arm/helper.c index e05c7230d4..db8bbe52a6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11348,20 +11348,12 @@ FLOAT_CONVS(ui, d, 64, u) /* floating point conversion */ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) { - float64 r = float32_to_float64(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float64_maybe_silence_nan(r, &env->vfp.fp_status); + return float32_to_float64(x, &env->vfp.fp_status); } float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) { - float32 r = float64_to_float32(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float32_maybe_silence_nan(r, &env->vfp.fp_status); + return float64_to_float32(x, &env->vfp.fp_status); } /* VFP3 fixed point conversion. */ From patchwork Sat May 12 00:43:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135611 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1581709lji; Fri, 11 May 2018 18:08:04 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpV3W6GZul3KMxLbBaSPNQQbHfX0cgyymI9mRC8AyqQ2XyG2bO2mLI1WiU0zrzQydlsMMaO X-Received: by 2002:a0c:9e05:: with SMTP id p5-v6mr667270qve.136.1526087283956; Fri, 11 May 2018 18:08:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526087283; cv=none; d=google.com; s=arc-20160816; b=mPMX54HTtUiahjwavEiurIKAMQC3E1horuoFmJ9Wq1IF8YSyrBxmBaxuveykG5jOEM IzDZZsJWXvtMz+zpzGKFxMRwLiCLc2zJp0m6ihxT6r1rqt13OxuGQbJr2XgTk7uw2BPV l4NLZk5U4MYt3sj0UzREgqQUniGhSk96hBMrP6h8aMgI8k6KnIZstNsEMfkaDhv/5UX1 k1oEdFeJNBNJpPBOGrl09hejH6OczmVgeWkZDG5NafuIj7IPCHWJStUI2Qar1X4VL76G uXvoNY4b47L47NA3IjAMq5MW5CT46EgUKo/ZuE7hzyFxL64Wfw1mHJIpENzlF2Uk4Ten lN8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=yyAYGNdO4kkJBfymYFw36wtSVFsJ2je7s9XYrOFvLZ0=; b=qJVvcGwwOY/2c4C/9DbAAEMTxBYelFoMTW5vzLlSCJbWzquFmCJNKqVZ+aVVKEZDw2 i9IsP5asoj/1kCL2sLJzn1kiSD8hzJz4slXA0+HPnNI2REYBPjDFFbUeLLHs0xm4BYwo T/X5mJuuPL+2hEpQqELLVHmkxn7LkOYvHcQ6Kypp0etS/zywa7XvPHyvO1g2/paSNZ/5 Xg+Kdt6tteND9/lvxSJ9xvBwzbsTy08NyiDX7lpir7MmTFDYK++Tv1mrfkw3Cz1i6Q4l cQPYuqqiJh+6Mb8Nt5VIDVhlijQ8wHltV3QonPVcDHZ9sxaWhlxtwlRrcEJMsdDWGMFq udkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Cpwe4F8o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a22-v6si2463303qte.202.2018.05.11.18.08.03 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 11 May 2018 18:08:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Cpwe4F8o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60559 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fHJ11-0002dV-EV for patch@linaro.org; Fri, 11 May 2018 21:08:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33535) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fHIdQ-0004lv-8g for qemu-devel@nongnu.org; Fri, 11 May 2018 20:43:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fHIdP-0002yF-F2 for qemu-devel@nongnu.org; Fri, 11 May 2018 20:43:40 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:46575) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fHIdP-0002xw-9T for qemu-devel@nongnu.org; Fri, 11 May 2018 20:43:39 -0400 Received: by mail-pg0-x241.google.com with SMTP id z4-v6so3071616pgu.13 for ; Fri, 11 May 2018 17:43:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yyAYGNdO4kkJBfymYFw36wtSVFsJ2je7s9XYrOFvLZ0=; b=Cpwe4F8oEfkl9wQODdUCIdap/kpWfLrHUA8aX45sOzmCxZX05s4U/GUlh+rLnExfnc h0YqtNHKuaVMAkVYPo7sFMThOn5Edwv6qcuZoDTzyom4akhplhsTreGCcb4OOUVGmx46 3RccJxdy+81ESe9Ip73FrEWHd6cqQ4EcgXkXg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yyAYGNdO4kkJBfymYFw36wtSVFsJ2je7s9XYrOFvLZ0=; b=qiuqvwOZPTfPHdXqD6RkoLt/tLfS7he7DjPZLLNd7zKhAjS7ap59j+EoVKC1BHPYbo UlxpDmaMr8D8Rn8KA59y6PAXq0dM1vUdn6L6jy07hL3ko07n7VpUtPkALD3u85mg8z5y k3NcM86qp3+pz0IbyXAxvonEI47oqEwsYbPEiS45z5GJex+iXZaXjK9082R9CpCwPJq1 d8qflW9uc8990QJGW7/F3VXGbFr4iXNt7eZWJsPlDLbNWnhuEp6ss3yBFFPOMjPAbdt0 yGrjZ4D9QXgmHVGxEevNf+AEqrTYCNjNRY8Q0err0E1h3OKoL/aHKdiwCCeH0oUNyQYA xrzw== X-Gm-Message-State: ALKqPwfNvXRdd1TKMDL0yCI3JJjjjXgHgG2HiVq+l0nTq9f2/OE8OzJA pP0AeEFjRg4FVe437g1SfbFm0IAxbf8= X-Received: by 2002:a63:ac43:: with SMTP id z3-v6mr957299pgn.291.1526085818018; Fri, 11 May 2018 17:43:38 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:43:01 -0700 Message-Id: <20180512004311.9299-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v2 17/27] target/hppa: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Signed-off-by: Richard Henderson --- target/hppa/op_helper.c | 2 -- 1 file changed, 2 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a3af62daf7..912e8d5be4 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -341,7 +341,6 @@ float64 HELPER(fdiv_d)(CPUHPPAState *env, float64 a, float64 b) float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg) { float64 ret = float32_to_float64(arg, &env->fp_status); - ret = float64_maybe_silence_nan(ret, &env->fp_status); update_fr0_op(env, GETPC()); return ret; } @@ -349,7 +348,6 @@ float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg) float32 HELPER(fcnv_d_s)(CPUHPPAState *env, float64 arg) { float32 ret = float64_to_float32(arg, &env->fp_status); - ret = float32_maybe_silence_nan(ret, &env->fp_status); update_fr0_op(env, GETPC()); return ret; } From patchwork Sat May 12 00:43:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135601 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1573241lji; Fri, 11 May 2018 17:56:43 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrUCIGHd7x2gK8Q1deYfE/1kQBTd7wgVy4N90RAVLYsF8j8kMemt87mP3Pa32VIDkKsfBIL X-Received: by 2002:ac8:530d:: with SMTP id t13-v6mr280902qtn.388.1526086603223; Fri, 11 May 2018 17:56:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086603; cv=none; d=google.com; s=arc-20160816; b=f3yalmpXAvMZLUGuyujdDMBf6GYc/3lXhqF8+VAijBet92muEKcLrPQMY+Ny1/88g7 XaR1lMhZmIKDpvvrIk0UtNRNxO0z9QlEfVqGDH7l5acA+u1qL/f3cmFQyyAdmkfw2rm1 FhU529WxbCZ9Fao/c3oTkryGpKNggHhW+tHD/A+E8BkRKx/uYhJVlMb/zNJ1UOEyYcs6 3/qPeEAaZK3e8A3a+fVNGecVQ0xeiHUx6b1S0nyk/Eq/Sri7rmGhTeprCzUvjwgEHO/v I7x67gmrAfLu6XecI+qdBWh4ypIiAnh7/mvKObh6qRvUQh7NRFJdeLePyM2WFjA6iFKY YfsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=r5VgKQ8Ajyu7ZWBJa/yIpnlKTDE34dKfFaKWj+XaeNY=; b=aLukdgrUfbrFqo1A5vMUE9MCTBTRrNd361ZR3slxsEvzUTI1c1fS8exAFPGRk+I1x7 /vTV3S7xh0JDM2TFE+5J+Ha08zpOJxxlPSPxzc7OSvfeet+MvW6ExpEPJT1v9Pq4pFzC Ki57qBAD6dHsSfGxObHfRqh57zj/2RUfjLkYflu/rBKk+o8AbTM6Tk/w3+MUq2gknnjJ 3NpAcq+Mxpn5UMHX41Hi0cr7vDQ+mkFRx4vZW04CUTWiFsVzLRot/GJoNRAQefj4hjvN /4p/0NdOw0n8jXIFQWobW9OLdbEsSo68sjetBEUZJ9pEbrliZDb7RyD03Ekvl88YKTZd 15NQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NJ48rM8s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:43:02 -0700 Message-Id: <20180512004311.9299-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v2 18/27] target/m68k: Use floatX_silence_nan when we have already checked for SNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/softfloat.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c index e41b07d042..6ec227e20f 100644 --- a/target/m68k/softfloat.c +++ b/target/m68k/softfloat.c @@ -31,13 +31,14 @@ static floatx80 propagateFloatx80NaNOneArg(floatx80 a, float_status *status) { if (floatx80_is_signaling_nan(a, status)) { float_raise(float_flag_invalid, status); + a = floatx80_silence_nan(a, status); } if (status->default_nan_mode) { return floatx80_default_nan(status); } - return floatx80_maybe_silence_nan(a, status); + return a; } /*---------------------------------------------------------------------------- From patchwork Sat May 12 00:43:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135595 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1570644lji; Fri, 11 May 2018 17:52:56 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqE3rCAb84e1ZOZIj0rlNxGTI7XlxpXZgup7pDJXT6GJN9zjoa0CtMR1koFDd+ZKkVbrr5Z X-Received: by 2002:ac8:4a2:: with SMTP id s34-v6mr260019qtg.129.1526086376778; Fri, 11 May 2018 17:52:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086376; cv=none; d=google.com; s=arc-20160816; b=pLQIFtSHjmo5xuzviCloCb20tJheaQPdAUN/14ylyMGGbw6cMaJO/AFZaV40IsfSTu COqDQkniJDOalCMwaGF5/qzucjwEkDSYlulVcWq6nVX+HarnOyAjOjscCD06TmOfd+uf LhfJrBJ8+2BqIZLbwIveZNo3RqlfK/Yw6Yzbr91YdTgj2DjKR1IKTiyNw4G1uBXhlv7X PQSG5XVPTVmQ9LB8YjQysyQxlx4bDw/rDk07aKIqkH/DKvopHaWalRnIgAf0R/WWeU3a JZj1VKGyvTy+MzAA/NLWrJQgL2C1AgW0HlktvZoLqTZQvFENBYpsw7vbDH4d0jcCKK+z 3Lcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=+6dmYgNBq5ftwjyPS2WMF6O8R65wvbccZZc/fwe9HEo=; b=pwQlBn4PwW8Uu0zASuiFbK7LRx0INRJr9y7R/gD0DPDcas5W9o7I+Ioyt+h7R/9dtF ALQcQ7hgX7G9FRnNHrwalqDTkUezkpKTCft4QzYniW5M0doFpk2Uo+MGKMOnIMsCs8gZ d5RMnXnfCRzQf90EEqWZ1z4qf6bzwa/hJCYWIK98UiftyrABIQlNv5u+g3barYVWN47Q noxpb8GU507mAzuQ+svhGWnXB/jv2bVLY49rW6AO2+zG6LEjJR7R86YKqV9TtY5kIeoG fWBikAM/ZddBQFJh8GiI3mW5wsF1pRirlnWl2Hg+LH+tlGxf0Qebz4dXcmL9Mu2T5C3e J1dg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X3MPVopC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:43:03 -0700 Message-Id: <20180512004311.9299-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v2 19/27] target/mips: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Yongbok Kim , alex.bennee@linaro.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Cc: Aurelien Jarno Cc: Yongbok Kim Signed-off-by: Richard Henderson --- target/mips/msa_helper.c | 4 ---- target/mips/op_helper.c | 2 -- 2 files changed, 6 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 8fb7a369ca..c74e3cdc65 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1615,7 +1615,6 @@ static inline float16 float16_from_float32(int32_t a, flag ieee, float16 f_val; f_val = float32_to_float16((float32)a, ieee, status); - f_val = float16_maybe_silence_nan(f_val, status); return a < 0 ? (f_val | (1 << 15)) : f_val; } @@ -1625,7 +1624,6 @@ static inline float32 float32_from_float64(int64_t a, float_status *status) float32 f_val; f_val = float64_to_float32((float64)a, status); - f_val = float32_maybe_silence_nan(f_val, status); return a < 0 ? (f_val | (1 << 31)) : f_val; } @@ -1636,7 +1634,6 @@ static inline float32 float32_from_float16(int16_t a, flag ieee, float32 f_val; f_val = float16_to_float32((float16)a, ieee, status); - f_val = float32_maybe_silence_nan(f_val, status); return a < 0 ? (f_val | (1 << 31)) : f_val; } @@ -1646,7 +1643,6 @@ static inline float64 float64_from_float32(int32_t a, float_status *status) float64 f_val; f_val = float32_to_float64((float64)a, status); - f_val = float64_maybe_silence_nan(f_val, status); return a < 0 ? (f_val | (1ULL << 63)) : f_val; } diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 798cdad030..9025f42366 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2700,7 +2700,6 @@ uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) uint64_t fdt2; fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); - fdt2 = float64_maybe_silence_nan(fdt2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return fdt2; } @@ -2790,7 +2789,6 @@ uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) uint32_t fst2; fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); - fst2 = float32_maybe_silence_nan(fst2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return fst2; } From patchwork Sat May 12 00:43:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135599 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1572723lji; Fri, 11 May 2018 17:55:51 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqifSSv1Ne9Ju2K0k99LZc7Wy5zojf3Ny4Br9OS+hrTqWULZ69iH4SF5UJzLJ20CsCDjF9+ X-Received: by 2002:a37:2995:: with SMTP id p21-v6mr242300qkp.397.1526086551489; Fri, 11 May 2018 17:55:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086551; cv=none; d=google.com; s=arc-20160816; b=cLpwTsI594THaK8ZWlXRI4n+VDCp9VA+LGCsJqfzWk8e8QH3fzsclz7zl1tIWCE/SX AJe+vSEKKiYgbZX/k2bU7y4YSzaXaQXsHa8Mu7u1zh/KymW03Uvfz9VNCyoCRO8DetVS gKSNIxRWlB3rY8/D3xO6oLbgoFe5VqOGaeqWUn4MdXC7Xu38V8gPNs9nW/wK7TyUoGkw FUgzhn/maMOdY9DqULQEn1HaTBatHo6clMlOYlV3Fq+2eTcfGVdCv2JVpbzYE8g+KuKm k6Y5bT3c0/g73IHNZ4/nd+XaILhFLcmbnBiZxQ3NbYVEAhwLalzNPEc9qoVDAvuQ4s0r hP8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Sl9puNuuuPbRgCmqDxPltmj/Vyt5J5Mk/0va5RwJCSQ=; b=bMC3Z6J3BNqAHILxdwr1S/0o9xfRhMukwKRgIL+pgVkoO9FroRTkkowwVBRwNE9odQ C5UpR7cklud0jZ/0My0gjV3QImSKBHWsNxfj3fBLBUNSOOJa9i1QT5k982ypLd7Kyy7h eEYSOW1NngmEnapMEg1pS9BV9LjoHDbIEFzvSArsfPp5xBO0aLzq+vjG/d0XWXw6LyQa C9d84rv7WoWEMcRcCHHC7qQMcSMfRXqA3I9tF7bxIMh84jrhUJeLRYpTbKonCvYnJwU3 AJPljihdaJto8VJK0vomtZFWC5Z163oNHiOA+jIT0/lfXX8CJebDIJhqxYXx2tqpx/4P +CfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HSC7yHZs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:43:04 -0700 Message-Id: <20180512004311.9299-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2 20/27] target/riscv: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/riscv/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.17.0 Reviewed-by: Michael Clark diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index abbadead5c..fdb87d8d82 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -279,14 +279,12 @@ uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) { - rs1 = float64_to_float32(rs1, &env->fp_status); - return float32_maybe_silence_nan(rs1, &env->fp_status); + return float64_to_float32(rs1, &env->fp_status); } uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) { - rs1 = float32_to_float64(rs1, &env->fp_status); - return float64_maybe_silence_nan(rs1, &env->fp_status); + return float32_to_float64(rs1, &env->fp_status); } uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) From patchwork Sat May 12 00:43:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135600 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1572940lji; Fri, 11 May 2018 17:56:14 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrb7svHa649p0l6KTswypMPiMTLyjcn+AdosezDL8UPYc5NRIgVyrP+QQc7IxVVKH/Qpy3h X-Received: by 2002:a37:7844:: with SMTP id t65-v6mr292541qkc.56.1526086574851; Fri, 11 May 2018 17:56:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086574; cv=none; d=google.com; s=arc-20160816; b=xn80nYqPLUB8Mykp6eP8fzzZ2+o76eNCtIHq/1X9LFxv/dqEFETyMjokqjVV2+o2CK NYXEJVsLQwGc0hh/HTh+cX/4auykz7VlLoytY3pypQY9zVe+qqkQfZnhtpCMhuqF0PmD vbxsI32XTQEMAxjql8/2Pw8a6ANfZlbQTsuRV0WtNmXY3ahkr74iqB9k9G2DCvyqhbbI x8QDEOAzMozx7LOZo/R+ak7p7ds2urUbi4JcQym62uEz5fAk7hqUeiUsBsL/zzZs8oqD Co5F36BFL8VpcsGTKCUPk4vIlZ7ezB+rGIn57wdhNgJuOJz+Mp34m0FOIY4SrvL/y4vO p9og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=N/MQDXmC5P0rKEPWLGL6olcs6gD/4PAiety6G0UTpec=; b=fkxjgnOFJNfnTTVRc9EvoUG/orI9bitK1I795Sb6hHXNYFv5A9flE7lH/pHhZ0r+Vl qM8t+KupytbZ+bA8w0R872xI2kf3kDB4QDZzkwzJ8UrEMjfgXk7HQk6t4u3G1pHsuBZt 23g2wZ9/b20n0BWwc4kHv0Oly4A1fKm4TcZi8o0bq+SZCyLxhrRE4ku2b/p277ZTP9OY QnUQBTFk/bCU+ycRyiLyLiCS821zcmCygmzaHczqtXaWpFVWYfh2wdZFVWxOMsLI+DST pd9dJwOQLUoLWxWo+OnZK/vSRvLZJEOezbRszhEMq/l+tipow3QROz7Ln8EuuTrr8d1J hwFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WTpSZfYG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:43:05 -0700 Message-Id: <20180512004311.9299-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 21/27] target/s390x: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, Alexander Graf Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Cc: Alexander Graf Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/fpu_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.17.0 diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c index 43f8bf1c94..5c5b451b3b 100644 --- a/target/s390x/fpu_helper.c +++ b/target/s390x/fpu_helper.c @@ -269,7 +269,7 @@ uint64_t HELPER(ldeb)(CPUS390XState *env, uint64_t f2) { float64 ret = float32_to_float64(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return float64_maybe_silence_nan(ret, &env->fpu_status); + return ret; } /* convert 128-bit float to 64-bit float */ @@ -277,7 +277,7 @@ uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, uint64_t al) { float64 ret = float128_to_float64(make_float128(ah, al), &env->fpu_status); handle_exceptions(env, GETPC()); - return float64_maybe_silence_nan(ret, &env->fpu_status); + return ret; } /* convert 64-bit float to 128-bit float */ @@ -285,7 +285,7 @@ uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) { float128 ret = float64_to_float128(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return RET128(float128_maybe_silence_nan(ret, &env->fpu_status)); + return RET128(ret); } /* convert 32-bit float to 128-bit float */ @@ -293,7 +293,7 @@ uint64_t HELPER(lxeb)(CPUS390XState *env, uint64_t f2) { float128 ret = float32_to_float128(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return RET128(float128_maybe_silence_nan(ret, &env->fpu_status)); + return RET128(ret); } /* convert 64-bit float to 32-bit float */ @@ -301,7 +301,7 @@ uint64_t HELPER(ledb)(CPUS390XState *env, uint64_t f2) { float32 ret = float64_to_float32(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return float32_maybe_silence_nan(ret, &env->fpu_status); + return ret; } /* convert 128-bit float to 32-bit float */ @@ -309,7 +309,7 @@ uint64_t HELPER(lexb)(CPUS390XState *env, uint64_t ah, uint64_t al) { float32 ret = float128_to_float32(make_float128(ah, al), &env->fpu_status); handle_exceptions(env, GETPC()); - return float32_maybe_silence_nan(ret, &env->fpu_status); + return ret; } /* 32-bit FP compare */ From patchwork Sat May 12 00:43:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135605 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1574582lji; Fri, 11 May 2018 17:59:01 -0700 (PDT) X-Google-Smtp-Source: AB8JxZr7ixwrUwxV766Owu7zILVkgKUmEK/YsO2kHbYsEGRH9tnDleYmjFmZY/aVYSOKAmc0MlJL X-Received: by 2002:a37:aa4b:: with SMTP id t72-v6mr246625qke.215.1526086741390; Fri, 11 May 2018 17:59:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086741; cv=none; d=google.com; s=arc-20160816; b=gUXScK3FZy1zbeVSkRiyBwp4vVECPALjBwIvWjeAlMvnqKUp5yO7iZv5pCJED1+O5D tFct9bn7CJYssT7TJpZOKMsOrqZ9pL2RbeUb0T79QfJPv7ZohZ+XdoyE/RxEq+MMQRWn 2FAeP/D/8Si1xL7kuuU1VNzlZeEUaR/UjWs4VQLdXa5eSw7Y/mJTJo9+oCyzBp0jCilw KjzTvNJiH7E862xDuTsGbb7T5ZC5k5UgJCdfQtET0z61dicNdF7zsVadJ7Zr4zmajghh fXBAt+k6h7Dmv8Mj7aPm+rTMcvNA5i9FH/PJMP5GeWUtbAYRFf9GjyQZYC8ZZpE5jxlI s3kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=QEmIRJzREeuGE85Fh+AuGexvV4Am9SrrRS3mM2qJ3bs=; b=fbZkftOAisqMsdfgR1GGxOWkWq/8wvEEohDt/NIt8rWCsM6FmyPAmEkWO8tGmcgnbA ZJbnIeTkR6sUA9R8u1vouMlrhxqpwdVqWTeRlHuTBRHXEFwSaCJlsLDPPWti/7s7gDuz XOntVquDqzpzsg5BvD9jS+fd0b+SL8pT9o6fDRT+TIUPaj4LvbNNgOqUAiHsvcEnGRnV q5zgiTP3TYLUbI90KatHEnpfaWwbKW7rHt7hn5ka7QgBAUXjIy+ETG+gImAXkZstKlGK LCjrb9qpA6Urn0xam7hq/AMXxj0k2FgMQNiZkXtqTmtXOoV58GgzGt/KneSsGvfoy9kh 8rEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VHRzfCW6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:43:06 -0700 Message-Id: <20180512004311.9299-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v2 22/27] fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have already checked the arguments for SNaN; we don't need to do it again. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 44 +++++++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 10 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 995a0132c6..4fa068a5dc 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -498,7 +498,7 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status) | The routine is passed various bits of information about the | two NaNs and should return 0 to select NaN a and 1 for NaN b. | Note that signalling NaNs are always squashed to quiet NaNs -| by the caller, by calling floatXX_maybe_silence_nan() before +| by the caller, by calling floatXX_silence_nan() before | returning them. | | aIsLargerSignificand is only valid if both a and b are NaNs @@ -536,7 +536,7 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, { /* According to MIPS specifications, if one of the two operands is * a sNaN, a new qNaN has to be generated. This is done in - * floatXX_maybe_silence_nan(). For qNaN inputs the specifications + * floatXX_silence_nan(). For qNaN inputs the specifications * says: "When possible, this QNaN result is one of the operand QNaN * values." In practice it seems that most implementations choose * the first operand if both operands are qNaN. In short this gives @@ -788,9 +788,15 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float32_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float32_silence_nan(b, status); + } + return b; } else { - return float32_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float32_silence_nan(a, status); + } + return a; } } @@ -950,9 +956,15 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float64_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float64_silence_nan(b, status); + } + return b; } else { - return float64_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float64_silence_nan(a, status); + } + return a; } } @@ -1121,9 +1133,15 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return floatx80_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return floatx80_silence_nan(b, status); + } + return b; } else { - return floatx80_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return floatx80_silence_nan(a, status); + } + return a; } } @@ -1270,8 +1288,14 @@ static float128 propagateFloat128NaN(float128 a, float128 b, if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float128_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float128_silence_nan(b, status); + } + return b; } else { - return float128_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float128_silence_nan(a, status); + } + return a; } } From patchwork Sat May 12 00:43:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135604 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1574284lji; Fri, 11 May 2018 17:58:33 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrErvkfiO0v2cJZ+/v4p78Zz9lRuv6t8L7+VlvdbJhyyKBPCmy0oWUbOfzJ65rpkoFYepzq X-Received: by 2002:ac8:2ff6:: with SMTP id m51-v6mr263249qta.265.1526086712968; Fri, 11 May 2018 17:58:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086712; cv=none; d=google.com; s=arc-20160816; b=rifQ7Lz0/2/D1qr/ZON3anz+MXNPP0sZP9dvsFktPFy1Fcds9YltZUvB4yKH2pZPhH BPAXyNxWTRn4iNUh/a7YoyKupIW/MjlPjt7Sj9s7oZCJEDlpDSHosPZTymYW7bchLC2b 65fcMoL91lyFzmDxh55cjhQUWbbR60gCGiSAMSmsg1IUwPkz6CXai/m/odBnufUn1Phf +vXOXAQgb7Ovgod1ZHiqb0HLndfcsIDzczfC7Smo8+q7+KvE+cmxZ27jfKj5H+VnnSp+ M8kQzj+FBZNuUpwRBDh1Y6Zssqx6V69IeQAGy+xxz57w8RCMcOxkcfTGrwVTDxy5O6Qk EsUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=wSDugTm/teP2CrsF2OH5tXaB6LTtiIgxQPsaPiD/oxM=; b=eaTAkbYCiDCWPvrotbjIa7td1XgVzBvx6AptkCiCyW2Ghj6MvmTpwO231xYQnX/C2x HiKG6GyyLQJdrxa8boji64XAHYXgRgTNzd8SlVQ6cwyByQNIYmCTADc8BPEm8O094M5w v/5+hdd6VRtn9raPShoDMZiaaV/19RYh6pgSdrowmXVsXidkdEoOoFzLUtFqbd0zpTcW SBw9YFv2OjLIEBAkAhr/dCnGrUqPaVUpGZUE7tLDSBZxPC79C4lecqVaSNRWOcz3M2Me Ha2jHCdRfdJNQAUm5lc2Gj9p86Pajd8+DoIvSukxbBrAAJxleXjx/ggWDCCKWqiVN4sr 5U8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IHvpkdR0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:43:07 -0700 Message-Id: <20180512004311.9299-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v2 23/27] fpu/softfloat: Remove floatX_maybe_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These functions are now unused. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 63 -------------------------------------- include/fpu/softfloat.h | 5 --- 2 files changed, 68 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 4fa068a5dc..d7033b7757 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -364,19 +364,6 @@ float16 float16_silence_nan(float16 a, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the half-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -float16 float16_maybe_silence_nan(float16 a, float_status *status) -{ - if (float16_is_signaling_nan(a, status)) { - return float16_silence_nan(a, status); - } - return a; -} - /*---------------------------------------------------------------------------- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -438,18 +425,6 @@ float32 float32_silence_nan(float32 a, float_status *status) } #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the single-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -float32 float32_maybe_silence_nan(float32 a, float_status *status) -{ - if (float32_is_signaling_nan(a, status)) { - return float32_silence_nan(a, status); - } - return a; -} /*---------------------------------------------------------------------------- | Returns the result of converting the single-precision floating-point NaN @@ -864,18 +839,6 @@ float64 float64_silence_nan(float64 a, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the double-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -float64 float64_maybe_silence_nan(float64 a, float_status *status) -{ - if (float64_is_signaling_nan(a, status)) { - return float64_silence_nan(a, status); - } - return a; -} /*---------------------------------------------------------------------------- | Returns the result of converting the double-precision floating-point NaN @@ -1037,19 +1000,6 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the extended double-precision floating point value -| `a' is a signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status) -{ - if (floatx80_is_signaling_nan(a, status)) { - return floatx80_silence_nan(a, status); - } - return a; -} - /*---------------------------------------------------------------------------- | Returns the result of converting the extended double-precision floating- | point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the @@ -1204,19 +1154,6 @@ float128 float128_silence_nan(float128 a, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the quadruple-precision floating point value `a' is -| a signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -float128 float128_maybe_silence_nan(float128 a, float_status *status) -{ - if (float128_is_signaling_nan(a, status)) { - return float128_silence_nan(a, status); - } - return a; -} - /*---------------------------------------------------------------------------- | Returns the result of converting the quadruple-precision floating-point NaN | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index a6860e858d..69f4dbc4db 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -258,7 +258,6 @@ int float16_compare_quiet(float16, float16, float_status *status); int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); float16 float16_silence_nan(float16, float_status *status); -float16 float16_maybe_silence_nan(float16, float_status *status); static inline int float16_is_any_nan(float16 a) { @@ -370,7 +369,6 @@ float32 float32_maxnummag(float32, float32, float_status *status); int float32_is_quiet_nan(float32, float_status *status); int float32_is_signaling_nan(float32, float_status *status); float32 float32_silence_nan(float32, float_status *status); -float32 float32_maybe_silence_nan(float32, float_status *status); float32 float32_scalbn(float32, int, float_status *status); static inline float32 float32_abs(float32 a) @@ -500,7 +498,6 @@ float64 float64_maxnummag(float64, float64, float_status *status); int float64_is_quiet_nan(float64 a, float_status *status); int float64_is_signaling_nan(float64, float_status *status); float64 float64_silence_nan(float64, float_status *status); -float64 float64_maybe_silence_nan(float64, float_status *status); float64 float64_scalbn(float64, int, float_status *status); static inline float64 float64_abs(float64 a) @@ -604,7 +601,6 @@ int floatx80_compare_quiet(floatx80, floatx80, float_status *status); int floatx80_is_quiet_nan(floatx80, float_status *status); int floatx80_is_signaling_nan(floatx80, float_status *status); floatx80 floatx80_silence_nan(floatx80, float_status *status); -floatx80 floatx80_maybe_silence_nan(floatx80, float_status *status); floatx80 floatx80_scalbn(floatx80, int, float_status *status); static inline floatx80 floatx80_abs(floatx80 a) @@ -816,7 +812,6 @@ int float128_compare_quiet(float128, float128, float_status *status); int float128_is_quiet_nan(float128, float_status *status); int float128_is_signaling_nan(float128, float_status *status); float128 float128_silence_nan(float128, float_status *status); -float128 float128_maybe_silence_nan(float128, float_status *status); float128 float128_scalbn(float128, int, float_status *status); static inline float128 float128_abs(float128 a) From patchwork Sat May 12 00:43:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135612 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1583156lji; Fri, 11 May 2018 18:09:50 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoeNmRUGrcoWd/wcbpHm7+vLB044CK1pcvmUvhqcTbDskVE8ZbPqLQpjOsk8bNnEj7/qFXb X-Received: by 2002:ac8:3653:: with SMTP id n19-v6mr282757qtb.271.1526087390120; Fri, 11 May 2018 18:09:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526087390; cv=none; d=google.com; s=arc-20160816; b=aHrATm5U8x2jXQVEnBfrYEE9iTyYji44tmHTXObjbf6vkVLSdu59xGv9VyBr4ae1EI EbVyLxFbjE2FF/oI3YlkmdFU/x9lP/nQbcCfM15nKpj/bT5CCProJz1k+7+6r4nm6EwM 6PgWq96mQcYG42p+2h38sbkyzeROniseGAaB3A6Yv1Gw1GIunWb1+n1fYb/W7S26rbqr zXkJdPO3Fle+YPHqK2B+aasNTGY9K50ElsifQbawHUEgcmxZixdbXZ7lTTzOYV5+7mGJ rqjfUFGPU2owCjWmxHhd9ByTa2mAM2Llu/KEXflBXpIz3LswmQcD0av9vvC9mWjisodg Zjxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=74hHDUr2PN/nlWammC4LQv19ml9vCrUPOxiwVLGqb0o=; b=dDYum6GwRcD8O7uT/qzKs0K+Sn354S1htA46+x0Qt4V9j/lGz6II6fl71WWzsjm0Zb Q28YTC1CYDcf0MCzpEKUHD75Xq+7iaLIXlg/LTkaG/Qd+l+OtG1cfaO1sSM1fF8YT2qT Jp5FOMY/Mx4cpl3tpf/WLrD29aQDAjL0yBVH+EovYkF2933n4MHOcsFSW84KjP0/9E6W /DnKU3Xdj14BCvpQYZRiJLY6MNxWGYKCb2TY9ZM8a1boPJDSxYnYCYSELFofMBYw4J1l F5sY+h1aIuSpaM6G1kHegcMPh1NzCXSI2rNuTzKnk1CcjTVVdc2+fYO9QPvFfjqCFHI8 QRNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DTwKff+D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:43:08 -0700 Message-Id: <20180512004311.9299-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v2 24/27] fpu/softfloat: Specialize on snan_bit_is_one X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, Alexander Graf , Guan Xuetao , Yongbok Kim , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Only MIPS requires snan_bit_is_one to be variable. While we are specializing softfloat behaviour, allow other targets to eliminate this runtime check. Cc: Aurelien Jarno Cc: Yongbok Kim Cc: David Gibson Cc: Alexander Graf Cc: Guan Xuetao Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 68 ++++++++++++++++++++++------------- include/fpu/softfloat-types.h | 1 + include/fpu/softfloat.h | 4 --- target/mips/cpu.h | 4 +-- target/hppa/cpu.c | 1 - target/mips/translate_init.c | 4 +-- target/ppc/fpu_helper.c | 1 - target/sh4/cpu.c | 1 - target/unicore32/cpu.c | 2 -- 9 files changed, 48 insertions(+), 38 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index d7033b7757..5cd9c2eedc 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -79,13 +79,31 @@ this code that are retained. * version 2 or later. See the COPYING file in the top-level directory. */ -#if defined(TARGET_XTENSA) /* Define for architectures which deviate from IEEE in not supporting * signaling NaNs (so all NaNs are treated as quiet). */ +#if defined(TARGET_XTENSA) #define NO_SIGNALING_NANS 1 #endif +/* Define how the architecture discriminates signaling NaNs. + * This done with the most significant bit of the fraction. + * In the original IEEE754 spec this was implementation defined; + * in the 2008 revision the msb is zero. MIPS is (so far) unique + * in supporting both the 2008 revision and backward compatibility + * with their original choice and thus must make the choice at runtime. + */ +static inline flag snan_bit_is_one(float_status *status) +{ +#if defined(TARGET_MIPS) + return status->snan_bit_is_one; +#elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4) + return 1; +#else + return 0; +#endif +} + /*---------------------------------------------------------------------------- | For the deconstructed floating-point with fraction FRAC, return true | if the fraction represents a signalling NaN; otherwise false. @@ -97,7 +115,7 @@ static bool parts_is_snan_frac(uint64_t frac, float_status *status) return false; #else flag msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); - return msb == status->snan_bit_is_one; + return msb == snan_bit_is_one(status); #endif } @@ -118,7 +136,7 @@ static FloatParts parts_default_nan(float_status *status) #elif defined(TARGET_HPPA) frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; } else { #if defined(TARGET_MIPS) @@ -151,7 +169,7 @@ static FloatParts parts_silence_nan(FloatParts a, float_status *status) a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return parts_default_nan(status); } else { a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); @@ -169,7 +187,7 @@ float16 float16_default_nan(float_status *status) #if defined(TARGET_ARM) return const_float16(0x7E00); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return const_float16(0x7DFF); } else { #if defined(TARGET_MIPS) @@ -195,7 +213,7 @@ float32 float32_default_nan(float_status *status) #elif defined(TARGET_HPPA) return const_float32(0x7FA00000); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return const_float32(0x7FBFFFFF); } else { #if defined(TARGET_MIPS) @@ -220,7 +238,7 @@ float64 float64_default_nan(float_status *status) #elif defined(TARGET_HPPA) return const_float64(LIT64(0x7FF4000000000000)); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return const_float64(LIT64(0x7FF7FFFFFFFFFFFF)); } else { #if defined(TARGET_MIPS) @@ -242,7 +260,7 @@ floatx80 floatx80_default_nan(float_status *status) r.low = LIT64(0xFFFFFFFFFFFFFFFF); r.high = 0x7FFF; #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { r.low = LIT64(0xBFFFFFFFFFFFFFFF); r.high = 0x7FFF; } else { @@ -274,7 +292,7 @@ float128 float128_default_nan(float_status *status) { float128 r; - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { r.low = LIT64(0xFFFFFFFFFFFFFFFF); r.high = LIT64(0x7FFF7FFFFFFFFFFF); } else { @@ -319,7 +337,7 @@ int float16_is_quiet_nan(float16 a_, float_status *status) return float16_is_any_nan(a_); #else uint16_t a = float16_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); } else { return ((a & ~0x8000) >= 0x7C80); @@ -338,7 +356,7 @@ int float16_is_signaling_nan(float16 a_, float_status *status) return 0; #else uint16_t a = float16_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a & ~0x8000) >= 0x7C80); } else { return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); @@ -356,7 +374,7 @@ float16 float16_silence_nan(float16 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return float16_default_nan(status); } else { return a | (1 << 9); @@ -375,7 +393,7 @@ int float32_is_quiet_nan(float32 a_, float_status *status) return float32_is_any_nan(a_); #else uint32_t a = float32_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); } else { return ((uint32_t)(a << 1) >= 0xFF800000); @@ -394,7 +412,7 @@ int float32_is_signaling_nan(float32 a_, float_status *status) return 0; #else uint32_t a = float32_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((uint32_t)(a << 1) >= 0xFF800000); } else { return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); @@ -412,7 +430,7 @@ float32 float32_silence_nan(float32 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { # ifdef TARGET_HPPA a &= ~0x00400000; a |= 0x00200000; @@ -651,7 +669,7 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, return 3; } - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { /* Prefer sNaN over qNaN, in the a, b, c order. */ if (aIsSNaN) { return 0; @@ -786,7 +804,7 @@ int float64_is_quiet_nan(float64 a_, float_status *status) return float64_is_any_nan(a_); #else uint64_t a = float64_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a >> 51) & 0xFFF) == 0xFFE) && (a & 0x0007FFFFFFFFFFFFULL); } else { @@ -806,7 +824,7 @@ int float64_is_signaling_nan(float64 a_, float_status *status) return 0; #else uint64_t a = float64_val(a_); - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a << 1) >= 0xFFF0000000000000ULL); } else { return (((a >> 51) & 0xFFF) == 0xFFE) @@ -825,7 +843,7 @@ float64 float64_silence_nan(float64 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { # ifdef TARGET_HPPA a &= ~0x0008000000000000ULL; a |= 0x0004000000000000ULL; @@ -942,7 +960,7 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *status) #ifdef NO_SIGNALING_NANS return floatx80_is_any_nan(a); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { uint64_t aLow; aLow = a.low & ~0x4000000000000000ULL; @@ -967,7 +985,7 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) #ifdef NO_SIGNALING_NANS return 0; #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a.high & 0x7FFF) == 0x7FFF) && ((a.low << 1) >= 0x8000000000000000ULL); } else { @@ -991,7 +1009,7 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return floatx80_default_nan(status); } else { a.low |= LIT64(0xC000000000000000); @@ -1105,7 +1123,7 @@ int float128_is_quiet_nan(float128 a, float_status *status) #ifdef NO_SIGNALING_NANS return float128_is_any_nan(a); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return (((a.high >> 47) & 0xFFFF) == 0xFFFE) && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); } else { @@ -1125,7 +1143,7 @@ int float128_is_signaling_nan(float128 a, float_status *status) #ifdef NO_SIGNALING_NANS return 0; #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return ((a.high << 1) >= 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); } else { @@ -1145,7 +1163,7 @@ float128 float128_silence_nan(float128 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (snan_bit_is_one(status)) { return float128_default_nan(status); } else { a.high |= LIT64(0x0000800000000000); diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 4e378cb612..b5207d4537 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -173,6 +173,7 @@ typedef struct float_status { /* should denormalised inputs go to zero and set the input_denormal flag? */ flag flush_inputs_to_zero; flag default_nan_mode; + /* not always used -- see SNAN_BIT_IS_ONE in softfloat-specialize.h */ flag snan_bit_is_one; } float_status; diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 69f4dbc4db..e72cc9525d 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -125,10 +125,6 @@ static inline void set_default_nan_mode(flag val, float_status *status) { status->default_nan_mode = val; } -static inline void set_snan_bit_is_one(flag val, float_status *status) -{ - status->snan_bit_is_one = val; -} static inline int get_float_detect_tininess(float_status *status) { return status->float_detect_tininess; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index cfe1735e0e..2abce47ea3 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -755,8 +755,8 @@ target_ulong exception_resume_pc (CPUMIPSState *env); static inline void restore_snan_bit_mode(CPUMIPSState *env) { - set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, - &env->active_fpu.fp_status); + env->active_fpu.fp_status.snan_bit_is_one + = (env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0; } static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c261b6b090..00bf444620 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -141,7 +141,6 @@ static void hppa_cpu_initfn(Object *obj) cs->env_ptr = env; cs->exception_index = -1; cpu_hppa_loaded_fr0(env); - set_snan_bit_is_one(true, &env->fp_status); cpu_hppa_put_psw(env, PSW_W); } diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c index c7ba6ee5f9..5e40d6a198 100644 --- a/target/mips/translate_init.c +++ b/target/mips/translate_init.c @@ -878,6 +878,6 @@ static void msa_reset(CPUMIPSState *env) /* clear float_status nan mode */ set_default_nan_mode(0, &env->active_tc.msa_fp_status); - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); + /* set proper signaling bit meaning ("1" means "quiet") */ + env->active_tc.msa_fp_status.snan_bit_is_one = 0; } diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 9ae418a577..d31a933cbb 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3382,7 +3382,6 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode) xt.f128 = xb.f128; } else if (float128_is_neg(xb.f128) && !float128_is_zero(xb.f128)) { float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); - set_snan_bit_is_one(0, &env->fp_status); xt.f128 = float128_default_nan(&env->fp_status); } } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 541ffc2d97..b9f393b7c7 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -71,7 +71,6 @@ static void superh_cpu_reset(CPUState *s) set_flush_to_zero(1, &env->fp_status); #endif set_default_nan_mode(1, &env->fp_status); - set_snan_bit_is_one(1, &env->fp_status); } static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 29d160a88d..68f978d80b 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -70,7 +70,6 @@ static void unicore_ii_cpu_initfn(Object *obj) set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); - set_snan_bit_is_one(1, &env->ucf64.fp_status); } static void uc32_any_cpu_initfn(Object *obj) @@ -83,7 +82,6 @@ static void uc32_any_cpu_initfn(Object *obj) set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); - set_snan_bit_is_one(1, &env->ucf64.fp_status); } static void uc32_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Sat May 12 00:43:09 2018 Content-Type: text/plain; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:43:09 -0700 Message-Id: <20180512004311.9299-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 25/27] fpu/softfloat: Make is_nan et al available to softfloat-specialize.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will need these helpers within softfloat-specialize.h, so move the definitions above the include. After specialization, they will not always be used so mark them to avoid the Werror. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 15a272759d..bafb3b17ec 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -181,6 +181,22 @@ typedef enum __attribute__ ((__packed__)) { float_class_snan, } FloatClass; +/* Simple helpers for checking if what NaN we have */ +static inline __attribute__((unused)) bool is_nan(FloatClass c) +{ + return unlikely(c >= float_class_qnan); +} + +static inline __attribute__((unused)) bool is_snan(FloatClass c) +{ + return c == float_class_snan; +} + +static inline __attribute__((unused)) bool is_qnan(FloatClass c) +{ + return c == float_class_qnan; +} + /* * Structure holding all of the decomposed parts of a float. The * exponent is unbiased and the fraction is normalized. All @@ -536,20 +552,6 @@ static float64 float64_round_pack_canonical(FloatParts p, float_status *s) return float64_pack_raw(round_canonical(p, s, &float64_params)); } -/* Simple helpers for checking if what NaN we have */ -static bool is_nan(FloatClass c) -{ - return unlikely(c >= float_class_qnan); -} -static bool is_snan(FloatClass c) -{ - return c == float_class_snan; -} -static bool is_qnan(FloatClass c) -{ - return c == float_class_qnan; -} - static FloatParts return_nan(FloatParts a, float_status *s) { switch (a.cls) { From patchwork Sat May 12 00:43:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135608 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1577853lji; Fri, 11 May 2018 18:03:17 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoV+lBdn1Y3BSnBQTl4LsMP/7P9nMa0QsL1wTLa+adA+3a/bMO0hvLRYpDRrKmoFdBZfwsm X-Received: by 2002:ac8:2947:: with SMTP id z7-v6mr262634qtz.251.1526086997726; Fri, 11 May 2018 18:03:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086997; cv=none; d=google.com; s=arc-20160816; b=YuLfMPKWT32BJ1YW/1FtFHbrDS8uxl/lgYzvSkCMG6m2LUvCALwyb3KuYQa7fLBqmo N295UuK1vhfCZIy2qWBXRCCONqxzJ1g/6oqWXm5zGsucX2mf3h08/l/OXu7Ms4CGFIca 5OCPe/IettqNaq2O0MVaETJAa9SQWvmcLnDJsd5s6IwoyeqvDdfHhnVZKJcYOhizDdpp n5QK7WPXfCM3kzykkSLAuKRaE+dJveXsBogL1cK0ujMb7hnK9p5JNwLxNuQdCkFjXyAp DG/FlErkGYiBwkJx5UEgZ7tNUoIrXajnxK2xKgZeNcItvHQfaHcuJy2E8jzMs3EsH3mu A5jA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=OLwRyqiVtAgxne/pAsfTeeYmFPSiAGQofxlUBv5JHyQ=; b=iNiIlmQM6hciI6Z0Vvi38PCA79FmPkN4qqBHx2jStugJVv2jqVglGL45w1+UST5Vy3 MG48gZtBPResYVYJnTZocBqH0GQ4xis8QHV7ioXwyHMjUfej7FxnZunELsuGnQvU1LuT RtkzwaRhAcfzR1brU6hKunYpnc/cE75ilUk4FBAb8OLG/44C7oORgRRbMCBTnQuFWbpM tmbwwBStcKHbulUfeNn0xEwjQMA5KQzNDo0ojUUtj9qj5/paUQHOT5/cGgvr6bETyG4e x6mR3EY+fsYoD3TuCAnI+iAPCBn7Trny+pr3WljKrXwO6OMUilLXd28dKcYHaXVyM+Rt vMzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X6sEfgPf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:43:10 -0700 Message-Id: <20180512004311.9299-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2 26/27] fpu/softfloat: Pass FloatClass to pickNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For each operand, pass a single enumeration instead of a pair of booleans. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 168 ++++++++++++++++++------------------- fpu/softfloat.c | 3 +- 2 files changed, 82 insertions(+), 89 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 5cd9c2eedc..47c67caec6 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -501,10 +501,10 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status) | tie-break rule. *----------------------------------------------------------------------------*/ -#if defined(TARGET_ARM) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, +static int pickNaN(FloatClass a_cls, FloatClass b_cls, flag aIsLargerSignificand) { +#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take * the first of: * 1. A if it is signaling @@ -513,20 +513,6 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, * 4. B (quiet) * A signaling NaN is always quietened before returning it. */ - if (aIsSNaN) { - return 0; - } else if (bIsSNaN) { - return 1; - } else if (aIsQNaN) { - return 0; - } else { - return 1; - } -} -#elif defined(TARGET_MIPS) || defined(TARGET_HPPA) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* According to MIPS specifications, if one of the two operands is * a sNaN, a new qNaN has to be generated. This is done in * floatXX_silence_nan(). For qNaN inputs the specifications @@ -540,35 +526,21 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, * 4. B (quiet) * A signaling NaN is always silenced before returning it. */ - if (aIsSNaN) { + if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } -} -#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ +#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K) /* PowerPC propagation rules: * 1. A if it sNaN or qNaN * 2. B if it sNaN or qNaN * A signaling NaN is always silenced before returning it. */ - if (aIsSNaN || aIsQNaN) { - return 0; - } else { - return 1; - } -} -#elif defined(TARGET_M68K) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL * 3.4 FLOATING-POINT INSTRUCTION DETAILS * If either operand, but not both operands, of an operation is a @@ -583,16 +555,12 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, * a nonsignaling NaN. The operation then continues as described in the * preceding paragraph for nonsignaling NaNs. */ - if (aIsQNaN || aIsSNaN) { /* a is the destination operand */ - return 0; /* return the destination operand */ + if (is_nan(a_cls)) { + return 0; } else { - return 1; /* return b */ + return 1; } -} #else -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* This implements x87 NaN propagation rules: * SNaN + QNaN => return the QNaN * two SNaNs => return the one with the larger significand, silenced @@ -603,13 +571,13 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, * If we get down to comparing significands and they are the same, * return the NaN with the positive sign bit (if any). */ - if (aIsSNaN) { - if (bIsSNaN) { + if (is_snan(a_cls)) { + if (is_snan(b_cls)) { return aIsLargerSignificand ? 0 : 1; } - return bIsQNaN ? 1 : 0; - } else if (aIsQNaN) { - if (bIsSNaN || !bIsQNaN) { + return is_qnan(b_cls) ? 1 : 0; + } else if (is_qnan(a_cls)) { + if (is_snan(b_cls) || !is_qnan(b_cls)) { return 0; } else { return aIsLargerSignificand ? 0 : 1; @@ -617,8 +585,8 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, } else { return 1; } -} #endif +} /*---------------------------------------------------------------------------- | Select which NaN to propagate for a three-input operation. @@ -752,18 +720,26 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; uint32_t av, bv; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!float32_is_any_nan(a) + ? float_class_normal + : float32_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!float32_is_any_nan(b) + ? float_class_normal + : float32_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); - aIsQuietNaN = float32_is_quiet_nan(a, status); - aIsSignalingNaN = float32_is_signaling_nan(a, status); - bIsQuietNaN = float32_is_quiet_nan(b, status); - bIsSignalingNaN = float32_is_signaling_nan(b, status); av = float32_val(a); bv = float32_val(b); - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } @@ -779,14 +755,13 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) aIsLargerSignificand = (av < bv) ? 1 : 0; } - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float32_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float32_silence_nan(a, status); } return a; @@ -908,18 +883,26 @@ static float64 commonNaNToFloat64(commonNaNT a, float_status *status) static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; uint64_t av, bv; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!float64_is_any_nan(a) + ? float_class_normal + : float64_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!float64_is_any_nan(b) + ? float_class_normal + : float64_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); - aIsQuietNaN = float64_is_quiet_nan(a, status); - aIsSignalingNaN = float64_is_signaling_nan(a, status); - bIsQuietNaN = float64_is_quiet_nan(b, status); - bIsSignalingNaN = float64_is_signaling_nan(b, status); av = float64_val(a); bv = float64_val(b); - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } @@ -935,14 +918,13 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) aIsLargerSignificand = (av < bv) ? 1 : 0; } - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float64_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float64_silence_nan(a, status); } return a; @@ -1075,15 +1057,22 @@ static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status) floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; + FloatClass a_cls, b_cls; - aIsQuietNaN = floatx80_is_quiet_nan(a, status); - aIsSignalingNaN = floatx80_is_signaling_nan(a, status); - bIsQuietNaN = floatx80_is_quiet_nan(b, status); - bIsSignalingNaN = floatx80_is_signaling_nan(b, status); + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!floatx80_is_any_nan(a) + ? float_class_normal + : floatx80_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!floatx80_is_any_nan(b) + ? float_class_normal + : floatx80_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } @@ -1099,14 +1088,13 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) aIsLargerSignificand = (a.high < b.high) ? 1 : 0; } - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return floatx80_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return floatx80_silence_nan(a, status); } return a; @@ -1217,15 +1205,22 @@ static float128 commonNaNToFloat128(commonNaNT a, float_status *status) static float128 propagateFloat128NaN(float128 a, float128 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; + FloatClass a_cls, b_cls; - aIsQuietNaN = float128_is_quiet_nan(a, status); - aIsSignalingNaN = float128_is_signaling_nan(a, status); - bIsQuietNaN = float128_is_quiet_nan(b, status); - bIsSignalingNaN = float128_is_signaling_nan(b, status); + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!float128_is_any_nan(a) + ? float_class_normal + : float128_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!float128_is_any_nan(b) + ? float_class_normal + : float128_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } @@ -1241,14 +1236,13 @@ static float128 propagateFloat128NaN(float128 a, float128 b, aIsLargerSignificand = (a.high < b.high) ? 1 : 0; } - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float128_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float128_silence_nan(a, status); } return a; diff --git a/fpu/softfloat.c b/fpu/softfloat.c index bafb3b17ec..593869e5a7 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -580,8 +580,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) if (s->default_nan_mode) { return parts_default_nan(s); } else { - if (pickNaN(is_qnan(a.cls), is_snan(a.cls), - is_qnan(b.cls), is_snan(b.cls), + if (pickNaN(a.cls, b.cls, a.frac > b.frac || (a.frac == b.frac && a.sign < b.sign))) { a = b; From patchwork Sat May 12 00:43:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135607 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1576570lji; Fri, 11 May 2018 18:01:34 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqZNhOcY+Nf6vBkvmz/oSoDEm4wlkcPFKb7UpiAfykThgMGdvVxVP8DPfvyhxqhuIcubJVf X-Received: by 2002:a37:8e82:: with SMTP id q124-v6mr297077qkd.164.1526086893893; Fri, 11 May 2018 18:01:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526086893; cv=none; d=google.com; s=arc-20160816; b=lx4on6Dp7w4Cxa6UjhFWXxlZS8c7UaoJ9isuWoIYd1BdQHCqug+A3X2aE2cbY5ADDQ OC4smKaQRKSsAkd002xDiyzrzpaXfkNW6TiuAFzADIaJS4BWBiEl27zEFOcAWlMKB7Nl iQ1HKRrIbWg+E7dkXwNorQ2b2sIkRszCgIpieMl/yyaWGEjEcICXjSyhsuBRpk8a3euF 8+nbfRut7cT/Q+JyC8NnSiLb6YuBxZfwfGY7WX6+a+blKv6r5shzp3BPOwEg8sY6XwhH 722lb16vxtlJk1Zaqll0uiEK9VZhZAyOB0qCnKotAu/rGdkGyN2OsiCh8LL2ZYQqFPqM 8Gzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=9Kw0v/bjdnoQ0gjwFI3jeD7E5e5E3uBbMXsOVv49YD0=; b=l9B85QsbXfL9rHnrCCronwFugRLO6/8QljpzcPjeq6VFsxBCrp4Yt8DhFWX532RYc/ bwhR8IlkpnpwdLWMAwKBChUofKrBOYkQnkD3Om52iXIyJS6dmc2dfrpuc37NEkEBpPcw AkjAmVQrhCEIV08pLjLrTa+o1kM0QW6G21Q52+E8NZZB7yozB9vrNGguH7meZPwjANpw mRZ6zosdBaavpVJt1H1MVIrTlEf7XKPKMQX8e+l0W/4bLXMbkVol3wmuvzqpGWZm7YRL Ursdd+EAFUx2SldO7GSKSysX/jK+l5YHfE64Ypx2vWmz+ZvAKXShBkUUZ1ElYUAgoR6e TnPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UTDn5DHu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:43:11 -0700 Message-Id: <20180512004311.9299-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512004311.9299-1-richard.henderson@linaro.org> References: <20180512004311.9299-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v2 27/27] fpu/softfloat: Pass FloatClass to pickNaNMulAdd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For each operand, pass a single enumeration instead of a pair of booleans. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 70 +++++++++++++++----------------------- fpu/softfloat.c | 5 +-- 2 files changed, 28 insertions(+), 47 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 47c67caec6..85c59c20d8 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -594,15 +594,14 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | information. | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN *----------------------------------------------------------------------------*/ -#if defined(TARGET_ARM) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) +static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, + bool infzero, float_status *status) { +#if defined(TARGET_ARM) /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN */ - if (infzero && cIsQNaN) { + if (infzero && is_qnan(c_cls)) { float_raise(float_flag_invalid, status); return 3; } @@ -610,25 +609,20 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, /* This looks different from the ARM ARM pseudocode, because the ARM ARM * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. */ - if (cIsSNaN) { + if (is_snan(c_cls)) { return 2; - } else if (aIsSNaN) { + } else if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsQNaN) { + } else if (is_qnan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } -} #elif defined(TARGET_MIPS) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN */ @@ -639,41 +633,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, if (snan_bit_is_one(status)) { /* Prefer sNaN over qNaN, in the a, b, c order. */ - if (aIsSNaN) { + if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsSNaN) { + } else if (is_snan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; - } else if (bIsQNaN) { + } else if (is_qnan(b_cls)) { return 1; } else { return 2; } } else { /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (cIsSNaN) { + if (is_snan(c_cls)) { return 2; - } else if (aIsSNaN) { + } else if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsQNaN) { + } else if (is_qnan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } } -} #elif defined(TARGET_PPC) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer * to return an input NaN if we have one (ie c) rather than generating * a default NaN @@ -686,31 +675,26 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB */ - if (aIsSNaN || aIsQNaN) { + if (is_nan(a_cls)) { return 0; - } else if (cIsSNaN || cIsQNaN) { + } else if (is_nan(c_cls)) { return 2; } else { return 1; } -} #else -/* A default implementation: prefer a to b to c. - * This is unlikely to actually match any real implementation. - */ -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ - if (aIsSNaN || aIsQNaN) { + /* A default implementation: prefer a to b to c. + * This is unlikely to actually match any real implementation. + */ + if (is_nan(a_cls)) { return 0; - } else if (bIsSNaN || bIsQNaN) { + } else if (is_nan(b_cls)) { return 1; } else { return 2; } -} #endif +} /*---------------------------------------------------------------------------- | Takes two single-precision floating-point values `a' and `b', one of which diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 593869e5a7..383f2f5f99 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -601,10 +601,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, s->float_exception_flags |= float_flag_invalid; } - which = pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls), - is_qnan(b.cls), is_snan(b.cls), - is_qnan(c.cls), is_snan(c.cls), - inf_zero, s); + which = pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s); if (s->default_nan_mode) { /* Note that this check is after pickNaNMulAdd so that function